B100NF04

STP100NF04 STB100NF04 N-channel 40V - 0.0043Ω - 120A - TO-220 - D2PAK STripFET™ II Power MOSFET General features Type STP100NF04 STB100NF04 ■ ■ VDSS 40V 40V RDS(on) < 0.0046Ω < 0.0046Ω ID 120A 120A Pw 300W 300W 3 1 1 2 3 Standard threshold drive 100% avalanche tested D²PAK TO-220 Description This Power MOSFET is the latest development of STMicroelectronics unique “Single Feature Size™” strip-based process. The resulting transistor shows extremely high packing density for low on-resistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. Internal schematic diagram Applications ■ Switching application Order codes Part number STB100NF04 STP100NF04 Marking B100NF04 P100NF04 Package D²PAK TO-220 Packaging Tape & Reel Tube February 2007 Rev 5 1/17 www.st.com 17 Contents: STB100NF04 - STP100NF04 Contents: 1 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 2.2 Electrical characteristics (curves) ............................ 6 Spice Thermal Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 4 5 6 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2/17 STB100NF04 - STP100NF04 Electrical ratings 1 Electrical ratings Table 1. Symbol VDS VGS ID ID (1) (1) Absolute maximum ratings Parameter Drain-source Voltage (VGS=0) Gate-source Voltage Drain-current (continuous) at Tc=25°C Drain-current (continuous) at Tc=100°C Drain-current (pulsed) Total dissipation at Tc=25°C Derating factor Value 40 ±20 120 120 480 300 2 6 1.2 -55 to 175 Unit V V A A A W W/°C V/ns J °C IDM(2) PTOT dv/dt(3) EAS(4) Tj Tstg Peak Diode Recovery voltage slope Single Pulse Avalanche Energy Operating Junction Temperature Storage Temperature 1. Current limited by package 2. Pulse width limited by safe operating area. 3. ISD ≤ 120A, di/dt ≤ 300A/µs, VDD < V(BR)DSS. Tj < Tjmax 4. Starting Tj=25°C, ID=60A, VDD=30V Table 2. Symbol Rthj-case Rthj-pcb Rthj-amb Tl Thermal resistance Parameter Thermal Resistance Junction-case Max Thermal Resistance Junction-pcb Max Thermal Resistance Junction-ambient (Free Air) Max Maximum Lead Temperature For Soldering Purpose Value 0.5 (see Figure 13) 62.5 300 Unit °C/W °C/W °C/W °C 3/17 Electrical characteristics STB100NF04 - STP100NF04 2 Electrical characteristics (TCASE=25°C unless otherwise specified) Table 3. Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on) On/off Parameter Test conditions Min. 40 1 10 ±100 2 4 0.0043 0.0046 Typ. Max. Unit V µA µA nA V Ω Drain-source Breakdown ID=250µA, VGS=0 Voltage Zero Gate Voltage Drain VDS=Max Rating Current (VGS=0) VDS=Max Rating Tc=125°C Gate-body Leakage Current (VDS=0) Gate Threshold Voltage Static Drain-source On Resistance VGS=±20V VDS=VGS, ID=250µA VGS=10V, ID=50A Table 4. Symbol gfs Ciss Coss Crss Qg Qgs Qgd td(on) tr td(off) tf Dynamic Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-on Delay Time Rise time Turn-off delay Time Fall Time Test conditions VDS=15V, ID=50A VDS=25V, f=1MHz,VGS=0 Min Typ. 150 5100 1300 160 110 35 70 35 220 80 50 150 Max. Unit S pF pF pF nC nC nC ns ns ns ns VDD=32V, ID=120A VGS=10V VDD=20V, ID=60A , RG=4.7Ω VGS=10V (see Figure 21) 4/17 STB100NF04 - STP100NF04 Electrical characteristics Table 5. Symbol ISD ISDM(1) VSD(2) trr Qrr IRRM Source drain diode Parameter Source-drain Current Source-drain Current (pulsed) Forward on Voltage Reverse Recovery Time Reverse Recovery Charge Reverse recovery Current ISD=120A, VGS=0 ISD=120A, VDD=20V, di/dt=100A/µs, Tj=150°C 75 185 5 Test conditions Min. Typ. Max. 120 480 1.3 Unit A A V ns nC A 1. Pulse width limited by safe operating area. 2. Pulsed: pulse duration=300µs, duty cycle 1.5% 5/17 Electrical characteristics STB100NF04 - STP100NF04 2.1 Figure 1. Electrical characteristics (curves) Power Derating vs. Tc Figure 2. Max Id Current vs. Tc Figure 3. Output Characteristics Figure 4. Transfer Characteristics Figure 5. Transconductance Figure 6. Static Drain-source on Resistance 6/17 STB100NF04 - STP100NF04 Figure 7. Gate Charge vs. Gate-source Voltage Figure 8. Electrical characteristics Capacitance Variations Figure 9. Normalized Gate Threshold Voltage Figure 10. Normalized on Resistance vs. vs. Temperature Temperature Figure 11. Source-Drain Diode Forward Characteristics Figure 12. Normalized BVdss vs. Temperature 7/17 Electrical characteristics Figure 13. Thermal Resistance Rthj-pcb vs. PCB Copper Area STB100NF04 - STP100NF04 Figure 14. Thermal Impedance Figure 15. Max Power Dissipation vs. PCB Copper Area Figure 16. Safe Operating Area 8/17 STB100NF04 - STP100NF04 Figure 17. Allowable Iav vs. Time in Avalanche Electrical characteristics The previous curve give the safe operating area for unclamped inductive loads, single pulse or repetitive, under the following conditions: PD(AVE) = 0.5*(1.3*BVDSS*IAV) EAS(AR) = PD(AVE) * tAV Where: IAV is the Allowable Current in Avalanche PD(AVE) is the Average Power Dissipation in Avalanche (Single Pulse) tAV is the Time in Avalanche To de rate above 25°C, at fixed IAV, the following equation must be applied: IAV=2*(Tjmax - TCASE) / (1.3*BVDSS * Zth) Where: Zth= K*Rth is the value coming from Normalized Thermal Response at fixed pulse width equal to TAV 9/17 Electrical characteristics STB100NF04 - STP100NF04 2.2 Spice thermal model Table 6. Spice parameter Parameter CTHERM1 CTHERM1 CTHERM3 CTHERM4 Node 5-4 4-3 3-2 2-1 Value 0.011 0.0012 0.05 0.1 RTHERM1 RTHERM2 RTHERM3 RTHERM4 5-4 4-3 3-2 2-1 0.09 0.02 0.11 0.17 Figure 18. Spice model schematic 10/17 STB100NF04 - STP100NF04 Test circuit 3 Test circuit Figure 20. Unclamped inductive waveform Figure 19. Unclamped inductive load test circuit Figure 21. Switching times test circuit for resistive load Figure 22. Gate charge test circuit Figure 23. Test circuit for inductive load switching Figure 24. Switching time waveform 11/17 Package mechanical data STB100NF04 - STP100NF04 4 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 12/17 STB100NF04 - STP100NF04 Package mechanical data TO-220 MECHANICAL DATA DIM. A b b1 c D E e e1 F H1 J1 L L1 L20 L30 mm. MIN. 4.40 0.61 1.15 0.49 15.25 10 2.40 4.95 1.23 6.20 2.40 13 3.50 16.40 28.90 3.75 2.65 3.85 2.95 0.147 0.104 TYP MAX. 4.60 0.88 1.70 0.70 15.75 10.40 2.70 5.15 1.32 6.60 2.72 14 3.93 MIN. 0.173 0.024 0.045 0.019 0.60 0.393 0.094 0.194 0.048 0.244 0.094 0.511 0.137 0.645 1.137 0.151 0.116 inch TYP. MAX. 0.181 0.034 0.066 0.027 0.620 0.409 0.106 0.202 0.052 0.256 0.107 0.551 0.154 øP Q 13/17 Package mechanical data STB100NF04 - STP100NF04 D2PAK MECHANICAL DATA TO-247 MECHANICAL DATA mm. DIM. MIN. A A1 A2 B B2 C C2 D D1 E E1 G L L2 L3 M R V2 0º 4.88 15 1.27 1.4 2.4 0.4 4º 10 8.5 5.28 15.85 1.4 1.75 3.2 0.192 0.590 0.050 0.055 0.094 0.015 4.4 2.49 0.03 0.7 1.14 0.45 1.23 8.95 8 10.4 0.393 0.334 0.208 0.625 0.055 0.068 0.126 TYP MAX. 4.6 2.69 0.23 0.93 1.7 0.6 1.36 9.35 MIN. 0.173 0.098 0.001 0.027 0.044 0.017 0.048 0.352 0.315 TYP. MAX. 0.181 0.106 0.009 0.036 0.067 0.023 0.053 0.368 inch 3 1 14/17 STB100NF04 - STP100NF04 Packaging mechanical data 5 Packaging mechanical data D2PAK FOOTPRINT TAPE AND REEL SHIPMENT REEL MECHANICAL DATA DIM. A B C D G N T 1.5 12.8 20.2 24.4 100 30.4 26.4 13.2 mm MIN. MAX. 330 0.059 0.504 0.520 0795 0.960 1.039 3.937 1.197 BULK QTY 1000 inch MIN. MAX. 12.992 TAPE MECHANICAL DATA DIM. A0 B0 D D1 E F K0 P0 P1 P2 R T W mm MIN. 10.5 15.7 1.5 1.59 1.65 11.4 4.8 3.9 11.9 1.9 50 0.25 23.7 24.3 MAX. 10.7 15.9 1.6 1.61 1.85 11.6 5.0 4.1 12.1 2.1 inch MIN. MAX. 0.413 0.421 0.618 0.626 0.059 0.063 0.062 0.063 0.065 0.073 0.449 0.456 0.189 0.197 0.153 0.161 0.468 0.476 0.075 0.082 1.574 0.35 0.0098 0.0137 0.933 0.956 BASE QTY 1000 * on sales type 15/17 Revision history STB100NF04 - STP100NF04 6 Revision history Table 7. Date 23-Mar-2005 01-Mar-2006 04-Sep-2006 20-Feb-2007 Revision history Revision 2 3 4 5 New template Removed I²PAK and inserted D²PAK. New template, no content change Typo mistake on page 1 Changes 16/17 STB100NF04 - STP100NF04 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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