CSTS0400MGA06

ST72334J/N, ST72314J/N, ST72124J 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES s s s s s s Memories – 8K or 16K Program memory (ROM or single voltage FLASH) with read-out protection and in-situ programming (remote ISP) – 256 bytes EEPROM Data memory (with readout protection option in ROM devices) – 384 or 512 bytes RAM Clock, Reset and Supply Management – Enhanced reset system – Enhanced low voltage supply supervisor with 3 programmable levels – Clock sources: crystal/ceramic resonator oscillators or RC oscillators, external clock, backup Clock Security System – 4 Power Saving Modes: Halt, Active-Halt, Wait and Slow – Beep and clock-out capabilities Interrupt Management – 10 interrupt vectors plus TRAP and RESET – 15 external interrupt lines (4 vectors) 44 or 32 I/O Ports – 44 or 32 multifunctional bidirectional I/O lines: – 21 or 19 alternate function lines – 12 or 8 high sink outputs 4 Timers – Configurable watchdog timer – Realtime base – Two 16-bit timers with: 2 input captures (only one on timer A), 2 output compares (only one on timer A), External clock input on timer A, PWM and Pulse generator modes 2 Communications Interfaces – SPI synchronous serial interface – SCI asynchronous serial interface (LIN compatible) Features PSDIP56 PSDIP42 TQFP64 14 x 14 TQFP44 10 x 10 s 1 Analog Peripheral – 8-bit ADC with 8 input channels (6 only on ST72334Jx, not available on ST72124J2) Instruction Set – 8-bit data manipulation – 63 basic instructions – 17 main addressing modes – 8 x 8 unsigned multiply instruction – True bit manipulation Development Tools – Full hardware/software development package s s Device Summary ST72124J2 ST72314J2 ST72314J4 ST72314N2 ST72314N4 ST72334J2 ST72334J4 ST72334N2 ST72334N4 8K 384 (256) 8K 384 (256) 16K 512 (256) 8K 16K 384 (256) 512 (256) 256 256 Watchdog, Two 16-bit Timers, SPI, SCI ADC 3.2V to 5.5V Up to 8 MHz (with up to 16 MHz oscillator) -40°C to +85°C (-40°C to +105/125°C optional) TQFP64 / SDIP56 TQFP44 / SDIP42 - Program memory - bytes RAM (stack) - bytes EEPROM - bytes Peripherals Operating Supply CPU Frequency Operating Temperature Packages 8K 384 (256) 16K 512 (256) 8K 384 (256) 256 16K 512 (256) 256 TQFP44 / SDIP42 TQFP64 / SDIP56 Rev. 2.5 April 2003 1/153 1 Table of Contents 1 PREAMBLE: ST72C334 VERSUS ST72E331 SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 5 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2 5.3 5.4 5.5 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 STRUCTURAL ORGANISATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 IN-SITU PROGRAMMING (ISP) MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 MEMORY READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 DATA EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.2 6.3 6.4 6.5 6.6 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 MEMORY ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ACCESS ERROR HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7 DATA EEPROM Register Map and Reset Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.1 READ-OUT PROTECTION OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.2 8.3 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9.1 LOW VOLTAGE DETECTOR (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.2 9.3 9.4 9.5 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 CLOCK SECURITY SYSTEM (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 SUPPLY, RESET AND CLOCK REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . 32 10 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.1 NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.2 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.3 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 11 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 11.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 11.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 11.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11.4 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 12 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 153 12.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2/153 2 Table of Contents 12.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 12.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 13 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 13.1 I/O PORT INTERRUPT SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 13.2 I/O PORT ALTERNATE FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 13.3 REGISTERS DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 14 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 14.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 14.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (MCC/RTC) . . . . . . . 52 14.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 14.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 14.5 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 14.6 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 15 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 15.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 15.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 16 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 16.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 16.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 16.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 16.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 16.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 16.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 16.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 16.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 16.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 16.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 16.11 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 135 16.12 8-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 17 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 17.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 17.2 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 18 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 144 18.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 18.2 TRANSFER OF CUSTOMER CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 18.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 18.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 19 IMPORTANT NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 19.1 SCI BAUD RATE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 20 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 3/153 3 ST72334J/N, ST72314J/N, ST72124J To obtain the most recent version of this datasheet, please check at www.st.com>products>technical literature>datasheet. Please also pay special attention to the Section “IMPORTANT NOTES” on page 151 4/153 ST72334J/N, ST72314J/N, ST72124J 1 PREAMBLE: ST72C334 VERSUS ST72E331 SPECIFICATION New Features available on the ST72C334 s8 or 16K FLASH/ROM with In-Situ Programming and Read-out protection s New ADC with a better accuracy and conversion time s New configurable Clock, Reset and Supply system s New power saving mode with real time base: Active Halt s Beep capability on PF1 s New interrupt source: Clock security system (CSS) or Main clock controller (MCC) ST72C334 I/O Configuration and Pinout s Same pinout as ST72E331 s PA6 and PA7 are true open drain I/O ports without pull-up (same as ST72E331) s PA3, PB3, PB4 and PF2 have no pull-up configuration (all I/Os present on TQFP44) s PA5:4, PC3:2, PE7:4 and PF7:6 have high sink capabilities (20mA on N-buffer, 2mA on P-buffer and pull-up). On the ST72E331, all these pads (except PA5:4) were 2mA push-pull pads without high sink capabilities. PA4 and PA5 were 20mA true open drains. New Memory Locations in ST72C334 s 20h: MISCR register becomes MISCR1 register (naming change) s 29h: new control/status register for the MCC module s 2Bh: new control/status register for the Clock, Reset and Supply control. This register replaces the WDGSR register keeping the WDOGF flag compatibility. s 40h: new MISCR2 register 5/153 ST72334J/N, ST72314J/N, ST72124J 2 INTRODUCTION The ST72334J/N, ST72314J/N and ST72124J devices are members of the ST7 microcontroller family. They can be grouped as follows: – ST72334J/N devices are designed for mid-range applications with Data EEPROM, ADC, SPI and SCI interface capabilities. – ST72314J/N devices target the same range of applications but without Data EEPROM. – ST72124J devices are for applications that do not need Data EEPROM and the ADC peripheral. All devices are based on a common industrystandard 8-bit core, featuring an enhanced instruction set. The ST72C334J/N, ST72C314J/N and ST72C124J versions feature single-voltage FLASH memory with byte-by-byte In-Situ Programming (ISP) capability. Under software control, all devices can be placed in WAIT, SLOW, ACTIVE-HALT or HALT mode, reducing power consumption when the application is in idle or standby state. The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes. For easy reference, all parametric data are located in Section 16 on page 107. Figure 1. General Block Diagram 8-BIT CORE ALU RESET ISPSEL VDD VSS OSC1 OSC2 CONTROL PROGRAM MEMORY (8K or 16K Bytes) RAM (384 or 512 Bytes) LVD MULTI OSC + CLOCK FILTER ADDRESS AND DATA BUS MCC/RTC EEPROM (256 Bytes) PORT A PORT B PORT C TIMER B SPI PORT D 8-BIT ADC PORT F PF7,6,4,2:0 (6-BIT) TIMER A BEEP PORT E PE7:0 (6-BIT for N versions) (2-BIT for J versions) SCI PA7:0 (8-BIT for N versions) (5-BIT for J versions) PB7:0 (8-BIT for N versions) (5-BIT for J versions) PC7:0 (8-BIT) WATCHDOG PD7:0 (8-BIT for N versions) (6-BIT for J versions) VDDA VSSA 6/153 ST72334J/N, ST72314J/N, ST72124J 3 PIN DESCRIPTION Figure 2. 64-Pin TQFP Package Pinout (N versions) (HS) PE4 (HS) PE5 (HS) PE6 (HS) PE7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 AIN0 / PD0 AIN1 / PD1 AIN2 / PD2 AIN3 / PD3 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 NC NC PE1 / RDI PE0 / TDO VDD_2 OSC1 OSC2 VSS_2 NC NC RESET ISPSEL PA7 (HS) PA6 (HS) PA5 (HS) PA4 (HS) 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 ei0 44 43 ei2 42 41 40 39 ei3 38 37 36 35 ei1 34 33 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VSS_1 VDD_1 PA3 PA2 PA1 PA0 PC7 / SS PC6 / SCK / ISPCLK PC5 / MOSI PC4 / MISO / ISPDATA PC3 (HS) / ICAP1_B PC2 (HS) / ICAP2_B PC1 / OCMP1_B PC0 / OCMP2_B VSS_0 VDD_0 AIN4 / PD4 AIN5 / PD5 AIN6 / PD6 AIN7 / PD7 VDDA VSSA VDD_3 VSS_3 MCO / PF0 BEEP / PF1 PF2 NC OCMP1_A / PF4 NC ICAP1_A / (HS) PF6 EXTCLK_A / (HS) PF7 (HS) 20mA high sink capability eix associated external interrupt vector 7/153 ST72334J/N, ST72314J/N, ST72124J PIN DESCRIPTION (Cont’d) Figure 3. 56-Pin SDIP Package Pinout (N versions) PB4 PB5 PB6 PB7 AIN0 / PD0 AIN1 / PD1 AIN2 / PD2 AIN3 / PD3 AIN4 / PD4 AIN5 / PD5 AIN6 / PD6 AIN7 / PD7 VDDA VSSA MCO / PF0 BEEP / PF1 PF2 OCMP1_A / PF4 ICAP1_A / (HS) PF6 EXTCLK_A / (HS) PF7 VDD_0 VSS_0 OCMP2_B / PC0 OCMP1_B / PC1 ICAP2_B / (HS) PC2 ICAP1_B / (HS) PC3 ISPDATA/ MISO / PC4 MOSI / PC5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ei3 ei2 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 PB3 PB2 PB1 PB0 PE7 (HS) PE6 (HS) PE5 (HS) PE4 (HS) PE1 / RDI PE0 / TDO VDD_2 OSC1 OSC2 VSS_2 RESET ISPSEL PA7 (HS) PA6 (HS)I PA5 (HS) PA4 (HS) VSS_1 VDD_1 PA3 PA2 PA1 PA0 PC7 / SS PC6 / SCK / ISPCLK (HS) 20mA high sink capability eix associated external interrupt vector ei1 ei0 8/153 ST72334J/N, ST72314J/N, ST72124J PIN DESCRIPTION (Cont’d) Figure 4. 44-Pin TQFP and 42-Pin SDIP Package Pinouts (J versions) PE1 / RDI PB0 PB1 PB2 PB3 PB4 AIN0 / PD0 AIN1 / PD1 AIN2 / PD2 AIN3 / PD3 AIN4 / PD4 44 43 42 41 40 39 38 37 36 35 34 1 33 2 32 3 31 ei0 ei2 4 30 5 29 ei3 6 28 7 27 8 26 9 25 ei1 10 24 11 23 12 13 14 15 16 17 18 19 20 21 22 AIN5 / PD5 VDDA VSSA MCO / PF0 BEEP / PF1 PF2 OCMP1_A / PF4 ICAP1_A / (HS) PF6 EXTCLK_A / (HS) PF7 VDD_0 VSS_0 PE0 / TDO VDD_2 OSC1 OSC2 VSS_2 RESET ISPSEL PA7 (HS) PA6 (HS) PA5 (HS) PA4 (HS) VSS_1 VDD_1 PA3 PC7 / SS PC6 / SCK / ISPCLK PC5 / MOSI PC4 / MISO / ISPDATA PC3 (HS) / ICAP1_B PC2 (HS) / ICAP2_B PC1 / OCMP1_B PC0 / OCMP2_B PB4 AIN0 / PD0 AIN1 / PD1 AIN2 / PD2 AIN3 / PD3 AIN4 / PD4 AIN5 / PD5 VDDA VSSA MCO / PF0 BEEP / PF1 PF2 OCMP1_A / PF4 ICAP1_A / (HS) PF6 EXTCLK_A / (HS) PF7 OCMP2_B / PC0 OCMP1_B / PC1 ICAP2_B/ (HS) PC2 ICAP1_B / (HS) PC3 ISPDATA / MISO / PC4 MOSI / PC5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 EI3 ei2 42 41 40 39 38 37 36 35 34 33 PB3 PB2 PB1 PB0 PE1 / RDI PE0 / TDO VDD_2 OSC1 OSC2 VSS_2 RESET ISPSEL PA7 (HS) PA6 (HS) PA5 (HS) PA4 (HS) VSS_1 VDD_1 PA3 PC7 / SS PC6 / SCK / ISPCLK (HS) 20mA high sink capability eix associated external interrupt vector ei1 32 31 30 29 28 27 26 ei0 25 24 23 22 9/153 ST72334J/N, ST72314J/N, ST72124J PIN DESCRIPTION (Cont’d) For external pin connection guidelines, refer to Section 16 "ELECTRICAL CHARACTERISTICS" on page 107. Legend / Abbreviations for Table 1: Type: I = input, O = output, S = supply Input level: A = Dedicated analog input In/Output level: C = CMOS 0.3VDD/0.7VDD, CT= CMOS 0.3VDD/0.7VDD with input trigger Output level: HS = 20mA high sink (on N-buffer only) Port and control configuration: – Input: float = floating, wpu = weak pull-up, int = interrupt 1), ana = analog – Output: OD = open drain 2), PP = push-pull Refer to Section 12 "I/O PORTS" on page 39 for more details on the software configuration of the I/O ports. The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is in reset state. Table 1. Device Pin Description Pin n° TQFP64 Type SDIP56 QFP44 SDIP42 Pin Name Level Output Input float wpu Port Input ana int Main Output function (after reset) OD X X X X X X X X X X X X X X X X X X X X X X X X X X X X PP X X X X X X X X X X X X X X X X X X X X Port E4 Port E5 Port E6 Port E7 Port B0 Port B1 Port B2 Port B3 Port B4 Port B5 Port B6 Port B7 Port D0 ADC Analog Input 0 Port D1 ADC Analog Input 1 Port D2 ADC Analog Input 2 Port D3 ADC Analog Input 3 Port D4 ADC Analog Input 4 Port D5 ADC Analog Input 5 Port D6 ADC Analog Input 6 Port D7 ADC Analog Input 7 Analog Power Supply Voltage Analog Ground Voltage Digital Main Supply Voltage Alternate function 1 49 2 50 3 51 4 52 PE4 (HS) PE5 (HS) PE6 (HS) PE7 (HS) I/O CT HS I/O CT HS I/O CT HS I/O CT HS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O S S S CT CT CT CT CT CT CT CT CT CT CT CT CT CT CT CT X X X X X X X X X X X X X X X X X X X X X X X X ei2 ei2 ei2 ei2 ei3 ei3 ei3 ei3 X X X X X X X X 5 53 2 39 PB0 6 54 3 40 PB1 7 55 4 41 PB2 8 56 5 42 PB3 9 1 6 1 PB4 10 2 11 3 12 4 PB5 PB6 PB7 13 5 7 2 PD0/AIN0 14 6 8 3 PD1/AIN1 15 7 9 4 PD2/AIN2 16 8 10 5 PD3/AIN3 17 9 11 6 PD4/AIN4 18 10 12 7 PD5/AIN5 19 11 20 12 PD6/AIN6 PD7/AIN7 21 13 13 8 VDDA 22 14 14 9 VSSA 23 VDD_3 10/153 ST72334J/N, ST72314J/N, ST72124J Pin n° TQFP64 Type SDIP56 QFP44 SDIP42 Pin Name Level Output Input float wpu Port Input ana int OD Main Output function (after reset) PP Alternate function 24 VSS_3 S I/O I/O I/O I/O CT CT CT CT X X X X X X X X X ei1 ei1 ei1 X X X X X X X X X X X X Digital Ground Voltage Port F0 Port F1 Port F2 Port F4 Port F6 Port F7 Timer A Output Compare 1 Timer A Input Capture 1 Timer A External Clock Source Main clock output (fOSC/2) Beep signal output 25 15 15 10 PF0/MCO 26 16 16 11 PF1/BEEP 27 17 17 12 PF2 28 30 NC NC 29 18 18 13 PF4/OCMP1_A 31 19 19 14 PF6 (HS)/ICAP1_A 33 21 21 34 22 22 VDD_0 VSS_0 Not Connected Not Connected I/O CT HS S S I/O I/O CT CT X X X X X X X X X X X X X X X X X X X X ei0 ei0 ei0 ei0 X X X X X X X X X X X X X X X X X X X X X X X X 32 20 20 15 PF7 (HS)/EXTCLK_A I/O CT HS Digital Main Supply Voltage Digital Ground Voltage Port C0 Timer B Output Compare 2 Port C1 Timer B Output Compare 1 Port C2 Timer B Input Capture 2 Port C3 Timer B Input Capture 1 Port C4 SPI Master In / Slave Out Data Port C5 SPI Master Out / Slave In Data Port C6 SPI Serial Clock Port C7 SPI Slave Select (active low) Port A0 Port A1 Port A2 Port A3 Digital Main Supply Voltage Digital Ground Voltage X X X X X X X X T T X X Port A4 Port A5 Port A6 Port A7 Must be tied low in user mode. In programming mode when available, this pin acts as In-Situ Programming mode selection. C X X Top priority non maskable interrupt (active low) 35 23 23 16 PC0/OCMP2_B 36 24 24 17 PC1/OCMP1_B 37 25 25 18 PC2 (HS)/ICAP2_B 38 26 26 19 PC3 (HS)/ICAP1_B 39 27 27 20 PC4/MISO 40 28 28 21 PC5/MOSI 41 29 29 22 PC6/SCK 42 30 30 23 PC7/SS 43 31 44 32 45 33 PA0 PA1 PA2 I/O CT HS I/O CT HS I/O I/O I/O I/O I/O I/O I/O I/O S S I/O CT HS I/O CT HS I/O CT HS I/O CT HS I CT CT CT CT CT CT CT CT 46 34 31 24 PA3 47 35 32 25 VDD_1 48 36 33 26 VSS_1 49 37 34 27 PA4 (HS) 50 38 35 28 PA5 (HS) 51 39 36 29 PA6 (HS) 52 40 37 30 PA7 (HS) 53 41 38 31 ISPSEL 54 42 39 32 RESET 55 56 NC NC I/O Not Connected S O Digital Ground Voltage Resonator oscillator inverter output or capacitor input for RC oscillator 57 43 40 33 VSS_3 58 44 41 34 OSC2 3) 11/153 ST72334J/N, ST72314J/N, ST72124J Pin n° TQFP64 Type SDIP56 QFP44 SDIP42 Pin Name Level Output Input float wpu Port Input ana int OD Main Output function (after reset) PP Alternate function 59 45 42 35 OSC1 3) 60 46 43 36 VDD_3 61 47 44 37 PE0/TDO 62 48 1 38 PE1/RDI 63 64 NC NC I S I/O I/O CT CT X X X X X X X X External clock input or Resonator oscillator inverter input or resistor input for RC oscillator Digital Main Supply Voltage Port E0 Port E1 SCI Transmit Data Out SCI Receive Data In Not Connected Notes: 1. In the interrupt input column, “eix” defines the associated external interrupt vector. If the weak pull-up column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input. 2. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to VDD are not implemented). See Section 12 "I/O PORTS" on page 39 and Section 16.8 "I/O PORT PIN CHARACTERISTICS" on page 128 for more details. 3. OSC1 and OSC2 pins connect a crystal or ceramic resonator, an external RC, or an external source to the on-chip oscillator see Section 3 "PIN DESCRIPTION" on page 7 and Section 16.5 "CLOCK AND TIMING CHARACTERISTICS" on page 116 for more details. 12/153 ST72334J/N, ST72314J/N, ST72124J 4 REGISTER & MEMORY MAP As shown in the Figure 5, the MCU is capable of addressing 64K bytes of memories and I/O registers. The available memory locations consist of 128 bytes of register locations, 384 or 512 bytes of RAM, up to 256 bytes of data EEPROM and 4 or 8 Kbytes of user program memory. The RAM space includes up to 256 bytes for the stack from 0100h to 01FFh. The highest address bytes contain the user reset and interrupt vectors. IMPORTANT: Memory locations marked as “Reserved” must never be accessed. Accessing a reserved area can have unpredictable effects on the device. Figure 5. Memory Map 0000h 0080h HW Registers (see Table 2) 007Fh 0080h 00FFh 0100h Short Addressing RAM Zero page (128 Bytes) Stack or 16-bit Addressing RAM (256 Bytes) 384 Bytes RAM 01FFh 027Fh 0200h / 0280h 01FFh 512 Bytes RAM 0080h Reserved 0BFFh 0C00h 0CFFh 0D00h BFFFh C000h E000h FFDFh FFE0h FFFFh 00FFh 0100h Short Addressing RAM Zero page (128 Bytes) 256 Bytes Data EEPROM Reserved 16K Bytes Program Memory Stack or 16-bit Addressing RAM (256 Bytes) 01FFh 0200h 027Fh 16-bit Addressing RAM 8K Bytes Program Memory C000h 16 KBytes E000h FFFFh Interrupt & Reset Vectors (see Table 5 on page 34) 8 KBytes 13/153 ST72334J/N, ST72314J/N, ST72124J REGISTER & MEMORY MAP (Cont’d) Table 2. Hardware Register Map Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h to 001Fh 0020h 0021h 0022h 0023h 0024h to 0028h 0029h MCC MCCSR MISCR1 SPIDR SPICR SPISR PFDR PFDDR PFOR PDDR PDDDR PDOR PEDR PEDDR PEOR PBDR PBDDR PBOR PCDR PCDDR PCOR Block Register Label PADR PADDR PAOR Register Name Port A Data Register Port A Data Direction Register Port A Option Register Reserved Area (1 Byte) Port C Data Register Port C Data Direction Register Port C Option Register Reserved Area (1 Byte) Port B Data Register Port B Data Direction Register Port B Option Register Reserved Area (1 Byte) Port E Data Register Port E Data Direction Register Port E Option Register Reserved Area (1 Byte) Port D Data Register Port D Data Direction Register Port D Option Register Reserved Area (1 Byte) Port F Data Register Port F Data Direction Register Port F Option Register 00h1) 00h 00h R/W R/W R/W 00h1) 00h 00h R/W R/W R/W 2) 00h1) 00h 00h R/W R/W R/W 2) 00h1) 00h 00h R/W R/W R/W 2) 00h1) 00h 00h R/W R/W R/W Reset Status 00h1) 00h 00h Remarks R/W R/W R/W 2) Port A Port C Port B Port E Port D Port F Reserved Area (9 Bytes) Miscellaneous Register 1 SPI Data I/O Register SPI Control Register SPI Status Register 00h xxh 0xh 00h R/W R/W R/W Read Only SPI Reserved Area (5 Bytes) Main Clock Control / Status Register 01h R/W 14/153 ST72334J/N, ST72314J/N, ST72124J Address 002Ah 002Bh 002Ch 002Dh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h Block WATCHDOG Register Label WDGCR CRSR Register Name Watchdog Control Register Reset Status 7Fh Remarks R/W R/W R/W Clock, Reset, Supply Control / Status Register 000x 000x Data-EEPROM Control/Status Register Reserved Area (4 Bytes) 00h Data-EEPROM EECSR TIMER A TACR2 TACR1 TASR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR MISCR2 TBCR2 TBCR1 TBSR TBIC1HR TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2HR TBIC2LR TBOC2HR TBOC2LR SCISR SCIDR SCIBRR SCICR1 SCICR2 SCIERPR SCIETPR Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer A Control Register 2 A Control Register 1 A Status Register A Input Capture 1 High Register A Input Capture 1 Low Register A Output Compare 1 High Register A Output Compare 1 Low Register A Counter High Register A Counter Low Register A Alternate Counter High Register A Alternate Counter Low Register A Input Capture 2 High Register A Input Capture 2 Low Register A Output Compare 2 High Register A Output Compare 2 Low Register 00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h 00h 00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h C0h xxh 00xx xxxx xxh 00h 00h --00h R/W R/W Read Only Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only 3) Read Only 3) R/W 3) R/W 3) R/W R/W R/W Read Only Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W Read Only R/W R/W R/W R/W R/W R/W Miscellaneous Register 2 Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer B Control Register 2 B Control Register 1 B Status Register B Input Capture 1 High Register B Input Capture 1 Low Register B Output Compare 1 High Register B Output Compare 1 Low Register B Counter High Register B Counter Low Register B Alternate Counter High Register B Alternate Counter Low Register B Input Capture 2 High Register B Input Capture 2 Low Register B Output Compare 2 High Register B Output Compare 2 Low Register TIMER B SCI SCI Status Register SCI Data Register SCI Baud Rate Register SCI Control Register 1 SCI Control Register 2 SCI Extended Receive Prescaler Register Reserved area SCI Extended Transmit Prescaler Register 15/153 ST72334J/N, ST72314J/N, ST72124J Address 0058h 006Fh 0070h 0071h 0072h to 007Fh Block Register Label Register Name Reset Status Remarks Reserved Area (24 Bytes) ADCDR ADCCSR Data Register Control/Status Register xxh 00h Read Only R/W ADC Reserved Area (14 Bytes) Legend: x=undefined, R/W=read/write Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents. 2. The bits corresponding to unavailable pins are forced to 1 by hardware, affecting accordingly the reset status value. These bits must always keep their reset value. 3. External pin not available. 16/153 ST72334J/N, ST72314J/N, ST72124J 5 FLASH PROGRAM MEMORY 5.1 INTRODUCTION FLASH devices have a single voltage non-volatile FLASH memory that may be programmed in-situ (or plugged in a programming tool) on a byte-bybyte basis. 5.2 MAIN FEATURES s s s s Remote In-Situ Programming (ISP) mode Up to 16 bytes programmed in the same cycle MTP memory (Multiple Time Programmable) Read-out memory protection against piracy 5.3 STRUCTURAL ORGANISATION The FLASH program memory is organised in a single 8-bit wide memory block which can be used for storing both code and data constants. The FLASH program memory is mapped in the upper part of the ST7 addressing space and includes the reset and interrupt user vector area . 5.4 IN-SITU PROGRAMMING (ISP) MODE The FLASH program memory can be programmed using Remote ISP mode. This ISP mode allows the contents of the ST7 program memory to be updated using a standard ST7 programming tools after the device is mounted on the application board. This feature can be implemented with a minimum number of added components and board area impact. An example Remote ISP hardware interface to the standard ST7 programming tool is described below. For more details on ISP programming, refer to the ST7 Programming Specification. Remote ISP Overview The Remote ISP mode is initiated by a specific sequence on the dedicated ISPSEL pin. The Remote ISP is performed in three steps: – Selection of the RAM execution mode – Download of Remote ISP code in RAM – Execution of Remote ISP code in RAM to program the user program into the FLASH Remote ISP hardware configuration In Remote ISP mode, the ST7 has to be supplied with power (VDD and VSS) and a clock signal (oscillator and application crystal circuit for example). This mode needs five signals (plus the VDD signal if necessary) to be connected to the programming tool. This signals are: – RESET: device reset – VSS: device ground power supply – ISPCLK: ISP output serial clock pin – ISPDATA: ISP input serial data pin – ISPSEL: Remote ISP mode selection. This pin must be connected to VSS on the application board through a pull-down resistor. If any of these pins are used for other purposes on the application, a serial resistor has to be implemented to avoid a conflict if the other device forces the signal level. Figure 6 shows a typical hardware interface to a standard ST7 programming tool. For more details on the pin locations, refer to the device pinout description. Figure 6. Typical Remote ISP Interface XTAL HE10 CONNECTOR TYPE TO PROGRAMMING TOOL 1 CL0 CL1 OSC2 OSC1 VDD ISPSEL 10K Ω VSS RESET ST7 ISPCLK ISPDATA 47KΩ APPLICATION 5.5 MEMORY READ-OUT PROTECTION The read-out protection is enabled through an option bit. For FLASH devices, when this option is selected, the program and data stored in the FLASH memory are protected against read-out piracy (including a re-write protection). When this protection option is removed the entire FLASH program memory is first automatically erased. However, the E2PROM data memory (when available) can be protected only with ROM devices. 17/153 ST72334J/N, ST72314J/N, ST72124J 6 DATA EEPROM 6.1 INTRODUCTION The Electrically Erasable Programmable Read Only Memory can be used as a non volatile backup for storing data. Using the EEPROM requires a basic access protocol described in this chapter. 6.2 MAIN FEATURES s s s s s s Up to 16 Bytes programmed in the same cycle EEPROM mono-voltage (charge pump) Chained erase and programming cycles Internal control of the global programming cycle duration End of programming cycle interrupt flag WAIT mode management Figure 7. EEPROM Block Diagram EEPROM INTERRUPT FALLING EDGE DETECTOR HIGH VOLTAGE PUMP RESERVED EEPROM 0 IE LAT PGM EECSR 0 0 0 0 ADDRESS DECODER 4 ROW DECODER EEPROM MEMORY MATRIX (1 ROW = 16 x 8 BITS) 128 DATA MULTIPLEXER 4 128 16 x 8 BITS DATA LATCHES 4 ADDRESS BUS DATA BUS 18/153 ST72334J/N, ST72314J/N, ST72124J DATA EEPROM (Cont’d) 6.3 MEMORY ACCESS The Data EEPROM memory read/write access modes are controlled by the LAT bit of the EEPROM Control/Status register (EECSR). The flowchart in Figure 8 describes these different memory access modes. Read Operation (LAT=0) The EEPROM can be read as a normal ROM location when the LAT bit of the EECSR register is cleared. In a read cycle, the byte to be accessed is put on the data bus in less than 1 CPU clock cycle. This means that reading data from EEPROM takes the same time as reading data from EPROM, but this memory cannot be used to execute machine code. Write Operation (LAT=1) To access the write mode, the LAT bit has to be set by software (the PGM bit remains cleared). When a write access to the EEPROM area occurs, the value is latched inside the 16 data latches according to its address. Figure 8. Data EEPROM Programming Flowchart When PGM bit is set by the software, all the previous bytes written in the data latches (up to 16) are programmed in the EEPROM cells. The effective high address (row) is determined by the last EEPROM write sequence. To avoid wrong programming, the user must take care that all the bytes written between two programming sequences have the same high address: only the four Least Significant Bits of the address can change. At the end of the programming cycle, the PGM and LAT bits are cleared simultaneously, and an interrupt is generated if the IE bit is set. The Data EEPROM interrupt request is cleared by hardware when the Data EEPROM interrupt vector is fetched. Note: Care should be taken during the programming cycle. Writing to the same memory location will over-program the memory (logical AND between the two write access data result) because the data latches are only cleared at the end of the programming cycle and by the falling edge of LAT bit. It is not possible to read the latched data. This note is ilustrated by the Figure 9. READ MODE LAT=0 PGM=0 WRITE MODE LAT=1 PGM=0 READ BYTES IN EEPROM AREA WRITE UP TO 16 BYTES IN EEPROM AREA (with the same 11 MSB of the address) START PROGRAMMING CYCLE LAT=1 PGM=1 (set by software) INTERRUPT GENERATION IF IE=1 CLEARED BY HARDWARE 0 LAT 1 19/153 ST72334J/N, ST72314J/N, ST72124J DATA EEPROM (Cont’d) 6.4 POWER SAVING MODES Wait mode The DATA EEPROM can enter WAIT mode on execution of the WFI instruction of the microcontroller. The DATA EEPROM will immediately enter this mode if there is no programming in progress, otherwise the DATA EEPROM will finish the cycle and then enter WAIT mode. Halt mode The DATA EEPROM immediatly enters HALT mode if the microcontroller executes the HALT instruction. Therefore the EEPROM will stop the function in progress, and data may be corrupted. Figure 9. Data EEPROM Programming Cycle READ OPERATION NOT POSSIBLE INTERNAL PROGRAMMING VOLTAGE ERASE CYCLE WRITE OF DATA LATCHES WRITE CYCLE READ OPERATION POSSIBLE 6.5 ACCESS ERROR HANDLING If a read access occurs while LAT=1, then the data bus will not be driven. If a write access occurs while LAT=0, then the data on the bus will not be latched. If a programming cycle is interrupted (by software/ RESET action), the memory data will not be guaranteed. tPROG LAT PGM EEPROM INTERRUPT 20/153 ST72334J/N, ST72314J/N, ST72124J DATA EEPROM (Cont’d) 6.6 REGISTER DESCRIPTION CONTROL/STATUS REGISTER (CSR) Read /Write Reset Value: 0000 0000 (00h) 7 0 0 0 0 0 IE LAT 0 PGM Bit 1 = LAT Latch Access Transfer This bit is set by software. It is cleared by hardware at the end of the programming cycle. It can only be cleared by software if PGM bit is cleared. 0: Read mode 1: Write mode Bit 0 = PGM Programming control and status This bit is set by software to begin the programming cycle. At the end of the programming cycle, this bit is cleared by hardware and an interrupt is generated if the ITE bit is set. 0: Programming finished or not yet started 1: Programming cycle is in progress Note: if the PGM bit is cleared during the programming cycle, the memory data is not guaranteed Bit 7:3 = Reserved, forced by hardware to 0. Bit 2 = IE Interrupt enable This bit is set and cleared by software. It enables the Data EEPROM interrupt capability when the PGM bit is cleared by hardware. The interrupt request is automatically cleared when the software enters the interrupt routine. 0: Interrupt disabled 1: Interrupt enabled 21/153 ST72334J/N, ST72314J/N, ST72124J 7 DATA EEPROM Register Map and Reset Values Address (Hex.) 002Ch Register Label EECSR Reset Value 0 0 0 0 0 7 6 5 4 3 2 IE 0 1 RWM 0 0 PGM 0 7.1 READ-OUT PROTECTION OPTION The Data EEPROM can be optionally read-out protected in ST72334 ROM devices (see option list on page 146). ST72C334 Flash devices do not have this protection option. 22/153 ST72334J/N, ST72314J/N, ST72124J 8 CENTRAL PROCESSING UNIT 8.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 8.2 MAIN FEATURES s s s s s s s s 63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes Two 8-bit index registers 16-bit stack pointer Low power modes Maskable hardware interrupts Non-maskable software interrupt 8.3 CPU REGISTERS The 6 CPU registers shown in Figure 10 are not present in the memory mapping and are accessed by specific instructions. Figure 10. CPU Registers 7 RESET VALUE = XXh 7 RESET VALUE = XXh 7 RESET VALUE = XXh 15 PCH 87 PCL 0 0 0 0 Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. Index Registers (X and Y) In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.) The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack). Program Counter (PC) The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB). ACCUMULATOR X INDEX REGISTER Y INDEX REGISTER PROGRAM COUNTER RESET VALUE = RESET VECTOR @ FFFEh-FFFFh 7 111HI 0 NZC CONDITION CODE REGISTER RESET VALUE = 1 1 1 X 1 X X X 15 87 0 STACK POINTER RESET VALUE = STACK HIGHER ADDRESS X = Undefined Value 23/153 ST72334J/N, ST72314J/N, ST72124J CPU REGISTERS (Cont’d) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx 7 1 1 1 H I N Z 0 C The 8-bit Condition Code register contains the interrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions. These bits can be individually tested and/or controlled by specific instructions. Bit 4 = H Half carry. This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines. Bit 3 = I Interrupt mask. This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software. 0: Interrupts are enabled. 1: Interrupts are disabled. This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions. Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptable because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine. Bit 2 = N N egative. This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7th bit of the result. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (i.e. the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instructions. Bit 1 = Z Zero. This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions. Bit 0 = C C arry/borrow. This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions. 24/153 ST72334J/N, ST72314J/N, ST72124J CENTRAL PROCESSING UNIT (Cont’d) Stack Pointer (SP) Read/Write Reset Value: 01 FFh 15 0 7 SP7 SP6 SP5 SP4 SP3 SP2 SP1 0 0 0 0 0 0 8 1 0 SP0 The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 11). Since the stack is 256 bytes deep, the 8th most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address. Figure 11. Stack Manipulation Example CALL Subroutine @ 0100h Interrupt Event PUSH Y The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction. Note: W hen the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow. The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 11. – When an interrupt is received, the SP is decremented and the context is pushed on the stack. – On return from interrupt, the SP is incremented and the context is popped from the stack. A subroutine call occupies two locations and an interrupt five locations in the stack area. POP Y IRET RET or RSP SP SP CC A X PCH SP PCH @ 01FFh PCL PCL PCH PCL Y CC A X PCH PCL PCH PCL SP CC A X PCH PCL PCH PCL SP PCH PCL SP Stack Higher Address = 01FFh Stack Lower Address = 0100h 25/153 ST72334J/N, ST72314J/N, ST72124J 9 SUPPLY, RESET AND CLOCK MANAGEMENT The ST72334J/N, ST72314J/N and ST72124J microcontrollers include a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. An overview is shown in Figure 12. See Section 16 "ELECTRICAL CHARACTERISTICS" on page 107 for more details. Main Features s Supply Manager with main supply low voltage detection (LVD) s Reset Sequence Manager (RSM) Figure 12. Clock, Reset and Supply Block Diagram s s Multi-Oscillator (MO) – 4 Crystal/Ceramic resonator oscillators – 1 External RC oscillator – 1 Internal RC oscillator Clock Security System (CSS) – Clock Filter – Backup Safe Oscillator CLOCK SECURITY SYSTEM (CSS) OSC2 OSC1 MULTIOSCILLATOR (MO) FILTER OSC CLOCK SAFE fOSC TO MAIN CLOCK CONTROLLER RESET SEQUENCE RESET MANAGER (RSM) FROM WATCHDOG PERIPHERAL VDD VSS LOW VOLTAGE DETECTOR (LVD) CRSR 0 0 0 LVD RF 0 IE CSS D WDG RF CSS INTERRUPT 26/153 ST72334J/N, ST72314J/N, ST72124J 9.1 LOW VOLTAGE DETECTOR (LVD) To allow the integration of power management features in the application, the Low Voltage Detector function (LVD) generates a static reset when the VDD supply voltage is below a VIT- reference value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset. The VIT- reference value for a voltage drop is lower than the VIT+ reference value for power-on in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis). The LVD Reset circuitry generates a reset when VDD is below: – VIT+ when VDD is rising – VIT- when VDD is falling The LVD function is illustrated in the Figure 13. Provided the minimum VDD value (guaranteed for the oscillator frequency) is above VIT-, the MCU can only be in two modes: – under full software control – in static safe reset Figure 13. Low Voltage Detector vs Reset VDD In these conditions, secure operation is always ensured for the application without the need for external reset hardware. During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU to reset other devices. Notes: 1. The LVD allows the device to be used without any external RESET circuitry. 2. Three different reference levels are selectable through the option byte according to the application requirement. LVD application note Application software can detect a reset caused by the LVD by reading the LVDRF bit in the CRSR register. This bit is set by hardware when a LVD reset is generated and cleared by software (writing zero). Vhyst VIT+ VIT- RESET 27/153 ST72334J/N, ST72314J/N, ST72124J 9.2 RESET SEQUENCE MANAGER (RSM) 9.2.1 Introduction The reset sequence manager includes three RESET sources as shown in Figure 15: s External RESET source pulse s Internal LVD RESET (Low Voltage Detection) s Internal WATCHDOG RESET These sources act on the RESET pin and it is always kept low during the delay phase. The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map. The basic RESET sequence consists of 3 phases as shown in Figure 14: s Delay depending on the RESET source s 4096 CPU clock cycle delay s RESET vector fetch Figure 15. Reset Block Diagram The 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state. The RESET vector fetch phase duration is 2 clock cycles. Figure 14. RESET Sequence Phases RESET DELAY INTERNAL RESET 4096 CLOCK CYCLES FETCH VECTOR VDD fCPU COUNTER INTERNAL RESET RON RESET WATCHDOG RESET LVD RESET 28/153 ST72334J/N, ST72314J/N, ST72124J RESET SEQUENCE MANAGER (Cont’d) 9.2.2 Asynchronous External RESET pin The RESET pin is both an input and an open-drain output with integrated RON weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See electrical characteristics section for more details. A RESET signal originating from an external source must have a duration of at least th(RSTL)in in order to be recognized. This detection is asynchronous and therefore the MCU can enter reset state even in HALT mode. The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section. Two RESET sequences can be associated with this RESET source: short or long external reset pulse (see Figure 16). Starting from the external RESET pulse recognition, the device RESET pin acts as an output that is pulled low during at least tw(RSTL)out. Figure 16. RESET Sequences VDD VIT+ VIT- 9.2.3 Internal Low Voltage Detection RESET Two different RESET sequences caused by the internal LVD circuitry can be distinguished: s Power-On RESET s Voltage Drop RESET The device RESET pin acts as an output that is pulled low when VDD jrf * Pop CC, A, X, PC inc X jp [TBL.w] reg, M H tst(Reg - M) A = FFH-A dec Y reg, M reg reg, M reg, M 0 I N N Z Z C M 0 N N N 1 Z Z Z C 1 Function/Example A=A+M+C A=A+M A=A.M tst (A . M) bres Byte, #3 bset Byte, #3 btjf Byte, #3, Jmp1 btjt Byte, #3, Jmp1 A A A A M M M M C C Dst M M M M Src H H H I N N N N N Z Z Z Z Z C C C 105/153 ST72334J/N, ST72314J/N, ST72124J INSTRUCTION GROUPS (Cont’d) Mnemo JRULE LD MUL NEG NOP OR POP Description Jump if (C + Z = 1) Load Multiply Negate (2's compl) No Operation OR operation Pop from the Stack A=A+M pop reg pop CC PUSH RCF RET RIM RLC RRC RSP SBC SCF SIM SLA SLL SRL SRA SUB SWAP TNZ TRAP WFI XOR Push onto the Stack Reset carry flag Subroutine Return Enable Interrupts Rotate left true C Rotate right true C Reset Stack Pointer Subtract with Carry Set carry flag Disable Interrupts Shift left Arithmetic Shift left Logic Shift right Logic Shift right Arithmetic Subtraction SWAP nibbles Test for Neg & Zero S/W trap Wait for Interrupt Exclusive OR A = A XOR M A M I=0 C C S = Max allowed A=A-M-C C=1 I=1 C C A=A-M reg, M reg, M reg, M reg, M A M 1 N N 0 N N N N 1 0 N Z Z Z Z Z Z Z Z C C C C C A M N Z C 1 reg, M reg, M 0 N N Z Z C C push Y C=0 A reg CC M M M M reg, CC 0 H I N Z C N Z Function/Example Unsigned 85°C fOSC [MHz] FUNCTIONALITY GUARANTEED IN THIS AREA 3) 16 FUNCTIONALITY NOT GUARANTEED IN THIS AREA 12 8 4 1 0 2.5 3.2 3.5 3.85 4 4.5 5 5.5 SUPPLY VOLTAGE [V] FUNCTIONALITY NOT GUARANTEED IN THIS AREA WITH RESONATOR 1) Notes: 1. Guaranteed by construction. A/D operation and resonator oscillator start-up are not guaranteed below 1MHz. 2. Operating conditions with TA=-40 to +125°C. 3. FLASH programming tested in production at maximum TA with two different conditions: VDD=5.5V, fCPU=6MHz and VDD=3.2V, fCPU=4MHz. 110/153 ST72334J/N, ST72314J/N, ST72124J OPERATING CONDITIONS (Cont’d) 16.3.2 Operating Conditions with Low Voltage Detector (LVD) Subject to general operating conditions for VDD, fOSC, and TA. Symbol VIT+ Parameter Reset release threshold (VDD rise) Conditions High Threshold Med. Threshold Low Threshold Min 4.10 3.75 2) 3.25 2) 3.852) 3.502) 3.00 200 0.2 Not detected by the LVD 2) Typ 1) 4.30 3.90 3.35 4.05 3.65 3.10 250 Max 4.50 4.05 3.55 4.30 3.95 3.35 300 50 40 Unit VITVhys VtPOR tg(VDD) High Threshold Reset generation threshold (VDD fall) Med. Threshold Low Threshold4) LVD voltage threshold hysteresis VDD rise time rate 3) Filtered glitch delay on VDD 2) VIT+-VIT- V mV V/ms ns Figure 57. High LVD Threshold Versus VDD and fOSC for FLASH devices 3) fOSC [MHz] DEVICE UNDER RESET IN THIS AREA 16 12 8 0 FUNCTIONALITY AND RESET NOT GUARANTEED IN THIS AREA FOR TEMPERATURES HIGHER THAN 85°C FUNCTIONALITY NOT GUARANTEED IN THIS AREA FUNCTIONAL AREA SUPPLY VOLTAGE [V] 4 4.5 5 5.5 2.5 Figure 58. Medium LVD Threshold Versus VDD and f OSC for FLASH devices 3) fOSC [MHz] DEVICE UNDER RESET IN THIS AREA 16 12 8 0 FUNCTIONALITY AND RESET NOT GUARANTEED IN THIS AREA FOR TEMPERATURES HIGHER THAN 85°C FUNCTIONALITY NOT GUARANTEED IN THIS AREA FUNCTIONAL AREA SUPPLY VOLTAGE [V] 4 4.5 5 5.5 2.5 Figure 59. Low LVD Threshold Versus VDD and fOSC for FLASH devices 2)4) fOSC [MHz] 16 12 DEVICE UNDER RESET IN THIS AREA 8 0 FUNCTIONALITY NOT GUARANTEED IN THIS AREA FOR TEMPERATURES HIGHER THAN 85°C FUNCTIONALITY NOT GUARANTEED IN THIS AREA 2.5 Notes: 1. LVD typical data are based on TA=25°C. They are given only as design guidelines and are not tested. 2. Data based on characterization results, not tested in production. 3. The VDD rise time rate condition is needed to insure a correct device power-on and LVD reset. Not tested in production. 4.If the low LVD threshold is selected, when VDD falls below 3.2V, (VDD minimum operating voltage), the device is guaranteed to continue functioning until it goes into reset state. The specified VDD min. value is necessary in the device power on phase, but during a power down phase or voltage drop the device will function below this min. level. 00000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3 3.5 VIT-≥3.85 0000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000 3 VIT-≥3.5V 000000000000000000000000000000000000000000000000000000000000000000000000 FUNCTIONAL AREA SEE NOTE 4 SUPPLY VOLTAGE [V] 3.5 4 4.5 5 5.5 VIT-≥3V 3.2 111/153 ST72334J/N, ST72314J/N, ST72124J FUNCTIONAL OPERATING CONDITIONS (Cont’d) Figure 60. High LVD Threshold Versus VDD and fOSC for ROM devices 2) fOSC [MHz] DEVICE UNDER RESET IN THIS AREA 16 8 0 FUNCTIONALITY NOT GUARANTEED IN THIS AREA 2.5 Figure 61. Medium LVD Threshold Versus VDD and f OSC for ROM devices 2) fOSC [MHz] DEVICE UNDER RESET IN THIS AREA 16 8 0 FUNCTIONALITY NOT GUARANTEED IN THIS AREA FUNCTIONAL AREA SUPPLY VOLTAGE [V] 4 4.5 5 5.5 2.5 Figure 62. Low LVD Threshold Versus VDD and fOSC for ROM devices 2)3) fOSC [MHz] 16 DEVICE UNDER RESET IN THIS AREA 8 0 FUNCTIONALITY NOT GUARANTEED IN THIS AREA FUNCTIONAL AREA SUPPLY VOLTAGE [V] 3.5 4 4.5 5 5.5 2.5 Notes: 1. LVD typical data are based on TA=25°C. They are given only as design guidelines and are not tested. 2. The minimum VDD rise time rate is needed to insure a correct device power-on and LVD reset. Not tested in production. 3. If the low LVD threshold is selected, when VDD falls below 3.2V, (VDD minimum operating voltage), the device is guaranteed to continue functioning until it goes into reset state. The specified VDD min. value is necessary in the device power on phase, but during a power down phase or voltage drop the device will function below this min. level. 112/153 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3 3.5 FUNCTIONAL AREA SUPPLY VOLTAGE [V] 4 4.5 5 5.5 VIT-≥3.85 0000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3 VIT-≥3.5V 000000000000000000000000000000000000000000000000 000000000000000000000000 VIT-≥3.00V ST72334J/N, ST72314J/N, ST72124J 16.4 SUPPLY CURRENT CHARACTERISTICS The following current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total deSymbol ∆IDD(∆Ta) Parameter Supply current variation vs. temperature vice consumption, the two current values must be added (except for HALT mode for which the clock is stopped). Conditions Constant VDD and fCPU Max 10 Unit % 16.4.1 RUN and SLOW Modes Symbol Parameter 4.5V≤VDD≤5.5V Supply current in RUN mode 3) (see Figure 63) Supply current in SLOW mode 4) (see Figure 64) IDD Supply current in RUN mode (see Figure 63) 3.2V≤VDD≤3.6V 3) Conditions fOSC=2MHz, fCPU=1MHz fOSC=4MHz, fCPU=2MHz fOSC=8MHz, fCPU=4MHz fOSC=16MHz, fCPU=8MHz fOSC=2MHz, fCPU=62.5kHz fOSC=4MHz, fCPU=125kHz fOSC=8MHz, fCPU=250kHz fOSC=16MHz, fCPU=500kHz fOSC=2MHz, fCPU=1MHz fOSC=4MHz, fCPU=2MHz fOSC=8MHz, fCPU=4MHz fOSC=16MHz, fCPU=8MHz fOSC=2MHz, fCPU=62.5kHz fOSC=4MHz, fCPU=125kHz fOSC=8MHz, fCPU=250kHz fOSC=16MHz, fCPU=500kHz Typ 1) 1.2 2.1 3.9 7.4 0.4 0.5 0.7 1.0 0.3 0.8 1.6 3.5 0.1 0.2 0.3 0.5 Max 2) 1.8 3.5 7.0 14.0 0.9 1.1 1.4 2.0 1 1.5 3 7 0.3 0.5 0.6 1.0 Unit mA Supply current in SLOW mode 4) (see Figure 64) Figure 63. Typical IDD in RUN vs. fCPU IDD [mA] 8 7 6 8MHz 4MHz 2MHz 1MHz Figure 64. Typical IDD in SLOW vs. fCPU IDD [mA] 1.2 500kHz 250kHz 1 125kHz 62.5kHz 0.8 5 4 3 2 0.2 1 0 3.2 3.5 4 4.5 5 5.5 VDD [V] 0 3.2 3.5 4 4.5 5 5.5 VDD [V] 0.6 0.4 Notes: 1. Typical data are based on TA=25°C, VDD=5V (4.5V≤VDD≤5.5V range) and VDD=3.4V (3.2V≤VDD≤3.6V range). 2. Data based on characterization results, tested in production at VDD max. and fCPU max. 3. CPU running with memory access, all I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (OSC1) driven by external square wave, CSS and LVD disabled. 4. SLOW mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (OSC1) driven by external square wave, CSS and LVD disabled. 113/153 ST72334J/N, ST72314J/N, ST72124J SUPPLY CURRENT CHARACTERISTICS (Cont’d) 16.4.2 WAIT and SLOW WAIT Modes Symbol Parameter 4.5V≤VDD≤5.5V Supply current in WAIT mode 3) (see Figure 65) 4) Conditions fOSC=2MHz, fCPU=1MHz fOSC=4MHz, fCPU=2MHz fOSC=8MHz, fCPU=4MHz fOSC=16MHz, fCPU=8MHz fOSC=2MHz, fCPU=62.5kHz fOSC=4MHz, fCPU=125kHz fOSC=8MHz, fCPU=250kHz fOSC=16MHz, fCPU=500kHz fOSC=2MHz, fCPU=1MHz fOSC=4MHz, fCPU=2MHz fOSC=8MHz, fCPU=4MHz fOSC=16MHz, fCPU=8MHz fOSC=2MHz, fCPU=62.5kHz fOSC=4MHz, fCPU=125kHz fOSC=8MHz, fCPU=250kHz fOSC=16MHz, fCPU=500kHz Typ 1) 0.35 0.7 1.3 2.5 0.05 0.1 0.2 0.5 45 150 300 500 6 40 80 120 Max 2) 0.6 1.2 2.1 4.0 0.1 0.2 0.4 1.0 100 300 600 1000 20 100 160 250 Unit mA Supply current in SLOW WAIT mode (see Figure 66) IDD Supply current in WAIT mode 3) (see Figure 65) 3.2V≤VDD≤3.6V µA Supply current in SLOW WAIT mode 4) (see Figure 66) Figure 65. Typical IDD in WAIT vs. fCPU IDD [mA] 3 8MHz 4MHz 2.5 2MHz 1MHz Figure 66. Typical IDD in SLOW-WAIT vs. fCPU IDD [mA] 0.35 0.3 0.25 500kHz 250kHz 125kHz 62.5kHz 2 0.2 1.5 0.15 1 0.1 0.5 0.05 0 3.2 3.5 4 4.5 5 5.5 3.2 3.5 4 4.5 5 5.5 VDD [V] VDD [V] 0 Notes: 1. Typical data are based on TA=25°C, VDD=5V (4.5V≤VDD≤5.5V range) and VDD=3.4V (3.2V≤VDD≤3.6V range). 2. Data based on characterization results, tested in production at VDD max. and fCPU max. 3. All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (OSC1) driven by external square wave, CSS and LVD disabled. 4. SLOW-WAIT mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (OSC1) driven by external square wave, CSS and LVD disabled. 114/153 ST72334J/N, ST72314J/N, ST72124J SUPPLY CURRENT CHARACTERISTICS (Cont’d) 16.4.3 HALT and ACTIVE-HALT Modes Symbol Parameter VDD=5.5V IDD Supply current in HALT mode 2) VDD=3.6V Supply current in ACTIVE-HALT mode 3) Conditions -40°C≤TA≤+85°C -40°C≤TA≤+125°C -40°C≤TA≤+85°C -40°C≤TA≤+125°C 50 2 >4 >8 20 38 32 18 15 40 110 180 400 Max 2 4 8 16 40 56 46 26 21 100 190 360 700 Unit fOSC RF CL1 CL2 LP: Low power oscillator MP: Medium power oscillator MS: Medium speed oscillator HS: High speed oscillator RS=200Ω RS=200Ω RS=200Ω RS=100Ω VDD=5V VIN=VSS LP oscillator MP oscillator MS oscillator HS oscillator LP oscillator MP oscillator MS oscillator HS oscillator MHz kΩ pF i2 OSC2 driving current µA 16.5.3.1 Typical Crystal Resonators Option Byte Config. LP JAUCH MP MS HS Reference S-200-30-30/50 SS3-400-30-30/30 SS3-800-30-30/30 SS3-1600-30-30/30 Freq. Characteristic 1) CL1 CL2 tSU(osc) [pF] [pF] [ms] 2) 33 33 33 33 34 34 34 34 10~15 7~10 2.5~3 1~1.5 2MHz ∆fOSC=[±30ppm25°C,±30ppm∆Ta], Typ. RS=200Ω 4MHz ∆fOSC=[±30ppm25°C,±30ppm∆Ta], Typ. RS=60Ω 8MHz ∆fOSC=[±30ppm25°C,±30ppm∆Ta], Typ. RS=25Ω 16MHz ∆fOSC=[±30ppm25°C,±30ppm∆Ta], Typ. RS=15Ω Figure 68. Application with a Crystal Resonator i2 fOSC OSC1 CL1 RESONATOR CL2 OSC2 RF ST72XXX Notes: 1. Resonator characteristics given by the crystal manufacturer. 2. tSU(OSC) is the typical oscillator start-up time measured between VDD=2.8V and the fetch of the first instruction (with a quick VDD ramp-up from 0 to 5V (