E-L6221AD

L6221 Quad Darlington switch Features ■ Four non-inverting inputs with enable ■ Output voltage up to 50 V ■ Output current up to 1.8 A ■ Very low saturation voltage ■ TTL compatible inputs ■ Integral fast recirculation diodes Power DIP 12+2+2 Applications The L6221 monolithic quad Darlington switch is designed for high current, high voltage switching applications. Description SO16+2+2 Figure 1. Block diagram Each of the four switches is controlled by a logic input and all four are controlled by a common enable input. All inputs are TTL-compatible for direct connection to logic circuits. Each switch consists of an open-collector Darlington transistor plus a fast diode for switching applications with inductive device loads. The emitters of the four switches are commoned. Any number of inputs and outputs of the same device may be paralleled. Table 1. Device summary Order code Package E-L6221AS Power DIP E-L6221AD SO16+2+2 E-L6221AD013TR SO16+2+2 (tape and reel) E-L6221C/CD/CN Obsolete product March 2009 Rev 4 1/22 www.st.com 22 Contents Contents 1 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7 Mounting instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2/22 Thermal data 1 Thermal data Table 2. Symbol Thermal data Parameter SO20 Power DIP Unit Rth j-pins Thermal resistance junction-pins max. 17 14 °C/W Rth j-amb Thermal resistance junction-ambient max. 80 80 °C/W 3/22 Pin information 2 Pin information Figure 2. Pin connections (top views) E-L6221AS (Power DIP) E-L6221AD (SO16+2+2) 4/22 Pin information Truth table(1) Table 3. Enable Input Power out H H ON H L OFF L X OFF 1. For each input: H = High level, L = Low level Table 4. Pin description(1) Name Function IN 1 Input to driver 1 IN 2 Input to driver 2 OUT 1 Output of driver 1 OUT 2 Output of driver 2 CLAMP A Diode clamp to driver 1 and driver 2 IN 3 Input to driver 3 IN 4 Input to driver 4 OUT 3 Output of driver 3 OUT 4 Output of driver 4 CLAMP B Diode clamp to driver 3 and driver 4 ENABLE Enable input to all drivers VS Logic supply voltage GND Common ground 1. See Figure 1: Block diagram 5/22 Absolute maximum ratings 3 Absolute maximum ratings Table 5. Absolute maximum ratings Symbol 6/22 Parameter Value Unit Vo Output voltage 50 V Vs Logic supply voltage 7 V VIN, VEN Input voltage, enable voltage VS IC Continuous collector current (for each channel) 1.8 A IC Collector peak current (repetitive, duty cycle = 10% ton = 5 ms) 2.5 A IC Collector peak current (non repetitive, t = 10 μ s) 3.2 A Top Operating temperature range (junction) -40 to +150 °C Tstg Storage temperature range -55 to +150 °C Isub Output substrate current 350 mA Ptot Total power dissipation at: Tpins = 90 ° C (Power DIP) Tcase = 90°C (SO20) Tamb = 70 ° C (Power DIP) Tamb = 70°C (SO20) 4.3 3.5 1 1 W W W W Electrical characteristics 4 Electrical characteristics Note: Refer to the test circuits Figure 3 to Figure 10 (VS = 5 V, Tamb = 25 °C unless otherwise specified). Table 6. Electrical characteristics Symbol Parameter Test condition Min. Typ. Max. 4.5 - 5.5 V All outputs ON, IC = 0.7A - - 20 mA All outputs OFF - - 20 mA - Unit VS Logic supply voltage Is Logic supply current VCE(sus) Output sustaining voltage VIN = VINL, VEN = VENH IC = 100 mA 46 - - V ICEX Output leakage current VCE = 50V VIN = VINL, VEN = VENH - - 1 mA VCE(sat) Collector emitter saturation voltage (one input on, all others inputs off.) Vs = 4.5 V VIN = VINH, VEN = VENH IC = 0.6 A IC = 1 A IC = 1.8 A - - 1 1.2 1.6 V VINL, VENL Input low voltage - - - 0.8 V IINL, IENL Input low current VIN = VINL, VEN = VENL - - -100 μA VINL, VENH Input high voltage - 2.0 - - V IINH, IENH Input high current VIN = VINH, VEN = VENH - - 10 μA IR Clamp diode leakage current VR = 50 V, VEN = VENH VIN = VINL - - 100 μA VF Clamp diode forward voltage IF = 1A IF = 1.8A - - 1.6 2.0 V V td (on) Turn-on delay time Vp = 5V, RL = 10Ω - - 2 μs td (off) Turn-off delay time Vp = 5V, RL = 10Ω - - 5 μs ΔIs Logic supply current variation VIN = 5V, VEN = 5V Iout = -300 mA for each channel - - 120 mA 7/22 Test circuits 5 Test circuits Note: Pin numbers without parentheses apply to the Power DIP package. Pin numbers in parentheses are not applicable. Figure 3. Logic supply current Set VIN = 4.5 V, VEN = 0.8 V, or VIN = 0.8 V, VEN = 4.5 V, for IS (all outputs off) Set VIN = 2 V, VEN = 2 V, for IS (all outputs on) 8/22 Figure 4. Output sustaining voltage Figure 5. Output leakage current Test circuits Figure 6. Collector-emitter saturation voltage Figure 7. Logic input characteristics Set S1, S2 open, VIN, VEN = 0.8 V for IIN L, IEN L Set S1, S2 open, VIN, VEN = 2 V for IIN H, IEN H Set S1, S2 closed, VIN, VEN = 0.8 V for VIN L, VEN L Set S1, S2 closed, VIN, VEN = 2 V for VIN H, VEN H Figure 8. Clamp-diode leakage current 9/22 Test circuits Figure 9. Clamp-diode forward voltage Figure 10. Switching time test circuit Figure 11. Switching time waveforms 10/22 Test circuits Figure 12. Allowed peak collector current versus duty cycle for 1, 2, 3 or 4 contemporary working outputs (L6221AS) Figure 13. Collector saturation voltage versus collector current Figure 14. Free-wheeling diode forward voltage versus diode current 11/22 Test circuits Figure 15. Collector saturation voltage versus junction temperature at IC = 1 A Figure 16. Free-wheeling diode forward voltage versus junction temperature at IF = 1 A Figure 17. Saturation voltage against junction temperature 12/22 Test circuits Figure 18. Free-wheeling diode forward voltage against junction temperature 13/22 Application information 6 Application information When inductive loads are driven by the L6221, a Zener diode in series with the integral freewheeling diodes increases the voltage across which energy stored in the load is discharged and therefore speeds the current decay (Figure 19). For reliability it is suggested that the Zener is chosen so that V p + V z < 35 V There are two reasons for this: ● The Zener voltage changes in temperature and current. ● The instantaneous power must be limited to avoid the reverse second breakdown. Figure 19. Free-wheeling diode connection when driving inductive loads Care must be taken to ensure that the collectors are placed close together to avoid different current partitioning at turn-off. It is suggested to put in parallel channel 1 and 4 and channel 2 and 3 as shown in Figure 20 for the similar electrical characteristics of the logic section (turn-on and turn-off delay time) and the power stages (collector saturation voltage, free-wheeling diode forward voltage). 14/22 Application information Figure 20. Driver for solenoids up to 3 A Figure 21. Saturation voltage versus collector current Figure 22. L6221AS peak collector current versus duty cycle for 1 or 2 paralleled outputs driven 15/22 Mounting instructions 7 Mounting instructions The Rth j-amb of the E-L6221AS can be reduced by soldering the GND pins to a suitable copper area of the printed circuit board (Figure 23) or to an external heat sink (Figure 24). Figure 23. Example of PCB copper area used as heat sink Figure 24. External heat sink mounting example 16/22 Mounting instructions Figure 25 shows the maximum dissipable power Ptot and the Rth j-amb as a function of the side "α" of two equal square copper areas having a thickness of 35 µm (1.4 mils). During soldering the pins temperature must not exceed 260 °C and the soldering time must not be longer than 12 seconds. The external heat sink or printed circuit copper area must be connected to electrical ground. Figure 25. Maximum dissipable power and junction-to-ambient thermal resistance versus side "α" Figure 26. Maximum allowable power dissipation versus ambient temperature 17/22 Package mechanical data 8 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 18/22 Package mechanical data mm DIM. MIN. a1 0.51 B 0.85 b b1 TYP. inch MAX. MIN. TYP. MAX. 0.020 1.40 0.033 0.50 0.38 0.055 0.020 0.50 D 0.015 0.020 20.0 0.787 E 8.80 0.346 e 2.54 0.100 e3 17.78 0.700 F 7.10 0.280 I 5.10 0.201 L Z OUTLINE AND MECHANICAL DATA 3.30 0.130 1.27 Power DIP 16 Powerdip 0.050 19/22 Package mechanical data 20/22 Revision history 9 Revision history Table 7. Document revision history Date Revision Changes 14-Jan-2004 2 Released in EDOCS 19-Jan-2009 3 Document reformatted. Inserted title for Figure 19. Removed reference to obsolete product L6221N and the associated package (multiwatt-15). 30-Mars-2009 4 Obsolete products E-L6221C/CD/CN added in Table 1. 21/22 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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