E-TDA7342NTR

TDA7342 Digitally controlled audio processor Features • Input multiplexer – Two stereo and one mono inputs – One quasi differential input – Selectable input gain for optimal adaptation to different sources • Fully programmable loudness function • Volume control in 0.3dB steps including gain up to 20dB • Zero crossing mute, soft mute and direct mute • Bass and treble control • Four speaker attenuators – Four independent speakers control in 1.25dB steps for balance and fader facilities – Independent mute function • All functions programmable via serial I2C bus Description The audioprocessor TDA7342 is an upgrade of the TDA731X audioprocessor family. LQFP32 Due to a highly linear signal processing, using CMOS-switching techniques instead of standard bipolar multipliers, very low distortion and very low noise are obtained. Several new features like softmute, and zero-crossing mute are implemented. The soft Mute function can be activated in two ways: 1. Via serial bus (Mute byte, bit D0) 2. Directly on pin 21 through an I/O line of the microcontroller Very low DC stepping is obtained by use of a BICMOS technology. Order codes Part number Package Packing TDA7342 LQFP32 Tray TDA7342TR LQFP32 Tape and reel September 2013 Rev 3 1/20 www.st.com 1 Contents TDA7342 Contents 1 2 3 4 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 Quick reference data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 I2C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 Data Validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 Start and Stop Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3 Byte Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.5 Transmission without Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Software specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1 Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2 Auto increment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3 Transmitted data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.4 Data byte specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2/20 TDA7342 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Quick reference data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Subaddress (receive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Send mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Input selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Loudness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Speaker attenuators (LF, LR, RF, RR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Bass/Treble. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3/20 List of figures TDA7342 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. 4/20 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Data Validity on the I2C BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Timing Diagram of I2C BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Acknowledge on the I2C BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 LQFP32 Mechanical Data & Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 TDA7342 Block diagram and pin description 1 Block diagram and pin description 1.1 Block diagram Figure 1. Block diagram BOUT(L) C17 100nF C11 C13 47nF C1 LEFT INPUTS L1 13 L2 12 IN(L) LOUD(L) 16 15 9 21 BIN(L) 18 C18 100nF C19 2.7nF TREBLE(L) 32 17 SPKR ATT 25 L1 MUTE ZERO CROSS + MUTE M L3 SM L2 C2 C6 OUT(L) R2 4.7K 11 LOUD+ VOL BASS TREBLE SPKR ATT L3 23 MUTE CD CD GND 10 28 INPUT SELECTOR + GAIN C3 C7 SOFT MUTE SERIAL BUS DECODER + LATCHES 27 26 RIGHT INPUTS C4 5 R3 M 8 M R2 6 R1 7 ZERO CROSS + MUTE R2 LOUD+ VOL BASS MUTE TREBLE SCL SDA BUS DIGGND 22 SUPPLY MUTE 30 31 VS OUT RIGHT FRONT SPKR ATT R1 C5 29 3 2 4 14 CREF OUT(R) IN(R) LOUD(R) CSM C12 47nF 10μF C9 C10 20 19 BOUT(R) C14 100nF CSM 47nF R1 OUT RIGHT REAR 1 BIN(R) TREBLE(R) D94AU104B C15 100nF C16 2.7nF 4.7K Pin description OUT LF DIG GND SDA SCL VS CREF TR L GND Pin connection (top view) 32 31 30 29 28 27 26 25 TR R 1 24 OUT RF IN R 2 23 OUT LR OUT R 3 22 OUT RR LOUD R 4 21 SM IN R3 5 20 BOUT R IN R2 6 19 BIN R IN R1 7 18 BOUT L MONO 8 17 BIN L OUT L IN L CSM IN L1 IN L2 IN L3 9 10 11 12 13 14 15 16 LOUD L Figure 2. CD GND 1.2 OUT LEFT REAR SPKR ATT R3 24 C8 MONO INPUT OUT LEFT FRONT D94AU105A 5/20 Electrical specifications TDA7342 2 Electrical specifications 2.1 Absolute maximum ratings Table 1. Absolute Maximum Ratings Symbol VS 2.2 Parameter Operating supply voltage 10.5 V Operating ambient temperature -40 to 85 C Tstg Storage temperature range -55 to 150 C Quick reference data Quick reference data Symbol Parameter Min. Typ. Max. Unit 6 9 10.2 V 2.1 2.6 VS Supply voltage VCL Max. input signal handling THD Total harmonic distortion V = 1Vrms f = 1KHz 0.01 S/N Signal to noise ratio 106 dB SC Channel separation 100 dB Volume control 0.3dB step Vrms 0.08 % -59.7 20 dB Treble control 2dB step -14 +14 dB Bass control 2dB step -10 +18 dB -38.75 0 dB 0 11.25 dB Fader and balance control 1.25dB step Input gain 3.75dB step Mute attenuation 100 dB Value Unit 150 C/W Thermal data Table 3. Symbol Rth j-amb 6/20 Unit Tamb Table 2. 2.3 Value Thermal data Parameter Thermal resistance junction to pins TDA7342 Electrical specifications 2.4 Electrical characteristics Table 4. Electrical characteristics (VS = 9V; RL = 10K; Rg = 50; Tamb = 25°C; all gains = 0dB; f = 1KHz. Refer to the test circuit, unless otherwise specified.) Symbol Parameter Test condition Min. Typ. Max. Unit 70 100 130 K 2.1 2.6 VRMS 100 dB Input selector RI VCL Input resistance Clipping level d 0.3% SI Input separation 80 RL Output load resistance 2 K GI MIN Minimum input gain -0.75 0 0.75 dB GI MAX Maximum input gain 10.25 11.25 12.25 dB Step resolution 2.75 3.75 4.75 dB Gstep eN VDC Input noise DC steps 20Hz to 20 KHz unweighted 2.3 Adiacent Gain Steps 1.5 GIINto GIMAX V 10 3 mV mV Differential input ( IN 3) RI CMRR Input resistance Common mode rejection ratio Input selector BIT D6 = 0 (0dB) 10 15 20 K Input selector BIT D6 = 1(-6dB) 14 20 30 K VCM = 1VRMS; f =1KHz 48 75 dB f = 10KHz 45 70 dB d Distortion VI= 1VRMS eIN Input noise 20Hz to 20KHz; Flat; D6 = 0 GDIFF Differential gain 0.01 0.08 % V 5 D6 = 0 -1 0 1 dB D6 = 1 -7 -6 -5 dB Volume control RI Input resistance 35 50 GMAX Maximum gain 18.75 20 21.25 dB AMAX Maximum attenuation 57.7 59.7 62.7 dB ASTEPC Step resolution coarse atten. 0.5 1.25 2.0 dB ASTEPF Step resolution fine attenuation 0.11 0.31 0.51 dB G = 20 to -20dB -1.25 0 1.25 dB G = -20 to -58dB -3 2 dB 2 dB 0 3 mV 0.5 5 mV EA Attenuation set error Et Tracking error VDC DC steps Adiacent Attenuation Steps From 0dB to AMAX -3 K 7/20 Electrical specifications Table 4. TDA7342 Electrical characteristics (continued) (VS = 9V; RL = 10K; Rg = 50; Tamb = 25°C; all gains = 0dB; f = 1KHz. Refer to the test circuit, unless otherwise specified.) Symbol Parameter Test condition Min. Typ. Max. Unit 35 50 65 K Loudness control RI Internal resistor Loud = On AMAX Maximum attenuation 17.5 18.75 20.0 dB Astep Step resolution 0.5 1.25 2.0 dB Zero crossing mute VTH AMUTE VDC Zero crossing threshold (1) WIN = 11 20 mV WIN = 10 40 mV WIN = 01 80 mV WIN = 00 160 mV 100 dB Mute attenuation DC step 80 0dB to Mute 0 3 mV Soft mute AMUTE Mute attenuation TDON On delay time IDOFF Off current VTHSM Soft mute threshold (pin 14) RINT Pull-up resistor (pin 21) VSMH (pin 21) level high VSML (pin 21) level low 45 60 CCSM = 22nF; 0 to -20dB; I = IMAX 0.7 1 1.7 ms CCSM = 22nF; 0 to -20dB; I = IMIN 20 35 55 ms VCSM= 0V; I = IMAX 25 50 75 A VCSM= 0V; I = IMIN (2) dB A 1 1.5 2.5 3.5 V 35 50 65 k 3.5 V Soft mute active 1 V Bass control BBOOST Max bass boost 15 18 20 dB BCUT Max bass cut -8.5 -10 -11.5 dB Astep Step resolution 1 2 3 dB Internal feedback resistance 45 65 85 K 13 14 15 dB 1 2 3 dB 35 37.5 40 dB 0.5 1.25 2.00 dB Rg Treble control CRANGE Control range Astep Step resolution Speaker attenuators CRANGE Control range Astep 8/20 Step resolution TDA7342 Electrical specifications Table 4. Electrical characteristics (continued) (VS = 9V; RL = 10K; Rg = 50; Tamb = 25°C; all gains = 0dB; f = 1KHz. Refer to the test circuit, unless otherwise specified.) Symbol AMUTE Parameter Output mute attenuation EA Attenuation set error VDC DC steps Test condition Data word = XXX11111 Min. Typ. 80 100 Adjacent attenuation steps 0 Max. Unit dB 1.25 dB 3 mV Audio output Vclip Clipping level RL Output load resistance RO Output impedance VDC DC voltage Level d = 0.3% 2.1 2.6 Vrms 2 K 30 100  3.5 3.8 4.1 V General VCC Supply voltage 6 9 10.2 V ICC Supply current 5 10 15 mA 60 80 dB B = 20 to 20kHz "A" weighted 65 dB Output Muted (B = 20 to 20kHz flat) 2.5 V All Gains 0dB (B = 20 to 20kHz flat) 5 15 V AV= 0 to -20dB 0 1 dB AV= -20 to -60dB 0 2 dB PSRR eNO Power supply rejection ratio Output noise Et Total tracking error S/N Signal to noise ratio SC Channel separation d Distortion f = 1KHz All Gains = 0dB; VO= 1Vrms 80 VIN =1V 106 dB 100 dB 0.01 0.08 % 1 V Bus inputs VIL Input low voltage VlN Input high voltage IlN Input current VIN = 0.4V VO Output voltage SDA acknowledge IO= 1.6mA 3 V -5 0.4 5 A 0.8 V 1. WIN represents the MUTE programming bit pair D6, D5 for the zero crossing window threshold. 2. Internal pull-up resistor to Vs/2; LOW = softmute active. 9/20 I2C bus interface 3 TDA7342 I2C bus interface Data transmission from microprocessor to the TDA7342 and viceversa takes place thru the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be externally connected). 3.1 Data Validity As shown in Figure 3, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. 3.2 Start and Stop Conditions As shown in Figure 5 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. A STOP conditions must be sent before each START condition. 3.3 Byte Format Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. 3.4 Acknowledge The master (µP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see Figure 5). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. 3.5 Transmission without Acknowledge Avoiding to detect the acknowledge of the audioprocessor, the P can use a simplier transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking and decreases the noise immunity. 10/20 TDA7342 I2C bus interface Figure 3. Data Validity on the I2C BUS SDA SCL DATA LINE STABLE, DATA VALID Figure 4. CHANGE DATA ALLOWED D99AU1031 Timing Diagram of I2C BUS SCL I2CBUS SDA D99AU1032 START Figure 5. STOP Acknowledge on the I2C BUS SCL 1 2 3 7 8 9 SDA MSB START Patent note: D99AU1033 ACKNOWLEDGMENT FROM RECEIVER Purchase of I2C Components of STMicrolectronics, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips. 11/20 Software specification TDA7342 4 Software specification 4.1 Interface Protocol The interface protocol comprises: ? A start condition (s) ? A chip address byte, (the LSB bit determines read/write transmission) ? A subaddress byte. ? A sequence of data (N-bytes + acknowledge) ? A stop condition (P) Figure 6. Interface protocol CHIP ADDRESS MSB S 1 SUBADDRESS LSB 0 0 0 1 0 0 R/W DATA 1 ... DATA n MSB ACK X LSB X X I A3 A2 A1 A0 MSB ACK LSB DATA ACK P D05AU1575 ACK = Acknowledge S = Start P = Stop I = Auto Increment X = Not used A = I2C address value selectable according to ADDR pin status ADDR = Open/GndA = O ADDR = VCC A=I MAX CLOCK SPEED 500kbits/s 4.2 Auto increment If bit I in the subaddress byte is set to "1", the autoincrement of the subaddress is enabled Table 5. Subaddress (receive mode) MSB X 12/20 LSB X X I Function A3 A2 A1 A0 0 0 0 0 Input Selector 0 0 0 1 Loudness 0 0 1 0 Volume 0 0 1 1 Bass, Treble 0 1 0 0 Speaker Attenuator LF 0 1 0 1 Speaker Attenuator LR 0 1 1 0 Speaker Attenuator RF 0 1 1 1 Speaker Attenuator RR 1 0 0 0 Mute TDA7342 4.3 Software specification Transmitted data Table 6. Send mode MSB LSB X X X X X SM ZM X ZM = Zero crossing muted (HIGH active) SM = Soft mute activated (HIGH active) X = Not used The transmitted data is automatically updated after each ACK. Transmission can be repeated without new chip address. 4.4 Data byte specification X = not relevant; set to "1" during testing Table 7. Input selector MSB D7 LSB D6 D5 D4 D3 D2 D1 D0 Function 0 1 0 0 0 not used 0 1 0 0 1 IN 2 0 1 0 1 0 IN 1 0 1 0 1 1 AM mono 0 1 1 0 0 not used 0 1 1 0 1 not used 0 1 1 1 0 not allowed 0 1 1 1 1 not allowed 0 1 0 0 11.25dB gain 0 1 0 1 7.5dB gain 0 1 1 0 3.75dB gain 0 1 1 1 0dB gain 0 0dB differential input gain (IN3) 1 -6dB differential input gain (IN3) For example to select the IN 2 input with a gain of 7.5dB the Data Byte is: X X 1 0 1 0 0 1 13/20 Software specification Table 8. TDA7342 Loudness MSB LSB Function D7 D6 D5 D4 D3 D2 D1 D0 X X X 0 0 0 0 0 0dB X X X 0 0 0 0 1 -1.25dB X X X 0 0 0 1 0 -2.5dB X X X 0 0 0 1 1 -3.75dB X X X 0 0 1 0 0 -5dB X X X 0 0 1 0 1 -6.25dB X X X 0 0 1 1 0 -7.5dB X X X 0 0 1 1 1 -8.75dB X X X 0 1 0 0 0 -10dB X X X 0 1 0 0 1 -11.25dB X X X 0 1 0 1 0 -12.5dB X X X 0 1 0 1 1 -13.75dB X X X 0 1 1 0 0 -15dB X X X 0 1 1 0 1 -16.25dB X X X 0 1 1 1 0 -17.5dB X X X 0 1 1 1 1 -18.75dB X X X 1 D3 D2 D1 D0 Loudness OFF (1) 1. If the loudness is switched OFF, the loudness stage is acting like a volume attenuator with flat frequency response. D0 to D3 determine the attenuation level. For example to select -17.5dB attenuation, loudness OFF, the Data Byte is: X X X1 1 1 1 0 Table 9. Mute MSB D7 LSB D6 D5 D4 D3 D2 1 14/20 0 Function D0 1 Soft Mute On 0 1 Soft Mute with fast slope (I = IMAX) 1 1 Soft Mute with slow slope (I = IMIN) Direct Mute 0 1 Zero Crossing Mute On 0 0 Zero Crossing Mute Off (delayed until next zerocrossing) 1 0 D1 Zero Crossing Mute and Pause Detector Reset 160mV ZC Window Threshold (WIN = 00) TDA7342 Software specification Table 9. Mute (continued) MSB D7 LSB D4 D3 D2 D1 Function D6 D5 D0 0 1 80mV ZC Window Threshold (WIN = 01) 1 0 40mV ZC Window Threshold (WIN = 10) 1 1 20mV ZC Window Threshold (WIN = 11) 0 Nonsymmetrical Bass Cut (1) 1 Symmetrical Bass Cut 1. Bass cut for very low frequencies; should not be used at +16 and +18dB bass boost (DC gain) An additional direct mute function is included in the Speaker Attenuators. Table 10. Speaker attenuators (LF, LR, RF, RR) MSB D7 LSB D6 D5 D4 D3 D2 D1 Function D0 1.25dB step X X X 0 0 0 0dB X X X 0 0 1 -1.25dB X X X 0 1 0 -2.5dB X X X 0 1 1 -3.75dB X X X 1 0 0 -5dB X X X 1 0 1 -6.25dB X X X 1 1 0 -7.5dB X X X 1 1 1 -8.75dB 10dB step X X X 0 0 0dB X X X 0 1 -10dB X X X 1 0 -20dB X X X 1 1 -30dB X X X 1 1 1 1 1 Speaker Mute For example an attenuation of 25dB on a selected output is given by: X X X1 0 1 0 0 Table 11. Bass/Treble MSB D7 LSB D6 D5 D4 D3 D2 D1 Function D0 Treble step 0 0 0 0 -14dB 0 0 0 1 -12dB 15/20 Software specification Table 11. TDA7342 Bass/Treble (continued) MSB D7 LSB D6 D5 D4 Function D3 D2 D1 D0 0 0 1 0 -10dB 0 0 1 1 -8dB 0 1 0 0 -6dB 0 1 0 1 -4dB 0 1 1 0 -2dB 0 1 1 1 0dB 1 1 1 1 0dB 1 1 1 0 2dB 1 1 0 1 4dB 1 1 0 0 6dB 1 0 1 1 8dB 1 0 1 0 10dB 1 0 0 1 12dB 1 0 0 0 14dB Bass steps 0 0 1 0 -10dB 0 0 1 1 -8dB 0 1 0 0 -6dB 0 1 0 1 -4dB 0 1 1 0 -2dB 0 1 1 1 -0dB 1 1 1 1 -0dB 1 1 1 0 2dB 1 1 0 1 4dB 1 1 0 0 6dB 1 0 1 1 8dB 1 0 1 0 10dB 1 0 0 1 12dB 1 0 0 0 14dB 0 0 0 1 146B 0 0 0 0 18dB For example 12dB Treble and -8dB Bass give the following DATA BYTE: 0 0 1 1 1 0 0 1 16/20 TDA7342 Software specification Table 12. Volume MSB D7 LSB D6 D5 D4 D3 D2 D1 Function D0 0.31dB Fine Attenuation Steps 0 0 0dB 0 1 -0.31dB 1 0 -0.62dB 1 1 -0.94dB 1.25dB Coarse Attenuation Steps 0 0 0 0dB 0 0 1 -1.25dB 0 1 0 -2.5dB 0 1 1 -3.75dB 1 0 0 -5dB 1 0 1 -6.25dB 1 1 0 -7.5dB 1 1 1 -8.75dB 10dB Gain / Attenuation Steps 0 0 0 20dB 0 0 1 10dB 0 1 0 0dB 0 1 1 -10dB 1 0 0 -20dB 1 0 1 -30dB 1 1 0 -40dB 1 1 1 -50dB For example to select -47.81dB Volume the Data Byte is: 1 1 0 1 1 0 0 1 Power on RESET: All Bytes Set to 1 1 1 1 1 1 1 0 17/20 Package information 5 TDA7342 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 7. LQFP32 Mechanical Data & Package Dimensions mm inch DIM. MIN. TYP. A MAX. MIN. TYP. MAX. 1.600 0.0630 0.150 0.0020 0.0059 A1 0.050 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.300 0.370 0.450 0.0118 0.0146 0.0177 c 0.090 D 8.800 9.000 9.200 0.3465 0.3543 0.3622 D1 6.800 7.000 7.200 0.2677 0.2756 0.2835 D3 5.600 E 8.800 E1 6.800 E3 7.000 7.200 0.2677 0.2756 0.2835 0.600 L1 1.000 K 3.500 ccc 0.2205 9.200 0.3465 0.3543 0.3622 0.2205 0.800 0.450 Weight: 0.20gr 0.0079 9.000 5.600 e L 0.200 0.0035 OUTLINE AND MECHANICAL DATA 0.0315 0.750 0.0177 0.0236 0.0295 0.0394 7.000 0.1378 0.2756 0.100 0.0039 LQFP32 (7 x 7 x 1.40mm) 0060661 D 18/20 TDA7342 6 Revision history Revision history Table 13. Document revision history Date Revision Changes 24-Jan-2006 1 Initial release. 20-Nov-2006 2 Layout changes, text modifications, updated package informations. 24-Sep-2013 3 Updated Disclaimer. 19/20 TDA7342 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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