EVAL6229PD

L6229 Datasheet DMOS driver for 3-phase brushless DC motor Features Power S036 SO24 • • • Operating supply voltage from 8 to 52 V 2.8 A output peak current (1.4 A DC) RDS(ON) 0.73 Ω typ. value at Tj = 25 °C • • • • Operating frequency up to 100 kHz Non-dissipative overcurrent detection and protection Diagnostic output Constant tOFF PWM current controller • • • • • • • • Slow decay synchronous rectification 60° and 120° Hall effect decoding logic Brake function Tachometer output for speed loop Cross conduction protection Thermal shutdown Undervoltage lockout Integrated fast free wheeling diodes (20 + 2 + 2) Application • • • • Product status link L6229 Product summary Description Order code Package Packing L6229D SO-24 Tube L6229DTR SO-24 Tape and reel L6229PD PowerSO36 Tube L6229PDTR PowerSO36 Product label Factory automation end-points Home appliances Small pumps ATMs Tape and reel The L6229 is a DMOS fully integrated 3-phase motor driver with overcurrent protection. Realized in BCD technology, the device combines isolated DMOS power transistors with CMOS and bipolar circuits on the same chip. The device includes all the circuitry needed to drive a 3-phase BLDC motor including: a 3-phase DMOS bridge, a constant off time PWM current controller and the decoding logic for single ended Hall sensors that generates the required sequence for the power stage. Available in Power SO36 and SO24 (20 + 2 + 2) packages, the L6229 features a non-dissipative overcurrent protection on the high-side power MOSFET and thermal shutdown. DS3275 - Rev 7 - April 2022 For further information contact your local STMicroelectronics sales office. www.st.com L6229 Block diagram 1 Block diagram Figure 1. Block diagram VBOOT VCP VBOOT VBOOT VS A THERMAL PROTECTION CHARGE PUMP OCD1 DIAG OCD OUT 1 10 V OCD1 OCD2 OCD OCD3 VBOOT EN BRAKE FWD/REV OCD2 H3 HALL EFFECT SENSORS DECODING LOGIC H2 GATE LOGIC SENSE VBOOT H1 RCPULSE OUT 2 10 V TACHO MONOSTABLE A VS B OCD3 OUT 3 10 V TACHO 10 V 5V VOLTAGE REGULATOR SENSE PWM ONE SHOT MONOSTABLE MASKING TIME B + SENSE COMPARATOR - VREF RCOFF DS3275 - Rev 7 page 2/34 L6229 Absolute maximum ratings 2 Absolute maximum ratings Table 1. Absolute maximum ratings Symbol VS VOD VBOOT Parameter Supply voltage Differential voltage between: VSA, OUT1, OUT2, SENSEA and VSB, OUT3, SENSEB Bootstrap peak voltage Value Unit VSA = VSB = VS 60 V 60 V VSA = VSB = VS VS + 10 V VSA = VSB = VS = 60 V; VSENSEA = VSENSEB = GND VIN, VEN Logic inputs voltage range - -0.3 to 7 V VREF Voltage range at pin VREF - -0.3 to 7 V Voltage range at pin RCOFF - -0.3 to 7 V - -0.3 to 7 V - -1 to 4 V VSA = VSB = VS; tPULSE < 1 ms 3.55 A VSA = VSB = VS 1.4 A - -40 to 150 °C VRCOFF VRCPULSE Voltage range at pin RCPULSE VSENSE Voltage range at pins SENSEA and SENSEB IS(peak) Pulsed supply current (for each VSA and VSB pin) IS Tstg, TOP DS3275 - Rev 7 Test conditions DC supply current (for each VSA and VSB pin) Storage and operating temperature range page 3/34 L6229 Recommended operating condition 3 Recommended operating condition Table 2. Recommended operating condition Symbol VS VOD VREF VSENSE DS3275 - Rev 7 Parameter Test conditions Min. Max. Unit Supply voltage VSA = VSB = VS 8 52 V Differential voltage between: VSA = VSB = VS; - 52 V - -0.1 5 V (pulsed tW < trr) -6 6 (DC) -1 1 VSA = VSB = VS - 1.4 A - - 100 kHz VSA, OUT1, OUT2, SENSEA and VSB, OUT3, SENSEB Voltage range at pin VREF Voltage range at pins SENSEA and SENSEB IOUT DC output current fSW Switching frequency VSENSEA = VSENSEB V page 4/34 L6229 Thermal data 4 Thermal data Table 3. Thermal data Symbol Description Rth(j-pins) Maximum thermal resistance junction pins Rth(j-case) Maximum thermalresistance junction case SO24 PowerSO36 Unit 15 - °C/W - 2 °C/W 55 - °C/W Rth(j-amb)1 Maximum thermal resistance junction ambient Rth(j-amb)1 Maximum thermal resistance junction ambient (2) - 36 °C/W Rth(j-amb)1 Maximum thermal resistance junction ambient (3) - 16 °C/W Rth(j-amb)2 Maximum thermal resistance junction ambient (4) 78 63 °C/W (1) 1. Mounted on a multilayer FR4 PCB with a dissipating copper surface on the bottom side of 6 cm2 (with a thickness of 35 μm). 2. Mounted on a multilayer FR4 PCB with a dissipating copper surface on the top side of 6 cm2 (with a thickness of 35 μm). 3. Mounted on a multilayer FR4 PCB with a dissipating copper surface on the top side of 6 cm2 (with a thickness of 35 μm), 16 via holes and a ground layer. 4. Mounted on a multilayer FR4 PCB without any heat-sinking surface on the board. DS3275 - Rev 7 page 5/34 L6229 Pin connections 5 Pin connections Figure 2. Pin connections (top view) GND 1 36 GND N.C. 2 35 N.C. H1 1 24 H3 N.C. 3 34 N.C. DIAG 2 23 H2 VS A 4 33 VS B S ENS E A 3 22 VCP OUT2 5 32 OUT3 RCOFF 4 21 OUT2 N.C. 6 31 N.C. OUT1 5 20 VS A VCP 7 30 VBOOT GND 6 19 GND GND 7 18 GND TACHO 8 17 VS B RCP ULS E 9 16 OUT3 S ENS E B 10 15 VBOOT FWD/REV 11 14 BRAKE EN 12 13 VREF H2 8 29 BRAKE H3 9 28 VREF H1 10 27 EN DIAG 11 26 FWD/REV SENSE A 12 25 SENSE B RCOFF 13 24 RCPULSE N.C. 14 23 N.C. OUT1 15 22 TACHO N.C. 16 21 N.C. N.C. 17 20 N.C. GND 18 19 GND SO24 PowerSO36 (1) 1. The slug is internally connected to pins 1, 18, 19 and 36 (GND pins). Table 4. Pin functions Package SO24 DS3275 - Rev 7 PowerSO36 Pin name Type Function Pin no. Pin no. 1 10 H1 Sensor input 2 11 DIAG Open drain output 3 12 SENSEA 4 13 RCOFF RC pin 5 15 OUT1 Power output 6, 7, 18, 19 1, 18, 19, 36 GND GND 8 22 TACHO Open drain output Frequency-to-voltage open drain output. Every pulse from pin H1 is shaped as a fixed and adjustable length pulse. 9 24 RCPULSE RC pin RC network pin. A parallel RC network connected between this pin and ground sets the duration of the monostable pulse used for the frequency-to-voltage converter. 10 25 SENSEB 11 26 FWD/REV Single ended Hall effect sensor input 1. Overcurrent detection and thermal protection pin. An internal open drain transistor pulls to GND when an overcurrent on one of the highside MOSFET is detected or during thermal protection. Half-bridge 1 and half-bridge 2 source pin. This pin must be connected Power supply together with pin SENSEB to power ground through a sensing power resistor. RC network pin. A parallel RC network connected between this pin and ground sets the current controller OFF-time. Output 1 Ground terminals. On SO24 package, these pins are also used for heat dissipation toward the PCB. On PowerSO36 package the slug is connected on these pins. Half-bridge 3 source pin. This pin must be connected together with pin Power supply SENSEA to power ground through a sensing power resistor. At this pin also the inverting input of the sense comparator is connected. Logic input Selects the direction of the rotation. HIGH logic level sets forward operation, whereas LOW logic level sets reverse operation. If not used, it has to be connected to GND or +5 V. page 6/34 L6229 Pin connections Package SO24 DS3275 - Rev 7 PowerSO36 Pin name Type Function Pin no. Pin no. 12 27 EN Logic input Chip enable. LOW logic level switches OFF all power MOSFET. If not used, it has to be connected to +5 V. 13 28 VREF Logic input Current controller reference voltage. Do not leave this pin open or connect to GND. 14 29 BRAKE Logic input Brake input pin. LOW logic level switches ON all high- side power MOSFET, implementing the brake function. If not used, it has to be connected to +5 V. 15 30 VBOOT Supply voltage 16 32 OUT3 Power output Output 3. 17 33 VSB Power supply Half-bridge 3 power supply voltage. It must be connected to the supply voltage together with pin VSA. 20 4 VSA Power supply Half-bridge 1 and half-bridge 2 power supply voltage. It must be connected to the supply voltage together with pin VSB. 21 5 OUT2 Power output Output 2. 22 7 VCP Output 23 8 H2 Sensor input Single ended Hall effect sensor input 2. 24 9 H3 Sensor input Single ended Hall effect sensor input 3. Bootstrap voltage needed for driving the upper power MOSFETs. Charge pump oscillator output. page 7/34 L6229 Electrical characteristics 6 Electrical characteristics Table 5. Electrical characteristics Test conditions: VS = 48 V, Tamb = 25 °C , unless otherwise specified) Symbol Parameter Test conditions Min. Typ. Max. Unit VSth(ON) Turn ON threshold - 5.8 6.3 6.8 V VSth(OFF) Turn OFF threshold - 5 5.5 6 V All bridges OFF; TJ = -25 to 125 °C (1) - 5 10 mA - - 165 - °C TJ = 25 °C - 1.47 1.69 Ω TJ = 125 °C(2) - 2.35 2.70 Ω EN = low; OUT = VCC - - 2 mA EN = low; OUT = GND -0.3 - - mA ISD = 1.4 A, EN = low - 1.15 1.3 V IS TJ(OFF) Quiescent supply current Thermal shutdown temperature Output DMOS transistors RDS(ON) IDSS High-side + low-side switch ON resistance Leakage current Source drain diodes VSD Forward ON voltage trr Reverse recovery time If = 1.4 A - 300 - ns tfr Forward recovery time - - 200 - ns Logic input (H1, H2, H3, EN, FWD/REV, BRAKE) VIL Low level logic input voltage - -0.3 - 0.8 V VIH High level logic input voltage - 2 - 7 V IIL Low level logic input current GND logic input voltage -10 - - μA IIH High level logic input current 7V logic input voltage - - 10 μA Vth(ON) Turn-ON input threshold - - 1.8 2.0 V Vth(OFF) Turn-OFF input threshold - 0.8 1.3 - V VthHYS Input thresholds hysteresis - 0.25 0.5 - V ILOAD = 1.4 A, resistive load 500 650 800 ns ILOAD = 1.4 A, resistive load 500 - 1000 ns Switching characteristics tD(on)EN Enable to out turn-ON delay time(2) tD(off)EN Enable to out turn-OFF delay tD(on)IN Other logic inputs to output turn-ON delay time ILOAD = 1.4 A, resistive load - 1.6 - µs tD(off)IN Other logic inputs to out turn-OFF delay time ILOAD = 1.4 A, resistive load - 800 - ns Outputrise time (2) ILOAD = 1.4 A, resistive load 40 - 250 ns ILOAD = 1.4 A, resistive load 40 - 250 ns - 0.5 1 - µs TJ = -25 to 125 °C(1) - 0.6 1 MHz VRCOFF = 2.5 V 3.5 5.5 - mA Vref = 0.5 V - ±5 - mV tRISE tFALL Outputfall time time(2) (2) tDT Deadtime fCP Charge pump frequency PWM comparator and monostable IRCOFF VOFFSET DS3275 - Rev 7 Source current at pin RCOFF Offset voltage on sense comparator page 8/34 L6229 Electrical characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit Vref = 0.5 V - 500 - ns tprop Turn OFF propagation delay(3) tblank Internal blanking time on sense comparator - - 1 - µs Minimum on time - - 2.5 3 µs ROFF = 20 kΩ; COFF = 1 nF - 13 - μs ROFF = 100 kΩ; COFF = 1 nF - 61 - μs - - - 10 µA VRCPULSE = 2.5 V 3.5 5.5 - mA RPUL = 20 kΩ; CPUL = 1 nF - 12 - ms RPUL = 100 kΩ; CPUL = 1 nF - 60 - ms - - 40 60 Ω TJ = -25 to 125 °C(1) 2 2.8 3.55 A tON(min) tOFF PWM recirculation time IBIAS Input bias current at pin VREF TACHO monostable IRCPULSE tPULSE RTACHO Source current at pin RCPULSE Monostable of time Open drain ON resistance Overcurrent detection and protection ISOVER Supply overcurrent protection threshold ROPDR Open drain ON resistance IDIAG = 4 mA - 40 60 Ω OCD high level leakage current VDIAG = 5 V - 1 - µA IOH tOCD(ON) OCD turn-ON delay time(4) IDIAG = 4mA; CDIAG < 100 pF - 200 - ns tOCD(OFF) OCD turn-OFF delay time(4) IDIAG = 4mA; CDIAG < 100 pF - 100 - ns 1. Tested at 25 °C in a restricted range and guaranteed by characterization. 2. See Figure 3: Switching characteristic definition. 3. Measured applying a voltage of 1 V to pin SENSE and a voltage drop from 2 V to 0 V to pin VREF. 4. See Figure 4: Overcurrent detection timing definition. Figure 3. Switching characteristic definition EN Vth(ON) Vth(OFF) t IOUT 90% 10% t tRIS E tFALL tD(OFF)EN DS3275 - Rev 7 tD(ON)EN page 9/34 L6229 Electrical characteristics Figure 4. Overcurrent detection timing definition IOUT IS OVER ON BRIDGE OFF VDIAG 90% 10% tOCD(ON) DS3275 - Rev 7 tOCD(OFF) page 10/34 L6229 Circuit description 7 Circuit description 7.1 Power stages and charge pump The L6229 device integrates a 3-phase bridge, which consists of 6 power MOSFETs connected as shown in Block diagram . Each power MOS has an RDS(ON) = 0.73 Ω (typical value at 25 °C) with intrinsic fast free-wheeling diode. Switching patterns are generated by the PWM current controller and the Hall effect sensor decoding logic (see Section 8 PWM current control and Section 10 Decoding logic). Cross conduction protection is implemented by using a deadtime (tDT = 1 μs typical value) set by internal timing circuit between the turn off and turn on of two power MOSFETs in one leg of a bridge. Pins VSA and VSB must be connected together to the supply voltage (VS). Using N-channel power MOS for the upper transistors in the bridge requires a gate drive voltage above the power supply voltage. The bootstrapped supply (VBOOT) is obtained through an internal oscillator and few external components to realize a charge pump circuit as shown in Figure 5. The oscillator output (pin VCP) is a square wave at 600 kHz (typically) with 10 V amplitude. Recommended values/part numbers for the charge pump circuit are shown in Table 6. Table 6. Charge pump external component values Component Value CBOOT 220 nF CP 10 nF RP 100 Ω D1 1N4148 D2 1N4148 Figure 5. Charge pump circuit VS D1 C BOOT D2 RP CP VCP DS3275 - Rev 7 VBOOT VS A VS B page 11/34 L6229 Logic inputs 7.2 Logic inputs Pins FWD/REV, BRAKE, EN, H1, H2 and H3 are TTL/CMOS compatible logic inputs. The internal structure is shown in Figure 6. Typical value for turn-ON and turn-OFF thresholds are respectively Vth(ON) = 1.8 V and Vth(OFF) = 1.3 V. Pin EN (enable) may be used to implement overcurrent and thermal protection by connecting it to the open collector DIAG output. If the protection and an external disable function are both desired, the appropriate connection must be implemented. When the external signal is from an open collector output, the circuit in Figure 7 can be used. For external circuits that are push-pull outputs the circuit in Figure 8 could be used. The resistor REN should be chosen in the range from 2.2 kΩ to 180 kΩ. Recommended values for REN and CEN are respectively 100 kΩ and 5.6 nF. More information for selecting the values can be found Section 12 Non-dissipative overcurrent detection and protection. Figure 6. Logic input internal structure 5V ESD PROTECTION Figure 7. Pin EN open collector driving DIAG 5V 5V R EN OPEN COLLECTOR OUTPUT C EN EN ESD PROTECTION Figure 8. Pin EN push-pull driving DIAG 5V PUSH-PULL OUTPUT R EN EN C EN DS3275 - Rev 7 ESD PROTECTION page 12/34 L6229 PWM current control 8 PWM current control The L6229 device includes a constant off time PWM current controller. The current control circuit senses the bridge current by sensing the voltage drop across an external sense resistor connected between the source of the three lower power MOS transistors and ground, as shown in Figure 9. As the current in the motor increases the voltage across the sense resistor increases proportionally. When the voltage drop across the sense resistor becomes greater than the voltage at the reference input pin VREF the sense comparator triggers the monostable switching the bridge off. The power MOS remains off for the time set by the monostable and the motor current recirculates around the upper half of the bridge in slow decay mode as described in Section 9 Slow decay mode. When the monostable times out, the bridge will again turn on. Since the internal deadtime, used to prevent cross conduction in the bridge, delays the turn on of the power MOS, the effective off time tOFF is the sum of the monostable time plus the deadtime. Figure 10 shows the typical operating waveforms of the output current, the voltage drop across the sensing resistor, the pin RC voltage and the status of the bridge. More details regarding the synchronous rectification and the output stage configuration are included in Section 9 Slow decay mode. Immediately after the power MOS turns on, a high peak current flows through the sense resistor due to the reverse recovery of the freewheeling diodes. The L6229 device provides a 1 μs blanking time tBLANK that inhibits the comparator output so that the current spike cannot prematurely retrigger the monostable. Figure 9. PWM current controller simplified schematic VS B VS A VS BLANKING TIME MONOSTABLE TO GATE LOGIC FROM THE LOW-SIDE GATE DRIVERS 5 mA MONOSTABLE SET S (0) (1) BLANKER OUT 2 Q OUT 3 R DRIVERS + DEADTIME - DRIVERS + DEADTIME + 5V 2.5 V OUT 1 DRIVERS + DEADTIME + SENSE COMPARATOR C OFF DS3275 - Rev 7 - RCOFF VREF R OFF R SENSE SENSE B SENSE A page 13/34 L6229 PWM current control Figure 10. Output current regulation waveforms IOUT VREF R SENSE tON tOFF tOFF VSENSE VREF 0 VRC Slow decay Slow decay tRCRISE tRCRISE 5V 2.5 V tRCFALL tRCFALL ON OFF SYNCHRONOUS RECTIFICATION B C D A B C D Figure 11 shows the magnitude of the off time tOFF versus COFF and ROFF values. It can be approximately calculated from the equations: tRCFALL = 0.6 ⋅ ROFF ⋅ COFF (1) tOFF = tRCFALL + tDT = 0.6 ⋅ ROFF ⋅ COFF + tDT where ROFF and COFF are the external component values and tDT is the internally generated deadtime with: 20kΩ ≤ ROFF ≤ 100 kΩ (2) 0.47 nF ≤ COFF ≤ 100 nF Therefore: tDT = 1μs tipical value tOFF MIN = 6.6 μs tOFF MAX = 6 ms (3) These values allow a sufficient range of tOFF to implement the drive circuit for most motors. The capacitor value chosen for COFF also affects the rise time tRCRISE of the voltage at the pin RCOFF. The rise time tRCRISE will only be an issue if the capacitor is not completely charged before the next time the monostable is triggered. Therefore, the on time tON, which depends by motors and supply parameters, has to be bigger than tRCRISE for allowing a good current regulation by the PWM stage. Furthermore, the on time tON cannot be smaller than the minimum on time tON(MIN). tON > tON MIN = 2.5μs tON > tRCRISE − tDT typ.value (4) tRCRISE = 600 ⋅ COFF DS3275 - Rev 7 page 14/34 L6229 PWM current control Figure 12 shows the lower limit for the on time tON for having a good PWM current regulation capacity. It has to be said that tON is always bigger than tON(MIN) because the device imposes this condition, but it can be smaller than tRCRISE - tDT. In this last case the device continues to work but the off time tOFF is not more constant. So, small COFF value gives more flexibility for the applications (allows smaller on time and, therefore, higher switching frequency), but, the smaller is the value for COFF, the more influential will be the noises on the circuit performance. Figure 11. tOFF versus COFF and ROFF 1 .10 4 R OFF = 10 1 .10 3 R OFF = 47 R OFF = 20 k 10 0 10 1 0.1 1 10 10 0 C OFF [nF] Figure 12. Area where tON can vary maintaining the PWM regulation 100 10 1.5 1 0. 1 1 10 10 0 C OFF [nF] DS3275 - Rev 7 page 15/34 L6229 Slow decay mode 9 Slow decay mode Figure 13 shows the operation of the bridge in the slow decay mode during the off time. At any time only two legs of the 3-phase bridge are active, therefore only the two active legs of the bridge are shown in Figure 13 and the third leg will be off. At the start of the off time, the lower power MOS is switched off and the current recirculates around the upper half of the bridge. Since the voltage across the coil is low, the current decays slowly. After the deadtime the upper power MOS is operated in the synchronous rectification mode reducing the impedance of the freewheeling diode and the related conducting losses. When the monostable times out, upper MOS that was operating the synchronous mode turns off and the lower power MOS is turned on again after some delay set by the deadtime to prevent cross conduction. Figure 13. Slow decay mode output stage configurations A) ON TIME DS3275 - Rev 7 C) SYNCHRONOUS RECTIFICATION page 16/34 L6229 Decoding logic 10 Decoding logic The decoding logic section is a combinatory logic that provides the appropriate driving of the 3-phase bridge outputs according to the signals coming from the three Hall effetct sensors that detect rotor position in a 3-phase BLDC motor. This novel combinatory logic discriminates between the actual sensors position for sensors spaced at 60, 120, 240 and 300 electrical degrees. This decoding method allows the implementation of a universal IC without dedicating pins to select the sensor configuration. There are eight possible input combinations for three sensor inputs. Six combinations are valid for rotor positions with 120 electrical degrees sensor phasing (see Figure 14, positions 1, 2, 3a, 4, 5 and 6a) and six combinations are valid for rotor positions with 60 electrical degrees phasing (see Figure 15, positions 1, 2, 3b, 4, 5 and 6b). Four of them are in common (1, 2, 4 and 5) whereas there are two combinations used only in 120 electrical degrees sensor phasing (3a and 6a) and two combinations used only in 60 electrical degrees sensor phasing (3b and 6b). The decoder can drive motors with different sensor configuration simply by following Table 7. For any input configuration (H1, H2 and H3) there is one output configuration (OUT1, OUT2 and OUT3). The output configuration 3a is the same as 3b and analogously output configuration 6a is the same as 6b. The sequence of the Hall codes for 300 electrical degrees phasing is the reverse of 60 and the sequence of the Hall codes for 240 phasing is the reverse of 120. So, by decoding the 60 and the 120 codes it is possible to drive the motor with all the four conventions by changing the direction set. Table 7. 60 and 120 electrical degree decoding logic in forward direction DS3275 - Rev 7 Hall 120° 1 2 3a - 4 5 6a - Hall 60° 1 2 - 3b 4 5 - 6b H1 H H L H L L H L H2 L H H H H L L L H3 L L L H H H H L OUT1 Vs High Z GND GND GND High Z Vs Vs OUT2 High Z Vs Vs Vs High Z GND GND GND OUT3 GND GND High Z High Z Vs Vs High Z High Z Phasing 1⇒3 2⇒3 2⇒1 2⇒1 3⇒1 3⇒2 1⇒2 1⇒2 page 17/34 L6229 Decoding logic Figure 14. 120° Hall sensor sequence H1 H3 H1 H2 1 =H H3 H1 H2 H3 2 H1 H2 3a H3 H1 H2 4 H3 H1 H2 5 H3 H2 6a =L Figure 15. 60° Hall sensor sequence H1 H1 H2 H3 DS3275 - Rev 7 H2 H3 1 =H H1 2 H1 H2 H3 3b H1 H2 H3 4 H1 H2 H3 5 H2 H3 6b =L page 18/34 L6229 Tachometer 11 Tachometer A tachometer function consists of a monostable, with constant off time (tPULSE), whose input is one Hall effect signal (H1). It allows developing an easy speed control loop by using an external op amp, as shown in Figure 16. For component values refer to Section 13 Application information. The monostable output drives an open drain output pin (TACHO). At each rising edge of the Hall effect sensors H1, the monostable is triggered and the MOSFET connected to pin TACHO is turned off for a constant time tPULSE (see Figure 17). The off time tPULSE can be set using the external RC network (RPUL, CPUL) connected to the pin RCPULSE. Figure 18 gives the relation between tPULSE and CPUL, RPUL. We have approximately: tPULSE = 0.6 ⋅ RPUL ⋅ CPUL (5) where CPUL should be chosen in the range from 1 nF to 100 nF and RPUL in the range from 20 kΩ to 100 kΩ. By connecting the tachometer pin to an external pull-up resistor, the output signal average value VM is proportional to the frequency of the Hall effect signal and, therefore, to the motor speed. This realizes a simple frequency-to-voltage converter. An op amp, configured as an integrator, filters the signal and compares it with a reference voltage VREF, which sets the speed of the motor. t VM = PULSE ⋅ VDD T (6) Figure 16. TACHO operation waveforms H1 H2 H3 VTACHO VDD VM t PULSE T DS3275 - Rev 7 page 19/34 L6229 Tachometer Figure 17. Tachometer speed control loop H1 RCP ULSE TACHO MONOST ABLE VDD R PU L C PU L R DD R3 TACHO C1 R4 VREF R1 VRE F C RE F2 C RE F1 R2 Figure 18. tPULSE versus CPUL and RPUL 4 1 .10 R PU L = 10 R PU L = 47 3 1 .10 tPULSE R PU L = 20 10 0 10 1 1 0 1 00 C PUL [nF] DS3275 - Rev 7 page 20/34 L6229 Non-dissipative overcurrent detection and protection 12 Non-dissipative overcurrent detection and protection The L6229 device integrates an “Overcurrent Detection” circuit (OCD) for full protection. This circuit provides output to output and output to ground short-circuit protection as well. With this internal overcurrent detection, the external current sense resistor normally used and its associated power dissipation are eliminated. Figure 19 shows a simplified schematic for the overcurrent detection circuit. To implement the overcurrent detection, a sensing element that delivers a small but precise fraction of the output current is implemented with each high-side power MOS. Since this current is a small fraction of the output current there is very little additional power dissipation. This current is compared with an internal reference current IREF. When the output current reaches the detection threshold (typically ISOVER = 2.8 A) the OCD comparator signals a fault condition. When a fault condition is detected, an internal open drain MOS with a pull down capability of 4 mA connected to pin DIAG is turned on. The pin DIAG can be used to signal the fault condition to a microcontroller or to shut down the 3-phase bridge simply by connecting it to pin EN and adding an external R-C (see REN, CEN). Figure 19. Overcurrent protection simplified schematic OUT 1 VS A HIGH-SIDE DMOS VDD R EN EN VS B HIGH-SIDE DMOS I2 POWER DMOS n cells OCD COMPARATOR OUT 3 HIGH-SIDE DMOS I1 POWER SENSE 1 cell TO GATE LOGIC OUT 2 + I1 / n POWER DMOS n cells I3 POWER SENSE 1 cell POWER DMOS n cells POWER SENSE 1 cell I2 / n I1 +I2 / n C EN DIAG INTERNAL OPEN DRAIN IREF OVERTEMPERATURE I3 / n IREF Figure 20 shows the overcurrent detection operation. The disable time tDISABLE before recovering normal operation can be easily programmed by means of the accurate thresholds of the logic inputs. It is affected whether by CEN and REN values and its magnitude is reported in Figure 21. The delay time tDELAY before turning off the bridge when an overcurrent has been detected depends only by CEN value. Its magnitude is reported in Figure 22. CEN is also used for providing immunity to pin EN against fast transient noises. Therefore the value of CEN should be chosen as big as possible according to the maximum tolerable delay time and the REN value should be chosen according to the desired disable time. The resistor REN should be chosen in the range from 2.2 kΩ to 180 kΩ. Recommended values for REN and CEN are respectively 100 kΩ and 5.6 nF that allow obtaining 200 μs disable time. DS3275 - Rev 7 page 21/34 L6229 Non-dissipative overcurrent detection and protection Figure 20. Overcurrent protection waveforms IOUT IS OVER ON BRIDGE OFF VDIAG 90% 10% tOCD(OFF) tOCD(ON) Figure 21. tDISABLE versus CEN and REN R E N = 2 2 0 kkΩ 3 1 .1 0 R EN = 100 k R E N = 4 7 kΩ k R EN = 33 k R EN = 10 k t DISABLE 1 00 10 1 1 1 0 1 00 C E N [n F ] DS3275 - Rev 7 page 22/34 L6229 Non-dissipative overcurrent detection and protection Figure 22. tDELAY versus CEN tDELAY 10 1 0.1 00 C EN [nF] DS3275 - Rev 7 page 23/34 L6229 Application information 13 Application information A typical application using the L6229 device is shown in Figure 23. Typical component values for the application are shown in Table 8. A high quality ceramic capacitor (C2) in the range of 100 nF to 200 nF should be placed between the power pins VSA and VSB and ground near the L6229 device to improve the high frequency filtering on the power supply and reduce high frequency transients generated by the switching. The capacitor (CEN) connected from the EN input to ground sets the shutdown time when an overcurrent is detected (see Section 12 Non-dissipative overcurrent detection and protection). The two current sensing inputs (SENSEA and SENSEB) should be connected to the sensing resistor RSENSE with a trace length as short as possible in the layout. The sense resistor should be non-inductive resistor to minimize the di/dt transients across the resistor. To increase noise immunity, unused logic pins are best connected to 5 V (high logic level) or GND (low logic level) see Table 4. It is recommended to keep power ground and signal ground separated on PCB. Table 8. Component values for typical application DS3275 - Rev 7 Component Value C1 100 µF C2 100 nF C3 220 nF CBOOT 220 nF COFF 1 nF CPUL 10 nF CREF1 33 nF CREF2 100 nF CEN 5.6 nF CP 10 nF D1 1N4148 D2 1N4148 R1 5.6 kΩ R2 1.8 kΩ R3 4.7 kΩ R4 1 MΩ RDD 1 kΩ REN 100 kΩ RP 100 Ω RSENSE 0.6 Ω ROFF 33 kΩ RPUL 47 kΩ RH1, RH2, RH3 10 Ω page 24/34 L6229 Output current capability and IC power dissipation Figure 23. Typical application VS A + VS 8 - 52 V DC C1 C2 VS B POWER GROUND - D1 VCP R SENSE SENSE SENSE 3-PHASE MOTOR A B OUT 1 HALL SENSOR +5 V OUT 2 M OUT 3 R H1 H1 R H2 H2 R H3 H3 GND 13.1 17 22 15 VREF + C REF2 - C REF1 R2 C3 DIAG 2 VBOOT R1 VREF 13 D2 C BOOT SIGNAL GROUND CP RP 20 R4 R EN EN 12 ENABLE C EN 3 11 10 14 5 21 BRAKE BRAKE 8 16 R3 FWD/REV FWD/REV TACHO C OFF R DD 1 23 RCOFF 4 5V R OFF C PUL 24 18 19 6 7 RCPULSE 9 R PUL Output current capability and IC power dissipation In Figure 24 is shown the approximate relation between the output current and the IC power dissipation using PWM current control. For a given output current the power dissipated by the IC can be easily evaluated, in order to establish which package should be used and how large must be the on-board copper dissipating area to guarantee a safe operating junction temperature (125 °C maximum). Figure 24. IC power dissipation versus output power I1 10 8 P D [W] I2 IOUT IOUT 6 I3 IOUT 4 2 0 Tes t c on dition s: S upp ly voltage = 24 V 0 0.25 0.5 0.75 IOUT [A] DS3275 - Rev 7 1 1.25 1.5 No P WM fS W = 30 kHz (s low de cay) page 25/34 L6229 Thermal management 13.2 Thermal management In most applications the power dissipation in the IC is the main factor that sets the maximum current that can be delivered by the device in a safe operating condition. Selecting the appropriate package and heatsinking configuration for the application is required to maintain the IC within the allowed operating temperature range for the application. Figure 25 and Figure 26 show the junction to ambient thermal resistance values for the PowerSO36 and SO24 packages. For instance, using a PowerSO package with a copper slug soldered on a 1.5 mm copper thickness FR4 board with a 6 cm2 dissipating footprint (copper thickness of 35 μm), the Rth(j-amb) is about 35 °C/W. Figure 26 shows mounting methods for this package. Using a multilayer board with vias to a ground plane, thermal impedance can be reduced down to 15 °C/W. Figure 25. PowerSO36 junction ambient thermal resistance versus on-board copper area º C/ W 43 38 33 Without ground layer 28 With ground layer 23 With ground layer + 16 via holes On-board copper area 18 13 1 2 3 4 5 6 7 8 9 10 11 12 13 s q . cm Figure 26. SO24 junction ambient thermal resistance versus on-board copper area º C/ W On-board copper area 68 66 64 62 Copper area is on top side 60 58 56 54 52 50 48 1 2 3 4 5 6 7 8 9 10 11 12 s q . cm Figure 27. Mounting the PowerSO package Slug soldered to PCB with dissipating area DS3275 - Rev 7 Slug soldered to PCB with dissipating area plus ground layer Slug soldered to PCB with dissipating area plus ground layer contacted through via holes page 26/34 L6229 Package information 14 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 14.1 PowerSO36 package information Figure 28. PowerSO36 package outline N N a2 e A DETAIL A A c a1 DETAIL B E e3 H DETAIL A lead D slug a3 36 BOTTOM VIEW 19 E3 B E1 E2 D1 DETAIL B 0.35 1 1 Gage Plane 8 -C - S h x 45 û DS3275 - Rev 7 b ⊕ 0.12 L SEATING PLANE G M AB C (COPLANARITY) page 27/34 L6229 PowerSO36 package information Table 9. PowerSO36 package mechanical data Dimensions mm Symbol inch Min. Typ. Max. Min. Typ. Max. A - - 3.60 - - 0.141 a1 0.10 - 0.30 0.004 - 0.012 a2 - - 3.30 - 0.130 a3 0 - 0.10 0 - 0.004 b 0.22 - 0.38 0.008 - 0.015 c 0.23 - 0.32 0.009 - 0.012 D (1) 15.80 - 16.00 0.622 - 0.630 D1 9.40 - 9.80 0.370 - 0.385 E 13.90 - 14.50 0.547 - 0.570 e - 0.65 - - 0.0256 - - 11.05 - - 0.435 - 10.90 - 11.10 0.429 - 0.437 E2 - - 2.90 - 0.114 E3 5.80 - 6.20 0.228 - 0.244 E4 2.90 - 3.20 0.114 - 0.126 G 0 - 0.10 0 - 0.004 H 15.50 - 15.90 0.610 - 0.626 h - - 1.10 - 0.043 L 0.80 - 1.10 - 0.043 e3 E1 (1) 0.031 N 10° (max.) S 8° (max.) 1. “D” and “E1” do not include mold flash or protrusions. DS3275 - Rev 7 • - Mold flash or protrusions shall not exceed 0.15 mm (0.006 inch) • - Critical dimensions are “a3”, “E” and “G”. page 28/34 L6229 SO24 package information 14.2 SO24 package information Figure 29. SO24 package outline Table 10. SO24 package mechanical data Symbol Dimensions (mm) Dimensions (inch) Min. Typ. Max. Min. Typ. Max. A 2.35 - 2.65 0.093 - 0.104 A1 0.10 - 0.30 0.004 - 0.012 B 0.33 - 0.51 0.013 - 0.020 C 0.23 - 0.32 0.009 - 0.013 15.20 - 15.60 0.598 - 0.614 E 7.40 - 7.60 0.291 - 0.299 e - 1.27 - - 0.050 - H 10.0 - 10.65 0.394 - 0.419 h 0.25 - 0.75 0.010 - 0.030 L 0.40 - 1.27 0.016 - 0.050 - 0.004 D (1) k ddd 0°(min.), 8° (max.) - - 0.10 - 1. “D” dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm per side. DS3275 - Rev 7 page 29/34 L6229 Revision hystory Date Revision Changes 1-Sep-2003 1 First issue 1-Jan-2004 2 Migration from ST-Press dms to EDOCS 1-Oct-2004 3 Updated the style graphic form Updated Section :Features on page 1 (removed section number from: Features, minor modifications). Updated Section : Description on page 1 (removed section number from:Description, removed “MultiPower-” from “MultiPower-BCD technology”). Added Contents on page 2. Updated Section 1: Blockdiagramonpage 3(added section title, renumbered Figure1:Block diagram ). Added title to Section 2:Maximum ratingson page 4. Added title to Section 3: Pin connections on page 6, renumbered Figure 2: Pin connections (top view), renumbered note 1below Figure 2. Added title to Section 4:Electricalcharacteristics onpage 8, renumbered notes 1 to4below Table 6, renumbered Figure 3and Figure 4. Renumbered Section 5:Circuitdescription onpage 11, Section 5.1 and Section5.2. Removed “and mC” fromfirst sentence in Section 5.2. Added header to Table7.Renumbered Figure 5 to Figure 8. Renumbered Section6:PWMcurrentcontrolonpage 13. Renumbered Figure9to 6-Mar-2014 4 Figure12. Numbered Equation 1 to Equation 4. Renumbered Section 7:Slowdecaymode on page 17and Figure 13. Renumbered Section 8:Decoding logicon page 18, Figure14and Figure 15. Renumbered and renamed Section 9: Tachometer on page 20, renumbered Figure16to Figure 18. Numbered Equation 5 and Equation 6. Renumbered Section 10:Non-dissipativeovercurrent detectionand protection on page 22, Figure 19to Figure22. Renumbered Section 11:Applicationinformation on page 25,Section 11.1 and Section 11.2. Added header to Table 9. Renumbered Figure 23 to Figure 28. Updated Section 12: Package information on page 29 (added main title and ECOPACK text. Added titles from Table 10: PowerSO36 package mechanical data toTable 12: SO24 package mechanical data and from Figure 29: PowerSO36 package outline to Figure 31: SO24 package outline, reversed order of named tables and figures. Removed 3D figures of packages. Replaced 0.200 by0.020 inch of max. B value in Table 12). Added cross-references throughout document. Added section number and title to Section13:Revisionhistory. Minor modifications throughout document 4-Oct-2018 5 4-Nov-2021 6 Removed PowerDIP24 package from the whole document. Removed “Tj“ from Table 3 Minor modifications throughout document Added Application section in cover page. Updated order codes, see Product status link / summary in cover page Updated VS Min. value in Table 2 1-Apr-2022 DS3275 - Rev 7 7 Updated Cover image page 30/34 L6229 Contents Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 Recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 5 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 6 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 7.1 Power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.2 Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8 PWM current control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 9 Slow decay mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 10 Decoding logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 11 Tachometer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 12 Non-dissipative overcurrent detection and protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 13 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 14 13.1 Output current capability and IC power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 13.2 Thermal management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 14.1 PowerSO36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 14.2 SO24 package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 List of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 DS3275 - Rev 7 page 31/34 L6229 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended operating condition . . . . . . . . . . . . . . . . . . . . Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . Charge pump external component values . . . . . . . . . . . . . . . . 60 and 120 electrical degree decoding logic in forward direction. Component values for typical application . . . . . . . . . . . . . . . . PowerSO36 package mechanical data . . . . . . . . . . . . . . . . . . SO24 package mechanical data . . . . . . . . . . . . . . . . . . . . . . DS3275 - Rev 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 . 4 . 5 . 6 . 8 11 17 24 28 29 page 32/34 L6229 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. DS3275 - Rev 7 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching characteristic definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overcurrent detection timing definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Charge pump circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic input internal structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin EN open collector driving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin EN push-pull driving. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM current controller simplified schematic. . . . . . . . . . . . . . . . . . . . . . . . . Output current regulation waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tOFF versus COFF and ROFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Area where tON can vary maintaining the PWM regulation . . . . . . . . . . . . . . . Slow decay mode output stage configurations . . . . . . . . . . . . . . . . . . . . . . . 120° Hall sensor sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60° Hall sensor sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TACHO operation waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tachometer speed control loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tPULSE versus CPUL and RPUL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overcurrent protection simplified schematic . . . . . . . . . . . . . . . . . . . . . . . . . Overcurrent protection waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tDISABLE versus CEN and REN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tDELAY versus CEN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC power dissipation versus output power . . . . . . . . . . . . . . . . . . . . . . . . . . PowerSO36 junction ambient thermal resistance versus on-board copper area . SO24 junction ambient thermal resistance versus on-board copper area . . . . . Mounting the PowerSO package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PowerSO36 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SO24 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 6 . 9 10 11 12 12 12 13 14 15 15 16 18 18 19 20 20 21 22 22 23 25 25 26 26 26 27 29 page 33/34 L6229 IMPORTANT NOTICE – READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2022 STMicroelectronics – All rights reserved DS3275 - Rev 7 page 34/34