EVAL6227PD

L6227 DMOS dual full bridge driver with PWM current controller Datasheet - production data  Thermal shutdown  Undervoltage lockout  Integrated fast freewheeling diodes Applications  Bipolar stepper motor  Dual DC motor 3RZHU62 Description The L6227 device is a DMOS dual full bridge designed for motor control applications, realized in BCD technology, which combines isolated DMOS power transistors with CMOS and bipolar circuits on the same chip. The device also includes two independent constant off time PWM current controllers that performs the chopping regulation. Available in PowerSO36 and SO24 (20 + 2 + 2) packages, the L6227 device features a non-dissipative overcurrent protection on the high-side power MOSFETs and thermal shutdown. 62  2UGHULQJQXPEHUV /13RZHU',3 /3'3RZHU62 /'62 Features  Operating supply voltage from 8 to 52 V  2.8 A output peak current (1.4 A DC)  RDS(ON) 0.73  typ. value at Tj = 25 °C  Operating frequency up to 100 KHz  Non-dissipative overcurrent protection  Dual independent constant tOFF PWM current controllers  Slow decay synchronous rectification  Cross conduction protection October 2018 This is information on a product in full production. DocID9453 Rev 3 1/31 www.st.com Contents L6227 Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.1 Power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 5.2 Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 6 PWM current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7 Slow decay mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8 9 10 2/31 7.1 Non-dissipative overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.2 Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.1 Output current capability and IC power dissipation . . . . . . . . . . . . . . . . . 24 8.2 Thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.1 PowerSO36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.2 SO24 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 DocID9453 Rev 3 L6227 1 Block diagram Block diagram Figure 1. Block diagram &+$5*( 3803 9%227 9%227 96$ 9%227 &855(17 /,0,7,1* 287$ 9 (1$ 287$ 9 ,1$ 6(16($ ,1$ 21( 6+27 5&$,1+ 0$6.,1* 7,0( 9WKH 95()$ %5,'*($ 92/7$*( 5(*8/$725 9 9 7+(50$/ 3527(&7,21 (1% 96% ,1% ,1% 287% %5,'*(% 287% 5&% 6(16(% 95()% ',19 DocID9453 Rev 3 3/31 31 Maximum ratings 2 L6227 Maximum ratings Table 1. Absolute maximum ratings Symbol Test conditions Value Unit VSA = VSB = VS 60 V VSA = VSB = VS = 60 V; VSENSEA = VSENSEB = GND 60 V VSA = VSB = VS VS + 10 V Input and enable voltage range - -0.3 to +7 V VREFA, VREFB Voltage range at pins VREFA and VREFB - -0.3 to +7 V VRCA, VRCB Voltage range at pins RCA and RCB - -0.3 to +7 V Voltage range at pins SENSEA and SENSEB - -1 to +4 V Pulsed supply current (for each VS pin), internally limited by the overcurrent protection VSA = VSB = VS; tPULSE < 1 ms 3.55 A RMS supply current (for each VS pin) VSA = VSB = VS 1.4 A - -40 to 150 C VS VOD VBOOT VIN, VEN VSENSEA, VSENSEB IS(peak) IS Tstg, TOP Parameter Supply voltage Differential voltage between VSA, OUT1A, OUT2A, SENSEA and VSB, OUT1B, OUT2B, SENSEB Bootstrap peak voltage Storage and operating temperature range Table 2. Recommended operating conditions Symbol VS VOD VREFA, VREFB VSENSEA, VSENSEB Parameter Test conditions Supply voltage Differential voltage between VSA, OUT1A, OUT2A, SENSEA and VSB, OUT1B, OUT2B, SENSEB Voltage range at pins VREFA and VREFB Voltage range at pins SENSEA and SENSEB Min. Max. Unit VSA = VSB = VS 8 52 V VSA = VSB = VS; VSENSEA = VSENSEB - 52 V - -0.1 5 V (pulsed tW < trr) (DC) -6 -1 6 1 V V IOUT RMS output current - - 1.4 A fsw Switching frequency - - 100 KHz 4/31 DocID9453 Rev 3 L6227 Maximum ratings Table 3. Thermal data Symbol Description SO24 PowerSO36 Unit 15 - C/W - 2 C/W 52 - C/W Rth-j-amb1 Maximum thermal resistance junction ambient(2) - 36 C/W (3) - 16 C/W (4) 78 63 C/W Rth-j-pins Maximum thermal resistance junction pins Rth-j-case Maximum thermal resistance junction case (1) Rth-j-amb1 Maximum thermal resistance junction ambient Rth-j-amb1 Maximum thermal resistance junction ambient Rth-j-amb2 Maximum thermal resistance junction ambient 1. Mounted on a multilayer FR4 PCB with a dissipating copper surface on the bottom side of 6 cm2 (with a thickness of 35 µm). 2. Mounted on a multilayer FR4 PCB with a dissipating copper surface on the top side of 6 cm2 (with a thickness of 35 µm). 3. Mounted on a multilayer FR4 PCB with a dissipating copper surface on the top side of 6 cm2 (with a thickness of 35 µm), 16 via holes and a ground layer. 4. Mounted on a multilayer FR4 PCB without any heat sinking surface on the board. DocID9453 Rev 3 5/31 31 Pin connections 3 L6227 Pin connections Figure 2. Pin connections (top view) ,1$ ,1$     *1'   *1' 1&   1& 95()$ 1&   1& (1$ 96$   96% 9&3 287$   287% 1&   1& 9&3   9%227 6(16($  5&$   287$ 287$   96$ (1$   (1% *1'   *1' 95()$   95()% *1'   *1' ,1$   ,1% 96% ,1$   ,1% 6(16($   6(16(% 5&$   5&% 1&   1& 287$   287% 1&   1& 1&   1& *1'   *1' 287% 5&%      287% 6(16(%   9%227 ,1%   (1% ,1%   95()% ',1 ',1 SO24 3RZHU' ,362 3RZHU62  1. The slug is internally connected to pins 1, 18, 19 and 36 (GND pins). Table 4. Pin description Package SO24 PowerSO36 Pin no. Pin no. 1 6/31 Name Type Function 10 IN1A Logic input Bridge A logic input 1. 2 11 IN2A Logic input Bridge A logic input 2. 3 12 SENSEA Power supply Bridge A source pin. This pin must be connected to power ground through a sensing power resistor. 4 13 RCA RC pin RC network pin. A parallel RC network connected between this pin and ground sets the current controller OFF-time of the bridge A. 5 15 OUT1A Power output Bridge A output 1. DocID9453 Rev 3 L6227 Pin connections Table 4. Pin description (continued) Package SO24 PowerSO36 Name Type Function Pin no. Pin no. 6, 7, 18, 19 1, 18, 19, 36 GND GND Signal ground terminals. In SO packages, these pins are also used for heat dissipation toward the PCB. 8 22 OUT1B Power output Bridge B output 1. 9 24 RCB RC pin RC network pin. A parallel RC network connected between this pin and ground sets the current controller OFF-time of the bridge B. 10 25 SENSEB Power supply Bridge B source pin. This pin must be connected to power ground through a sensing power resistor. 11 26 IN1B Logic input Bridge B input 1 12 27 IN2B Logic input Bridge B input 2 13 28 VREFB Analog input Bridge B current controller reference voltage. Do not leave this pin open or connect to GND. Logic input(1) Bridge B enable. LOW logic level switches OFF all power MOSFETs of bridge B. This pin is also connected to the collector of the overcurrent and thermal protection transistor to implement overcurrent protection. If not used, it has to be connected to +5 V through a resistor. 14 29 ENB 15 30 VBOOT Supply voltage 16 32 OUT2B Power output Bridge B output 2. 17 33 VSB Power supply Bridge B power supply voltage. It must be connected to the supply voltage together with pin VSA. 20 4 VSA Power supply Bridge A power supply voltage. It must be connected to the supply voltage together with pin VSB. 21 5 OUT2A Power output Bridge A output 2. 22 7 VCP Output Charge pump oscillator output. Bootstrap voltage needed for driving the upper power MOSFETs of both bridge A and bridge B. 23 8 ENA Logic input(1) Bridge A enable. LOW logic level switches OFF all power MOSFETs of bridge A. This pin is also connected to the collector of the overcurrent and thermal protection transistor to implement overcurrent protection. If not used, it has to be connected to +5 V through a resistor. 24 9 VREFA Analog input Bridge A current controller reference voltage. Do not leave this pin open or connect to GND. 1. Also connected at the output drain of the overcurrent and thermal protection MOSFET. Therefore, it has to be driven putting in series a resistor with a value in the range of 2.2 K - 180 K, recommended 100 K. DocID9453 Rev 3 7/31 31 Electrical characteristics 4 L6227 Electrical characteristics Table 5. Electrical characteristics (Tamb = 25 °C, Vs = 48 V, unless otherwise specified) Symbol Parameter Test conditions Min. Typ. Max. Unit VSth(ON) Turn-on threshold - 5.8 6.3 6.8 V VSth(OFF) Turn-off threshold - 5 5.5 6 V All bridges OFF; Tj = -25 °C to 125 °C(1) - 5 10 mA - - 165 - C Tj = 25 °C - 1.47 1.69 W Tj = 125 °C(1) - 2.35 2.7 W EN = low; OUT = VS - - 2 mA EN = low; OUT = GND -0.3 - - mA ISD = 1.4 A, EN = LOW - 1.15 1.3 V IS Tj(OFF) Quiescent supply current Thermal shutdown temperature Output DMOS transistors RDS(ON) IDSS High-side + low-side switch ON resistance Leakage current Source drain diodes VSD Forward ON voltage trr Reverse recovery time If = 1.4 A - 300 - ns tfr Forward recovery time - - 200 - ns VIL Low level logic input voltage - -0.3 - 0.8 V VIH High level logic input voltage - 2 - 7 V IIL Low level logic input current GND logic input voltage -10 - IIH High level logic input current 7 V logic input voltage - - 10 µA Logic input µA Vth(ON) Turn-on input threshold - - 1.8 2.0 V Vth(OFF) Turn-off input threshold - 0.8 1.3 - V Vth(HYS) Input threshold hysteresis - 0.25 0.5 - V Switching characteristics tD(on)EN Enable to out turn ON delay time(2) ILOAD = 1.4 A, resistive load 500 - 800 ns tD(on)IN Input to out turn ON delay time ILOAD = 1.4 A, resistive load (deadtime included) - 1.9 - µs Output rise time(2) ILOAD = 1.4 A, resistive load 40 250 ns tD(off)EN Enable to out turn OFF delay time(2) ILOAD = 1.4 A, resistive load 500 800 1000 ns tD(off)IN Input to out turn OFF delay time ILOAD = 1.4 A, resistive load 500 800 1000 ns tFALL (2) ILOAD = 1.4 A, resistive load 40 - 250 ns - 0.5 1 - µs -25 °C t ON  MIN  = 2.5s (typ. value)   t ON > t RCRISE – t DT Figure 12 shows the lower limit for the on time tON for having a good PWM current regulation capacity. It has to be said that tON is always bigger than tON(MIN) because the device imposes this condition, but it can be smaller than tRCRISE - tDT. In this last case the device continues to work but the off time tOFF is not more constant. So, small COFF value gives more flexibility for the applications (allows smaller on time and, therefore, higher switching frequency), but, the smaller is the value for COFF, the more influential will be the noises on the circuit performance. 16/31 DocID9453 Rev 3 L6227 PWM current control Figure 11. tOFF versus COFF and ROFF    52))    52))  W2)) > 5 2))       &2)) >Q)@ $0 Figure 12. Area where tON can vary maintaining the PWM regulation W V@ 21PLQ    W\SYDOXH    & >Q)@ 2)) $0 DocID9453 Rev 3 17/31 31 Slow decay mode 7 L6227 Slow decay mode Figure 13 shows the operation of the bridge in the slow decay mode. At the start of the off time, the lower power MOS is switched off and the current recirculates around the upper half of the bridge. Since the voltage across the coil is low, the current decays slowly. After the deadtime the upper power MOS is operated in the synchronous rectification mode. When the monostable times out, the lower power MOS is turned on again after some delay set by the deadtime to prevent cross conduction. Figure 13. Slow decay mode output stage configurations $217,0( ',19 7.1 &6Q)@ $0 7.2 Thermal protection In addition to the overcurrent protection, the L6227 device integrates a thermal protection for preventing the device destruction in case of junction overtemperature. It works sensing the die temperature by means of a sensible element integrated in the die. The device switches-off when the junction temperature reaches 165 °C (typ. value) with 15 °C hysteresis (typ. value). DocID9453 Rev 3 21/31 31 Application information 8 L6227 Application information A typical application using the L6227 device is shown in Figure 18. Typical component values for the application are shown in Table 3. A high quality ceramic capacitor in the range of 100 to 200 nF should be placed between the power pins (VSA and VSB) and ground near the L6227 to improve the high frequency filtering on the power supply and reduce high frequency transients generated by the switching. The capacitors connected from the ENA and ENB inputs to ground set the shutdown time for the bridge A and bridge B respectively when an overcurrent is detected (see Section 7.1: Non-dissipative overcurrent protection). The two current sensing inputs (SENSEA and SENSEB) should be connected to the sensing resistors with a trace length as short as possible in the layout. The sense resistors should be non-inductive resistors to minimize the di/dt transients across the resistor. To increase noise immunity, unused logic pins (except ENA and ENB) are best connected to 5 V (high logic level) or GND (low logic level) (see Table 4: Pin description on page 6). It is recommended to keep power ground and signal ground separated on the PCB. Table 8. Component values for typical application 22/31 Component Value C1 100 F C2 100 nF CA 1 nF CB 1 nF CBOOT 220 nF CP 10 nF CENA 5.6 nF CENB 5.6 nF CREFA 68 nF CREFB 68 nF D1 1N4148 D2 1N4148 RA 39 K RB 39 K RENA 100 K RENB 100 K RP 100  RSENSEA 0.6  RSENSEB 0.6  DocID9453 Rev 3 L6227 Application information Figure 18. Typical application  96 9'& 96$ & 32:(5 *5281'  6,*1$/ *5281' 96% &    95()$ 95()$ 9 95()% 95()% 9 &5()$ ' &%227  53 ' 9&3 9%227 56(16($ 6(16($ 56(16(% 6(16(% /2$'$ 287$ 287$ /2$'%  &3 287% 287% *1' *1' *1' *1'    &5()% (1$ 5(1$ (1% 5(1% (1$ (1% &(1$ &(1%          ,1%  &$ ,1$ 5&$ 5$ &%   5&% ',19 DocID9453 Rev 3 ,1$ ,1$   ,1% ,1$   ,1% ,1% 5% 23/31 31 Application information 8.1 L6227 Output current capability and IC power dissipation In Figure 19 and Figure 20 are shown the approximate relation between the output current and the IC power dissipation using PWM current control driving two loads, for two different driving types:  One full bridge ON at a time (Figure 19) in which only one load at a time is energized.  Two full bridges ON at the same time (Figure 20) in which two loads at the same time are energized. For a given output current and driving type the power dissipated by the IC can be easily evaluated, in order to establish which package should be used and how large must be the on-board copper dissipating area to guarantee a safe operating junction temperature (125 °C maximum). Figure 19. IC power dissipation versus output current with one full bridge ON at a time 21()8//%5,'*(21$7$7,0(  ,$  , 287 ,%  3'>:@ , 287  7HVWFRQGLWLRQV 6XSSO\YROWDJH 9         1R3:0 I6:  N+]VORZGHFD\  , 287>$@ $0 Figure 20. IC power dissipation versus output current with two full bridges ON at the same time 7:2)8//%5,'*(621$77+(6$0(7,0(   ,$ , 287 ,%  , 287 3'>: @  7HVWFRQGLW LRQV 6XSSO\YROWDJH 9          , 287 >$ @ 1R3:0 I6: N+]VORZGHFD\ $0 24/31 DocID9453 Rev 3 L6227 8.2 Application information Thermal management In most applications the power dissipation in the IC is the main factor that sets the maximum current that can be delivered by the device in a safe operating condition. Therefore, it has to be taken into account very carefully. Besides the available space on the PCB, the right package should be chosen considering the power dissipation. Heat sinking can be achieved using copper on the PCB with proper area and thickness. Figure 22 and 23 show the junction to ambient thermal resistance values for the PowerSO36 and SO24 packages. For instance, using a PowerSO package with a copper slug soldered on a 1.5 mm copper thickness FR4 board with a 6 cm2 dissipating footprint (copper thickness of 35 µm), the Rth j-amb is about 35 °C/W. Figure 21 shows mounting methods for this package. Using a multilayer board with vias to a ground plane, thermal impedance can be reduced down to 15 °C/W. Figure 21. Mounting the PowerSO package Slug soldered to PCB with dissipating area Slug soldered to PCB with dissipating area plus ground layer Slug soldered to PCB with dissipating area plus ground layer contacted through via holes Figure 22. PowerSO36 junction ambient thermal resistance versus on-board copper area ž & :    :LWKRXWJURXQGOD\HU  :LWKJURXQGOD\HU  :LWKJURXQGOD\HU YLDKROHV 2QERDUGFRSSHUDUHD                V T  FP $0 DocID9453 Rev 3 25/31 31 Application information L6227 Figure 23. SO24 junction ambient thermal resistance versus on-board copper area ž &:  2QERDUGFRSSHUDUHD    &RSSHUDUHD LVRQWRSVLGH                    V T  FP $0 26/31 DocID9453 Rev 3 L6227 9 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 9.1 PowerSO36 package information Figure 24. PowerSO36 package outline 1 1 D H $ '(7$,/ $ $ F D '(7$,/ % ( H + '(7$,/ $ OHDG ' VOXJ D  %277209,(:  ( % ( ( ' '(7$,/ %    *DJH3ODQH  &  6 K[€ E / 6($7,1*3/$1( * †  0 $% DocID9453 Rev 3 3620(& & &23/$1$5,7< 27/31 31 Package information L6227 Table 9. PowerSO36 package mechanical data Dimensions Symbol mm inch Min. Typ. Max. Min. Typ. Max. A - - 3.60 - - 0.141 a1 0.10 - 0.30 0.004 - 0.012 a2 - - 3.30 - - 0.130 a3 0 - 0.10 0 - 0.004 b 0.22 - 0.38 0.008 - 0.015 c 0.23 - 0.32 0.009 - 0.012 D(1) 15.80 - 16.00 0.622 - 0.630 D1 9.40 - 9.80 0.370 - 0.385 E 13.90 - 14.50 0.547 - 0.570 e - 0.65 - - 0.0256 - e3 - 11.05 - - 0.435 - 10.90 - 11.10 0.429 - 0.437 E2 - - 2.90 - - 0.114 E3 5.80 - 6.20 0.228 - 0.244 E4 2.90 - 3.20 0.114 - 0.126 G 0 - 0.10 0 - 0.004 H 15.50 - 15.90 0.610 - 0.626 h - - 1.10 - - 0.043 L 0.80 - 1.10 0.031 - 0.043 (1) E1 N 10° (max.) S 8° (max.) 1. “D” and “E1” do not include mold flash or protrusions. - Mold flash or protrusions shall not exceed 0.15 mm (0.006 inch). - Critical dimensions are “a3”, “E” and “G”. 28/31 DocID9453 Rev 3 L6227 9.2 Package information SO24 package information Figure 25. SO24 package outline  & Table 10. SO24 package mechanical data Dimensions (mm) Dimensions (inch) Symbol Min. Typ. Max. Min. Typ. Max. A 2.35 - 2.65 0.093 - 0.104 A1 0.10 - 0.30 0.004 - 0.012 B 0.33 - 0.51 0.013 - 0.020 C 0.23 - 0.32 0.009 - 0.013 D(1) 15.20 - 15.60 0.598 - 0.614 E 7.40 - 7.60 0.291 - 0.299 e - 1.27 - - 0.050 - H 10.0 - 10.65 0.394 - 0.419 h 0.25 - 0.75 0.010 - 0.030 L 0.40 - 1.27 0.016 - 0.050 - 0.004 k ddd 0° (min.), 8° (max.) - - 0.10 - 1. D” dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm per side. DocID9453 Rev 3 29/31 31 Revision history 10 L6227 Revision history Table 11. Document revision history 30/31 Date Revision Changes 03-Sep-2003 1 Initial release. 18-Feb-2014 2 Updated Section : Description on page 1 (removed “MultiPower-” from “MultiPower-BCD technology”. Added Contents on page 2. Updated Section 1: Block diagram (added section title, numbered and moved Figure 1: Block diagram to page 3. Added title to Section 2: Maximum ratings on page 4, added numbers and titles from Table 1: Absolute maximum ratings to Table 3: Thermal data. Added title to Section 3: Pin connections on page 6, added number and title to Figure 2: Pin connections (top view), renumbered note 1 below Figure 2, added title to Table 4: Pin description, renumbered note 1 below Table 4. Added title to Section 4: Electrical characteristics on page 8, added title and number to Table 5, renumbered notes 1 to 4 below Table 5. Renumbered Figure 3 and Figure 4. Added title numbers to Section 5: Circuit description on page 11 (including Section 5.1 to Section 5.2). Removed “and C” from first sentence of Section 5.2. Renumbered Table 6 and Table 7, added header to Table 6 and Table 7. Renumbered Figure 5 to Figure 8. Added title numbers to Section 6: PWM current control on page 14. Renumbered Figure 9 to Figure 12. Added titles to Equation 1: on page 16 till Equation 4: on page 16. Added title numbers to Section 7: Slow decay mode on page 18 (including Section 7.1 and Section 7.2). Renumbered Figure 13 to Figure 17. Added title numbers to Section 8: Application information on page 22 (including Section 8.1 and Section 8.2). Renumbered Table 8, added header to Table 8. Renumbered Figure 18 to Figure 24. Updated Section 9: Package information on page 27 (added main title and ECOPACK text. Added titles from Table 9: PowerSO36 package mechanical data to Table 11: SO24 package mechanical data and from Figure 25: PowerSO36 package outline to Figure 27: SO24 package outline, reversed order of named tables and figures. Removed 3D figures of packages, replaced 0.200 by 0.020 inch of max. B value in Table 11). Added cross-references throughout document. Added Section 10: Revision history and Table 12. Minor modifications throughout document. 03-Oct-2018 3 Removed PowerDIP24 package from the whole document. Removed “Tj“ from Table 2 on page 4. Minor modifications throughout document. DocID9453 Rev 3 L6227 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2018 STMicroelectronics – All rights reserved DocID9453 Rev 3 31/31 31