L6227Q_09

L6227Q DMOS dual full bridge driver with PWM current controller Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Operating supply voltage from 8 to 52 V 2.8 A output peak current (1.4 A DC) RDS(on) 0.73 Ω typ. value @ TJ = 25 °C Operating frequency up to 100 kHz Non dissipative overcurrent protection Dual independent constant tOFF PWM current controllers Slow decay synchronous rectification Cross conduction protection Thermal shutdown Under voltage lockout Integrated fast free wheeling diodes VFQFPN32 5 mm x 5 mm Description The L6227Q is a DMOS dual full bridge designed for motor control applications, realized in BCDmultipower technology, which combines isolated DMOS power transistors with CMOS and bipolar circuits on the same chip. The device also includes two independent constant off time PWM current controllers that performs the chopping regulation. Available in VQFPN32 5 mm x 5 mm package, the L6227Q features a non-dissipative overcurrent protection on the high side power MOSFETs and thermal shutdown. Applications ■ ■ Bipolar stepper motor Dual or quad DC motor Block diagram VBOOT VBOOT Figure 1. VBOOT VCP CHARGE PUMP OCDA OVER CURRENT DETECTION 10V VBOOT VSA OUT1A 10V OUT2A THERMAL PROTECTION ENA IN1A IN2A VOLTAGE REGULATOR GATE LOGIC SENSEA PWM ONE SHOT MONOSTABLE MASKING TIME + SENSE COMPARATOR BRIDGE A OVER CURRENT DETECTION VSB VREFA RCA 10V 5V OCDB OUT1B OUT2B SENSEB VREFB RCB BRIDGE B ENB IN1B IN2B GATE LOGIC D99IN1085A January 2009 Rev 3 1/27 www.st.com 27 Contents L6227Q Contents 1 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 1.2 1.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 3 4 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1 4.2 4.3 4.4 4.5 4.6 4.7 Power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 PWM current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Slow decay mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Non-dissipative overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 6 7 8 9 10 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Output current capability and IC power dissipation . . . . . . . . . . . . . . 21 Thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2/27 L6227Q Electrical data 1 1.1 Table 1. Symbol VS VOD VBOOT VIN,VEN Electrical data Absolute maximum ratings Absolute maximum ratings Parameter Supply voltage Differential voltage between VSA, OUT1A, OUT2A, SENSEA and VSB, OUT1B, OUT2B, SENSEB Bootstrap peak voltage Input and enable voltage range Voltage range at pins VREFA and VREFB Voltage range at pins RCA and RCB Voltage range at pins SENSEA and SENSEB Pulsed supply current (for each VS pin), internally limited by the overcurrent protection VSA = VSB = VS; tPULSE < 1 ms Parameter VSA = VSB = VS VSA = VSB = VS = 60 V; VSENSEA = VSENSEB = GND VSA = VSB = VS Value 60 60 VS + 10 -0.3 to +7 -0.3 to +7 -0.3 to +7 -1 to +4 Unit V V V V V V V VREFA, VREFB VRCA, VRCB VSENSEA, VSENSEB IS(peak) IS Tstg, TOP 3.55 1.4 -40 to 150 A A °C RMS supply current (for each VS pin) VSA = VSB = VS Storage and operating temperature range 1.2 Table 2. Symbol VS VOD Recommended operating conditions Recommended operating conditions Parameter Supply voltage Differential voltage between VSA, OUT1A, OUT2A, SENSEA and VSB, OUT1B, OUT2B, SENSEB Voltage range at pins VREFA and VREFB Voltage range at pins SENSEA and SENSEB RMS output current Operating junction temperature Switching frequency -25 (pulsed tW < trr) (DC) Parameter VSA = VSB = VS VSA = VSB = VS; VSENSEA = VSENSEB -0.1 -6 -1 Min 8 Max 52 52 Unit V V VREFA, VREFB VSENSEA, VSENSEB IOUT TJ fsw 5 6 1 1.4 +125 100 V V V A °C kHz 3/27 Electrical data L6227Q 1.3 Thermal data Table 3. Symbol Rth(JA) Thermal data Parameter Thermal resistance junction-ambient max (1). 2 Value 42 Unit ° C/W 1. Mounted on a double-layer FR4 PCB with a dissipating copper surface of 0.5 cm on the top side plus 6 cm2 ground layer connected through 18 via holes (9 below the IC). 4/27 L6227Q Pin connection 2 Pin connection Figure 2. Pin connection (top view) Note: 1 2 The pins 2 to 8 are connected to die PAD The die PAD must be connected to GND pin 5/27 Pin connection L6227Q Table 4. N° 1, 21 9 11 12 13 14 15 Pin description Pin GND OUT1B RCB SENSEB IN1B IN2B VREFB Type GND Signal ground terminals. Function Power output Bridge B output 1. RC pin Power supply Logic input Logic input Analog input RC network pin. A parallel RC network connected between this pin and ground sets the current controller OFF-time of the bridge B. Bridge B source pin. This pin must be connected to power ground through a sensing power resistor. Bridge B input 1 Bridge B input 2 Bridge B current controller reference voltage. Do not leave this pin open or connect to GND. 16 ENB Bridge B enable. LOW logic level switches OFF all power MOSFETs of bridge B. This pin is also connected to the collector of the overcurrent and thermal Logic input (1) protection transistor to implement over current protection. If not used, it has to be connected to +5 V through a resistor. Supply voltage Bootstrap voltage needed for driving the upper power MOSFETs of both bridge A and Bridge B. 17 19 20 22 23 24 VBOOT OUT2B VSB VSA OUT2A VCP Power output Bridge B output 2. Power supply Power supply Bridge B power supply voltage. It must be connected to the supply voltage together with pin VSA. Bridge A power supply voltage. It must be connected to the supply voltage together with pin VSB. Power output Bridge A output 2. Output Charge pump oscillator output. 25 ENA Bridge A enable. LOW logic level switches OFF all power MOSFETs of bridge A. This pin is also connected to the collector of the overcurrent and thermal Logic input (1) protection transistor to implement over current protection. If not used, it has to be connected to +5 V through a resistor. Analog input Logic input Logic input Power supply RC pin Bridge A current controller reference voltage. Do not leave this pin open or connect to GND. Bridge A logic input 1. Bridge A logic input 2. Bridge A source pin. This pin must be connected to power ground through a sensing power resistor. RC network pin. A parallel RC network connected between this pin and ground sets the current controller OFF-time of the bridge A. 26 27 28 29 30 31 VREFA IN1A IN2A SENSEA RCA OUT1A Power output Bridge A output 1. 1. Also connected at the output drain of the over current and thermal protection MOSFET. Therefore, it has to be driven putting in series a resistor with a value in the range of 2.2 kΩ - 180 kΩ, recommended 100 kΩ. 6/27 L6227Q Electrical characteristics 3 Table 5. Symbol VSth(ON) VSth(OFF) IS TJ(OFF) Electrical characteristics Electrical characteristics (TA = 25 °C, Vs = 48 V, unless otherwise specified) Parameter Turn-on threshold Turn-off threshold Quiescent supply current Thermal shutdown temperature All Bridges OFF; TJ = -25 °C to 125 °C (1) Test condition Min 5.8 5 Typ 6.3 5.5 5 165 Max 6.8 6 10 Unit V V mA °C Output DMOS transistors RDS(on) IDSS High-side + low-side switch ON resistance Leakage current TJ = 25 ° C TJ =125 ° C (1) EN = Low; OUT = VS EN = Low; OUT = GND -0.3 1.47 2.35 1.69 2.7 2 Ω Ω mA mA Source drain diodes VSD trr tfr Logic input VIL VIH IIL IIH Vth(ON) Vth(OFF) Vth(HYS) Low level logic input voltage High level logic input voltage Low level logic input current High level logic input current Turn-on input threshold Turn-off input threshold Input threshold hysteresis 0.8 0.25 GND logic input voltage 7 V logic input voltage 1.8 1.3 0.5 -0.3 2 -10 10 2.0 0.8 7 V V µA µA V V V Forward ON voltage Reverse recovery time Forward recovery time ISD = 1.4 A, EN = LOW If = 1.4 A 1.15 300 200 1.3 V ns ns Switching characteristics tD(on)EN tD(on)IN tRISE tD(off)EN tD(off)IN tFALL tdt fCP Enable to out turn ON delay time (2) Input to out turn ON delay time Output rise time(2) Enable to out turn OFF delay time (2) Input to out turn OFF delay time Output fall time (2) ILOAD =1.4 A, resistive load ILOAD =1.4 A, resistive load (dead time included) ILOAD =1.4 A, resistive load ILOAD =1.4 A, resistive load ILOAD =1.4 A, resistive load ILOAD =1.4 A, resistive load 500 1.9 40 500 500 40 0.5 1 0.6 800 800 800 ns µs 250 1000 1000 250 ns ns ns ns µs Dead time protection Charge pump frequency -25 °C < TJ < 125 °C 1 MHz 7/27 Electrical characteristics Table 5. Symbol L6227Q Electrical characteristics (continued) (TA = 25 °C, Vs = 48 V, unless otherwise specified) Parameter Test condition Min Typ Max Unit PWM comparator and monostable IRCA, IRCB Voffset tPROP tBLANK tON(MIN) tOFF IBIAS Source current at pins RCA and RCB Offset voltage on sense comparator Turn OFF propagation delay (3) VRCA = VRCB = 2.5 V VREFA, VREFB = 0.5 V 3.5 5.5 ±5 500 1 2.5 3 mA mV ns µs µs µs µs 10 µA Internal blanking time on SENSE pins Minimum on time PWM recirculation time Input bias current at pins VREFA and VREFB ROFF = 20 kΩ; COFF = 1 nF ROFF = 100 kΩ; COFF = 1 nF 13 61 Over current protection ISOVER ROPDR tOCD(ON) tOCD(OFF) Input supply overcurrent protection threshold Open drain ON resistance OCD turn-on delay time OCD turn-off delay time (4) (4) TJ = -25 °C to 125 °C (1) I = 4 mA I = 4 mA; CEN < 100 pF I = 4 mA; CEN < 100 pF 2.8 40 200 100 60 A Ω ns ns 1. Tested at 25 °C in a restricted range and guaranteed by characterization. 2. See Figure 3 on page 9 3. Measured applying a voltage of 1 V to pin SENSE and a voltage drop from 2 V to 0 V to pin VREF. 4. See Figure 4 on page 9 8/27 L6227Q Figure 3. Switching characteristic definition EN Electrical characteristics Vth(ON) Vth(OFF) t IOUT 90% 10% D01IN1316 t tFALL tD(OFF)EN tD(ON)EN tRISE Figure 4. Overcurrent detection timing definition IOUT ISOVER ON BRIDGE OFF VEN 90% 10% tOCD(ON) tOCD(OFF) D02IN1399 9/27 Circuit description L6227Q 4 4.1 Circuit description Power stages and charge pump The L6227Q integrates two independent power MOS Full Bridges. Each power MOS has an RDS(on) = 0.73 Ω (typical value @ 25 °C), with intrinsic fast freewheeling diode. Cross conduction protection is achieved using a dead time (td = 1 µs typical) between the switch off and switch on of two power MOS in one leg of a bridge. Using N-channel power MOS for the upper transistors in the bridge requires a gate drive voltage above the power supply voltage. The bootstrapped (VBOOT) supply is obtained through an internal oscillator and few external components to realize a charge pump circuit as shown in Figure 5. The oscillator output (VCP) is a square wave at 600 kHz (typical) with 10 V amplitude. Recommended values/part numbers for the charge pump circuit are shown in Table 6. Table 6. Charge pump external components values Component CBOOT CP D1 D2 220 nF 10 nF 1N4148 1N4148 Value Figure 5. Charge pump circuit VS D1 D2 CBOO T CP VCP VBOO T VS A VS B D01IN1328 10/27 L6227Q Circuit description 4.2 Logic inputs Pins IN1A, IN2B, IN1B and IN2B are TTL/CMOS and microcontroller compatible logic inputs. The internal structure is shown in Figure 6. Typical value for turn-on and turn-off thresholds are respectively Vthon = 1.8 V and Vthoff = 1.3 V. Pins ENA and ENB have identical input structure with the exception that the drains of the Overcurrent and thermal protection MOSFETs (one for the bridge A and one for the bridge B) are also connected to these pins. Due to these connections some care needs to be taken in driving these pins. The ENA and ENB inputs may be driven in one of two configurations as shown in Figure 7 or Figure 8. If driven by an open drain (collector) structure, a pull-up resistor REN and a capacitor CEN are connected as shown in Figure 7. If the driver is a standard push-pull structure the resistor REN and the capacitor CEN are connected as shown in Figure 8. The resistor REN should be chosen in the range from 2.2 kΩ to 180 kΩ Recommended values for REN and CEN are respectively 100 kΩ and 5.6 nF. . More information on selecting the values is found in the overcurrent protection section. Figure 6. Logic inputs internal structure 5V ESD PROTECTION D01IN1329 Figure 7. ENA and ENB pins open collector driving 5V REN OPEN COLLECTOR OUTPUT EN CEN ESD PROTECTION D01IN1330 5V Figure 8. ENA and ENB pins push-pull driving 5V REN PUSH-PULL OUTPUT EN CEN ESD PROTECTION D01IN1331 11/27 Circuit description L6227Q 4.3 Truth table Table 7. Truth table Inputs EN L H H H H IN1 X (2) L H L H IN2 X L L H H OUT1 High Z (3) GND Vs GND (Vs) (4) Vs Outputs OUT2 High Z GND GND (Vs) Vs Vs Disable Brake mode (lower path) Forward Reverse Brake mode (upper path) Description (1) 1. Valid only in case of load connected between OUT1 and OUT2 2. X = don't care 3. High Z = high impedance output 4. GND (Vs) = GND during Ton, Vs during Toff 4.4 PWM current control The L6227Q includes a constant off time PWM current controller for each of the two bridges. The current control circuit senses the bridge current by sensing the voltage drop across an external sense resistor connected between the source of the two lower power MOS transistors and ground, as shown in Figure 9. As the current in the load builds up the voltage across the sense resistor increases proportionally. When the voltage drop across the sense resistor becomes greater than the voltage at the reference input (VREFA or VREFB) the sense comparator triggers the monostable switching the low-side MOS off. The low-side MOS remain off for the time set by the monostable and the motor current recirculates in the upper path. When the monostable times out the bridge will again turn on. Since the internal dead time, used to prevent cross conduction in the bridge, delays the turn on of the power MOS, the effective off time is the sum of the monostable time plus the dead time. Figure 9. PWM current controller simplified schematic 12/27 L6227Q Circuit description Figure 10 shows the typical operating waveforms of the output current, the voltage drop across the sensing resistor, the RC pin voltage and the status of the bridge. Immediately after the low-side power MOS turns on, a high peak current flows through the sensing resistor due to the reverse recovery of the freewheeling diodes. The L6227Q provides a 1 µs blanking time tBLANK that inhibits the comparator output so that this current spike cannot prematurely re-trigger the monostable. Figure 10. Output current regulation waveforms IOUT VREF RSENSE tOFF 1µs tBLANK tON tOFF 1µs tBLANK VSENSE VREF 0 Slow Decay c Fast De ay Slow Decay c Fast De ay VRC 5V 2.5V tRCRISE tRCRISE tRCFALL 1µs tDT ON SYNCHRONOUS OR QUASI SYNCHRONOUS RECTIFICATION D01IN1334 tRCFALL 1µs tDT OFF B C D A B C D Figure 11 shows the magnitude of the off time tOFF versus COFF and ROFF values. It can be approximately calculated from the equations: tRCFALL = 0.6 · ROFF · COFF tOFF = tRCFALL + tDT = 0.6 · ROFF · COFF + tDT where ROFF and COFF are the external component values and tDT is the internally generated Dead Time with: 20 kΩ ≤ROFF ≤100 kΩ 0.47 nF ≤COFF ≤100 nF tDT = 1 µs (typical value) Therefore: tOFF(MIN) = 6.6 µs tOFF(MAX) = 6 ms 13/27 Circuit description L6227Q These values allow a sufficient range of tOFF to implement the drive circuit for most motors. The capacitor value chosen for COFF also affects the rise time tRCRISE of the voltage at the pin RCOFF. The rise time tRCRISE will only be an issue if the capacitor is not completely charged before the next time the monostable is triggered. Therefore, the on time tON, which depends by motors and supply parameters, has to be bigger than tRCRISE for allowing a good current regulation by the PWM stage. Furthermore, the on time tON can not be smaller than the minimum on time tON(MIN). ⎧ t ON > t ON ( MIN ) = 2.5 µs ⎨ ⎩ t ON > t TCRISE – t DT + W tRCRISE = 600 · COFF Figure 12 on page 15 shows the lower limit for the on time tON for having a good PWM current regulation capacity. It has to be said that tON is always bigger than tON(MIN) because the device imposes this condition, but it can be smaller than tRCRISE - tDT. In this last case the device continues to work but the off time tOFF is not more constant. So, small COFF value gives more flexibility for the applications (allows smaller on time and, therefore, higher switching frequency), but, the smaller is the value for COFF, the more influential will be the noises on the circuit performance. Figure 11. tOFF versus COFF and ROFF 1 .10 4 R off = 100kΩ 3 1 .10 R off = 47kΩ R off = 20kΩ toff [µs] 100 10 1 0.1 1 Coff [nF] 10 100 14/27 L6227Q Circuit description Figure 12. Area where tON can vary maintaining the PWM regulation 100 ton(min) [µs] 10 1.5µs (typ. value) 1 0.1 1 Coff [nF] 10 100 4.5 Slow decay mode Figure 13 shows the operation of the bridge in the slow decay mode. At the start of the off time, the lower power MOS is switched off and the current recirculates around the upper half of the bridge. Since the voltage across the coil is low, the current decays slowly. After the dead time the upper power MOS is operated in the synchronous rectification mode. When the monostable times out, the lower power MOS is turned on again after some delay set by the dead time to prevent cross conduction. Figure 13. Slow decay mode output stage configurations 15/27 Circuit description L6227Q 4.6 Non-dissipative overcurrent protection The L6227Q integrates an overcurrent detection circuit (OCD). This circuit provides protection against a short circuit to ground or between two phases of the bridge. With this internal over current detection, the external current sense resistor normally used and its associated power dissipation are eliminated. Figure 14 shows a simplified schematic of the overcurrent detection circuit. To implement the over current detection, a sensing element that delivers a small but precise fraction of the output current is implemented with each high side power MOS. Since this current is a small fraction of the output current there is very little additional power dissipation. This current is compared with an internal reference current IREF. When the output current in one bridge reaches the detection threshold (typically 2.8 A) the relative OCD comparator signals a fault condition. When a fault condition is detected, the EN pin is pulled below the turn off threshold (1.3 V typical) by an internal open drain MOS with a pull down capability of 4 mA. By using an external R-C on the EN pin, the off time before recovering normal operation can be easily programmed by means of the accurate thresholds of the logic inputs. Figure 14. Overcurrent protection simplified schematic OUT1A POWER SENSE 1 cell I1A POWER DMOS n cells I2A POWER DMOS n cells POWER SENSE 1 cell VSA OUT2A HIGH SIDE DMOSs OF THE BRIDGE A TO GATE LOGIC µC or LOGIC + OCD COMPARATOR I1A / n (I1A+I2A) / n I2A / n VDD REN. CEN. EN RDS(ON) 40Ω TYP. INTERNAL OPEN-DRAIN IREF OVER TEMPERATURE OCD COMPARATOR FROM THE BRIDGE B D01IN1337 Figure 15 shows the overcurrent detection operation. The disable time tDISABLE before recovering normal operation can be easily programmed by means of the accurate thresholds of the logic inputs. It is affected whether by CEN and REN values and its magnitude is reported in Figure 16. The delay time tDELAY before turning off the bridge when an overcurrent has been detected depends only by CEN value. Its magnitude is reported in Figure 17. CEN is also used for providing immunity to pin EN against fast transient noises. Therefore the value of CEN should be chosen as big as possible according to the maximum tolerable delay time and the REN value should be chosen according to the desired disable time. The resistor REN should be chosen in the range from 2.2 kΩ to 180 kΩ. Recommended values for REN and CEN are respectively 100 kΩ and 5.6 nF that allow obtaining 200 µs disable time. 16/27 L6227Q Figure 15. Overcurrent protection waveforms IOUT ISOVER Circuit description VEN VDD Vth(ON) Vth(OFF) VEN(LOW) ON OCD OFF ON BRIDGE OFF tOCD(ON) tEN(FALL) tD(OFF)EN tOCD(OFF) tEN(RISE) tD(ON)EN D02IN1400 tDELAY tDISABLE Figure 16. tDISABLE versus CEN and REN (VDD = 5 V) 3 1 .1 0 R EN = 220 kΩ R EN = 100 kΩ R EN = 47 kΩ R EN = 33 kΩ R EN = 10 kΩ tDISABLE [µs] 100 10 1 1 10 100 C E N [n F ] 17/27 Circuit description Figure 17. tDELAY versus CEN (VDD = 5 V) 10 L6227Q tdelay [µs] 1 0.1 1 10 Cen [nF] 100 4.7 Thermal protection In addition to the ovecurrent protection, the L6227Q integrates a thermal protection for preventing the device destruction in case of junction over temperature. It works sensing the die temperature by means of a sensible element integrated in the die. The device switch-off when the junction temperature reaches 165 °C (typ. value) with 15 °C hysteresis (typ. value). 18/27 L6227Q Application information 5 Application information A typical application using L6227Q is shown in Figure 18. Typical component values for the application are shown in Table 8. A high quality ceramic capacitor in the range of 100 to 200 nF should be placed between the power pins (VSA and VSB) and ground near the L6227Q to improve the high frequency filtering on the power supply and reduce high frequency transients generated by the switching. The capacitors connected from the ENA and ENB inputs to ground set the shut down time for the bridge A and bridge B respectively when an over current is detected (see overcurrent protection). The two current sensing inputs (SENSEA and SENSEB) should be connected to the sensing resistors with a trace length as short as possible in the layout. The sense resistors should be non-inductive resistors to minimize the dI/dt transients across the resistor. To increase noise immunity, unused logic pins (except ENA and ENB) are best connected to 5 V (high logic level) or GND (low logic level) (see pin description). It is recommended to keep power ground and signal ground separated on PCB. Table 8. Component values for typical application Component C1 C2 CA CB CBOOT CP CENA CENB CREFA CREFB D1 D2 RA RB RENA RENB RSENSEA RSENSEB Value 100 µF 100 nF 1 nF 1 nF 220 nF 10 nF 5.6 nF 5.6 nF 68 nF 68 nF 1N4148 1N4148 39 kΩ 39 kΩ 100 kΩ 100 kΩ 0.6 Ω 0.6 Ω 19/27 Application information Figure 18. Typical application L6227Q Note: To reduce the IC thermal resistance, therefore improve the dissipation path, the NC pins can be connected to GND. 20/27 L6227Q Output current capability and IC power dissipation 6 Output current capability and IC power dissipation In Figure 19 and Figure 20 are shown the approximate relation between the output current and the IC power dissipation using PWM current control driving two loads, for two different driving types: – – One full bridge ON at a time (Figure 19) in which only one load at a time is energized. Two full bridges ON at the same time (Figure 20) in which two loads at the same time are energized. For a given output current and driving type the power dissipated by the IC can be easily evaluated, in order to establish which package should be used and how large must be the on-board copper dissipating area to guarantee a safe operating junction temperature (125 °C maximum). Figure 19. IC power dissipation vs output current with one full bridge ON at a time ONE FULL BRIDGE ON AT A TIME 10 8 IA IB I OUT 6 PD [W] 4 2 0 I OUT Test Conditions: Supply Voltage = 24V 0 0.25 0.5 0.75 1 1.25 1.5 No PW M fSW = 3 0 kHz (slow decay) I OUT [A] Figure 20. IC power dissipation versus output current with two full bridges ON at the same time TWO FULL BRIDGES ON AT THE SAME TIME IA 10 8 6 I OUT IB I OUT PD [W ] 4 2 0 Test Conditions: Supply Volt age =24 V 0 0.25 0.5 0.75 1 1.25 1.5 I OUT [A ] No PWM f SW = 30 kHz (slow decay) 21/27 Thermal management L6227Q 7 Thermal management In most applications the power dissipation in the IC is the main factor that sets the maximum current that can be delivered by the device in a safe operating condition. Therefore, it has to be taken into account very carefully. Besides the available space on the PCB, the right package should be chosen considering the power dissipation. Heat sinking can be achieved using copper on the PCB with proper area and thickness. For instance, using a VFQFPN32L 5x5 package the typical Rth(JA) is about 42 °C/W when mounted on a double-layer FR4 PCB with a dissipating copper surface of 0.5 cm2 on the top side plus 6 cm2 ground layer connected through 18 via holes (9 below the IC). 22/27 L6227Q Package mechanical data 8 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Table 9. VFQFPN32 5x5x1.0 pitch 0.50 Databook (mm) Dim. Min A b b1 D D2 D3 E E2 E3 e L ddd 0.30 0.80 0.18 0.165 4.85 3.00 1.10 4.85 4.20 0.60 Typ 0.85 0.25 0.175 5.00 3.10 1.20 5.00 4.30 0.70 0.50 0.40 0.50 0.08 Max 0.95 0.30 0.185 5.15 3.20 1.30 5.15 4.40 0.80 Note: 1 2 VFQFPN stands for thermally enhanced very thin profile fine pitch quad flat package no lead. Very thin profile: 0.80 < A = 1.00 mm. Details of terminal 1 are optional but must be located on the top surface of the package by using either a mold or marked features. 23/27 Package mechanical data Figure 21. Package dimensions L6227Q 24/27 L6227Q Order codes 9 Order codes Table 10. Order code Order code L6227Q Package VFQFPN32 5 x 5 x 1.0 mm Packaging Tube 25/27 Revision history L6227Q 10 Revision history Table 11. Date 07-Dec-2007 10-Jun-2008 28-Jan-2009 Document revision history Revision 1 2 3 First release Updated: Figure 18 on page 20 Added: Note 1 on page 4 Updated value in Table 3: Thermal data on page 4 Changes 26/27 L6227Q Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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