L6564

L6564 10 pin transition-mode PFC controller Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Fast “bidirectional” input voltage feedforward (1/V2 correction) Accurate adjustable output overvoltage protection Protection against feedback loop disconnection (latched shutdown) Inductor saturation protection AC brownout detection Low (≤100 µA) start-up current 6 mA max. operating bias current 1% (@ TJ = 25 °C) internal reference voltage -600/+800 mA totem pole gate driver with active pull-down during UVLO SSOP10 package SSOP10 Applications PFC pre-regulators for: ■ ■ ■ High-end AC-DC adapter/charger Desktop PC, server, Web server IEC61000-3-2 or JEITA-MITI compliant SMPS Figure 1. Block diagram September 2009 Doc ID 16202 Rev 1 1/34 www.st.com 34 Contents L6564 Contents 1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 2.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 4 5 6 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Typical electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1 6.2 6.3 6.4 6.5 6.6 Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Feedback failure protection (FFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Voltage feedforward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 THD optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Inductor saturation detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Power management/housekeeping functions . . . . . . . . . . . . . . . . . . . . . . 26 7 8 9 10 Application examples and ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Ordering codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2/34 Doc ID 16202 Rev 1 L6564 List of table List of table Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Summary of L6564 idle states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SSO10 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Doc ID 16202 Rev 1 3/34 List of figure L6564 List of figure Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 IC consumption vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 IC consumption vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Vcc Zener voltage vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Start-up and UVLO vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Feedback reference vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 E/A output clamp levels vs TJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 UVLO saturation vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 OVP levels vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Inductor saturation threshold vs TJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Vcs clamp vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 ZCD sink/source capability vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 ZCD clamp level vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 TBO clamp vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 VVFF - VTBO dropout vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 IINV - ITBO current mismatch vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 IINV - ITBO mismatch vs ITBO current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 R discharge vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Line drop detection threshold vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 VMULTpk - VVFF dropout vs TJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PFC_OK threshold vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PFC_OK FFD threshold vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PWM_LATCH high saturation vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 RUN threshold vs TJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PWM_STOP low saturation vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Multiplier characteristics @ VFF = 1 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Multiplier characteristics @ VFF = 3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Multiplier gain vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Gate drive clamp vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Gate drive output saturation vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Delay to output vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Start-up timer period vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Output voltage setting, OVP and FFP functions: internal block diagram . . . . . . . . . . . . . . 20 Voltage feedforward: squarer-divider (1/V2) block diagram and transfer characteristic . . 22 RFF·CFF as a function of 3rd harmonic distortion introduced in the input current . . . . . . . 23 THD optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 THD optimization: standard TM PFC controller (left side) and L6564 (right side) . . . . . . . 24 Effect of boost inductor saturation on the MOSFET current and detection method . . . . . . 25 Interface circuits that let dc-dc converter's controller IC disable the L6564 . . . . . . . . . . . . 26 Demonstration board EVL6564-100W, wide-range mains: electrical schematic . . . . . . . . 28 L6564 100 W TM PFC: compliance to EN61000-3-2 standard. . . . . . . . . . . . . . . . . . . . . . 29 L6564 100 W TM PFC: compliance to JEITA-MITI standard . . . . . . . . . . . . . . . . . . . . . . . 29 L6564 100 W TM PFC: input current waveform @230-50 Hz - 100 W load . . . . . . . . . . . . 29 L6564 100W TM PFC: input current waveform @100 V-50 Hz - 100 W load . . . . . . . . . . 29 SSO10 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4/34 Doc ID 16202 Rev 1 L6564 Description 1 Description The L6564 is a current-mode PFC controller operating in transition mode (TM) and represents the compact version of L6563S as it embeds the same driver, reference and control stages in a very compact 10 pin SO package. The highly linear multiplier, along with a special correction circuit that reduces crossover distortion of the mains current, allows wide-range-mains operation with an extremely low THD even over a large load range. The output voltage is controlled by means of a voltage-mode error amplifier and an accurate (1% @TJ = 25 °C) internal voltage reference. The loop stability is optimized by the voltage feedforward function (1/V2 correction), which in this IC uses a proprietary technique that considerably improves line transient response as well in case of mains both drops and surges ( "bidirectional"). In addition to overvoltage protection able to control the output voltage during transient conditions, the IC also provides protection against feedback loop failures or erroneous settings. Other on-board protection functions allow brownout conditions and boost inductor saturation to be safely handled. The totem-pole output stage, capable of 600 mA source and 800 mA sink current, is suitable for high power MOSFET or IGBT drive. This, combined with the other features and the possibility to operate with ST's proprietary fixed-off-time control, makes the device an excellent solution for SMPS up to 400 W that require compliance with EN61000-3-2 and JEITA-MITI standards. Doc ID 16202 Rev 1 5/34 Maximum ratings L6564 2 2.1 Maximum ratings Absolute maximum ratings Table 1. Symbol Vcc ----IZCD VFF pin Other pins Absolute maximum ratings Pin 10 1, 3, 6 2, 4, 5 7 5 1 to 4 6 to 10 Parameter IC supply voltage (Icc ≤ 20 mA) Max. pin voltage (Ipin ≤ 1 mA) Analog inputs and outputs Zero current detector max. current Maximum withstanding voltage range test condition: CDF-AEC-Q100-002 “human body model” Acceptance criteria: “normal performance” Value self-limited Self-limited -0.3 to 8 -10 (source) 10 (sink) +/- 1750 +/- 2000 Unit V V V mA V V 2.2 Thermal data Table 2. Symbol RthJA Ptot TJ Tstg Thermal data Parameter Max. thermal resistance, junction-to-ambient Power dissipation @TA = 50 °C Junction temperature operating range Storage temperature Value 120 0.75 -40 to 150 -55 to 150 Unit °C/W W °C °C 6/34 Doc ID 16202 Rev 1 L6564 Pin connection 3 Pin connection Figure 2. Pin connection Table 3. n° Pin description Function Inverting input of the error amplifier. The information on the output voltage of the PFC preregulator is fed into the pin through a resistor divider. The pin normally features high impedance. Output of the error amplifier. A compensation network is placed between this pin and INV (pin 1) to achieve stability of the voltage control loop and ensure high power factor and low THD. To avoid uncontrolled rise of the output voltage at zero load, when the voltage on the pin falls below 2.4 V the gate driver output will be inhibited (burst-mode operation). Main input to the multiplier. This pin is connected to the rectified mains voltage via a resistor divider and provides the sinusoidal reference to the current loop. The voltage on this pin is used also to derive the information on the RMS mains voltage. Input to the PWM comparator. The current flowing in the MOSFET is sensed through a resistor, the resulting voltage is applied to this pin and compared with an internal reference to determine MOSFET’s turn-off. A second comparison level at 1.7V detects abnormal currents (e.g. due to boost inductor saturation) and, on this occurrence, activates a safety procedure that temporarily stops the converter and limits the stress of the power components. Second input to the multiplier for 1/V2 function. A capacitor and a parallel resistor must be connected from the pin to GND. They complete the internal peak-holding circuit that derives the information on the RMS mains voltage. The voltage at this pin, a dc level equal to the peak voltage on pin MULT (3), compensates the control loop gain dependence on the mains voltage. Never connect the pin directly to GND but with a resistor ranging from 100K ohm (minimum) to 2M ohm (maximum). This pin is internally connected to a comparator in order to provide the brownout (AC mains undervoltage) protection. A voltage below 0.8V shuts down (not latched) the IC and brings its consumption to a considerably lower level. The IC restarts as the voltage at the pin goes above 0.88V. Name 1 INV 2 COMP 3 MULT 4 CS 5 VFF Doc ID 16202 Rev 1 7/34 Pin connection Table 3. n° L6564 Pin description (continued) Function PFC pre-regulator output voltage monitoring/disable function. This pin senses the output voltage of the PFC pre-regulator through a resistor divider and is used for protection purposes. If the voltage on the pin exceeds 2.5V the IC stops switching and restarts as the voltage on the pin falls below 2.4V. However, if the voltage of the INV pin falls 40 mV below that of the pin PFC_OK, a feedback failure is assumed. In this case the device is latched off. Normal operation can be resumed only by cycling Vcc. bringing its value lower than 6V before to move up to Turnon threshold. If the voltage on this pin is brought below 0.23V the IC is shut down. To restart the IC the voltage on the pin must go above 0.27V. This can be used as a remote on/off control input. Boost inductor’s demagnetization sensing input for transition-mode operation. A negative-going edge triggers MOSFET’s turn-on. Ground. Current return for both the signal part of the IC and the gate driver. Gate driver output. The totem pole output stage is able to drive power MOSFET’s and IGBT’s with a peak current of 600 mA source and 800 mA sink. The high-level voltage of this pin is clamped at about 12V to avoid excessive gate voltages. Supply Voltage of both the signal part of the IC and the gate driver. Sometimes a small bypass capacitor (0.1 µF typ.) to GND might be useful to get a clean bias voltage for the signal part of the IC. Name 6 PFC_OK 7 8 9 ZCD GND GD 10 Vcc 8/34 Doc ID 16202 Rev 1 L6564 Electrical characteristics 4 Electrical characteristics TJ = -25 to 125 °C, VCC = 12 V, CO = 1 nF between pin GD and GND, CFF = 1 µF and RFF = 1 MΩ between pin VFF and GND; unless otherwise specified. Table 4. Symbol Electrical characteristics Parameter Test condition Min. Typ. Max. Unit Supply voltage Vcc VccOn VccOff Vccrestart Hys VZ Operating range Turn-on threshold Turn-off threshold Vcc for resuming from latch Hysteresis Zener voltage Icc = 20mA After turn-on (1) (1) 10.3 11 8.7 5 2.3 22.5 25 12 9.5 6 22.5 13 10.3 7 2.7 28 V V V V V V OVP Latched Supply current Istart-up Iq ICC Iqdis Start-up current Quiescent current Operating supply current Before turn-on, Vcc=10V After turn-on, VMULT = 1V @ 70kHz VPFC_OK> VPFC_OK_S AND VINV< VPFC_OK – VFFD VPFC_OKVPFC_OK_S OR VCOMP VCS_th, before restarting Start-up timer tSTART_DEL Start-up delay tSTART Timer period Restart after VCS > VCS_th 150 300 600 First cycle after wake-up 25 75 50 150 75 300 µs µs Current sense comparator ICS tLEB td(H-L) VCSclamp Vcsofst Input bias current Leading edge blanking Delay to output Current sense reference clamp VCOMP = Upper clamp, VMULT =1V, VVFF = 1V VMULT = 0, VVFF = 3V VMULT = 3V, VVFF = 3V VCS = 0 100 100 1.0 150 200 1.08 40 20 1 250 300 1.16 70 mV µA ns ns V Current sense offset PFC_OK functions IPFC_OK Input bias current VPFC_OK = 0 to 2.6V IPFC_OK = 1mA (1) (1) (1) (1) (1) (1) -0.1 9 2.435 2.34 0.12 0.17 0.23 0.15 0.21 0.27 15 25 40 40 9.5 -1 µA V V V V V V V mV mV VPFC_OK_C Clamp voltage VPFC_OK_S OVP threshold VPFC_OK_R Restart threshold after OVP VPFC_OK_D Disable threshold VPFC_OK_D Disable threshold VPFC_OK_E Enable threshold VPFC_OK_E Enable threshold VFFD VFFD Feedback failure detection threshold (VPFC_OK -VINV) Feedback failure detection threshold (VPFC_OK -VINV) voltage rising voltage falling voltage falling voltage falling Tj = 25 °C voltage rising voltage rising Tj = 25 °C 2.5 2.565 2.4 2.46 0.35 0.29 0.38 0.32 65 55 VPFC_OK = VPFC_OK_S VPFC_OK = VPFC_OK_S Tj = 25 °C 10/34 Doc ID 16202 Rev 1 L6564 Table 4. Symbol Voltage feedforward VVFF ΔV ΔVVFF ΔVVFF RDISCH VDIS VEN Linear operation range Dropout VMULTpk-VVFF Line drop detection thresh. Line drop detection thresh. Internal discharge resistor Vcc < VccOn Vcc > or = to VccOn Below peak value Below peak value Tj =25°C Tj = 25 °C Electrical characteristics Electrical characteristics (continued) Parameter Test condition Min. Typ. Max. Unit 1 3 800 V mV 20 40 50 7.5 5 70 70 10 100 90 12.5 20 0.8 0.855 V V mV mV kΩ Disable threshold Enable threshold (2) (2) voltage falling voltage rising 0.745 0.845 0.88 0.915 Zero current detector VZCDH VZCDL VZCDA VZCDT IZCDb IZCDsrc IZCDsnk Gate driver VOL VOH Isrcpk Isnkpk tf tr VOclamp Output low voltage Output high voltage Peak source current Peak sink current Voltage fall time Voltage rise time Output clamp voltage UVLO saturation 1. Upper clamp voltage Lower clamp voltage Arming voltage (positive-going edge) Triggering voltage (negative-going edge) Input bias current Source current capability Sink current capability IZCD = 2.5mA IZCD = - 2.5mA 5.0 -0.3 1.1 0.5 5.7 0 1.4 0.7 0.3 1.9 0.9 1 V V V V µA mA mA VZCD = 1 to 4.5V -2.5 2.5 -4 5 Isink = 100mA Isource = 5mA 9.8 -0.6 0.8 0.6 10.3 1.2 V V A A 30 45 Isource = 5mA; Vcc = 20V Vcc= 0 to VCCon, Isink= 2mA 10 12 60 110 15 1.1 ns ns V V Parameters tracking each other VMULT ⋅ VCOMP − 2.5 2. The multiplier output is given by: Vcs = VCS_Ofst + K M ⋅ 2 3. Parameters tracking each other V VFF ( ) Doc ID 16202 Rev 1 11/34 Typical electrical performance L6564 5 Figure 3. Typical electrical performance IC consumption vs VCC Figure 4. IC consumption vs TJ   100   10 Operating 10 Quiescent Disabled or d uring OV P VCC=12V Co = 1nF f =70kHz L atched off 0.1 1 1 I cc [m A] Co=1nF f =70kHz Tj = 25°C 0.1 I c current (m A) 0.01 VccOFF VccON 0. 001 0 5 10 15 Vcc [V ] 20 25 30 0.01 -50 -25 0 25 50 Tj (C) 75 Before Start up 100 125 150 175 Figure 5. Vcc Zener voltage vs TJ Figure 6. Start-up and UVLO vs TJ   28   13 12 V CC- ON 27 11 26 10 25 VCC-OFF V 9 8 7 6 -50 -25 0 25 50 Tj (C) 75 100 125 150 175 V 24 23 22 -50 -25 0 25 50 Tj (C) 75 100 125 150 175 12/34 Doc ID 16202 Rev 1 L6564 Typical electrical performance Figure 7. Feedback reference vs TJ Figure 8. E/A output clamp levels vs TJ   2. 6   7 U per Clam p VCC = 12V 2.55 6 5 V CC = 12V V COM P (V ) pi n INV (V ) 4 2. 5 3 Lower Clamp 2 2.45 1 2. 4 -50 -25 0 25 50 75 Tj (C) 100 125 150 175 0 -50 -25 0 25 50 Tj (C) 75 100 125 150 175 Figure 9. UVLO saturation vs TJ Figure 10. OVP levels vs TJ   1 0.9 VCC = 0V 0.8 0.7 0.6 V 0.5 0.4 0.3 0.2 0.1   2. 5 2. 48 OV P T h 2. 46 P FC_OK l evels (V ) 2. 44 2. 42 2. 4 Resta rt Th 2. 38 2. 36 0 -50 -25 0 25 50 Tj (C) 75 100 125 150 175 -50 -25 0 25 50 Tj (C) 75 100 125 150 175 Doc ID 16202 Rev 1 13/34 Typical electrical performance L6564 Figure 11. Inductor saturation threshold vs TJ Figure 12. Vcs clamp vs TJ   1.9 1.8   1. 4 1.7 1.6 CS pi n (V ) VCSx (V ) 1. 3 VCC = 12V VCOMP =Upp clamp er 1. 2 1.5 1.4 1.3 1.2 1. 1 1.1 -50 -25 0 25 50 Tj (C) 75 100 125 150 175 1 -50 -25 0 25 50 Tj (C) 75 100 125 150 175 Figure 13. ZCD sink/source capability vs TJ Figure 14. ZCD clamp level vs TJ   8 6 4 2 V CC = 12V Si nk curren t   7 6 Upper Clamp 5 4 3 2 IZCDsrc (mA ) 0 -2 Source current -4 -6 -8 -50 -25 0 25 50 Tj (C) 75 100 125 150 175 V ZCD pin (V ) VCC = 12V Izcd =± 2.5mV 1 0 Lower Cl am p -1 -50 -25 0 25 50 Tj (C) 75 100 125 150 175 14/34 Doc ID 16202 Rev 1 L6564 Typical electrical performance Figure 15. TBO clamp vs TJ Figure 16. VVFF - VTBO dropout vs TJ 5 4 3   3.5 3.25 2 1 mV 3 V 0 -1 -2 2.75 -3 -4 -5 2.5 -50 -25 0 25 50 T (C) j 75 100 125 150 175 -50 -25 0 25 50 T j (C) 75 100 125 150 175 Figure 17. IINV - ITBO current mismatch vs TJ Figure 18. IINV - ITBO mismatch vs ITBO current   0 VCC = 12V -0.5 -1 I TBO = 200uA -1.5 -2   -1.6 -1.8 100*{I(I NV )-I(TBO)}/I (TBO) [ % ] 100*{I(INV)-I(TBO)}/I(TBO) [ % ] -2 -2.2 ITBO = 25uA -2.4 -2.5 -3 -3.5 VCC = 12V T = 25°C j -2.6 -2.8 -4 -50 -25 0 25 50 T (C) j 75 100 125 150 175 -3 0 100 200 300 I(TBO) 400 500 600 Doc ID 16202 Rev 1 15/34 Typical electrical performance L6564 Figure 19. R discharge vs TJ Figure 20. Line drop detection threshold vs TJ   20 18 16 14   90 80 70 60 12 kOhm 50 10 8 mV 40 30 20 10 0 -50 -25 0 25 50 Tj (C) 75 100 125 150 175 6 4 2 0 -50 -25 0 25 50 75 Tj (C) 100 125 150 175 Figure 21. VMULTpk - VVFF dropout vs TJ Figure 22. PFC_OK threshold vs TJ 0.4 0.35   2 1. 5 1 0. 5 ⎯ (m V) 0.3 0.25 Th (V ) ON 0.2 OF F 0 -0. 5 -1 0.15 0.1 -1. 5 0.05 -2 -50 -25 0 25 50 75 Tj (C) 100 125 150 175 0 -50 -25 0 25 50 Tj (C) 75 100 125 150 175 16/34 Doc ID 16202 Rev 1 L6564 Typical electrical performance Figure 23. PFC_OK FFD threshold vs TJ Figure 24. PWM_LATCH high saturation vs TJ   60   10 VCC = 12V 9 50 40 VFFD Th (V) 8 Iso urce =500u A V 30 7 Iso urce =250u A 20 6 10 5 0 -50 -25 0 25 50 75 T j (C) 100 125 150 175 4 -50 -25 0 25 50 75 T j (C) 100 125 150 175 Figure 25. RUN threshold vs TJ Figure 26. PWM_STOP low saturation vs TJ 0. 25   1 ON 0.2 VCC = 12V Isink = 0. 5m A 0.8 OF F 0. 15 V VCC = 12V V 0.1 0. 05 0 -50 0.6 0.4 -50 -25 0 25 50 T j (C) 75 100 125 150 175 -25 0 25 50 Tj (C) 75 100 125 150 175 Doc ID 16202 Rev 1 17/34 Typical electrical performance L6564 Figure 27. Multiplier characteristics @ VFF = 1 V Figure 28. Multiplier characteristics @ VFF = 3 V   1. 2 1. 1 1 0. 9 0. 8 VCOMP Upper voltage cl amp 5 .5 5 .0V 4.5 V   700 V COM P 600 Upper vo ltage 500 5. 5V 0. 6 0. 5 3.5 V V CS (m V) 0. 7 V CS (V ) 4. 0V 400 5. 0V 4. 5V 4. 0V 300 0. 4 0. 3 0. 2 0. 1 2.6 V 3.0 200 3. 5V 100 3. 0V 2. 6V 0 0 0. 1 0.2 0. 3 0. 4 0.5 0.6 0.7 0. 8 0.9 1 1.1 VM UL T (V ) 0 0 0. 5 1 1. 5 2 V MULT (V ) 2. 5 3 3. 5 Figure 29. Multiplier gain vs TJ Figure 30. Gate drive clamp vs TJ   0. 5   12. 9 V CC = 20V 12.85 0. 4 Gai n (1/V ) 12. 8 VCC = 12V VCOMP = 4V VMUL = VFF= 1V T 0. 3 V 12.75 12. 7 150 175 0. 2 -50 -25 0 25 50 Tj (C) 75 100 125 12.65 -50 -25 0 25 50 75 Tj (C) 100 125 150 175 18/34 Doc ID 16202 Rev 1 L6564 Typical electrical performance Figure 31. Gate drive output saturation vs TJ Figure 32. Delay to output vs TJ 300   12 10 High level 250 8 TD(H-L) (n s) 200 VCC = 12V 150 6 V 4 2 Low level 100 0 -50 -25 0 25 50 Tj (C) 75 100 125 150 175 50 -50 -25 0 25 50 Tj (C) 75 100 125 150 175 Figure 33. Start-up timer period vs TJ   450 After OCP 400 350 300 Ti m e (us) 250 200 150 100 50 0 -50 -25 0 25 50 Tj (C) 75 100 125 150 175 Timer F irst Cicle Doc ID 16202 Rev 1 19/34 Application information L6564 6 6.1 Application information Overvoltage protection Normally, the voltage control loop keeps the output voltage Vo of the PFC pre-regulator close to its nominal value, set by the ratio of the resistors R1 and R2 of the output divider. A pin of the device (PFC_OK) has been dedicated to monitor the output voltage with a separate resistor divider (R3 high, R4 low, see Figure 34). This divider is selected so that the voltage at the pin reaches 2.5 V if the output voltage exceeds a preset value, usually larger than the maximum Vo that can be expected. Example: VO = 400 V, VOX = 434 V. Select: R3 = 8.8 MΩ; then: R4 = 8.8 MΩ ·2.5/(434-2.5) = 51 kΩ. When this function is triggered, the gate drive activity is immediately stopped until the voltage on the pin PFC_OK drops below 2.4 V. Notice that R1, R2, R3 and R4 can be selected without any constraints. The unique criterion is that both dividers have to sink a current from the output bus which needs to be significantly higher than the bias current of both INV and PFC_OK pins. Figure 34. Output voltage setting, OVP and FFP functions: internal block diagram 20/34 Doc ID 16202 Rev 1 L6564 Application information 6.2 Feedback failure protection (FFP) The OVP function above described handles “normal” over voltage conditions, i.e. those resulting from an abrupt load/line change or occurring at start-up. In case the overvoltage is generated by a feedback disconnection, for instance when the upper resistor of the output divider (R1) fails open, an additional circuitry behind the pin PFC_OK detects the voltage gap with respect to pin INV. If the voltage gap is greater than 40 mV and the OVP is active, the FFP is triggered, the gate drive activity is immediately stopped, the device is shut down, its quiescent consumption is reduced below 180 µA and the condition is latched as long as the supply voltage of the IC is above the UVLO threshold. To restart the system it is necessary to recycle the input power, so that the Vcc voltage of the L6564 goes below 6 V. The pin PFC_OK doubles its function as a not-latched IC disable: a voltage below 0.23 V will shut down the IC, reducing its consumption below 2 mA. To restart the IC simply let the voltage at the pin go above 0.27 V. Note that these functions offer complete protection against not only feedback loop failures or erroneous settings, but also against a failure of the protection itself. Either resistor of the PFC_OK divider failing short or open or a PFC_OK pin floating will result in shutting down the IC and stopping the pre-regulator. 6.3 Voltage feedforward The power stage gain of PFC pre-regulators varies with the square of the RMS input voltage. So does the crossover frequency fc of the overall open-loop gain because the gain has a single pole characteristic. This leads to large trade-offs in the design. For example, setting the gain of the error amplifier to get fc = 20 Hz @ 264 Vac means having fc 4 Hz @ 88 Vac, resulting in a sluggish control dynamics. Additionally, the slow control loop causes large transient current flow during rapid line or load changes that are limited by the dynamics of the multiplier output. This limit is considered when selecting the sense resistor to let the full load power pass under minimum line voltage conditions, with some margin. But a fixed current limit allows excessive power input at high line, whereas a fixed power limit requires the current limit to vary inversely with the line voltage. Voltage feedforward can compensate for the gain variation with the line voltage and allow minimizing all of the above-mentioned issues. It consists of deriving a voltage proportional to the input RMS voltage, feeding this voltage into a squarer/divider circuit (1/V2 corrector) and providing the resulting signal to the multiplier that generates the current reference for the inner current control loop (see Figure 35). Doc ID 16202 Rev 1 21/34 Application information L6564 Figure 35. Voltage feedforward: squarer-divider (1/V2) block diagram and transfer characteristic In this way a change of the line voltage will cause an inversely proportional change of the half sine amplitude at the output of the multiplier (if the line voltage doubles the amplitude of the multiplier output will be halved and vice versa) so that the current reference is adapted to the new operating conditions with (ideally) no need for invoking the slow dynamics of the error amplifier. Additionally, the loop gain will be constant throughout the input voltage range, which improves significantly dynamic behavior at low line and simplifies loop design. Actually, deriving a voltage proportional to the RMS line voltage implies a form of integration, which has its own time constant. If it is too small the voltage generated will be affected by a considerable amount of ripple at twice the mains frequency that will cause distortion of the current reference (resulting in high THD and poor PF); if it is too large there will be a considerable delay in setting the right amount of feedforward, resulting in excessive overshoot and undershoot of the pre-regulator's output voltage in response to large line voltage changes. Clearly a trade-off was required. The L6564 realizes a NEW voltage feed forward that, with a technique that makes use of just two external parts, strongly minimizes this time constant trade-off issue whichever voltage change occurs on the mains, both surges and drops. A capacitor CFF and a resistor RFF, both connected from the pin VFF (#5) to ground, complete an internal peak-holding circuit that provides a DC voltage equal to the peak of the rectified sine wave applied on pin MULT (#3). In this way, in case of sudden line voltage rise, CFF will be rapidly charged through the low impedance of the internal diode; in case of line voltage drop, an internal “mains drop” detector enables a low impedance switch which suddenly discharges CFF avoiding long settling time before reaching the new voltage level. Consequently, an acceptably low steady-state ripple and low current distortion can be achieved without any considerable undershoot or overshoot on the pre-regulator's output, like in systems with no feedforward compensation. The twice-mains-frequency (2•fL) ripple appearing across CFF is triangular with a peak-topeak amplitude that, with good approximation, is given by: ΔVFF = 2 VMULTpk 1 + 4fLRFF CFF 22/34 Doc ID 16202 Rev 1 L6564 Application information where fL is the line frequency. The amount of 3rd harmonic distortion introduced by this ripple, related to the amplitude of its 2•fL component, will be: D3 % = 100 2π fLRFF CFF Figure 36 shows a diagram that helps choose the time constant RFF·CFF based on the amount of maximum desired 3rd harmonic distortion. Always connect RFF and CFF to the pin, the IC will not work properly if the pin is either left floating or connected directly to ground. Figure 36. RFF·CFF as a function of 3rd harmonic distortion introduced in the input current   10 1 f L= 50 Hz R FF · C FF [s] 0.1 f L= 60 Hz 0.01 0.1 1 10 D3 % The dynamics of the voltage feedforward input, that is the output of the multiplier, is limited downwards at 0.8 V (see Figure 35), so that cannot increase any more if the voltage on the VFF pin is below 0.8 V. This helps to prevent excessive power flow when the line voltage is lower than the minimum specified value. 6.4 THD optimizer circuit The L6564 is provided with a special circuit that reduces the conduction dead-angle occurring to the AC input current near the zero-crossings of the line voltage (crossover distortion). In this way the THD (total harmonic distortion) of the current is considerably reduced. A major cause of this distortion is the inability of the system to transfer energy effectively when the instantaneous line voltage is very low. This effect is magnified by the highfrequency filter capacitor placed after the bridge rectifier, which retains some residual voltage that causes the diodes of the bridge rectifier to be reverse-biased and the input current flow to temporarily stop. To overcome this issue the device forces the PFC pre-regulator to process more energy near the line voltage zero-crossings as compared to that commanded by the control loop. This will result in both minimizing the time interval where energy transfer is lacking and fully discharging the high-frequency filter capacitor after the bridge. Figure 37 shows the internal block diagram of the THD optimizer circuit. Doc ID 16202 Rev 1 23/34 Application information Figure 37. THD optimizer circuit L6564 Figure 38. THD optimization: standard TM PFC controller (left side) and L6564 (right side)   Input current Input current Rectified mains voltage Rectified mains voltage Imains Input current Vdrain MOSFET's drain voltage Imains Input current Vdrain MOSFET's drain voltage 24/34 Doc ID 16202 Rev 1 L6564 Application information Essentially, the circuit artificially increases the ON-time of the power switch with a positive offset added to the output of the multiplier in the proximity of the line voltage zero-crossings. This offset is reduced as the instantaneous line voltage increases, so that it becomes negligible as the line voltage moves toward the top of the sinusoid. Furthermore the offset is modulated by the voltage on the VFF pin (see “Voltage Feedforward” section) so as to have little offset at low line, where energy transfer at zero crossings is typically quite good, and a larger offset at high line where the energy transfer gets worse. The effect of the circuit is shown in Figure 38, where the key waveforms of a standard TM PFC controller are compared to those of this chip. To take maximum benefit from the THD optimizer circuit, the high-frequency filter capacitor after the bridge rectifier should be minimized, compatibly with EMI filtering needs. A large capacitance, in fact, introduces a conduction dead-angle of the AC input current in itself even with an ideal energy transfer by the PFC pre-regulator - thus reducing the effectiveness of the optimizer circuit. 6.5 Inductor saturation detection Boost inductor's hard saturation may be a fatal event for a PFC pre-regulator: the current upslope becomes so large (50-100 times steeper, see Figure 39) that during the current sense propagation delay the current may reach abnormally high values. The voltage drop caused by this abnormal current on the sense resistor reduces the gate-to-source voltage, so that the MOSFET may work in the active region and dissipate a huge amount of power, which leads to a catastrophic failure after few switching cycles. However, in some applications such as ac-dc adapters, where the PFC pre-regulator is turned off at light load for energy saving reasons, even a well-designed boost inductor may occasionally slightly saturate when the PFC stage is restarted because of a larger load demand. This happens when the restart occurs at an unfavorable line voltage phase, i.e. when the output voltage is significantly below the rectified peak voltage. As a result, in the boost inductor the inrush current coming from the bridge rectifier adds up to the switched current and, furthermore, there is little or no voltage available for demagnetization. To cope with a saturated inductor, the L6564 is provided with a second comparator on the current sense pin (CS, pin 4) that stops the IC if the voltage, normally limited within 1.1 V, exceeds 1.7 V. After that, the IC will be attempted to restart by the internal starter circuitry; the starter repetition time is twice the nominal value to guarantee lower stress for the inductor and boost diode. Hence, the system safety will be considerably increased. Figure 39. Effect of boost inductor saturation on the MOSFET current and detection method Doc ID 16202 Rev 1 25/34 Application information L6564 6.6 Power management/housekeeping functions A communication line with the control IC of the cascaded dc-dc converter can be established via the disable function included in the PFC_OK pin (see “Feedback failure protection” section for more details). Typically this line is used to allow the PWM controller of the cascaded dc-dc converter to shut down the L6564 in case of light load and to minimize the no-load input consumption. Should the residual consumption of the chip be an issue, it is also possible to cut down the supply voltage. Interface circuits like those are shown in figure 32. Needless to say, this operation assumes that the cascaded dc-dc converter stage works as the master and the PFC stage as the slave or, in other words, that the dc-dc stage starts first, it powers both controllers and enables/disables the operation of the PFC stage. Figure 40. Interface circuits that let dc-dc converter's controller IC disable the L6564 Another function available is the brownout protection which is basically a not-latched shutdown function that is activated when a condition of mains under voltage is detected. This condition may cause overheating of the primary power section due to an excess of RMS current. Brownout can also cause the PFC pre-regulator to work open loop and this could be dangerous to the PFC stage itself and the downstream converter, should the input voltage return abruptly to its rated value. Another problem is the spurious restarts that may occur during converter power down and that cause the output voltage of the converter not to decay to zero monotonically. For these reasons it is usually preferable to shutdown the unit in case of brownout. Brownout threshold is internally fixed at 0.8V and is sensed on pin VFF (5) during the voltage falling and 80 mV threshold hysteresis prevents from rebounding at input voltage turn off. In Table 5 it is possible to find a summary of all of the above mentioned working conditions that cause the device to stop operating. 26/34 Doc ID 16202 Rev 1 L6564 Application information Table 5. Condition UVLO Summary of L6564 idle states Caused or revealed bey Vcc < VccOff PFC_OK > VPFC_OK_S AND INV < PFC_OK - 40mV PFC_OK < VPFC_OK_D VFF < VDIS PFC_OK > VPFC_OK_S COMP < 2.4V Vcs > VCS_th IC behavior Disabled Latched Stop switching Stop switching Restart condition Vcc > VccOn Vcc < Vccrestart then Vcc > VccOn PFC_OK > VPFC_OK_E RUN > VEN Typical IC consumption 90 µA 180 µA 1.5 mA 1.5 mA 2.2 mA 2.2 mA 2.2 mA Feedback disconnected Standby AC Brownout OVP Low consumption Saturated boost inductor Stop Switching PFC_OK < VPFC_OK_R Burst mode Doubled Tstart COMP > 2.4V Auto restart Doc ID 16202 Rev 1 27/34 Application examples and ideas L6564 7 Application examples and ideas Figure 41. Demonstration board EVL6564-100W, wide-range mains: electrical schematic 28/34 Doc ID 16202 Rev 1 L6564 Application examples and ideas Figure 42. L6564 100 W TM PFC: compliance to EN61000-3-2 standard Figure 43. L6564 100 W TM PFC: compliance to JEITA-MITI standard Measur ed value 10 1 0.1 0.01 JEITA-MITI Class-Dlim its   1 Meas ured value EN61000-3- 2 class- D lim its 0.1 0.01 0.001 0.0001 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 Harmonic Current [A] Harmonic Current [A] 0.001 0.0001 1 35 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 Harmonic Order [n] Harm onic Order [n] Figure 44. L6564 100 W TM PFC: input current Figure 45. L6564 100W TM PFC: input current waveform @230-50 Hz - 100 W load waveform @100 V-50 Hz - 100 W load Doc ID 16202 Rev 1 29/34 Package mechanical data L6564 8 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Table 6. SSO10 mechanical data Databook (mm.) Dim. Min A A1 A2 b c D E E1 e h L K 4.90 6 3.90 1 0.25 0.40 0° 0.50 0.90 8° 0.10 1.25 0.31 0.17 4.80 5.80 3.80 0.51 0.25 5 6.20 4 Typ. Max 1.75 0.25 30/34 Doc ID 16202 Rev 1 L6564 Figure 46. SSO10 package dimensions Package mechanical data 8140761 rev. A Doc ID 16202 Rev 1 31/34 Ordering codes L6564 9 Ordering codes Table 7. Ordering information Order codes L6564D SO14 L6564DTR Tape and reel Package Packing Tube 32/34 Doc ID 16202 Rev 1 L6564 Revision history 10 Revision history Table 8. Date 08-Sep-2009 Document revision history Revision 1 Initial release. Changes Doc ID 16202 Rev 1 33/34 L6564 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2009 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 34/34 Doc ID 16202 Rev 1