L6726A
Single phase PWM controller
Feature
■
Flexible power supply from 5 V to 12 V
■
Power conversion input as low as 1.5 V
■
1% output voltage accuracy
■
High-current integrated drivers
■
Adjustable output voltage
■
0.8 V internal reference
■
Sensorless and programmable OCP across
Low-side RdsON
■
Oscillator internally fixed at 270 kHz
■
Programmable soft-start
■
Ls-less start up
■
Disable function
■
FB disconnection protection
■
SO-8 package
SO-8
Description
L6726A is a single-phase step-down controller
with integrated high-current drivers that provides
complete control logic, protections and reference
voltage to realize in an easy and simple way
general DC-DC converters by using a compact
SO-8 package.
Device flexibility allows managing conversions
with power input VIN as low as 1.5 V and device
supply voltage ranging from 5 V to 12 V.
L6726A provides simple control loop with transconductance error amplifier. The integrated 0.8 V
reference allows regulating output voltage with
±1% accuracy over line and temperature
variations. Oscillator is internally fixed to 270 kHz.
Applications
■
Subsystem power supply (MCH, IOCH, PCI...)
■
Memory and termination supply
■
CPU and DSP power supply
■
Distributed power supply
■
General DC / DC converters
L6726A provides programmable over current
protection. Current information is monitored
across the low-side MOSFET RdsON saving the
use of expensive and space-consuming sense
resistors.
FB disconnection protection prevents excessive
and dangerous output voltages in case of floating
FB pin.
Table 1.
March 2010
Device summary
Order codes
Package
Packaging
L6726A
SO-8
Tube
L6726ATR
SO-8
Tape and reel
Doc ID 12754 Rev 4
1/35
www.st.com
35
Contents
L6726A
Contents
1
2
3
Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 4
1.1
Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pins description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . 5
2.1
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1
6
7
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Soft start and disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.1
Low-side-less start up (LSLess) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.2
Enable / disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.1
Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.1.1
8
2/35
Overcurrent threshold setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.2
Feedback disconnection protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.3
Undervoltage lock out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Application details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8.1
Output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8.2
Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8.3
Soft-start time calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8.4
Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8.5
Embedding L6726A-based VRs… . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Doc ID 12754 Rev 4
L6726A
9
10
Contents
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
9.1
Output inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
9.2
Output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
9.3
Input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
20 A demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
10.1
11
Board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10.1.1
Power input (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10.1.2
Power output (VOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10.1.3
IC additional supply (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10.1.4
Test points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10.1.5
Demonstration board efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5 A demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
11.1
Board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
11.1.1
Power input (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
11.1.2
Power output (VOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
11.1.3
IC additional supply (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
11.1.4
Test points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
11.1.5
Demonstration board efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
12
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
13
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Doc ID 12754 Rev 4
3/35
Typical application circuit and block diagram
L6726A
1
Typical application circuit and block diagram
1.1
Application circuit
Figure 1.
Typical application circuit
VIN = 1.5V to 19V (1)
VCC = 5V to 12V
CDEC
D
5
7
VCC
BOOT
FB
COMP
/ DIS
CF
RFB
ROS
CP
RF
3
RD
1
CBOOT
L6726A
6
GND
UGATE
PHASE
LGATE
/ OC
2
CHF
CBULK
HS
RgHS
8
4
L
RgLS
LS
Vout
RSN
COUT
LOAD
CSN
ROCSET
L6726A Reference Schematic
(1) Up to 12V with Vcc > 5V
1.2
Block diagram
Block diagram
VCC
Figure 2.
VOCTH
OCP
CONTROL LOGIC
& PROTECTIONS
ISS
BOOT
CLOCK
S
PWM
Q
R
OSCILLATOR
TRANSCONDUCTANCE
ERROR AMPLIFIER
ADAPTIVE ANTI
CROSS CONDUCTION
DISABLE
HS
UGATE
PHASE
VCC
LS
LGATE
/ OC
GND
+
-
L6726A
FB
IOCSET
COMP
/ DIS
4/35
0.8V
Doc ID 12754 Rev 4
L6726A
2
Pins description and connection diagrams
Pins description and connection diagrams
Figure 3.
Pins connection (top view)
BOOT
UGATE
GND
LGATE / OC
2.1
1
8
2
7
3
L6726A
4
6
5
PHASE
COMP / DIS
FB
VCC
Pin descriptions
Table 2.
Pins descriptions
Pin n
Name
1
BOOT
HS driver supply.
Connect through a capacitor (100 nF) to the floating node (LS-drain) pin
and provide necessary bootstrap diode from VCC.
2
UGATE
HS driver output. Connect to HS MOSFET gate.
3
GND
4
5
6
Function
All internal references, logic and drivers are connected to this pin.
Connect to the PCB ground plane.
LGATE. LS driver output. Connect to LS MOSFET gate.
OC. Over current threshold set. During a short period of time following VCC
rising over UVLO threshold, a 10μA current is sourced from this pin.
Connect to GND with an ROCSET resistor greater than 5kΩ to program OC
LGATE / OC Threshold. The resulting voltage at this pin is sampled and held internally
as the OC set point. Maximum programmable OC threshold is 0.55 V. A
voltage greater than 0.75V (max) activates an internal clamp and causes
OC threshold to be set at 400 mV. ROCSET not connected sets the 400 mV
default threshold.
VCC
FB
Device and LS driver power supply.
Operative range from 4.1 V to 13.2 V. Filter with at least 1μF MLCC to GND.
Error amplifier inverting input.
Connect with a resistor RFB to the output regulated voltage. Additional
resistor ROS to GND may be used to regulate voltages higher than the
reference.
7
COMP. Error amplifier output. Connect with an RF - CF // CP to GND to
compensate the device control loop in conjunction to the FB pin.
During the soft-start phase, a 10 μA current is sourced from this pin so the
COMP / DIS
compensation capacitors also act to program the SS time.
DIS. The device can be disabled by pulling this pin lower than 0.4 V (min).
Setting free the pin, the device enables again.
8
HS driver return path, current-reading and adaptive-dead-time monitor.
Connect to the LS drain to sense RdsON drop to measure the output current.
This pin is also used by the adaptive-dead-time control circuitry to monitor
when HS MOSFET is OFF.
PHASE
Doc ID 12754 Rev 4
5/35
Pins description and connection diagrams
2.2
L6726A
Thermal data
Table 3.
Symbol
Thermal data
Parameter
Value
Unit
RthJA
Thermal resistance junction to ambient(1)
85
°C/W
TMAX
Maximum junction temperature
150
°C
TSTG
Storage temperature range
-40 to 150
°C
TJ
Junction temperature range
-20 to 150
°C
1. Measured with the component mounted on a 2S2P board in free air (6.7 cm x 6.7 cm, 35 μm (P) and
17.5 μm (S) copper thickness).
6/35
Doc ID 12754 Rev 4
L6726A
Electrical specifications
3
Electrical specifications
3.1
Absolute maximum ratings
Table 4.
Absolute maximum ratings
Symbol
VCC
Parameter
Value
Unit
-0.3 to 15
V
15
45
V
-0.3 to (VBOOT - VPHASE) + 0.3
-1
VBOOT + 0.3
V
-8 to 30
V
-0.3 to VCC + 0.3
-2.5
V
-0.3 to 3.6
V
to GND
VBOOT
to PHASE
to GND
VUGATE
to PHASE
to PHASE; t < 50ns
to GND
VPHASE
to GND
VLGATE
to GND
to GND; t < 50ns
FB, COMP to GND
3.2
Electrical characteristics
VCC = 12 V; TA = -20 °C to +85 °C unless otherwise specified.
Table 5.
Symbol
Electrical characteristics
Parameter
Test conditions
Min.
Typ.
Max.
Unit
13.2
V
13.2
V
19.0
V
Recommended operating conditions
VCC
VIN
Device supply voltage
4.1
See Figure 1
Conversion input voltage
VCC < 7.0 V
Supply current and power-ON
ICC
VCC supply current
UGATE and LGATE = OPEN
IBOOT
BOOT supply current
UGATE = OPEN; PHASE to GND
UVLO
VCC Turn-ON
VCC rising
6
mA
0.5
mA
4.1
Hysteresis
0.2
V
V
Oscillator
FSW
Main oscillator accuracy
ΔVOSC
PWM ramp amplitude
dMAX
Maximum duty cycle
TA = 0 °C to +70 °C
243
270
297
225
270
315
kHz
1.1
80
Doc ID 12754 Rev 4
V
%
7/35
Electrical specifications
Table 5.
Symbol
L6726A
Electrical characteristics (continued)
Parameter
Test conditions
Min.
Typ.
Max.
-1
-
1
-1.5
-
1.5
Unit
Reference
Output voltage accuracy
VOUT = 0.8 V, TA = 0 °C to 70 °C
VOUT = 0.8 V
%
Transconductance error amplifier
gm
Transconductance(1)
IFB
Input bias current
A0
F0
ICOMP
5
Sourced from FB
mS
100
nA
Open loop gain(1)
70
dB
Unity gain(1)
4
MHz
Source current
360
μA
Sink current
-360
μA
10
μA
0.5
V
Current capability
Soft-Start and disable
ISS
Soft-start current
From COMP pin
DIS
Disable threshold
COMP falling
IUGATE
HS source current
BOOT - PHASE = 5 V to 12 V
1.5
A
RUGATE
HS sink resistance
BOOT - PHASE = 5 V to 12 V
1.1
Ω
ILGATE
LS source current
VCC = 5 V to 12 V
1.5
A
RLGATE
LS sink resistance
VCC = 5 V to 12 V
0.65
Ω
10
μA
0.4
Gate drivers
Over-current protection
IOCSET
OCSET current source
Sourced from LGATE pin.
See Section 7.1.1
VOC_SW
OC switch-over threshold
VLGATE/OC rising
VOCTH_FIXED Fixed OC threshold
VPHASE to GND
1. Guaranteed by design, not subject to test.
8/35
Doc ID 12754 Rev 4
780
-400
mV
mV
L6726A
4
Device description
Device description
L6726A is a single-phase PWM controller with embedded high-current drivers that provides
complete control logic and protections to realize in an easy and simple way a general DCDC step-down converter. Designed to drive N-channel MOSFETs in a synchronous buck
topology, with its high level of integration this 8-pin device allows reducing cost and size of
the power supply solution.
L6726A is designed to operate from a 5 V or 12 V supply bus. Thanks to the high precision
0.8V internal reference, the output voltage can be precisely regulated to as low as 0.8 V with
±1% accuracy over line and temperature variations (between 0 °C and +70 °C). The
switching frequency is internally set to 270 kHz.
This device provides a simple control loop with externally compensated transconductance
error-amplifier and programmable soft start. Low-side-less feature allows the device to
perform soft-start over pre-charged output avoiding negative spikes at the load side.
In order to avoid load damages, L6726A provides programmable threshold over current
protection. Output current is monitored across low-side MOSFET RdsON, saving the use of
expensive and space-consuming sense resistor. L6726A also features FB disconnection
protection, preventing dangerous uncontrolled output voltages in case of floating FB pin.
Doc ID 12754 Rev 4
9/35
Driver section
5
L6726A
Driver section
The integrated high-current drivers allow using different types of power MOSFET (also
multiple MOSFETs to reduce the equivalent RdsON), maintaining fast switching transition.
The driver for high-side MOSFET uses BOOT pin for supply and PHASE pin for return. The
driver for low-side MOSFET uses the VCC pin for supply and GND pin for return.
The controller embodies an anti-shoot-through and adaptive dead-time control to minimize
low side body diode conduction time, maintaining good efficiency while saving the use of
Schottky diode:
●
to check for high-side MOSFET turn off, PHASE pin is sensed. When the voltage at
PHASE pin drops down, the low-side MOSFET gate drive is suddenly applied;
●
to check for low-side MOSFET turn off, LGATE pin is sensed. When the voltage at
LGATE has fallen, the high-side MOSFET gate drive is suddenly applied.
If the current flowing in the inductor is negative, voltage on PHASE pin will never drop. To
allow the low-side MOSFET to turn-on even in this case, a watchdog controller is enabled: if
the source of the high-side MOSFET doesn't drop, the low side MOSFET is switched on so
allowing the negative current of the inductor to recirculate. This mechanism allows the
system to regulate even if the current is negative.
Power conversion input is flexible: 5 V, 12 V bus or any bus that allows the conversion (See
maximum duty cycle limitation and recommended operating conditions) can be chosen
freely.
10/35
Doc ID 12754 Rev 4
L6726A
5.1
Driver section
Power dissipation
L6726A embeds high current MOSFET drivers for both high side and low side MOSFETs: it
is then important to consider the power that the device is going to dissipate in driving them
in order to avoid overcoming the maximum junction operative temperature.
Two main terms contribute in the device power dissipation: bias power and drivers power.
●
Device bias power (PDC) depends on the static consumption of the device through the
supply pins and it is simply quantifiable as follow (assuming to supply HS and LS
drivers with the same VCC of the device):
P DC = V CC ⋅ ( I CC + I BOOT )
●
Drivers power is the power needed by the driver to continuously switch on and off the
external MOSFETs; it is a function of the switching frequency, the voltage supply of the
driver and total gate charge of the selected MOSFETs. It can be quantified considering
that the total power PSW dissipated to switch the MOSFETs (easy calculable) is
dissipated by three main factors: external gate resistance (when present), intrinsic
MOSFET resistance and intrinsic driver resistance. This last term is the important one
to be determined to calculate the device power dissipation. The total power dissipated
to switch the MOSFETs results:
P SW = F SW ⋅ [ Q gHS ⋅ ( V BOOT – V PHASE ) + Q gLS ⋅ V CC ]
where VBOOT - VPHASE is the voltage across the bootstrap capacitor.
External gate resistors helps the device to dissipate the switching power since the same
power PSW will be shared between the internal driver impedance and the external resistor
resulting in a general cooling of the device.
Figure 4.
Soft start (left) and disable (right)
Doc ID 12754 Rev 4
11/35
Soft start and disable
6
L6726A
Soft start and disable
L6726A implements a soft start to smoothly charge the output filter avoiding high in-rush
currents to be required from the input power supply. The device sources a 10 µA soft start
current from COMP, linearly charging the compensation network capacitors. The ramping
COMP voltage is compared to the oscillator triangular waveform generating PWM pulses of
increasing width that charge the output capacitors.
When the FB voltage crosses 800 mV, the output voltage is in regulation: soft start phase
will end and the transconductance error amplifier output will be enabled closing the control
loop.
In the event of an over current during soft start, the over current logic will override the soft
start sequence and will shut down the PWM logic and both the high side and low side gates.
This condition is latched, cycle VCC to recover.
The device sources soft start current only when VCC power supply is above UVLO
threshold and over current threshold setting phase has been completed.
6.1
Low-side-less start up (LSLess)
L6726A performs a special sequence in enabling LS driver to switch: during the soft-start
phase, the LS driver results disabled (LS = OFF) until the HS starts to switch. This avoids
the dangerous negative spike on the output voltage that can happen if starting over a precharged output and limits the output discharge (amount of output discharge depends on
programmed SS time length: the shorter the programmed SS, the more limited the output
discharge).
If the output voltage is pre-charged to a voltage higher than the final one, the HS would
never start to switch. In this case, LS is enabled and discharges the output to the final
regulation value.
Figure 5.
6.2
LSLess startup (left) vs non-LSLess startup (right)
Enable / disable
The device can be disabled by pushing COMP / DIS pin under 0.4 V (min). In this condition
HS and LS MOSFETs are turned off, and the 10 μA SS current is sourced from COMP / DIS
pin. Setting free the pin, the device enables again performing a new SS.
12/35
Doc ID 12754 Rev 4
L6726A
Protections
7
Protections
7.1
Overcurrent protection
The overcurrent feature protects the converter from a shorted output or overload, by sensing
the output current information across the low side MOSFET drain-source on-resistance,
RdsON. This method reduces cost and enhances converter efficiency by avoiding the use of
expensive and space-consuming sense resistors.
The low side RdsON current sense is implemented by comparing the voltage at the PHASE
node when LS MOSFET is turned on with the programmed OCP threshold voltage,
internally held. If the monitored voltage drop (GND to PHASE) exceeds this threshold, an
Overcurrent event is detected. If two overcurrent events are detected in two consecutive
switching cycles, the protection will be triggered and the device will turn off both LS and HS
MOSFETs in a latched condition.
To recover from over current protection triggered, VCC power supply must be cycled.
7.1.1
Overcurrent threshold setting
L6726A allows to easily program an overcurrent threshold ranging from 50 mV to 550 mV,
simply by adding a resistor (ROCSET) between LGATE and GND.
During a short time following VCC rising over UVLO threshold, an internal 10µA current
(IOCSET) is sourced from LGATE pin, determining a voltage drop across ROCSET. This
voltage drop will be sampled and internally held by the device as overcurrent Threshold. The
OC setting procedure overall time length ranges from 5.5 ms to 6.5 ms, proportionally to the
threshold being set.
Connecting a ROCSET resistor between LGATE and GND, the programmed threshold will be:
I OCSET ⋅ R OCSET
I OCth = ------------------------------------------R dsON
ROCSET values range from 5 kΩ to 55 kΩ.
If the voltage drop across ROCSET is too low, the system will be very sensitive to start-up
inrush current and noise. This can result in undesired OCP triggering. In this case, consider
increasing ROCSET value.
In case ROCSET is not connected, the device switches the OCP threshold to a 400 mV
default value: an internal safety clamp on LGATE is triggered as soon as LGATE voltage
reaches 700 mV (typ), enabling the 400 mV default threshold and suddenly ending OC
setting phase.
See Figure 6 for OC threshold setting procedure timings picture and oscilloscope sample
waveforms.
7.2
Feedback disconnection protection
In order to provide load protection even if FB pin is not connected, a 100 nA bias current is
always sourced from this pin. If FB pin is not connected, bias current will permanently pull
up FB: this forces COMP pin low, avoiding output voltage rising to dangerous levels.
Doc ID 12754 Rev 4
13/35
Protections
L6726A
Figure 6.
OC threshold setting procedure timings (top) and waveforms (bottom)
ROCSET connected
ROCSET not connected
UVLO Th
UVLO Th
VCC
VCC
PWM ramp
bottom edge
PWM ramp
bottom edge
Enable Th
Enable Th
COMP
COMP
700mV
700mV
LGATE
LGATE
5.5ms - 6.5ms
tDELAY
Setting Procedure
7.3
Setting Procedure
tDELAY
Undervoltage lock out
In order to avoid anomalous behaviors of the device when the supply voltage is too low to
support its internal rails, UVLO is provided: the device will start up when VCC reaches
UVLO upper threshold and will shutdown when VCC drops below UVLO lower threshold.
The 4.1 V maximum UVLO upper threshold allows L6726A to be supplied from 5 V and 12 V
busses in or-ing diode configuration.
Figure 7.
14/35
OCP trip, default threshold, LS: STD38NH02L (left) UVLO turn off (right)
Doc ID 12754 Rev 4
L6726A
Application details
8
Application details
8.1
Output voltage selection
L6726A is capable to precisely regulate an output voltage as low as 0.8 V. In fact, the device
comes with a fixed 0.8 V internal reference that guarantees the output regulated voltage to
be within ±1% tolerance over line and temperature variations between 0 °C and 70 °C
(excluding output resistor divider tolerance, when present).
Output voltage higher than 0.8 V can be achieved by adding a resistor ROS between FB pin
and ground. Referring to Figure 1, the steady state DC output voltage will be:
R FB ⎞
V OUT = V REF ⋅ ⎛⎝ 1 + ---------R OS⎠
where VREF is 0.8 V.
8.2
Compensation network
The control loop shown in Figure 8 is a voltage mode control loop. The error amplifier is a
transconductance type with fixed gain (3.3 ms typ.). The FB voltage is regulated to the
internal reference, thus the output voltage is fixed accordingly to the output resistor divider
(when present).
Transconductance error amplifier output current generates a voltage across ZF, which is
compared to oscillator saw-tooth waveform to provide PWM signal to the driver section.
PWM signal is then transferred to the switching node with VIN amplitude. This waveform is
filtered by the output filter.
Figure 8.
PWM control loop
VIN
OSC
ΔV OSC
_
L
+
COUT
PWM
COMPARATOR
ESR
OTA
+
COMP
_
VREF
FB
CF
RF
V OUT
R
CP
R FB
R OS
OUTPUT
DIVIDER
ZF
The converter transfer function is the small signal transfer function between the voltage at
the output node of the EA (COMP) and VOUT. This function has a double pole (complex
conjugate) at frequency FLC depending on the L-COUT resonance and a zero at FESR
Doc ID 12754 Rev 4
15/35
Application details
L6726A
depending on the output capacitor ESR. The DC gain of the modulator is simply the input
voltage VIN divided by the peak-to-peak oscillator voltage ΔVOSC.
VOUT is scaled and transferred to FB node by the output resistor divider.
The compensation network closes the loop joining FB and COMP node with transfer
function ideally equal to -gm·ZF.
Compensation goal is to close the control loop assuring high DC regulation accuracy, good
dynamic performances and stability. To achieve this, the overall loop needs high DC gain,
high bandwidth and good phase margin.
High DC gain is achieved giving an integrator shape to compensation network transfer
function. Loop bandwidth (F0dB) can be fixed choosing the right RF; however, for stability, it
should not exceed FSW/2π. To achieve a good phase margin, the control loop gain has to
cross 0 dB axis with -20 dB/decade slope.
As an example, Figure 9 shows an asymptotic bode plot of a type II compensation.
Figure 9.
Example of type II compensation.
Gain
[dB]
OTA
open loop
gain
closed loop
gain
compensation
gain
FZ
FP
20log (gm·RF )
converter
open loop
gain
0dB
20log [VIN/ΔVOSC·ROS/(RFB+ROS)]
F0dB
FLC
●
Open loop converter singularities:
a)
b)
●
1
F LC = --------------------------------2π L ⋅ C OUT
1
F ESR = ------------------------------------------2π ⋅ C OUT ⋅ ESR
Compensation Network singularities frequencies:
a)
b)
16/35
FESR
1
F Z = -----------------------------2π ⋅ R F ⋅ C F
1
F P = ------------------------------------------------CF ⋅ CP ⎞
⎛
2π ⋅ R F ⋅ --------------------⎝ C F + C P⎠
Doc ID 12754 Rev 4
Log (Freq)
L6726A
Application details
Type II compensation relies on the zero introduced by the output capacitors bank to achieve
stability. Thus, a needed condition to successfully apply type II compensation is F ESR < F 0dB
(usually true when output capacitor is based on electrolytic, aluminium electrolytic or
tantalum capacitor).
To define compensation network components values, the below suggestions may be
followed:
a)
Set the output resistor divider in order to obtain the desired output voltage:
V OUT
R FB
---------- = -------------–1
R OS
V REF
Usual values of RFB and ROS ranges from some hundreds of Ω to some kΩ
(consider trade-off between power dissipation on output resistor divider and offset
introduced by FB bias current).
If the desired output voltage is equal to internal reference, ROS has to be NC and
FB pin can be directly connected to VOUT.
b)
Set RF in order to obtain the desired closed loop regulator bandwidth according to
the approximated formula:
F 0dB ⋅ F ESR ΔV OSC 1 R FB + R OS
- ⋅ ------------------- ⋅ -------- ⋅ ---------------------------R F = -----------------------------2
R OS
V IN
gm
F LC
If VOUT = VREF, just consider (RFB+ROS)/ROS factor equal to 1.
c)
Place FZ below FLC (typically 0.2·FLC):
5
C F = -------------------------------2π ⋅ R F ⋅ F LC
d)
Place FP at 0.5·FSW:
CF
1
C P = ---------------------------------------------------- ≅ ------------------------------π ⋅ R F ⋅ C F ⋅ F SW – 1 π ⋅ R F ⋅ F SW
e)
Check that compensation network gain is lower than open loop transconductance
EA gain.
f)
Estimate phase margin obtained (it should be greater than 45°) and repeat,
modifying parameters, if necessary.
Doc ID 12754 Rev 4
17/35
Application details
8.3
L6726A
Soft-start time calculation
To calculate SS time (tSS), the following approximated equation can be used (CP