L6788A
3-phase controller with embedded drivers
for the next GPU generation
Features
■
1, 2 or 3 selectable phase operation
■
Phases self detection
■
High current internal drivers
■
Versatile solution: serial and parallel VID for
output voltage setting
■
Serial BUS interface for power manager and
monitoring
■
Automatic startup phase procedure
■
Advanced IC and VRM thermal management
to assure robust design and safe operation
■
5 V LDO regulator output to increases design
flexibility.
■
Adjustable and precise output voltage
■
Full differential current sense across inductor
■
Differential remote voltage sensing
■
LSLess startup to manage pre-biased output
■
Programmable overcurrent protection
■
Adjustable switching frequency
The controller assures fast protection against load
overcurrent and under / overvoltage.
■
Enable signal
L6788A is available in VPQFN 6 x 6 mm package.
■
VPQFN40 6x6 mm package with exposed pad
VPQFN40 - 6 x 6 mm
The device manages serial BUS communication
to program power management functionalities as
well as monitoring.
The device features automatic startup phase
procedure and phases self detection for safe
operation.
The controller embeds 5 V LDO regulator
increasing design flexibility.
Advanced IC and VRM thermal management to
assure robust design and safe operation.
Table 1.
Applications
■
Graphic card GPU supply
■
High current DC-DC converters
Device summary
Order code
Package
Packing
L6788A
VPQFN40
Tray
L6788ATR
VPQFN40
Tape and reel
Description
The device implements a one-to-three phases
step-down controller with three integrated high
current drivers in a compact 6x6 mm body
package with exposed pad.
Output voltage can be selected trough serial and
parallel VID up to 1.3500 V and managing D-VID
with ±2% output voltage accuracy.
July 2009
Doc ID 15341 Rev 2
1/18
www.st.com
18
Contents
L6788A
Contents
1
2
Application circuit and block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1
Principle application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pins description and connection diagram . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
3
4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5
Mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . 16
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2/18
Doc ID 15341 Rev 2
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Principle application circuit
5
1.1
Application circuit and block diagram
5
1
Doc ID 15341 Rev 2
Figure 1.
L6788A
Application circuit and block diagram
Principle application circuit (a)
3/18
Application circuit and block diagram
Block diagram
PGND
VCC2_DR
LGATE3
PHASE3
BOOT3
UGATE3
LGATE2
PHASE2
BOOT2
UGATE2
LGATE1
PHASE1
Block diagram
BOOT1
Figure 2.
UGATE1
1.2
L6788A
3V3
PGND
VCC2_DR
HS1
LS1
HS2
VCC2_DR
PGND
LS2
HS3
PGND
LS3
10uA
CURRENT SHARING
CORRECTION
PWM1
PWM2
DIGITAL
SOFT START
PWM1
PWM3
VCC2_DR
DAC &
SMBUS INTERFACE
SCL
SDA
IREF
RT/DROOP
Mode
L6788A
CONTROL LOGIC
AND PROTECTIONS
R1
R2
R3
TH
CH1 CURRENT
READING
CS1CS1+
CH2 CURRENT
READING
CS2CS2+
CH3 CURRENT
READING
CS3CS3+
IOUT/OCP
140%Vref
&SMBUS
Fsw sel
OVP
COMP.
+.1700V
&SMBUS
IREF
VREF
a. Refer to the application note for the reference schematic
Doc ID 15341 Rev 2
UVP
COMP.
TO OCP
50%Vref
&SMBUS
VSEN
COMP
FB
FBRTN
IREF
1.240V
ERROR
AMPLIFIER
RT/DROOP
GND DROP
RECOVERY
OCP
COMP.
VCC
VCC1_IC
AGND
IOUT/OCP
Circuitry
OUTEN & VR_HOT
1.240V
4/18
TCS
OCP
TOTAL DELIVERED
CURRENT
10uA
VR_HOT/EN
VR_HOT
IREF
IDROOP
IREF
OUTEN
5VCC
5.00V
TH
PWM3
PWM2
VCC1_IC
VID0
VID1
CURRENT SHARING
CORRECTION
VR_HOT
2.500V
10uA
CURRENT SHARING
CORRECTION
LOGIC PWM
ADAPTIVE ANTI
CROSS CONDUCTION
AVERAGE
CURRENT
1/2/3 PHASE
OSCILLATOR
RT/DROOP
LOGIC PWM
ADAPTIVE ANTI
CROSS CONDUCTION
TH
Die Temp.
Sensor
200k
LOGIC PWM
ADAPTIVE ANTI
CROSS CONDUCTION
VCC2_DR
1.500V
(SMBUS)
VCC2_DR
200k
Mode
MODE
L6788A
2
Pins description and connection diagram
Pins description and connection diagram
Pin connection (top view)
BOOT3
UGATE3
5VCC
TCS
MODE
IOUT/OCP
RT/DROOP
VSEN
AGND
COMP
Figure 3.
31
30
29
28
21
20
32
19
33
18
34
17
35
27
26
25
24
23
22
16
PGND
36
15
37
14
38
13
39
12
11
40
1
2
3
4
5
6
7
8
9
10
FB
FBRTN
CS3+
CS3CS2+
CS2CS1+
CS1R1
R2
BOOT1
UGATE1
POK
SCL
SDA
VR_HOT/EN
VID1
VID0
IREF
R3
PHASE3
LGATE3
VCC2_DR
UGATE2
BOOT2
PHASE2
LGATE2
VCC1_IC
LGATE1
PHASE1
2.1
Pin description
Table 2.
Pin n°
Pin description
Name
Description
1
BOOT1
Channel 1 HS driver supply. Connect through a capacitor (100 nF typ.) to
PHASE1
Needed external bootstrap diode.
The device implements Vin detections through this pin. See “vin detection”
section for details. A small resistor in series to the boot diode helps in reducing
Boot capacitor overcharge (see reference schematic).
2
UGATE1
Channel 1 HS driver output. It must be connected to the HS1 MOSFET gate.
A small series resistors helps in reducing device-dissipated power.
3
POK
Power OK
Open drain output sets free after soft start has finished and pulled low when
triggering any latched protection (OVP, UVP, OCP average).
Pull up to a voltage lower than 3.3 V (typ), if not used it can be left floating.
4
SCL
Serial BUS clock input.
5
SDA
Serial BUS data input.
Doc ID 15341 Rev 2
5/18
Pins description and connection diagram
Table 2.
Pin n°
6
L6788A
Pin description (continued)
Name
VR_HOT/
EN
Description
Voltage regulator HOT / enable pin. Internally pulled up by 10 µA (typ) to 3.3 V.
Multifunction pin to enable/disable the system (input-signal) and to provide the
information about the warning temperature (output-signal).
Forced low, the device stops operations with all MOSFETs OFF: all the latched
protections are disabled. Removing the short on VR_HOT/EN pin, the device
starts-up implementing soft-start and the voltage at the pin is clamped by the
device at 1.5 V (typ). When a warning temperature is detected the device
leaves the pin floating.
Thermal monitoring enabled if Vcc > UVLOVCC (See “thermal monitoring”
section for details).
VR_HOT/EN pin is set free when:
• Either TCS pin voltage overcomes the warning threshold voltage (see TCS
pin for details).
• Or Tj_IC Die temperature overcomes the die warning temperature (T_HOT)
Where T_HOT=T_Shutdown-T_Delta
Use a pull-up resistor in the range of 10 kΩ−30 kΩ when VR_HOT/EN pin is
directly pulled up to 3.3 V. (see VR_HOT/EN pin voltage Electrical
Characteristic table).
Cycle this pin to recover latch from protections.
7
VID1
8
VID0
9
10
11
6/18
IREF
R3
R2
Voltage identification pins. Internally pulled low by 10 µA.
They allow programming output voltage from the 4-level “power play table” in
PVID mode.
Current reference pin.
Internally fixed at 1.240 V, connecting a RIREF = 12.4 kΩ (+/-0.1%) resistor vs.
AGND allows setting 100 µA current that is mirrored into R1, R2, R3 pins in
order to program the three power play table levels voltage. See “power play
table level” section for details.
Default “power play table” voltage setting pins.
The device sources from each Rx pin the same constant current sourced from
the IREF pin (
Internally mirrored). As a consequence the Voltage between Rx pin and AGND
is given by the following relationship: VRx= IREF * Rx=100 µA*Rx, where IREF
is the current programmed on IREF pin (100 µA). As soon as the ENABLE is
released the device reads the Rx pin voltage and it stores these value. As a
consequence if the power play table is re-written by serial BUS the analog
values can not be recovered (voltage fixed by Rx resistor). See “power play
table level” section for details.
12
R1
13
CS1-
Channel 1 current sense negative input.
Connect through a Rg resistor to the output-side of the channel 1 inductor.
14
CS1+
Channel 1 current sense positive input.
Connect through an R-C filter to the phase-side of the channel 1 inductor.
15
CS2-
Channel 2 current sense negative input.
Connect through a Rg resistor to the output-side of the channel 2 inductor.
Still connect to VOUT through Rg resistor when using 1-phase operation.
Doc ID 15341 Rev 2
L6788A
Pins description and connection diagram
Table 2.
Pin n°
Pin description (continued)
Name
Description
16
CS2+
Channel 2 current sense positive input.
Connect through an R-C filter to the phase-side of the channel 2 inductor.
Short to VOUT when using 1-Phase operation.
17
CS3-
Channel 3 current sense negative input.
Connect through a Rg resistor to the output-side of the channel 3 inductor.
Still connect to VOUT through Rg resistor when using 1 or 2-phase operation.
18
CS3+
Channel 3 current sense positive input.
Connect through an R-C filter to the phase-side of the channel 3 inductor.
Short to VOUT when using 1 or 2-phase operation.
19
FBRTN
Feedback return.
This pin is the ground return for remote sensing the output voltage.
Connect directly to the point where the output voltage is to be regulated.
Error amplifier inverting input pin.
Connect with a resistor RFB vs. VSEN and with an RF - CF//CP vs. COMP pin.
See reference schematic for more details.
A current proportional to the load current can be sourced (in according to
RT/DROOP pin status) from this pin in order to implement the droop effect.
See “droop function” section for details.
20
FB
21
COMP
Error amplifier output. Connect with an RF - CF//CP vs. FB pin.
22
AGND
Signal ground pin. All the internal references are referred to this pin.
Connect it to the PCB signal ground (AGND).
23
VSEN
Output voltage monitor, manages OVP/UVP protections.
Connect to the positive side of the load to perform remote sense.
See “output voltage protections” section for more details.
24
25
RT/
DROOP
Operation frequency setting.
Internally fixed at 1.240 V it allows programming the switching frequency FSW
of each channel.
Frequency is programmed according to the Rosc resistor connected from the
pin vs. AGND with again of 9 kHz/µA. Leaving the pin floating programs a
switching frequency of 200 kHz per phase.
The device uses this pin also to enable/disable the droop function.
See “droop function“ section for details.
Output current indication and over current protection setting.
The device sources from this pin a current proportional to the load current
[(DCR/Rg)*IOUT)].
Connect a resistor from this pin to AGND to program the over current
IOUT/OCP protection level.
This pin is also used as output current indication. Voltage measured at this pin
is proportional to the output current. External NTC can be used for
temperature compensation of OCP and IOUT readings. See “over current
protection “section for details.
Doc ID 15341 Rev 2
7/18
Pins description and connection diagram
Table 2.
Pin n°
Pin description (continued)
Name
Description
MODE
Phase Number selection pin. The maximum voltage on mode pin has to be
limited to 3.6 V.
The voltage on MODE pin is used to select the number of phase used during
normal operation. The device has an internal resistor divider in order to have
1.7 V on MODE pin when it is left floating. See “phase number selection”
section for more details.
TCS
Temperature sense input pin.
Connecting the PTC network between 5 VCC and AGND in order to generate
on TCS pin a voltage proportional to the temperature.
The device reads the TCS pin voltage and compare it with two thresholds in
order to implements the warning and shutdown temperature action.
See “thermal monitoring” section for details.
28
5VCC
5 VCC pin. The pin output is 5 V voltage with a minimum of 20 mAdc.
The device supply the 5 VCC if VCC1_IC pin voltage is higher than 8 (typ).
Filter the 5 VCC pin with a capacitor (470 nFMIN - 2.2 µF MAX) versus PGND.
29
UGATE3
Channel 3 HS driver output. It must be connected to the HS3 MOSFET gate.
A small series resistors helps in reducing device-dissipated power.
30
BOOT3
Channel 3 HS driver supply. Connect through a capacitor (100 nF typ.) to
PHASE3
Needed external bootstrap diode.
The device implements Vin detections through this pin. see “vin detection”
section for details. A small resistor in series to the boot diode helps in reducing
Boot capacitor overcharge (see reference schematic).
31
PHASE3
Channel 3 HS driver return path. Connected to the HS3 MOSFET source and
provides return path for the HS driver of channel 3.
32
LGATE3
Channel 3 LS driver output. Driver can support 12 V bus voltage.
A small series resistor helps in reducing device-dissipated power.
26
27
33
LS driver supply. Driver can support 12 V bus voltage.
VCC2_DR Connect to 12 V_BUS and filter with RC network.
(Suggested value: R = 2.2 /0805 size; C=2x1 µF MLCC capacitor vs. PGND).
UGATE2
Channel 2 HS driver output. It must be connected to the HS2 MOSFET gate.
A small series resistors helps in reducing device-dissipated power.
35
BOOT2
Channel 2 HS driver supply. Connect through a capacitor (100 nF typ.) to
PHASE2
Needed external bootstrap diode.
The device implements Vin detections through this pin. See “vin detection”
section for details. A small resistor in series to the boot diode helps in reducing
Boot capacitor overcharge (see Reference schematic).
36
PHASE2
Channel 2 HS driver return path. Connected to the HS2 MOSFET source and
provides return path for the HS driver of channel 2.
37
LGATE2
Channel 2 LS driver output. Driver can support 12 V bus voltage.
A small series resistor helps in reducing device-dissipated power.
34
8/18
L6788A
Doc ID 15341 Rev 2
L6788A
Pins description and connection diagram
Table 2.
Pin description (continued)
Pin n°
Name
38
VCC1_IC
Device supply voltage pin. The operative supply voltage is 12 V ± 10%.
Connect to 12 V_BUS and filter with RC network (R = 2.2 /0603 size, and
C=1x1 µF MLCC capacitor vs. PGND).
39
LGATE1
Channel 1 LS driver output. Driver can support 12 V bus voltage.
A small series resistor helps in reducing device-dissipated power.
40
PHASE1
Channel 1 HS driver return path. Connected to the HS1 MOSFET source and
provides return path for the HS driver of channel 1.
PGND
Power ground pin (LS drivers return path). Connect to power ground plane.
Exposed pad connects also the silicon substrate. As a consequence it makes
a good thermal contact with the PCB to dissipate the power necessary to drive
the external MOSFETs. Connect it to the power ground plane using 4.2x4.2
mm square area on the PCB and with sixteen vias to improve electrical and
thermal conductivity.
41
Description
Doc ID 15341 Rev 2
9/18
Maximum ratings
L6788A
3
Maximum ratings
3.1
Thermal data
Table 3.
Thermal data
Symbol
3.2
Parameter
Unit
RthJA
Thermal resistance junction to ambient
(Device soldered on 2s2p PC board)
35
°C / W
RthJC
Thermal resistance junction to case
1
°C / W
TMAX
Maximum junction temperature
150
°C
Tstg
Storage temperature range
-40 to 150
°C
TJ
Junction temperature range
0 to 125
°C
Value
Unit
VCC1_IC, VCC2_DR To PGNDx
15
V
VBOOTx-VPHASEx Boot voltage
15
V
VUGATEx-VPHASEx
15
V
LGATEx to PGND
-0.3 to
Vcc+0.3
V
5VCC to PGND
-0.3 to 7
V
SCL, SDA to PGND
-0.3 to 5.5
V
All other pins to PGND
-0.3 to 3.6
V
Negative peak voltage to PGND; T < 400 ns
VCC1_IC = VCC2_DR = 12 V; VBOOTx = 8.5 V
-8
V
Positive peak voltage to PGND;
VCC1_IC = VCC2_DR = 15 V; VBOOTx = 41 V
26
V
Absolute maximum ratings
Table 4.
Absolute maximum ratings
Symbol
VPHASEx
10/18
Value
Parameter
Doc ID 15341 Rev 2
L6788A
Electrical specifications
4
Electrical specifications
4.1
Electrical characteristics
VCC = 12 V ± 15%, TJ = 25 °C unless otherwise specified.
Table 5.
Symbol
Electrical characteristics
Parameter
Test condition
Min.
Typ.
Max.
Unit
Supply voltages operating conditions
VCC1_IC
Device supply voltage
10.8
12
13.2
V
VCC2_DR
LS driver supply voltage
10.8
12
13.2
V
Vsuorces
(VIN)
Conversion input voltage
Vsource1 = Vsource2
13.2
V
Vsource1Vsource2
BOOTx supply current
Max difference between conversion
input voltages (static condition)
2.4
V
10.8
Supply current and power-on
ICC1_IC
VCC1_IC supply current
UGATEx and LGATEx OPEN;
VCC1_IC=VCC2_DR=VBOOTx=12 V
25
mA
ICC2_DR
VCC2_DR supply current
LGATEx = OPEN;
VCC1_IC=VCC2_DR= 12 V
6
mA
IBOOTx
BOOTx supply current
UGATEx = OPEN; PHASEx to PGND;
VCC1_IC=VCC2_DR=BOOTx=12 V
2
mA
VCC1_IC turn-ON threshold
VCC1_IC rising;
VCC2_DR = VCC1_IC
7
V
VCC1_IC turn-OFF
threshold
VCC1_IC falling;
VCC2_DR = VCC1_IC
5.8
V
5VCC turn-ON threshold
5 VCC rising; VCC1_IC=VCC2_DR>7
3
V
5VCC turn-OFF threshold
5 VCC falling; VCC1_IC=VCC2_DR>7
1
V
200
kHz
UVLOVCC_IC
UVLO5VCC
Oscillator, soft start time and inhibit
FOSC
Trp
Default value
RT = OPEN
Programmability range
RT connected to AGND
Soft start time
VCC1_IC = 12 V; 5VCC = 5 V;
VOUT=1.350 V; EN rising.
200
3
Input low
800
kHz
5
ms
0.7
V
ENABLE threshold
Input high
VR_HOT/EN Pull-Up current
Voltage at VR_HOT/EN pin
during normal operation
ΔVosc
Ramp amplitude
FAULT
Voltage at pin RT pin
1.3
V
VR_HOT/EN to AGND
10
μA
IVR_HOT_EN = 50 μA to 150 μA;
(current sunk by VR_HOT/EN)
1.5
V
1.5
V
3.3
V
OVP, UVP and OCP avg and thermal
shutdown active
Doc ID 15341 Rev 2
11/18
Electrical specifications
Table 5.
L6788A
Electrical characteristics (continued)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
-2
-
2
%
Reference and DAC
VOUT
Output voltage accuracy
VOUT > 0.800 V; RIREF=12.4 kΩ
IRX
RX source current
RIREF = 12.4 kΩ resistor to AGND.
100
μA
VIREF
IREF pin voltage
RIREF = 12.4 kΩ resistor to AGND.
1.240
V
Accuracy
I5VCC = 2 mA to 20 mA; C = 1 µF
to PGND.
Maximum output current
C = 1 µF to PGND.
5VCC
-2.5
2.5
25
%
mA
Input low
0.7
V
VID threshold; PVID mode
Input high
VID
1.3
V
10
μA
1.700
V
ICSX- rising;
RIREF = 12.4 kΩ resistor to AGND.
33
μA
Over voltage threshold
VSEN rising;
% programmed reference voltage
140
%
Under voltage threshold
VSEN falling;
% programmed reference voltage
50
%
Pull-down current
VIDx to 3.3 V
OCPAVG
Over current threshold
on total output current
IOUT/OCP rising
IOCTH
Over current threshold
for each phase
OVP
UVP
Protections
Thermal monitor
VTCS
OT warning
TCS rising
1.500
V
OT shut down
TCS rising
2.500
V
Soft-start end indicator
VPOK
POK low voltage
I = -4 mA
0.4
V
Error amplifier
AO
100
dB
15
MHz
2
V/μs
1.5
A
GBWP
Gain bandwidth product
SR
Slew rate
COMP = 10 pF to AGND
IUGATEx
High side source current
BOOTx-PHASEx = 12 V;
CUGATEx to PHASEx = 3.3 nF
RUGATEx
High side sink resistance
BOOTx-PHASEx = 12 V;
2
Ω
ILGATEx
Low side source current
VCC1_IC=VCC2_DR = 12 V;
CLGATEx to PGND = 5.6 nF
2
A
RLGATEx
Low side sink resistance
VCC1_IC = VCC2_DR = 12 V;
1
Ω
Gate drivers
12/18
Doc ID 15341 Rev 2
L6788A
Electrical specifications
Table 6.
GPU table for SVID mode
STEP
VID5
VID4
VID3
VID2
VID1
VID0
VREF
1
0
0
0
0
0
0
1.3500
2
0
0
0
0
0
1
1.3375
3
0
0
0
0
1
0
1.3250
4
0
0
0
0
1
1
1.3125
5
0
0
0
1
0
0
1.3000
6
0
0
0
1
0
1
1.2875
7
0
0
0
1
1
0
1.2750
8
0
0
0
1
1
1
1.2650
9
0
0
1
0
0
0
1.2500
10
0
0
1
0
0
1
1.2375
11
0
0
1
0
1
0
1.2250
12
0
0
1
0
1
1
1.2125
13
0
0
1
1
0
0
1.2000
14
0
0
1
1
0
1
1.1875
15
0
0
1
1
1
0
1.1750
16
0
0
1
1
1
1
1.1650
17
0
1
0
0
0
0
1.1500
18
0
1
0
0
0
1
1.1375
19
0
1
0
0
1
0
1.1250
20
0
1
0
0
1
1
1.1125
21
0
1
0
1
0
0
1.1000
22
0
1
0
1
0
1
1.0875
23
0
1
0
1
1
0
1.0750
24
0
1
0
1
1
1
1.0650
25
0
1
1
0
0
0
1.0500
26
0
1
1
0
0
1
1.0375
27
0
1
1
0
1
0
1.0250
28
0
1
1
0
1
1
1.0125
29
0
1
1
1
0
0
1.0000
30
0
1
1
1
0
1
0.9875
31
0
1
1
1
1
0
0.9750
32
0
1
1
1
1
1
0.9650
33
1
0
0
0
0
0
0.9500
Doc ID 15341 Rev 2
13/18
Electrical specifications
Table 6.
14/18
L6788A
GPU table for SVID mode (continued)
STEP
VID5
VID4
VID3
VID2
VID1
VID0
VREF
34
1
0
0
0
0
1
0.9375
35
1
0
0
0
1
0
0.9250
36
1
0
0
0
1
1
0.9125
37
1
0
0
1
0
0
0.9000
38
1
0
0
1
0
1
0.8875
39
1
0
0
1
1
0
0.8750
40
1
0
0
1
1
1
0.8650
41
1
0
1
0
0
0
0.8500
42
1
0
1
0
0
1
0.8375
43
1
0
1
0
1
0
0.8250
44
1
0
1
0
1
1
0.8125
45
1
0
1
1
0
0
0.8000
46
1
0
1
1
0
1
0.7875
47
1
0
1
1
1
0
0.7750
48
1
0
1
1
1
1
0.7650
49
1
1
0
0
0
0
0.7500
50
1
1
0
0
0
1
0.7375
51
1
1
0
0
1
0
0.7250
52
1
1
0
0
1
1
0.7125
53
1
1
0
1
0
0
0.7000
54
1
1
0
1
0
1
0.6875
55
1
1
0
1
1
0
0.6750
56
1
1
0
1
1
1
0.6650
57
1
1
1
0
0
0
0.6500
58
1
1
1
0
0
1
0.6375
59
1
1
1
0
1
0
0.6250
60
1
1
1
0
1
1
0.6125
61
1
1
1
1
0
0
0.6000
62
1
1
1
1
0
1
0.5875
63
1
1
1
1
1
0
0.5750
64
1
1
1
1
1
1
0.5625
Doc ID 15341 Rev 2
L6788A
Electrical specifications
Table 7.
PVID mode table
VID1 (pin)
VID0 (pin)
Selected dynamic voltage table (DVT) level
Resistor strap
0
0
Level 1
R1
0
1
Level 2
R2
1
0
Level 3
R3
1
1
Level 4
R3
Doc ID 15341 Rev 2
15/18
Mechanical data and package dimensions
5
L6788A
Mechanical data and package dimensions
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
Figure 4.
VFQFPN40 package mechanical data
mm
inch
DIM.
A
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.800
0.900
1.000
0.031
0.035
0.039
0.020
0.050
A1
0.0008 0.0019
b
0.180
0.250
0.300
0.007
0.009
0.012
D
5.900
6.000
6.100
0.232
0.236
0.240
D2
3.950
4.100
4.200
0.155
0.161
0.165
E
5.900
6.000
6.100
0.232
0.236
0.240
E2
3.950
4.100
4.200
0.155
0.161
0.165
e
L
ddd
0.500
0.300
0.400
OUTLINE AND
MECHANICAL DATA
0.020
0.500
0.080
0.012
0.015
0.018
0.003
VFQFPN40 ( 6x6x1.0mm)
Very Fine Quad Flat Package No lead
ddd
16/18
Doc ID 15341 Rev 2
L6788A
6
Revision history
Revision history
f
Table 8.
Document revision history
Date
Revision
Changes
27-Jan-2009
1
Initial release
22-Jul-2009
2
Updated Figure 2 on page 4
Doc ID 15341 Rev 2
17/18
L6788A
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Doc ID 15341 Rev 2
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