L6932D1.5TR

L6932 HIGH PERFORMANCE 2A ULDO LINEAR REGULATOR ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 2V TO 14V INPUT VOLTAGE RANGE 200mΩ Rdson MAX. 200µA QUIESCENT CURRENT AT ANY LOAD EXCELLENT LOAD AND LINE REGULATION 1.5V, 1.8V AND 2.5V FIXED VOLTAGE ADJUSTABLE FROM 1.2V TO 5V (L6932D1.2) 1% VOLTAGE REGULATION ACCURACY SHORT CIRCUIT PROTECTION THERMAL SHUT DOWN SO-8 (4+4) PACKAGE SO-8 (4+4) ORDERING NUMBERS: L6932D1.2 (SO-8) L6932D1.2TR (T&R) L6932D1.5 (SO-8) L6932D1.5TR (T&R) L6932D1.8 (SO-8) L6932D1.8TR (T&R) L6932D2.5 (SO-8) L6932D2.5TR (T&R) APPLICATIONS ■ MOTHERBOARDS ■ ■ ■ ■ ■ MOBILE PC HAND-HELD INSTRUMENTS PCMCIA CARDS PROCESSORS I/O CHIPSET AND RAM SUPPLY Mosfet, can be usefull for the DC-DC conversion between 2.5V and 1.5V at 2A in portable applications reducing the power dissipation. L6932 is available in 1.5V, 1.8V, 2.5V and adj version from 1.2V and ensure a voltage regulation accuracy of 1%. The current limit is fixed at 2.5A to control the current in short circuit condition within ±8%. The current is sensed in the power mos in order to limit the power dissipation. The device is also provided of a thermal shut down that limits the internal temperature at 150°C with an histeresys of 20°C. L6932 provides the Enable and the Power good functions. DESCRIPTION The L6932 Ultra Low Drop Output linear regulator operates from 2V to 14V and is able to support 2A. Designed with an internal 50mΩ N-channel TYPICAL OPERATING CIRCUIT VIN 2V to 14V IN 2 3 OUT VOUT 1.5V-1.8V-2.5V L6932D C1 5,6,7,8 GND EN 1 4 PGOOD C2 VIN 2V to 14V IN 2 4 OUT R1 VOUT 1.2V to 5V L6932D C1 5,6,7,8 GND EN 1 3 ADJ C2 R2 December 2005 Rev. 9 1/11 L6932 PIN CONNECTIONS EN IN ADJ OUT 1 2 3 4 8 7 6 5 GND GND GND GND EN IN OUT PGOOD 1 2 3 4 8 7 6 5 GND GND GND GND L6932D1.2 L6932D1.5 L6932D1.8 L6932D2.5 PIN FUNCTION N° L6232D 1.2 L6232D 1.5/1.8/ 2.5 Description 1 2 ADJ 3 – OUT 4 – 5, 6, 7, 8 EN IN – OUT – Enables the device if connected to Vin and disables the device if forced to gnd. Supply voltage. This pin is connected to the drain of the internal N-mos. Connect this pin to a capacitor larger than 10µF. Connecting this pin to a voltage divider it is possible to programme the output voltage between 1.2V and 5V. Regulated output voltage. This pin is connected to the source of the internal N-mos. Connect this pin to a capacitor of 10µF. Regulated output voltage. This pin is connected to the source of the internal N-mos. Connect this pin to a capacitor of 10µF. PGOOD Power good output. The pin is open drain and detects the output voltage. It is forced low if the output voltage is lower than 90% of the programmed voltage. GND Ground pin. ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit Vin VIN and Pgood EN, OUT and ADJ 14.5 -0.3 to (Vin +0.3) V V THERMAL DATA Symbol Parameter Value Unit Rth J-amb Tmax Thermal Resistance Junction to Ambient Maximum Junction Temperature Storage Temperature Range 62 (*) 150 -65 to 150 °C/W °C °C Tstg (*) Measured on Demoboard with about 4 cm2 of dissipating area 2 Oz. 2/11 L6932 BLOCK DIAGRAM (Referred to the Fixed Voltage version) IN CHARGE PUMP VREF REFERENCE VREF=1.25V DRIVER CURRENT LIMIT + ERROR AMPL. OUT EN ENABLE THERMAL SENSOR 0.9 VREF + PG GND D99IN1100 ELECTRICAL CHARACTERISTCS (Tj = 25°C, VIN = 5V unless otherwise specified) (*) Specification referred to Tj from -25°C to 125°C. Symbol Parameter Test Condition Min. Typ. Max. Unit Vin Vo Operating Supply Voltage Output voltage L6932D1.2 Output voltage L6932D1.5 Output voltage L6932D1.8 Output voltage L6932D2.5 L6932D1.2 Line Regulation Io = 0.1A; Vin = 3.3V Io = 0.1A; Vin = 3.3V Io = 0.1A; Vin = 3.3V Io = 0.1A; Vin = 3.3V Vin = 2.5V ±10%; Io = 10mA Vin = 3.3V ±10%; Io = 10mA Vin = 5V ±10%; L6932D1.5 Line Regulation Io = 10mA Vin = 2.5V ±10%; Io = 10mA Vin = 3.3V ±10%; Io = 10mA Vin = 5V ±10%; L6932D1.8 Line Regulation Io = 10mA Vin = 2.5V ±10%; Io = 10mA Vin = 3.3V ±10%; Io = 10mA Vin = 5V ±10%; L6932D2.5 Line Regulation L6932D1.2 Load Regulation L6932D1.5 Load Regulation L6932D1.8 Load Regulation L6932D2.5 Load Regulation Vin = 5V ±10%; Io = 10mA Io = 10mA Vin = 3.3V ±10%; Io = 10mA Vin = 3.3V; 0.1A < Io < 2A Vin = 3.3V; 0.1A < Io < 2A Vin = 3.3V; 0.1A < Io < 2A Vin = 3.3V; 0.1A < Io < 2A 2 1.188 1.485 1.782 2.475 1.2 1.5 1.8 2.5 14 1.212 1.515 1.818 2.525 5 5 5 5 5 5 5 5 5 5 5 15 15 15 15 200 V V V V V mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mΩ Rdson Drain Source ON resistance 3/11 L6932 ELECTRICAL CHARACTERISTCS (continued) Symbol Parameter Test Condition Min. Typ. Max. Unit Iocc Iq Ish Current limiting Quiescent current Shutdown current Ripple Rejection 2V < Vin < 14V f = 120Hz, Io = 1A Vin = 5V, ∆Vin = 2Vpp Vo rise Ipgood =1mA * 2.3 2.5 0.2 2.7 0.4 25 A mA µA 60 0.5 75 0.65 90 10 0.2 0.4 0.8 dB V %Vo %Vo V Ven EN Input Threshold Pgood threshold Pgood Hysteresis Pgood saturation Figure 1. Output Voltage vs. Junction Temperature (L6932D1.2) 1.213 1.212 Figure 3. Output Voltage vs. Junction Temperature (L6932D2.5) 2.520 2.515 1.212 1.211 V 1.211 2.510 V 2.505 1.210 1.210 1.209 -60 -40 -20 0 20 40 60 80 100 120 140 160 Temp [°C] 2.500 2.495 -60 -40 -20 0 20 40 60 80 100 120 140 160 Temp [°C] Figure 2. Output Voltage vs. Junction Temperature (L6932D1.8) 1.808 Figure 4. Quiescent Current vs. Junction Temperature 310 300 Vin=5V 290 1.804 1.800 V Iq 280 1.796 (uA) 270 1.792 260 1.788 -60 -40 -20 0 20 40 60 80 Temp [°C] 100 120 140 160 250 -40 -20 0 20 40 60 Temp [°C ] 80 100 120 140 4/11 L6932 Figure 5. Shutdown Current vs. Junction TemperatureAPPLICATION INFORMATIONS 7.5 7 6.5 Ishdn (uA) 5.5 5 4.5 4 Vin=5V 6 -40 -20 0 20 40 Temp [°C ] 60 80 100 120 140 APPLICATION CIRCUIT In figure 6 the schematic circuit of the demoboards are shown. Figure 6. Demoboards Schematic Circuit VIN VOUT IN EN C1 OUT 2 1 5 GND L6932D1.5 L6932D1.8 L6932D2.5 6 7 8 3 4 PGOOD C2 VIN IN EN C1 2 1 5 GND 4 OUT R1 VOUT 1.2V to 5V L6932D1.2 3 6 7 8 ADJ C2 R2 VOUT = 1.2 × (R1+ R2) R2 COMPONENT LIST Fixed version Reference Part Number Description Manufacturer C1 C2 C34Y5U1E106Z C34Y5U1E106Z 10uF, 25V 10uF, 25V TOKIN TOKIN 5/11 L6932 Figure 7. Demoboard Layout (Fixed Version) Adjustable version Reference Part Number Description Manufacturer C1 C2 R1 R2 C34Y5U1E106Z C34Y5U1E106Z 10uF, 25V 10uF, 25V 5.6K, 1%, 0.25W 3.3K, 1%, 0.25W TOKIN TOKIN Neohm Neohm Figure 8. Demoboard Layout (Adjustable Version) COMPONENTS SELECTION Input Capacitor The input capacitor value depends on a lot of factors such as load transient requirements, input source (battery or DC/DC converter) and its distance from the input cap. Usually a 47µF is enough for any application but a much lower value can be sufficient in many cases. Output Capacitor The output capacitor choice depends basically on the load transient requirements. Tantalum, Speciality Polimer, POSCAP and aluminum capacitors are good and offer very low ESR values. 6/11 L6932 Multilayer ceramic caps have the lowest ESR and can be required for particular applications. Nevertheless in several applications they are ok, the loop stability issue has to be considered (see loop stability section). Below a list of some suggested capacitor manufacturers. Manufacturer Type Cap Value (µF) Rated Voltage (V) PANASONIC TAYO YUDEN TDK TOKIN SANYO PANASONIC KEMET CERAMIC CERAMIC CERAMIC CERAMIC POSCAP SP TANTALUM 1 to 47 1 to 47 1 to 47 1 to 47 1 to 47 1 to 47 1 to 47 4 to 16 4 to 16 4 to 16 4 to 16 4 to 16 4 to 16 4 to 16 Loop Stability The stability of the loop is affected by the zero introduced by the output capacitor. The time constant of the zero is given by: T = ESR ⋅ C OUT 1 F ZERO = -------------------------------------------2 π ⋅ ESR ⋅ C OUT This zero helps to increase the phase margin of the loop until the time constant is higher than some hundreds of nsec, depending also on the output voltage and current. So, using very low ESR ceramic capacitors could produce oscillations at the output, in particular when regulating high output voltages (adjustable version). To solve this issue is sufficient to add a small capacitor (e.g. 1nF to 10nF) in parallel to the high side resistor of the external divider, as shown in figure 9. Figure 9. Compensation Network VIN=2V TO 14V IN OUT VOUT=1.2V TO 5V UP to 2A 2 L6932D1.2 4 R1 ADJ C3 EN C1 1 5 GND 6 7 3 8 R2 C2 Thermal Considerations Since the device is housed in a small SO(4+2+2) package the thermal issue can be the bottleneck of many applications. The power dissipated by the device is given by: PDISS = (VIN - VOUT) · IOUT 7/11 L6932 The thermal resistance junction to ambient of the demoboard is approximately 62°C/W. This mean that, considering an ambient temperature of 60°C and a maximum junction temperature of 150°C, the maximum power that the device can handle is 1.5W. This means that the device is able to deliver a DC output current of 2A only with a very low dropout. In many applications, high output current pulses are required. If their duration is shorter than the thermal constant time of the board, the thermal impedance (not the thermal resistance) has to be considered. In figure 10 the thermal impedance versus the duration of the current pulse for the SO(4+2+2) mounted on board is shown. Figure 10. Thermal Impedance Considering a pulse duration of 1sec, the thermal impedance is close to 20°C/W, allowing much bigger power dissipated. Example: Vin = 3.3V Vout = 1.8V Iout = 2A Pulse Duration = 1sec The power dissipated by the device is: PDISS = (VIN - VOUT) · IOUT = 1.5 · 2 3W Considering a thermal impedance of 20°C/W, the maximum junction temperature will be: TJ = TA + ZTHJA · PDISS = 60 + 60 = 120°C Obviously, with pulse durations longer than approximately 10sec the thermal impedance is very close to the thermal resistance (60°C/W to 70°C/W). 8/11 L6932 Figure 11. SO-8 Mechanical Data & Package Dimensions mm DIM. MIN. A A1 A2 B C D (1) E e H h L k ddd 5.80 0.25 0.40 1.35 0.10 1.10 0.33 0.19 4.80 3.80 1.27 6.20 0.50 1.27 0.228 0.010 0.016 TYP. MAX. 1.75 0.25 1.65 0.51 0.25 5.00 4.00 MIN. 0.053 0.004 0.043 0.013 0.007 0.189 0.15 0.050 0.244 0.020 0.050 TYP. MAX. 0.069 0.010 0.065 0.020 0.010 0.197 0.157 inch OUTLINE AND MECHANICAL DATA 0˚ (min.), 8˚ (max.) 0.10 0.004 Note: (1) Dimensions D does not include mold flash, protrusions or gate burrs. Mold flash, potrusions or gate burrs shall not exceed 0.15mm (.006inch) in total (both side). SO-8 0016023 C 9/11 L6932 Table 1. Revision History Date Revision Description of Changes February 2003 December 2005 8 9 First Issue Added new Ordering Numbers: L6932D1.5 & L6932D1.5TR. 10/11 L6932 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 11/11