L6997S

L6997S STEP DOWN CONTROLLER FOR LOW VOLTAGE OPERATIONS 1 ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Features FROM 3V TO 5.5V VCC RANGE MINIMUM OUTPUT VOLTAGE AS LOW AS 0.6V 1V TO 35V INPUT VOLTAGE RANGE CONSTANT ON TIME TOPOLOGY VERY FAST LOAD TRANSIENTS 0.6V, ±1% VREF SELECTABLE SINKING MODE LOSSLESS CURRENT LIMIT, AVAILABLE ALSO IN SINKING MODE REMOTE SENSING OVP,UVP LATCHED PROTECTIONS 600µA TYP QUIESCENT CURRENT POWER GOOD AND OVP SIGNALS PULSE SKIPPING AT LIGTH LOADS 94% EFFICIENCY FROM 3.3V TO 2.5V Figure 1. Package TSSOP20 Table 1. Order Codes Part Number L6997S L6997STR Package TSSOP20 Tape & Reel 3 Description 2 ■ Applications NETWORKING ■ DC/DC MODULES ■ DISTRIBUTED POWER ■ MOBILE APPLICATIONS ■ CHIP SET, CPU, DSP AND MEMORIES SUPPLY Figure 2. Minimum Component Count Application Rin2 Rin1 The device is a high efficient solution for networking dc/dc modules and mobile applications compatible with 3.3V bus and 5V bus. It's able to regulate an output voltage as low as 0.6V. The constant on time topology assures fast load transient response. The embedded voltage feed-forward provides nearly constant switching frequency operation in spite of a wide input voltage range. An integrator can be introduced in the control loop to reduce the static output voltage error. The remote sensing improves the static and dynamic regulation, recovering the wires voltage drop. Pulse skipping technique reduces power consumption at light loads. Drivers current capability allows output currents in excess of 20A. 3.3V Cin VCC VDR OSC BOOT HGATE HS Dboot Cboot L 0.6V Ro1 PHASE PGOOD OVP LGATE LS DS Ro2 ILIM Rilim L6997SPGND GND GNDSENSE Cout SS Css VSENSE INT VFB SHDN Vref Cvref June 2004 REV. 1 1/30 L6997S Table 2. Absolute Maximum Ratings Symbol VCC VDR VCC to GND VDR to GND HGATE and BOOT, to PHASE HGATE and BOOT, to PGND VPHASE PHASE LGATE to PGND ILIM, VFB, VSENSE, NOSKIP, SHDN, PGOOD, OVP, VREF, INT, GNDSENSE to GND BOOT, HGATE and PHASE PINS OTHER PINS Ptot Tstg Power dissipation at Tamb = 25°C Storage temperature range Maximum Withstanding Voltage Range Test Condition:CDF-AEC-Q100-002 “Human Body Model” Accepatance Criteria: “Normal Performance” Parameter Value -0.3 to 6 -0.3 to 6 -0.3 to 6 -0.3 to 42 -0.3-to 36 -0.3 to VDR+0.3 -0.3 to VCC+0.3 ±750 Unit V V V V V V V V ±2000 1 -40 to 150 V W °C Table 3. Thermal Data Symbol Rth j-amb Tj Parameter Thermal Resistance Junction to Ambient Junction operating temperature range Value 125 -40 to 125 Unit °C/W °C Figure 3. Pin Connection (Top View) NOSKIP GNDSENSE INT VSENSE VCC GND VREF VFB OSC SS 1 2 3 4 5 6 7 8 9 10 TSSOP20 20 19 18 17 16 15 14 13 12 11 BOOT HGATE PHASE VDR LGATE PGND PGOOD OVP SHDN ILIM Table 4. Pin Function N° 1 2 3 4 Name NOSKIP GNDSENSE INT VSENSE Remote ground sensing pin Integrator output. Short this pin to VFB pin and connect it via a capacitor to VOUT to insert the integrator in the control loop. If the integrator is not used, short this pin to VREF. This pin must be connected to the remote output voltage to detect overvoltage and undervoltage conditions and to provide integrator feedback input. Description Connect to VCC to force continuous conduction mode and sink mode. 2/30 L6997S Table 4. Pin Function (continued) N° 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Name VCC GND VREF VFB OSC SS ILIM SHDN OVP PGOOD PGND LGATE VDR PHASE HGATE BOOT IC Supply Voltage. Signal ground 0.6V voltage reference. Connect a ceramic capacitor (max. 10nF) between this pin and ground. This pin is capable to source or sink up to 250uA PWM comparator feedback input. Short this pin to INT pin to enable the integrator function, or to VSENSE to disable the integrator function. Connect this pin to the input voltage through a voltage divider in order to provide the feedforward function don’t leave floating. Soft Start pin. A 5µA constant current charges an external capacitor. Itsvalue sets the softstart time don’t leave floating. An external resistor connected between this pin and GND sets the current limit threshold don’t leave floating.. Shutdown. When connected to GND the device and the drivers are OFF. It cannot be left floating. Open drain output. During the over voltage condition it is pulled up by an external resistor. Open drain output. It is pulled down when the output voltage is not within the specified thresholds. Otherwise is pulled up by external resistor. If not used it can be left floating. Low Side driver ground. Low Side driver output. Low Side driver supply. Return path of the High Side driver. High side driver output. Bootstrap capacitor pin. High Side driver is supplied through this pin. Description Table 5. Electrical Characteristics (VCC = VDR = 3.3V; Tamb = 0°C to 85°C unless otherwise specified) Symbol SUPPLY SECTION Vin VCC, VDR VCC Turn-onvoltage Turn-off voltage Hysteresis IqVDR IqVcc SHDN ISHVDR ISHVCC ISS ∆VSS Drivers Quiescent Current Device Quiescent current Device On Device Off Drivers shutdown current Devices shutdown current Soft Start current Active Soft start and voltage SHDN to GND SHDN to GND VSS = 0.4V 4 300 400 1 VFB > VREF VFB > VREF 1.2 0.6 5 15 6 500 Input voltage range Vout=Vref Fsw=110Khz Iout=1A 1 3 2.86 2.75 90 7 400 20 600 35 5.5 2.97 2.9 V V V V mV µA µA V V µA µA µA mV Parameter Test Condition Min. Typ. Max. Unit SHUTDOWN SECTION SOFT START SECTION 3/30 L6997S Table 5. Electrical Characteristics (continued) (VCC = VDR = 3.3V; Tamb = 0°C to 85°C unless otherwise specified) Symbol ILIM Parameter Input bias current Zero Crossing Comparator offset Phase-gnd KILIM ON TIME Ton On time duration VREF=VSENSE OSC=125mV VREF=VSENSE OSC=250mV VREF=VSENSE OSC=500mV VREF=VSENSE OSC=1000mV OFF TIME TOFFMIN Minimum off time KOSC/TOFFMIN VOLTAGE REFERENCE VREF Voltage Accuracy Input voltage offset IFB Input Bias Current Over Voltage Clamp Under Voltage Clamp Integrator Input Offset Voltage VSENSE-VREF IVSENSE Input Bias Current High side rise time High side fall time Low side rise time Low side fall time PGOOD UVP/OVP PROTECTIONS OVP UVP Over voltage threshold Under voltage threshold Upper threshold (VSENSE-VREF) Lower threshold (VSENSE-VREF) VPGOOD VSENSE rising VSENSE falling ISink=2mA with respect to VREF 118 67 110 85 121 70 112 88 0.2 124 73 116 91 0.4 % % % % V VDR=3.3V; C=7nF HGATE - PHASE from 1 to 3V VDR=3.3V; C=14nF LGATE from 1 to 3V GATE DRIVERS 50 50 50 50 90 100 90 90 ns ns ns ns VSENSE = VCC VSENSE = GND 0.62 0.45 -4 20 INTEGRATOR 0.75 0.55 0.88 0.65 -4 V V mV nA 0µA < IREF < 100µA 0.594 -2 20 0.6 0.606 +2 V mV nA PWM COMPARATOR OSC=250mV 0.20 600 0.40 ns 720 370 200 90 800 420 230 115 880 470 260 140 ns ns ns ns Current limit factor Test Condition RILIM = 2KΩ to 200KΩ Min. 4.6 -2 1.6 1.8 Typ. 5 Max. 5.4 2 2 Unit µA mV µA CURRENT LIMIT AND ZERO CURRENT COMPARATOR 4/30 Vcc SHDN + VSENSE 1.12 VREF undervoltage comparator VSENSE 0.6 VREF IC enable pgood comparators + VSENSE VCC VSENSE 0.925 VREF HGATE BOOT V(LGATE) Output voltage Figure 29. Eff. vs Output Current sink mode Figure 31. Normal functionality in SINK mode.. 100 95 Efficiency (%) 90 85 80 75 70 65 60 0 1 2 3 4 5 6 7 Output current (A) Vout=0.9V Vcc=5V Fsw=200KHz Vin=12V Vin = 1.8V Vin = 12V Ch1-> Inductor current Ch2-> Phase Node Ch3-> Output voltage 26/30 L6997S Figure 32. Normal functionality in PWM mode. Figure 34. Start up waveform with 0A load. Ch1-> Inductor current Ch2-> Phase Node Ch3-> Output voltage Ch1-> Inductor current Ch2-> Soft start Voltage Ch3-> Output voltage Figure 33. Normal functionality in PFM mode. Figure 35. Start up waveform with 5A load.. Ch1-> Inductor current Ch2-> Phase Node Ch3-> Output voltage Ch1-> Inductor current Ch2-> Soft start Voltage Ch3-> Output voltage 27/30 L6997S Figure 36. TSSOP20 Mechanical Data & Package Dimensions mm DIM. MIN. A A1 A2 b c D (1) E 0.050 0.800 0.190 0.090 6.400 6.200 6.500 6.400 4.400 0.650 0.450 0.600 1.000 0˚ (min.) 8˚ (max.) 0.100 0.004 0.750 0.018 1.000 TYP. MAX. 1.20 0.150 1.050 0.300 0.200 6.600 6.600 4.500 0.002 0.031 0.007 0.004 0.252 0.244 0.170 0.256 0.252 0.173 0.026 0.024 0.039 0.030 0.039 MIN. TYP. MAX. 0.047 0.006 0.041 0.012 0.008 0.260 0.260 0.177 inch OUTLINE AND MECHANICAL DATA E1 (1) 4.300 e L L1 k aaa TSSOP20 Thin Shrink Small Outline Package Note: 1. D and E1 does not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch) per side. 0087225 (Jedec MO-153-AC) 28/30 L6997S Table 15. Revision History Date June 2004 Revision 1 First Issue. Description of Changes 29/30 L6997S Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com 30/30