L9610C013TR

L9610 PWM PowerMOS controller Features ■ High efficiency due to PWM control and PowerMOS driver ■ Load dump protection ■ Load power limitation ■ External PowerMOS protection ■ Limited output voltage slew rate SO16 Description The L9610C is a monolithic integrated circuit working in PWM mode as controller of an external PowerMOS transistor in high side driver configuration. Table 1. Features of the device include controlled slope of the leading and trailing edge of the gate driving voltage, linear current limiting with protection timer, settable switching frequency fo, TTL compatible enable function, protection status ouput pin. c u d e t le so Package L9610C b O SO16N L9610C013TR SO16N ) s ( ct o r P The device is mounted in SO16 micropackage. Device summary Order code ) s t( Packing Tube Tape and reel u d o r P e t e l o s b O February 2009 Rev 2 1/15 www.st.com 15 L9610 Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ) s t( 4.1 Pulse width comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.2 Ground compatible triangle oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.3 Timer and protection latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.4 Under and overvoltage sense with load dump protection . . . . . . . . . . . . . 7 4.5 Short circuit current regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.6 Bandgap voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.7 Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 c u d e t le o r P o s b O - Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ) s ( ct 5.1 Controlling a 120 W halogen lamp with the L9610C dimmer . . . . . . . . . . 11 u d o 6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 t e l o r P e s b O 2/15 L9610 1 Block diagram Figure 1. Block diagram c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O 3/15 L9610 2 Pin description Figure 2. Pin connection (top view) Table 2. Pin functions Pin Name INT 2 IN Analog input controlling the PWM ratio. The operating range of the input voltage is 0 to VR. 3 VR Output of an internal voltage reference. 4 EN TTL compatible input for switching off the output. 5 PWL If this pin is connected to GND and VS > 13 V, the duty cycle and the frequency fo are reduced : this allows to transfer a costant power to the load. 6 Osc Current sink and source stage connection of a triangle oscillator with definite voltage swing. 7 IND e t le ) s ( ct o r P o s b O - u d o Input of an operational amplifier for short current sensing and regulation. 8 NC Not connected. 9 VS Common supply voltage input. 10 GND Common ground connection. 11 TIM A capacitor connected between this pin and GND defines the protection delay time. 12 MON t e l o 4/15 A capacitor connected between this pin and OutG defines the gate voltage slew rate. 1 r P e s b O c u d Functions ) s t( 13, 15 Open collector monitoring output off the PowerMOS protection. P2, P1 Connection for the charge pump capacitor. 14 BS 16 Out G The capacitor connected between this pin and the source of the PowerMOS allows to bootstrap the gate driving voltage. Output for driving the gate of the external PowerMOS. L9610 3 Electrical specification 3.1 Absolute maximum ratings Table 3. Absolute maximum ratings Symbol VS Parameter Value Unit 26 V Load dump: 5 ms ≤ trise ≤ 10 ms; τf Fall time constant = 100 ms; RSOURCE ≥ 0.5 Ω 60 V Field decay: 5 ms ≤ tfall ≤ 10 ms; τr Rise time constant = 33 ms; RSOURCE ≥ 10 Ω –80 V Low energy spike: trise =1 μσ, tfall = 2 ms, RSOURCE ≥ 10 Ω ±100 Max. supply voltage Transient peak supply voltage (R1 ≥ 100 Ω): Is Max. supply current (t < 300 ms) VIN TJ /Tstg Thermal data Table 4. Thermal data Symbol Rth j-amb Thermal resistance junction-alumina Table 5. Symbol ol Vs bs Iq O A V -55 to 150 °C d o r P e let Parameter 3.3 uc -0.3 < VIN < VS - 2.5 Junction and storage temperature range 3.2 V 0.3 Input voltage ) s t( o s b O - ) s ( t Electrical characteristics c u d o r P ete Value Unit 50 °C/W Max. Electrical characteristcs (Tamb = -40 °C to 85 °C; 6 V < Vs < 16 V unless otherwise specified) Parameter Test conditions Operating supply voltage Min. Typ. Max. Unit 16 V 2.5 6 mA 28 32 36 V 6 Quiescent current VSC Internal supply voltage clamp VSH Supply voltage high threshold 16 18.5 21 V VSL Supply voltage low threshold 4 5 6 V VR Reference voltage 3.3 3.5 3.7 V IR Reference current 1 mA VINL Input low threshold 0.2 VIN/VR IS=200 mA ΔVR ≤ 100 mV 0.13 0.15 5/15 L9610 Table 5. Electrical characteristcs (continued) (Tamb = -40 °C to 85 °C; 6 V < Vs < 16 V unless otherwise specified) Symbol Parameter Oscillator freq. constant KS Gate voltage slew rate constant (2) 3 KT Protection time delay constant (3) 0.12 VSi Sense input volt. Gate driving volt. above VS Vs =16 V VGOFF Gate voltage in off condition IG=100 µA -5 VENL Low enable voltage VENH High enable voltage IEN Enable input current SR Slew rate without CS Saturation voltage (pin 12) VMON = 2.5 mA 1. f0 = KF ⁄ CF 2. dV G ⁄ ( dt ) = K S ⁄ C S t prot = K T C T 2500 nF/s 9 nFV/ms 0.44 ms/nF 120 mV 16 V 1.2 V -1 µA 0.5 c u d 1.5 o s b O - V V 2 u d o s b O 100 Unit 2.0 ) s ( ct t e l o 5 Max. 0.8 e t le r P e Typ. 8 Input current VMONsat 800 80 VGON 6/15 Min. KF IIN 3. Test conditions (1) o r P ) s t( µA V/µs V L9610 4 Functional description 4.1 Pulse width comparator A ground compatible comparator generates the PWM signal which controls the gate of the external PowerMOS. The slopes of the leading and trailing edges of the gate driving signal are defined by the external capacitor CS according to : dV G ⁄ ( dt ) = K S ⁄ C S This feature allows to optimize the switching speed for the power and RFI performance best suited for the application. The lower limit of the duty cycle is fixed at 15 % of the ratio between the input and the reference voltage (see Figure 3.). Input voltages lower than this value disable the internal oscillator signal and therefore the gate driver. 4.2 Ground compatible triangle oscillator c u d ) s t( The triangle oscillator provides the switching frequency fo set by the external capacitor CF according to: o r P f0 = KF ⁄ CF If the pin PWL (power limitation) is connected to ground and Vs is higher than the PWL threshold voltage, the duty cycle and the fo frequency are reduced: this allows to transfer a costant power to the load (see Figure 4.). e t le 4.3 o s b O - Timer and protection latch When an overcurrent occurs, the device starts charging the external capacitor CT ; the protection time is set according to : ) s ( ct t prot = K T ⋅ C T u d o After the overcurrent protection time is reached, the PowerMOS is switched-off ; this condition is latched by setting an internal flip-flop and is externally monitored by the low state of the MON pin. r P e To reset the latch the supply voltage has to fall below VSL or the device must be switched off. 4.4 s b O t e Under and overvoltage sense with load dump protection l o The undervoltage detection feature resets the timer and switches off the output driving signal when the supply voltage is less than VSL. If the supply voltage exceeds the max operating supply voltage value, an internal comparator disables the charge pump, the oscillator and the external PowerMOS. In both cases the thresholds are provided with suitable hysteresis values. The load dump protection function allows the device to withstand, for a limited time, high overvoltages. It consists of an active clamping diode which limits the circuit supply voltage to 7/15 L9610 VCLAMP and an external current limiting resistor R1. The maximum pulse supply current (see abs. max. ratings is equal to 0.3 A. Therefore the maximum load dump voltage is given by: V DUMP = V SC + 0.3R 1 In this condition the gate of the PowerMOS is held at the GND pin potential and thus the load voltage is : V L = V S – V CLAMP – V GS Figure 3. Typical transfer curve c u d e t le Figure 4. The typical waveforms for the power limitation function ) s ( ct u d o r P e t e l o s b O 8/15 o s b O - o r P ) s t( L9610 4.5 Short circuit current regulation The maximum load current in the short circuit condition can be chosen by the value of the current sensing resistor RS according to : I SC = V SI ⁄ R S Two identical VS compatible comparators are provided to realize the short circuit protection. After reaching the lower threshold voltage (typical value VSI-10 mV), the first comparator enables the timer and the gate is driven with the full continuous pump voltage : when the upper threshold voltage value is reached the second comparator maintains the chosen ISC driving the NMOS gate in continuous mode. This function, showed in Figure 5., speeds up the switch on phase for a lamp as a load. 4.6 Bandgap voltage reference The circuit provides a reference voltage which may be used as control input voltage through a resistive divider. This reference is protected against the short circuit current. 4.7 c u d Charge pump ) s t( o r P The charge pump circuit holds the N-MOS gate above the supply voltage during the ON phase. This circuit consists of an RC astable which drives a comparator with a push-pull output stage. The external charge pump capacitor CP must be at least equal to the NMOS parasitic input capacitance. e t le o s b O - For fast gate voltage variation CP must be increased or the bootstrap function can be used. The bootstrap capacitor should be at least 10 times greater than the PowerMOS parasitic capacitance. The charge pump voltage VPUMP can reach to : ) s ( ct V PUMP = 2V S – V BE – V CESAT The circuit is disabled if the supply voltage is higher than VSH. u d o r P e t e l o s b O 9/15 L9610 Figure 5. Typical waveforms for short circuit current condition. c u d e t le ) s ( ct u d o r P e t e l o s b O 10/15 o s b O - o r P ) s t( L9610 5 Application circuit Figure 6. Application circuit c u d e t le 1. All node voltages are referred to ground pin (GND). ) s t( o r P o s b O - 2. The currents flowing in the arrow direction are assumed positive without CBS : CP = 1 nF without CBS : CBS must be at least 10 times higher than the gate capacitance : CP = 100 pF. ) s ( ct 5.1 Controlling a 120 W halogen lamp with the L9610C dimmer The L9610C lamp dimmer is used to control the brightness of vehicle headlamps using H4 type lamps (see Figure 7.). With switch S1 open the full supply voltage is applied to the lamps: closing the switch it is a possible to reduce the average lamp voltage as desired: R3 VL = VS ---------------------R2 + R3 If pin 5 is connected to ground the average lamp voltage is constant, even for supply voltages in excess of 13 V. u d o r P e t e l o s b O 11/15 L9610 Figure 7. Application circuit with controlling a 120 W halogen lamp c u d ) s t( The sensing resistor RS and timing capacitor Ct should be dimensioned according to : V Si R S = -----------------------------------------------------2Inom ( @V S = 14V ) 2 × limitation time C t = ------------------------------------------------KT e t le o r P o s b O - In normal conditions (VCC = 14 V, maximum brightness) the voltage drop across the sense resistor must be 50 mV. The current limiter intervenes attwice the nominal current, Inom. The timing capacitor Ct (Vct = 3.5 V) must be chosen so that the delay before intervention is twice the duration of the current limitation at power-on. ) s ( ct The optimal value of the oscillator frequency, taking tolerances into account, must be slightly higher than the frequency at which lamp flicker is noticable (min 60 Hz). u d o The switching times are a compromise between possible EMI and switching power losses. The recommended value for Cs is 47 pF. r P e t e l o s b O 12/15 L9610 6 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 8. SO16 narrow mechanical data and package dimensions mm inch OUTLINE AND MECHANICAL DATA DIM. MIN. TYP. A MAX. MIN. TYP. MAX. 1.750 0.0689 A1 0.100 0.250 0.0039 0.0098 A2 1.250 0.0492 b 0.310 0.510 0.0122 0.0201 c 0.170 0.250 0.0067 0.0098 D 9.800 9.900 10.000 0.3858 0.3898 0.3937 E 5.800 6.000 6.200 0.2283 0.2362 0.2441 E1 3.800 3.900 4.000 0.1496 0.1535 0.1575 e 1.270 h 0.250 L 0.400 c u d 0.0500 0.500 0.0098 0.0197 1.270 0.0157 0.0500 k 8.000 0.3150 ccc 0.100 o s b O 0.0039 "D" do not include mold flash or protrusions Mold flash, protrusions or gate burrs shall not exceed 0.15mm in total (both side). ) s ( ct e t le ) s t( o r P SO16 (Narrow) u d o r P e t e l o s b O 0016020 E 13/15 L9610 7 Revision history Table 6. Document revision history Date Revision Changes 09-Oct-2000 1 Initial release. 18-Feb-2009 2 Document reformatted. Added Table 1: Device summary on page 1. Updated Section 6: Package information on page 13. c u d e t le ) s ( ct u d o r P e t e l o s b O 14/15 o s b O - o r P ) s t( L9610 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. c u d ) s t( Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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