L9660TR

L9660 Quad squib driver ASIC for safety application Datasheet - production data  Analog output available for resistance measurement  Squib short to ground, short to battery and MOS diagnostic available on SPI register  Capability to deploy the squib when the low side MOS is shorted to ground  2 fire enable inputs '!0'03  5.5 MHz SPI interface LQFP64 (10x10x1.4mm)  Low voltage internal reset  2 kV ESD capability on all pins  Package: LQFP64 Features  Technology: ST proprietary BCD5 (0.65µm)  4 deployment drivers with SPI selectable firing current and times  RoHS compliant  Capability to deploy the squib with 1.2 A (min)/2 ms, 1.75 A (min)/1.0 ms and 1.75 A (min)/0.65 ms between VRES of 7 V to 37 V Description  Firing capability to deploy all channels simultaneously The L9660 is intended to deploy up to 4 squibs. Squib drivers are sized to deploy 1.2 A minimum for 2 ms, 1.75 A minimum for 1 ms and 1.75 A minimum for 0.65 ms during load dump along with 1.5 A minimum for 2 ms for VRES voltages less than 25 V.  Independently controlled high-side and lowside MOS for diagnosis Full diagnostic capabilities of the squib interface are provided.  Capability to deploy the squib with 1.5 A (min)/2 ms between VRES of 7 V to 25 V Table 1. Device summary Order code Amb. temp range, C Package Packing L9660 -40 to +95 LQFP64 Tray L9660TR -40 to +95 LQFP64 Tape and reel September 2013 This is information on a product in full production. DocID024714 Rev 2 1/49 www.st.com Contents L9660 Contents 1 2 3 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Absolute maximum degraded operating ratings . . . . . . . . . . . . . . . . . . . . . 9 2.3 Operating ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4.2 Electrical characteristics - Squib deployment drivers and diagnostics . 11 2.4.3 SPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2 General functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3 3.2.1 Power on reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2.2 RESETB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2.3 Reference resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.4 Loss of ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.5 VRESx capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.6 Supply voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.7 Ground connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3.1 3.4 SPI pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Squib drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4.1 Firing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4.2 Firing current measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.4.3 Fire enable (FEN) function description . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4.4 Squib diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4.5 SPI register definition for squib functions . . . . . . . . . . . . . . . . . . . . . . . 30 4 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 2/49 DocID024714 Rev 2 L9660 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Absolute maximum degraded operating ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Operating ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 General - DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Squib deployment drivers and diagnostics - DC electrical characteristics . . . . . . . . . . . . . 11 SPI timing - DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Features that are accessed/controlled for the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SPI MOSI/MISO response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 How faults shall be interpreted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Diagnostic Mode HSS selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Diagnostic mode 3 VRESx selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 MISO responses to various events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Command description summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Configuration mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Configuration mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Deployment mode 1 bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Deployment mode 2 bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Diagnostic selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Diagnostic mode LS FET selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Diagnostic mode HS FET selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Diagnostic mode HSS selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Diagnostic mode VRESx selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 MOSI diagnostic mode 1 bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 DEPLOY_STATUSx flag and DEPLOY_SUCCESSx flag conditions. . . . . . . . . . . . . . . . . 42 MOSI monitor mode 2 Bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Current measurement channel selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 MOSI monitor mode 3 bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 MOSI monitor mode 4 bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 DocID024714 Rev 2 3/49 3 List of figures L9660 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. 4/49 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 MOS settling time and turn-on time 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 SPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 MISO loading for disable time measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 POR timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Deployment drivers diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Driver activation timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Squib diagnostics block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 LQFP64 (10 x 10 x mm) mechanical data and package dimensions.. . . . . . . . . . . . . . . . . 47 DocID024714 Rev 2 L9660 Block diagram and pin description 1 Block diagram and pin description 1.1 Block diagram Figure 1. Block diagram 3QUIB DEPLOYMENT ) DIAGNOSTICS30) #3?$ 3#,+ -/3) -)3/ )2%& 6$$ 4%34 '.$ &%. &%. 62%3 31( 31, '.$ 62%3 31( 31, '.$ 62%3 31( 31, '.$ 62%3 31( 31, '.$ $EPLOYMENT $RIVER  $IAGNOSTICS 63$)!' 2%3%4" !/54 !'.$ '!0'03 1.2 Pin description Table 2. Pin description Pin Number Pin name 1 MISO 2 Description I/O type Reset state SPI Data Out Output Hi-Z N.C. Not connected - - 3 FEN1 Fire enable for channels 0 and 1 Input Pull-down 4 N.C. Not connected - - 5 RESETB Input Pull-up 6 GND Ground (Analog & Digital) - - 7 VDD VDD Supply Voltage Input - 8 N.C. Not connected - - 9 FEN2 Fire enable for channels 2 and 3 Input Pull-down 10 N.C. Not connected - - 11 N.C. Not connected - - 12 CS_D SPI Chip Select for Deployment Driver Input Pull-up 13 MOSI SPI Data In Input Hi-Z 14 N.C. Not connected - - Reset pin DocID024714 Rev 2 5/49 48 Block diagram and pin description L9660 Table 2. Pin description (continued) Pin Number Pin name 15 N.C. 16 SCLK 17 N.C. 18 6/49 Description I/O type Reset state - - Input Hi-Z Not connected - - N.C. Not connected - - 19 N.C. Not connected - - 20 N.C. Not connected - - 21 N.C. Not connected - - 22 N.C. Not connected - - 23 N.C. Not connected - - 24 N.C. Not connected - - 25 GND2 Power Ground for Loop Channel 2 - - 26 SQL2 Low Side Driver Output for Channel 2 Output Pull-down 27 SQH2 High Side Driver Output for Channel 2 Output Hi-Z 28 VRES2 Reserve Voltage for Loop Channel 2 Input - 29 VRES3 Reserve Voltage for Loop Channel 3 Input - 30 SQH3 High Side Driver Output for Channel 3 Output Hi-Z 31 SQL3 Low Side Driver Output for Channel 3 Output Pull-down 32 GND3 Power Ground for Loop Channel 3 - - 33 TEST Test pin Input Pull-down 34 VSDIAG Supply for Deployment Driver Diagnostics Input - 35 N.C. Not connected - - 36 Reserved Factory testmode output - - 37 Reserved Factory testmode output - - 38 N.C. Not connected - - 39 N.C. Not connected - - 40 N.C. Not connected - - 41 N.C. Not connected - - 42 N.C. Not connected - - 43 N.C. Not connected - - 44 N.C. Not connected - - 45 N.C. Not connected - - 46 IREF External Current Reference Resistor Output - 47 AGND Ground Reference for AOUT - - 48 AOUT Analog Output for Loop Diagnostics Output Hi-Z 49 N.C. - - Not connected SPI Clock Not connected DocID024714 Rev 2 L9660 Block diagram and pin description Table 2. Pin description (continued) Pin Number Pin name 50 N.C. 51 1.3 Description I/O type Reset state Not connected - - N.C. Not connected - - 52 N.C. Not connected - - 53 N.C. Not connected - - 54 N.C. Not connected - - 55 N.C. Not connected - - 56 N.C. Not connected - - 57 GND1 Power Ground for Loop Channel 1 - - 58 SQL1 Low Side Driver Output for Channel 1 Output Pull-down 59 SQH1 High Side Driver Output for Channel 1 Output Hi-Z 60 VRES1 Reserve Voltage for Loop Channel 1 Input - 61 VRES0 Reserve Voltage for Loop Channel 0 Input - 62 SQH0 High Side Driver Output for Channel 0 Output Hi-Z 63 SQL0 Low Side Driver Output for Channel 0 Output Pull-down 64 GND0 Power Ground for Loop Channel 0 - - Application schematic Figure 2. Application schematic #3?$ 3#,+ -/3) -)3/ &%. &%. 62%3 62%3 #VRES? 30) 62%3 62%3 3QUIB$EPLOYMENT $IAGNOSTICS #VRES? 31( 31, '.$ 63$)!' —& 31( K: 4O !$# !/54 !'.$ —& 6$$ —& '.$ 0IN $EPLOYMENT $RIVERS $IAGNOSTICS 31, '.$ 31( 31, '.$ 2%3%4" 4%34 31( 31, '.$ 6$$ 2)2%& )2%& '!0'03 DocID024714 Rev 2 7/49 48 Electrical specifications L9660 2 Electrical specifications 2.1 Absolute maximum ratings The following maximum ratings are continuous absolute ratings; exceeding any one of these values may cause permanent damage to the integrated circuit. Table 3. Absolute maximum ratings Symbol Parameter Value Unit VDD (1) Supply voltage - 0.3 to 5.5 V VSDIAG Supply voltage for squib diagnostics - 0.3 to 40 V VRESx VRES voltage (VRES0, VRES1, VRES2, VRES3) - 0.3 to 40 V SQHx Squib high side drivers (SQH0, SQH1, SQH2, SQH3) - 0.6 to 40 V SQLx Squib low side drivers (SQL0, SQL1, SQL2, SQL3) - 0.3 to 40 V TEST Test pin -0.3 to 40 V VI Discrete input voltage (RESETB, CS_D, SCLK, MOSI, FEN1, FEN2, IREF) - 0.3 to 5.5 V VO Discrete output voltage (MISO, AOUT) - 0.3 to 5.5 V AGND Analog output reference -0.3 to 5.5 V GNDx Ground (GND0, GND1, GND2, GND3) -0.3 to 5.5 V 150 °C Tj (2) Maximum steady-state junction temperature Tamb Ambient temperature -40 to 95 °C Tstg Storage temperature -65 to 150 °C 46 °C/W Rth j amb Thermal resistance junction to ambient (on FR-4 board) The following maximum ratings are up to 48 hours; exceeding any one of these values for longer than a total time of 48 hours may cause permanent damage to the integrated circuit. VDD Supply voltage - 0.3 to 6.0 V VI Discrete input voltage (RESETB, CS_D, SCLK, MOSI, FEN1, FEN2, IREF) - 0.3 to 6.0 V VO Discrete output voltage (MISO, AOUT) - 0.3 to 6.0 V AGND Analog output reference -0.3 to 6.0 V GNDx Ground (GND0, GND1, GND2, GND6, GND7) -0.3 to 6.0 V 150 °C Tj (2) amb Maximum steady-state junction temperature T Ambient temperature -40 to 95 °C Tstg Storage temperature -65 to 150 °C 46 °C/W Rth j amb Thermal resistance junction to ambient (on FR-4 board) 1. Exceeding a VDD of 5.1V during a deployment may cause damage 2. To allow for deployment the maximum steady state junction temperature cannot exceed 130°C. Under the operating ratings defined in Section 2.3 the steady state junction temperature does not exceed 130°C. 8/49 DocID024714 Rev 2 L9660 Electrical specifications 2.2 Absolute maximum degraded operating ratings Under the following deviations to the ratings indicated in Section 2.3 the L9660 performance is degraded and not meeting the electrical characteristics outlined in Section 2.4. The SPI and diagnostics still function but not meet specified electrical parameters. Table 4. Absolute maximum degraded operating ratings Symbol Parameter Value Unit 4.5 to 5.5 V VDD (1) Supply voltage VSDIAG Supply voltage for squib diagnostics 7 to 40 V VRES voltage (VRES0, VRES1, VRES2, VRES3) 7 to 40 V VRES VI Discrete input voltage (RESETB, DEPEN, CS_D, SCLK, MOSI, FEN1, FEN2, IREF) - 0.3 to (VDD +0.3) V VO Discrete output voltage (MISO, AOUT) -0.3 to (VDD + 0.3) V Tj Junction temperature -40 to 150 °C 1. Exceeding a VDD of 5.1V during a deployment may cause damage. Note: The above is provided for informational purposes only and results in degraded operation. Under the above conditions the SPI is functional as well as diagnostics, though the electrical performance may not conform to the parameters outlined in Section 2.4. Firing requirements as indicated in Section 2.4 may not be met with the conditions above. 2.3 Operating ratings Table 5. Operating ratings Symbol VDD Parameter Supply voltage Value Unit 4.9 to 5.1 V VSDIAG Supply voltage for squib diagnostics 7 to 37 V VRESx VRES voltage (VRES0, VRES1, VRES2, VRES3,) 7 to 37 V VI Discrete input voltage (RESETB, CS_D, SCLK, MOSI, FEN1, FEN2, IREF) - 0.3 to (VDD +0.3) V VO Discrete output voltage (MISO, AOUT) -0.3 to (VDD + 0.3) V -40 to 95 °C 46 °C/W Tamb RTh j-amb Ambient temperature Thermal resistance junction to ambient (on FR-4 board) Comments: VSDIAG supply provides power for squib resistance and HSS diagnostics VDD is used for all internal functions as well as short to battery/ground and high squib resistance diagnostics. DocID024714 Rev 2 9/49 48 Electrical specifications L9660 2.4 Electrical characteristics 2.4.1 General 4.9 V  VDD  5.1 V; 7 V  VRESX  37 V; 7 V  VSDIAG  37 V; FEN1 = FEN2 = VDD; R_REF = 10 k, ±1 %, 100 PPM; -40 °C  TA  +95 °C; unless other specified. Table 6. General - DC electrical characteristics Symbol Osc Parameter Internal oscillator frequency Test condition Tested with 10K, 1%, 100ppm Iref resistor Min. Typ. Max. Unit 4.75 - 5.25 MHz VRST1 Internal voltage reset VDD VDD level for L9660 to report reset after de-glitch time (tPOR) condition -deployment drivers are See Figure 6 disabled 4.0 - 4.5 V VRST2 Internal voltage reset VDD with no de-glitch time See Guaranteed by design Figure 6 2.1 - 3.0 V Timer for VRST1 5 - 25 µs No squib diagnostics. No deployment. - - 15 Resistance measurement diagnostics with no fault condition present. - - 17 Short to –0.3V on SQL; VRCM active - - 35 During deployment - - 15 - - - 60.0 k RIREF_L - 2.0 - - k VIH_RESETB - - - 2.0 V - 0.8 - - V - 100 - 300 mV - 3.2 - V 1.0 - 2.5 mA - - 20 mA -10 - -50 µA tPOR IDD RIREF_H POR De-glitch timer Input current VDD Resistance threshold IREF Input voltage threshold VIL_RESETB RESETB VHYS_RST VIH_TEST Input voltage threshold TEST Guaranteed by design ITESTPD Input pull-down current TEST - IAOUT_SHRT AOUT pin current limit IRESETPU IRESx VIH VIL VHYST 10/49 mA AOUT short to ground during squib resistance diagnostics Input pull-up current RESETB RESETB = VIH to GND Quiescent current for VRESx during HSS test Current per pin during HSS test excluding selected channel - - 10 µA Input voltage threshold (MOSI, SCLK, CS_D) Input Logic = 1 - - 2.0 V Input Logic = 0 0.8 - - V 100 - 300 mV Input hysteresis (MOSI, SCLK, CS_D) DocID024714 Rev 2 L9660 Electrical specifications Table 6. General - DC electrical characteristics (continued) Symbol Parameter Test condition Min. Typ. Max. Unit VIN = VDD - - 1 µA VIN = 0 to VIH -1 - - µA -10 - -50 µA IOH = -800µA VDD– 0.8 - - V IOL = 1.6mA - - 0.4 V MISO = VDD - - 1 µA MISO = 0V -1 - - µA ILKGD Input leakage current MOSI, SCLK IPU_CS Input pull-up current CS_D VIN = VIH to GND VOH Output voltage MISO VOL IHI_Z Tri-state current MISO 2.4.2 Electrical characteristics - Squib deployment drivers and diagnostics 4.9 V  VDD  5. 1V; 7 V  VRESX  37 V; 7 V  VSDIAG  37 V; FEN1 = FEN2 = VDD; R_REF = 10 k, ±1%, 100 PPM; -40 °C  TA  +95 °C; C_VRES0_1  68nF; C_VRES2_3  68nF; unless other specified. Table 7. Squib deployment drivers and diagnostics - DC electrical characteristics Symbol Parameter Test condition Min. Typ. Max. Unit General ILKGSQH Leakage current SQH VSDIAG = VDD = 0, VRES = 37V, VSQH = 0V - - 50 µA ILKGVRES Bias current VRESX VSDIAG = 18V; VDD = 5V; VRES = 37V; SQH shorted to SQL - - 10 µA ILKGSQL Leakage current SQL VSDIAG = VDD = 0, VSQL = 18V -10 - 10 µA IPD Pull-down current SQL VSQL = 1.5V to 20V 3.3 - 4.1 mA Diagnostics Bias voltage Nominal 3.6V -5% VDD* 0.72 +5% V 5 - 20 mA Vbatt = 6.5V 1.92 - 3.42 K Vbatt = 16V 8.61 - 13.98 K Vbatt = 20V 11.42 - 18.42 K VBIAS Short to battery/ground diagnostics - Rsqb from 0 to Open ISVRCM Maximum diagnostics bias current limit RSTB Short to battery resistance threshold Short to battery or ground test active VSQH = 0V ISTB Short to battery current threshold - 0.9 - 1.42 mA RSTG Short to ground threshold - 1.07 - 2.1 K ISTG Short to ground current threshold - 1.8 - 3.2 mA DocID024714 Rev 2 11/49 48 Electrical specifications L9660 Table 7. Squib deployment drivers and diagnostics - DC electrical characteristics (continued) Symbol Parameter tDIAGTIMEOUT Diagnostic delay time Test condition Min. Typ. Max. Unit From/CS  until Test Results are Valid, Output voltage change 0V to VDD * 0.72 CSQHx= 0.12µF CSQLx= 0.12µF - - 300 µs High side safing diagnostics Diagnostic current into selected VRESx pin during test Normal conditions 710 - 950 µA Current during diagnostic All 4 VRESx pins tied together 710 - 1020 µA Normal resistance range when running high side safing diagnostics All 4 VRESx pins tied together 1.4 - 2.5 k All 4 VRESx pins tied together 1.0 - 2.5 V Short voltage threshold between VSDIAG and VRESx pin) All 4 VRESx pins tied together 0.5 - 1.0 V Open voltage threshold VHSSOPEN_th between VSDIAG and VRESx pin) All 4 VRESx pins tied together 2.5 - 4.0 V tDIAGTIMEOUT Diagnostic delay time From/CS  until test results are valid, CSQHx= 0.12µF CSQLx= 0.12µF - - 500 µs - - 50 µA ISRC_HSS IHSS_4 RHSSNORM_t h Normal voltage range VHSSNORM_r between VSDIAG and VRESx pin) when running ange high side safing diagnostics VHSSSHORT_t h Voltage measurement diagnostics (VRESx) Max diagnostic current into VRESx pin Normal Conditions VVRESXLO_th Low voltage threshold for VRESx pin - 5.0 - 7 V VVRESXHI_th High voltage threshold for VRESx pin - 13.7 - 18.0 V From/CS  until test results are valid. - - 100 µs MOS test max current Normal conditions - - ISVRCM mA LS/HS MOS turn off under fault condition Time is measured from the valid LS/ HS MOS current > 100mA to the LS/HS turn off - - 4 µs IRESx tDIAGTIMEOUT Diagnostic delay time MOS diagnostics I_MOS tSHUTOFF 12/49 DocID024714 Rev 2 L9660 Electrical specifications Table 7. Squib deployment drivers and diagnostics - DC electrical characteristics (continued) Symbol tFETtimeout Parameter FET time-out Test condition Normal Conditions Min. Typ. Max. Unit - - 100 µs 1.07 - 2.1 k High squib resistance diagnostics RSQHIZ IHR High load resistance threshold - High resistance current threshold - tDIAGTIMEOUT MOS diagnostic delay time ISTG From/CS  until test results are valid, CSQHx = 0.12µF CSQLx = 0.12µF mA - - 300 µs High saturation voltage; IAOUT = -500µA VDD0.2 - - V Low Saturation Voltage; IAOUT = +500µA - - 0.2 V AOUT = VDD - - 1 µA AOUT = 0V -1 - - 0 - 10.0  VAOUT0.095V - VAOUT+ 0.095V V VAOUT· 0.95V - VAOUT· 1.05V V Squib resistance diagnostics VOH Output voltage AOUT VOL IZ Tri-State Current AOUT RSQB RANGE Load resistance range VAOUT Resistance measurement 0  RSQB < 3.5 analog output tolerance VAOUT = R SQB 1 VDD  ----------- +  0.08  --------------- 3.5  RSQB  10 9.75    µA ISRC Resistance measurement current source VDD = 5.0V; VSDIAG = 7.0V to 37V 38 - 42 mA ISINK Resistance measurement current sink IPD OFF, VSQLx = 4 V 45 - 57 mA ISLEW Rmeas current di/dt 30% - 70% of ISRC 2 - 11 mA/µs Vcmpr Voltage threshold on squib pin to shutdown ISRC - 2.65 - 3.25 V tisrcshtdwn Shutdown time Guaranteed by design - - 30 µs VLSDrsqb LSD (V_SQL) voltage during resistance measure - 0.8 - 2.2 V Rmeas wait time Wait time before AOUT voltage is stable for ADC reading R AOUT= 5.1k; CAOUT=10nF - - 300 µs tR_WAIT FENx input pins tFENfilter Minimum pulse width - 12 - 16 µs IFENPD Internal pull-down current VIN = VIL to VDD 20 - 50 µA DocID024714 Rev 2 13/49 48 Electrical specifications L9660 Table 7. Squib deployment drivers and diagnostics - DC electrical characteristics (continued) Symbol Parameter Test condition Min. Typ. Max. Unit VFENLO Input low voltage threshold - 0.8 - - V VFENHI Input high voltage threshold - - - 2.0 V TFENLATCH FEN Latch timer - 0 - 512 ms tFLACC FEN latch timer accuracy - - 20% - 20 % 22.5 25 27.5 µs - - 2 LSB IHSX x 0.90 - IHSX x 0.99 A - - 2.0  - 0.3 0.8  - 0.6 1.2  IHS_12A Configuration mode 1 bits D9:D8=”00” SQHx shorted to ground; VRES = 7 to 37V 1.21 - 1.47 A IHS_15A Configuration Mode 1 bits High side deployment current D9:D8=”01” SQHx shorted to ground; limit VRES = 7 to 25V 1.51 - 1.85 A IHS_175A Configuration Mode 1 bits D9:D8=”11” SQHx shorted to ground; VRES = 7 to 37V 1.76 - 2.14 A 90 - 110 µs 2.2 - 4.0 A - - 150 µs Deployment drivers TRESOLUTION Diagnostic timing / resolution IHS  IMEAS, 0s  TMEASURE_TIME  3.7ms Diagnostic time TACCURACY CSQUIB _HI = 0.12µF accuracy CSQUIB _LO = 0.12µF IMEAS High side driver current limit detect threshold Guaranteed by design RDSonTOTAL Total high and low side MOS on resistance High side MOS + low side MOS D9:D8=”11”; VRES = 7V; I = 1.6A @95°C RDSonHS RDSonLS High side MOS on resistance D9:D8=”11”; VRES = 7V; Low side MOS on resistance Tamb = 95°C; IVRES = 1.6A; tILIM Low side MOS shutdown under short to battery ILS Low side MOS current limit tsettle 14/49 Firing current settling time Vsqblo=18V Time from fire command CS_D rising edge to where firing current remains within specified limits CSQUIB _HI = 0 to 0.12µF CSQUIB _LO = 0 to 0.12µF DocID024714 Rev 2 L9660 Electrical specifications Table 7. Squib deployment drivers and diagnostics - DC electrical characteristics (continued) Symbol Parameter Test condition tDEPLOY-2ms tDEPLOY-1ms Deployment time tDEPLOY0.65ms Min. Typ. Max. Unit VRES = 7Vto 37@ IHS_12A VRES = 7Vto 25@ IHS_15A For IHS_12A and IHS_15A Firing current measured from CS_D rising edge 2.15 - 2.5 ms VRES = 7Vto 37V For IHS_175A Firing current measured from CS_D rising edge 1.15 - 1.40 ms VRES = 7Vto 37V For IHS_175A Firing current measured from CS_D rising edge 0.65 - 0.85 ms Figure 3. MOS settling time and turn-on time 2 )0%!+ )(3?XX!-AXIMUM )(3?XX!-INIMUM TSETTLE #3?$2ISING%DGE '!0'03 DocID024714 Rev 2 15/49 48 Electrical specifications 2.4.3 L9660 SPI timing All SPI timing is performed with a 150 pF load on MISO unless otherwise noted. 4.9V  VDD  5.1V; 7V  VRESX  37V; 7V  VSDIAG  37V; (FEN1 = FEN2 = VDD; R_REF = 10K, ±1%, 100PPM; -40°C  TA  +95°C; C_VRES0_1  68nF; C_VRES2_3  68nF; unless other specified. . Table 8. SPI timing - DC electrical characteristics No. Symbol Min. Typ. Max. Unit - fop Transfer frequency dc - 5.50 MHz 1 tSCK SCLK Period 181 - - ns 2 tLEAD Enable Lead Time 65 - - ns 3 tLAG Enable Lag Time 50 - - ns 4 tSCLKHS SCLK, High Time 65 - - ns 5 tSCLKLS SCLK, Low Time 65 - - ns 6 tSUS MOSI, Input Setup Time 20 - - ns 7 tHS MOSI, Input Hold Time 20 - - ns 8 tA MISO, Access Time - - 60 ns 9 tDIS (1) MISO, Disable Time - - 100 ns 10 tVS MISO, Output Valid Time - - 60 ns 11 tHO (1) MISO, Output Hold Time 0 - - ns 12 tRO Rise Time (Design Information) - - 30 ns 13 tFO Fall Time (Design Information) - - 30 ns 14 tCSN CS_D, Negated Time 640 - - ns tCLKN Time between CS rising edge and first transition of SCLK must be higher than tCLKN. It happens when multiple devices are connected to the same SCLK and MOSI but with different chip select. 500 - - ns 15 Parameter 1. Parameters tDIS and tHO shall be measured with no additional capacitive load beyond the normal test fixture capacitance on the MISO pin. Additional capacitance during the disable time test erroneously extends the measured output disable time, and minimum capacitance on MISO is the worst case for output hold time. Figure 4. SPI timing diagram T,!' #3?$ T #3. T,%!$ T3#,+(3 F/0 T#,+. 3#,+ T 3#,+,3 T63 T! -3"/54 -)3/ T353 -/3) $!4 ! ,3"/54 $/.g4 #!2% T2/ T &/ T(3 -3"). T$)3 T(/ $!4 ! ,3"). '!0'03 16/49 DocID024714 Rev 2 L9660 Electrical specifications Figure 5. MISO loading for disable time measurement 6$$ 6 6 -)3/ K 6 -)3/ 6 T$)3 K #3 '!0'03 DocID024714 Rev 2 17/49 48 Functional description L9660 3 Functional description 3.1 Overview The L9660 is an integrated circuit to be used in air bag systems. Its main functions include deployment of air bags. The L9660 supports 4 deployment loops. 3.2 General functions 3.2.1 Power on reset (POR) The ASIC has a power on reset (POR) circuit, which monitors VDD voltage. When VDD voltage falls below VRST1 for longer than or equal to tPOR, all outputs are disabled and all internal registers are reset to their default condition. A second reset level, VRST2, also monitors VDD but uses no filter time, so all outputs are disabled and all internal registers are reset to their default condition when VDD falls below the reset threshold. Figure 6. POR timing 40/2 -IN 40/2 -INd4d40/2 -AX 6$$-). 6234 6234 ).4%2.!, 2%3%4 40/2 -IN d 4d40/2 -AX '!0'03 3.2.2 RESETB The RESETB pin is active low. The effects of RESETB are similar to those of a POR event, except during a deployment. When a deployment is in-progress, the L9660 ignore the RESETB signal. However, it shuts itself down as soon as it detects a POR condition. When the deployment is completed and RESETB signal is asserted, the L9660 disables its outputs and reset its internal registers to their default states. A de-glitch timer is provided for the RESETB pin. The timer protects this pin against spurious glitches. The L9660 neglects RESETB signal if it is asserted for shorter than tGLITCH. RESETB has an internal pull-up in case of an open circuit. 18/49 DocID024714 Rev 2 L9660 3.2.3 Functional description Reference resistor IREF pin shall be connected to VDD supply through a resistor, RIREF. When the L9660 detects the resistor on IREF pin is larger than RIREF_H or smaller than RIREF_L, it goes into a reset condition. All outputs are disabled and all internal registers are reset to their default conditions. 3.2.4 Loss of ground GND When the GND pin is disconnected from PC-board ground, the L9660 goes in reset condition. All outputs are disabled and all internal registers are reset to their default conditions. GND0-GND3 A loss of power-ground (GND0 – GND3) pin/s disables the respective low side driver/s on SQLx. However, the high side driver of the respective channel is still able to be turned on. Thus under the scenario where the low side is shorted to ground the L9660 is able to provide the programmed firing current for the specified time. An open GNDx connection on any channel has no affect on the other channels. An open GNDx condition is detected using the low side MOS diagnostics. AGND The AGND pin is a reference for AOUT pin. When AGND loses its connection, the voltage on AOUT pin is pulled up to VDD voltage and L9660 goes in reset condition. All outputs are disabled and all internal register are reset to their default conditions. 3.2.5 VRESx capacitance To properly ensure all diagnostics functions a typical capacitor of equal to or greater than 68nF is required close to the firing supply pins. Thus a minimum of 2 capacitors are required with one placed close to the VRES0 and VRES1 pins and a second capacitor close to the VRES2 and VRES3 pins. 3.2.6 Supply voltages The primary current sources for the different functions of the ASIC are as follows: 3.2.7  VRESx - Firing currents along with HSS and HS FET diagnostic currents  VSDIAG - Squib resistance and HSS diagnostics  VDD is used for all internal functions as well as short to battery/ground and high squib resistance diagnostics. Ground connections GND pin (6) is not connected internally to other ground pins (AGND or power ground GNDx). A ground plane is needed to directly connect the GND pin. This ground plane needs to be isolated from the high current ground for the squib drivers to prevent voltage shifts. AGND pin should be connected to ground plane too to minimize drop versus ground reference of ADC that capture AOUT voltage. DocID024714 Rev 2 19/49 48 Functional description 3.3 L9660 Serial peripheral interface (SPI) The L9660 contains one serial peripheral interface for control of the squib functions. The following table shows features that are accessed/controlled by the SPI. . Table 9. Features that are accessed/controlled for the SPI Function Pin names Squib diagnostic and deployment SPI SCLK MISO MOSI CS_D Features accessed All Squib Diagnostics; Squib related status information; Squib Arming and Firing; Software Reset; Component ID & Revision The software reset accessed over SPI is resets squib functions. The L9660 has a counter to verify the number of clocks in SCLK. If the number of clocks in SCLK is not equal to 16 clocks while CS_D is asserted, it ignores the SPI message and sends a SPI fault response. L9660 computes SPI error length flag through counting the number of SCLK rising edges occurring when CS_D is active. If the first SCLK rising edge occurs when CS_D is inactive and the falling edge occurs when CS_D is low, it is considered as valid edge. MOSI commands contain several unused bits, all those bits must be 0. Commands are not recognized valid if one or more unused bits are not 0. 3.3.1 SPI pin descriptions Chip select (CS_D) Chip-select inputs select the L9660 for serial transfers. CS_D can be asserted at any given time and are active low. When chip-select is asserted, the respective MISO pin is released from tri-state mode, and all status information is latched into the SPI shift register. While chip-select is asserted, register data is shifted into MOSI pin and shifted out of MISO pin on each subsequent SCLK. When chip-select is negated, MISO pin is tri-stated. To allow sufficient time to reload the registers; chip-select pin shall remain negated for at least tCSN. The chip-select inputs have current sinks which pull these pins to the negated state when there is an open circuit condition. These pins have TTL level compatible input voltages allowing proper operation with microprocessors using a 3.3 to 5.0 volt supply. Serial clock (SCLK) SCLK input is the clock signal input for synchronization of serial data transfer. This pin has TTL level compatible input voltages allowing proper operation with microprocessors using a 3.3 to 5.0 volt supply. When chip select is asserted, both the SPI master and L9660 latch input data on the rising edge of SCLK. The L9660 shifts data out on the falling edge of SCLK. Serial data output (MISO) MISO output pins shall be in one tri-state condition when chip select is negated. When chip select is asserted, the MSB is the first bit of the word/byte transmitted on MISO and the LSB is the last bit of the word/byte transmitted. This pin supplies a rail to rail output, so if interfaced to a microprocessor that is using a lower VDD supply, the appropriate microprocessor input pin shall not sink more than IOH(min) and shall not clamp the MISO output voltage to less than VOH(min) while MISO pin is in a logic “1” state. When connecting to a micro using a lower supply, such as 3.3V, a resistor divider shall be used with high enough impedance to prevent excess current flow. 20/49 DocID024714 Rev 2 L9660 Functional description Serial data input (MOSI) MOSI inputs take data from the master processor while chip select is asserted. The MSB shall be the first bit of each word/byte received on MOSI and the LSB shall be the last bit of each word/byte received. This pin has TTL level compatible input voltages allowing proper operation with microprocessors using a 3.3 to 5.0 volt supply. 3.4 Squib drivers 3.4.1 Firing The on-chip deployment drivers are designed to deliver 1.2 A (min) for 2ms (min) and 1.75A (min) for 1ms (min) and 1.75A (min) for 0.65ms (min) with VRESx voltages between 7V and 37 V. In addition the L9660 can provide 1.5A minimum for 2ms for VRESx voltages between 7V and 25V. The firing condition is selectable via the SPI. At the end of a deployment, a deploy success flag is asserted and can be read using the appropriate SPI command. Each VRESx and GNDx connection is used to accommodate 4 loops that can be deployed simultaneously. Upon receiving a valid deployment condition, the respective SQHx and SQLx drivers are turned on. The only other activation of the SQHx and SQLx drivers is momentarily during a MOS diagnostic. Otherwise, SQHx and SQLx are inactive under any normal, fault, or transient conditions. Upon a successful deployment of the respective SQHx and SQLx drivers, a deploy command success flag is asserted via SPI. Refer to Figure 8 for the valid conditions and the deploy success flag timing. DocID024714 Rev 2 21/49 48 Functional description L9660 Figure 7. Deployment drivers diagram '.$ 3#,+ 6$$ &%. &%. ,OGIC -/3) -)3/ #3?$ 62%3 62%3 (3DRIVER (3DRIVER 31( DIAGNOSTIC DIAGNOSTIC 31( 31, 31, ,3DRIVER ,3DRIVER '.$ '.$ 62%3 62%3 (3DRIVER (3DRIVER 31( DIAGNOSTIC DIAGNOSTIC ,3DRIVER ,3DRIVER '.$ '.$ 63$)!' 31( 31, 31, !NALOG SQUIB RESISTANCE )2%& !/54 !'.$ '!0'03 The L9660 is protected against inadvertent turn on of the firing drivers unless the appropriate conditions are present. Non-typical conditions do not cause driver activation. This includes the case where VRESx and/or VSDIAG pins are connected to a supply up to 40V and VDD is between 0V and VDD min. Under these conditions the L9660 ensures that driver activation does not occur. No flow of current shall be allowed through the SQHx and SQLx pins. Driver activation The firing of a squib driver requires the appropriate FEN function to be active and two separate sixteen bit writes be made over the SPI. The FEN function is defined as the result of the FENx pin OR’d with the internal FENx latch. The FENx pin going high initiates the FEN function. With the FEN 1 function being active and the appropriate Arm and Fire commands sent then Squib_0 & 1 drivers would be activated. With the FEN 2 function being active and the appropriate Arm and Fire commands sent then Squib_2 & 3 drivers would be activated. The first write is to ARM the drivers in preparation of receiving the fire command. The ARM command stops on all channels any diagnostics that are active. Any combination of squibs can be armed. The second write is a FIRE command that must directly follow the ARM command and that activates the desired driver pairs assuming the FEN function is valid. If there is a parity mismatch the data bits are ignored and the squib drivers do not have their status changed, and the two write sequence must then be started again. If there is a mismatch in channels selected then only those channels selected in both the Arm and Fire commands are activated. 22/49 DocID024714 Rev 2 L9660 Functional description During the first write, when the drivers are armed, all diagnostic functions are cleared. The FIRE command must follow the ARM command along with the FEN function active for driver activation. If a command is between the ARM and FIRE command then the sequence must be restarted. An error response is received for the Fire command if the ARM/FIRE sequence is not followed. The ARM/FIRE commands and FEN function are independent from each other. The L9660 begins the tDEPLOY timer once a valid ARM/FIRE sequence has been received. If a valid ARM/FIRE command has been sent and the FEN function is inactive then the drivers are not activated but the tDEPLOY timer starts. If the FEN function becomes active before tDEPLOY has expired then the drivers become active for the full tDEPLOY time. If the FEN does not become active before tDEPLOY has expired then the sequence needs to be restarted. A diagram illustrating this is shown in Figure 8. Figure 8. Driver activation timing diagram 4IME 4$%0,/9 30)#OMMANDS ! & ! ! & &%.&UNCTION 4$%0,/9 4$%0,/9 $RIVER!CTIVE 4$%0,/9 $%0,/9?34!453 &LAG $%0,/9?35##%33 &LAG !!RM#OMMAND $EPL OYMENT- ODE &&IRE#OM MAND $EPL OYMENT -ODE '!0'03 Only the channels selected in the ARM and, directly following, the FIRE command are activated. By reading the appropriate registers a status of the deployment is provided. If a valid Arm/Fire sequence has been provided the status flag becomes active. This flag remains active for as long as the TDEPLOY timer is counting. Depending on the state of the FEN function the DEPLOY_STATUS flag is active a minimum of TDEPLOY and a maximum of 2 x TDEPLOY. If driver activation did occur (both a valid Arm/Fire sequence and the appropriate FEN function active within the appropriate time) then the DEPLOY_SUCCESS flag is active following the completion of the driver activation period. This flag is active until cleared by software. If a valid Arm/Fire sequence did occur but the FEN function was never activated within the TDEPLOY time then the DEPLOY_SUCCESS flag remains ‘0’. Once the Deploy Success Flag is set, it inhibits the subsequent deployment command until a SPI command to clear this deployment success flag is received. Bits D7 through bit D0 are used to clear/keep the deploy success flag. When these bits are set to ‘1,’ the flag can be DocID024714 Rev 2 23/49 48 Functional description L9660 cleared. Otherwise, the state of these flags is not affected. The Success flag must be cleared to allow re-activation of the drivers. During driver activation the respective high side (SQHx) and low side (SQLx) drivers turn on for tDEPLOY. L9660 driver activation does not occur or, if firing is in process, is terminated under the following conditions:  Power On Reset (POR)  IREF resistance is larger than RIREF_H or smaller than RIREF_L  Loss of ground condition on GND pin The following conditions are ignored when driver activation is in progress:  RESETB  Valid soft reset sequences  SPI commands except as noted below. Response for ignored commands is 0xD009  FEN function The following table shows the response when sending SPI commands during deployment. Table 10. SPI MOSI/MISO response SPI MOSI Configuration Commands SPI MISO SPI fault response Response MOSI register mode messages are ignored Deployment Commands Command mode Execute for channels not in deployment; no effect to deploying channel Diagnostic Commands SPI fault response MOSI diagnostic mode messages are ignored Monitor Commands Status response Execute for all channels Note 1: SPI MISO sent in the next SPI transmission. The L9660 can only deploy a channel when the FEN function is active. Once the drivers are active the L9660 keeps the drivers on for the required duration regardless of the FEN state. Once complete a status bit is set to indicate firing is complete. 3.4.2 Firing current measurement All channels have a 7 bit current measurement register that is used to measure the amount of time the current is above IMEAS during firing. The maximum measurement for each channel is 3.175ms nominal based on a bit weight of 25µs. The current measurement register does not increment outside the deployment time. The current measurement begins incrementing once the current has exceeded 95% of the nominal target value. The count continues to increment from the stored value until either a clear command has been issued for that channel or all ‘1’s are present in the corresponding channel measurement register. If all ‘1’s are present for a channel’s measurement register and another firing sequence has been issued the register remains all ‘1’s. Only if a clear command has been issued that particular register resets to all ‘0’s. All other channels shall keep the stored measurement count. During firing the current measurement register cannot be cleared. After a clear command has been issued for a channel then the channel is ready to count if the current exceeds the specified level. After a POR or software reset the L9660 resets all 4 measurement registers to all ‘0’s. 24/49 DocID024714 Rev 2 L9660 Functional description A “real-time” current measurement status of all the channels is available. If a current limit status request is sent then the L9660 reports in the next SPI transfer whether the current is above or below IMEAS for each of the channels. The current status results can be read at any time and correctly reports whether current is flowing. The content of the internal current status register is captured on the falling edge of chip select during the SPI response. The internal status register is updated at a nominal sample time of 25 µs and is independent from SPI transfers. For this circuit there is a continuously performed compensation of the comparator in order to remove offset errors, which is independent from SPI commands. The compensation is being performed every 12.8 µs based on the internal clock. 3.4.3 Fire enable (FEN) function description The Fire Enable (FEN) function is the result of the FENx input OR’d with the internal FEN latch. If the FEN latch is not enabled and the FENx pin is low then activations of the FET drivers are disabled except as indicated during the MOS test. All internal diagnostics are active, and results are available through the serial interface. This pin must be pulled high to initiate the FEN latch function (if programmed) and enable firing of the FET drivers. There are two FEN function blocks  FEN Function 1 is FEN1 input OR’d with FEN1 latch timer and used for enabling channels 0 & 1  FEN Function 2 is FEN1 input OR’d with FEN2 latch timer and used for enabling channels 2 & 3 The FEN function is considered active when the pin is active (‘1’ or high) for more than 12 microseconds. Tolerance range for the filter used is 12 to 16 µs. When the FENx input is active, ‘1’, the FEN function activates. When the FENx input state transitions from ‘1’ to ‘0’, the programmable latching function holds the FEN function active until the time-out of the FEN timer. The programmable latch and hold function are capable of delays of 0ms, 128ms, 256ms, and 512ms. There are 2 independent timers with the timer for FEN1 associated with channels 0 & 1, timer for FEN2 associated with channels 2 & 3. The timer is reset to the programmed time when the FENx pin transitions from ‘0’ to ‘1’. The programmable counter delay is set through a SPI command. 3.4.4 Squib diagnostics Overview The ASIC is able to perform the following diagnostics  Short to battery and ground on both SQHx and SQLx pins with or without a squib  Loop to loop diagnostics  Squib resistance measurement  Squib High resistance  High side safing FET diagnostics  VRESx voltage status  High and low side FET diagnostics Below is a block diagram showing the components involved in the squib diagnostics. DocID024714 Rev 2 25/49 48 Functional description L9660 Figure 9. Squib diagnostics block diagram (IGHSIDE3AFING DIAGNOSTIC 63$)!' % (33OPEN 2(33 COMP (33SHORT #,+?(33 )32# $ N 62%3 62%3X 6OLTAGEMEASUREMENTDIAGNOSTIC 3EL 6TH?( % 3EL COMP 62%3X,/ 6TH?, 31( 3QUIBRESISTANCEDIAGNOSTIC 3EL ! N 62%3X() 3EL # 31(X COMP 3EL & 3EL )32#?(33 #AL 2SQUIB 'AIN !/54 # N 31, 31,X 3EL 3EL 3EL 3EL ' " 3HORTTO"ATTERY'ROUND(IGHSQUIBRESISTANCEDIAGNOSTICS 3EL MIRROR )0$ )0$ 62#-BLOCK 3'3",(32 )3).+ '.$X '.$ 6OLT '.$ 3" MIRROR '!0'03 Short to battery/ground and loop to loop diagnostics The leakage diagnostic includes short to battery, short to ground and a short between loop tests. The test has to run for each SQHx and SQLx pin so that shorts can be detected regardless of the resistance between the squib pins. Normal short to battery/ground diagnostics. For the test the internal VRCM is switched on and connected to the selected pin (SQHx or SQLx) pin. The IPD bit selected OFF deactivates the pull-down current on the channel under test and all other channels. During the test with no leakage present the voltage on the selected SQHx or SQLx pin is equal to VBIAS and no current is sunk or sourced by VRCM. If a leakage to ground, battery or to SQLy is present, the VRCM sinks or sources a current less then ISVRCM trying to keep VBIAS. Two current comparators, ISTB and ISTG, detect the abnormal current flow. Loop to loop diagnostics For this test the same procedure is followed except the pull-down current (IPD) is selected to be ON that deactivates the pull-down current only on the channel under test with all other channel pull-down currents active. If a short to ground fault is active, assuming it was not active during normal short to battery/ground diagnostics, then that particular channel has a short to another squib loop. To detect loop to loop shorts between ASICs in the system the Stop diagnostics command with IPD enabled needs to be sent to the other ASICs before running the loop to loop diagnostics on the channel to be monitored. If the channel being monitored has a short to ground fault active, assuming it was not active during normal short 26/49 DocID024714 Rev 2 L9660 Functional description to battery/ground diagnostics, then that particular channel has a short to another squib loop in the system. The following table indicated how faults would be interpreted. Table 11. How faults shall be interpreted Fault condition for channel(1) Channel leakage diagnostics results with IPD ON Channel leakage diagnostics results with IPD OFF No Shorts No Fault No Fault Short to battery STB Fault STB Fault Loop to loop short STG Fault No Fault Short to ground STG Fault STG Fault 1. Condition where 2 open channels have the SQHx pins shorted is not detected. If one squib is open and the other has a normal squib connection then the fault is indicated on the channel that is open. Assumes both pins are tested. Once the command is issued the state of the comparators is captured on the next falling edge of CS_D. The results are valid after TSHORTDIAG time, which is mainly dependant on the external capacitors on the squib lines. Squib resistance measurement During a resistance measurement, both ISRC and ISINK are switched on and connected to the selected SQHx and SQLx channel. A differential voltage is created between the SQHx and SQLx pin based in the ISRC current and resistance between the pins. The analog output pin, AOUT, provides the resistance-measurement voltage based on the scaling factor indicated in the electrical parameters section. The tri-state output, AOUT, is connected to an ADC input of a microprocessor. When not running squib resistance diagnostics the AOUT pin is in high impedance state. To increase accuracy of the squib resistance measurements the offset of the internal amplifier can be provided on the AOUT pin. This is done by setting the appropriate calibration bit, waiting the required time, and reading the converted AOUT voltage connected to the microprocessor ADC. The normal measurement method for squib resistance is to take a single ended analog output measurement for a channel (VAOUT with AMC bit=0) and use the tolerances and equation shown in the parametric table. The L9660 is also capable of improving the tolerance at resistances below 3.5 Ohms by removing the offset of the differential comparator. This method works taking the single ended analog output results for a channel (VAOUT with AMC bit=0) and subtracting the internal comparator offset measurement of VAOUT_CAL (VAOUT with AMC bit=1). The summary of the equation for this is as follows: AOUT_CAL = (VAOUT – VAOUT_CAL)/VDD AOUT_CAL typical = 0.08 x RSQUIB High squib resistance diagnostics During a high squib resistance diagnostic, VRCM and ISINK are switched ON and connected to SQHx and SQLx on the selected channel. Current flowing on SQHx is measured and compared to IHR threshold to identify if resistance is above or below RSQHZ. The results are reported in the next SPI message. Once the command is issued DocID024714 Rev 2 27/49 48 Functional description L9660 the state of the squib resistance is valid after THSR is captured on the next falling edge of CS_D. The voltage source for this test is VBIAS which is based on the VDD supply. A way to reduce the time required until valid results are available is to perform a leakage diagnostics prior to this test. The leakage diagnostics biases the voltage on the squibs to around 3.5V, which is the same bias voltage required for the high squib resistance diagnostic. By running this sequence of diagnostics the test time reduces from 1.5ms to 200µs. High and low side FET diagnostics Prior to either the HS or LS FET diagnostics being run it is required to have the VRCM switched ON. Running the leakage diagnostics with the appropriate delay time prior to either the HS or LS FET diagnostics can do this. When the FET diagnostic command is issued the flags is initially cleared. If the VRMC is not active or some leakage is present then the MOS is not turned ON, the test is aborted and Fault Present (FP) bit set. The FEN function must be inactive to run test. The test does not start if FEN function is active on channel under test and it results in the Fault Present (FP) bit to set. If no leakage is present and FEN function is inactive, the MOS (High side or Low Side) is turned ON. The L9660 monitors the current sink or sourced by VRCM. If the MOS is working properly, this current exceeds ISTB (HS test) or ISTG (LS test) and the L9660 turns off the driver under test within the specified time TSHUTOFF. If the current does not exceed ISTB or ISTG then the test is terminated and the MOS switched off by the L9660 within TFETTIMEOUT. During the TFETTIMEOUT period the FET Time-out bit is set (FT=1) and cleared at the expiration of the timer. The results must be compared with the leakage diagnostic results to distinguish between a real leakage/short versus a FET fault. For high side FET diagnostics if no faults were indicated in the preceding leakage diagnostics then a normal result would be STB=1;STG=0 (with FT=0;FP=0). If the returned results for the high side FET test is not STB=1;STG=0 (with FT=0;FP=0) then either the FET is not functional, a short occurred during the test, or there is a missing VRESx connection for that channel. For low side FET diagnostics if no faults were indicated in the preceding leakage diagnostics then a normal result would be STB=0;STG=1 (with FT=0;FP=0). If the returned results for the low side FET test is not STB=0;STG=1 (with FT=0;FP=0) then either the FET is not functional, a short occurred during the test, or there is a missing GNDx connection for that channel. If the test is in progress then a bit (FT) is used in the response to indicate this status. Once the command is issued, output of comparators is latched. On the next falling edge of CS_D, comparator latched data is captured and reported to MISO response. The results remain latched until the next test is initiated (diagnostic write command). If the test is in progress then a bit is used in the response to indicate the test completion. If the FET under test is working properly then the results indicate a “Short to Ground” for LS test and “Short to Battery” for HS test. If a leakage is present prior to the test or FENx is asserted then both “Short to Ground” and Short to Battery” are indicated in the response for either a LS or HS FET test. For all conditions the current on SQHx/SQLx never exceeds ISVRCM. On the squib lines there may be higher transient currents due to the presence of the filter capacitor. 28/49 DocID024714 Rev 2 L9660 Functional description High side safing diagnostics When the command is received the L9660 activates IHSS on the selected VRESx. The diagnostics measures the difference between VSDIAG and VRESx. The internal comparator detects open, short or normal condition based on the differential voltage between VSDIAG and VRESx. The results are reported in the next SPI message using bits HSS1 and HSS0 as indicated in the following table. Once the command is issued the voltages are captured on the next falling edge of CS_D. Table 12. Diagnostic Mode HSS selection Condition HSS1 HSS0 (VSDIAG-VRESx) < VHSSSHORT_th 0 0 VHSSSHORT_th < (VSDIAG-VRESx) < VHSSOPEN_th 0 1 VHSSOPEN_th < (VSDIAG-VRESx) 1 1 Voltage measurement diagnostics (VRESx) When the command is received the L9660 activates a comparator for the selected channel. A 2 bit indication of the state of the VRESx pins is reported as indicated below. The results are reported in the next SPI message. Once the command is issued the voltages are captured on the next falling edge of CS_D. Table 13. Diagnostic mode 3 VRESx selection Condition VR1 VR0 VRESx < VVRESXLO_th 0 0 VVRESXLO_th < VRESx < VVRESXHI_th 0 1 VVRESXHI_th < VRESx 1 1 Loss of power ground When any of the power grounds (GND0 – 3) are lost, no deployment can occur on the respective deployment channels because the low side driver is inactive. The high side driver for the respective channel can still be activated. A loss of ground condition on one or several channels does not affect the operation of the remaining channels. When a loss of ground condition occurs, the source of the low side MOS is floating. In this case, no current flows through the low side driver. This condition is detected as a fault by a low side MOS diagnostic. No additional faults are reported from any other diagnostic due to this condition. DocID024714 Rev 2 29/49 48 Functional description 3.4.5 L9660 SPI register definition for squib functions The SPI provides access to read/write to the registers internal to the L9660. All commands and responses sent to/from the L9660 on SPI use set D13 as required for odd parity on the 16 bit word. The responses to the commands are sent in the next valid CS_D. The table below summarizes the MISO register mode response of various events and MOSI messages. After POR event, RESETB negated, and loss of GND, the L9660 sends 0x0000 in MISO for the first SPI transmission. The MISO response shown here is the one received in the next valid SPI transmission after each event or MOSI write. Table 14. MISO responses to various events Event/MOSI message MISO response MOSI Parity error or unrecognized command 0xD000 MOSI transmission - Incorrect number of clocks/bits 0xD003 Incorrect firing sequence received (Firing Command without a valid Arm Command) 0xD005 Error due to message not allowed during deployment 0xD009 POR 0x0000 RESETB 0x0000 LOSS OF gnd 0x0000 RIREF out of range 0x0000 MOSI Write Soft Reset: $AA 0x1X02 MOSI Write Soft Reset: $55 (after $AA) 0x2003 Note: X in software reset response interpreted as follows: D11=1;D10=0;D9:D8=CL bits The SPI fault responses (0xD000 or 0xD003) indicate a fault in the last MOSI transmission. The L9660 uses the parity bit to determine the integrity of the MOSI command transmission. 3.4.5.1 Squib SPI commands The following are the modes that are supported by the squib L9660 using SPI.  Configuration mode  Deployment mode  Diagnostic mode  Monitor mode The table below is a summary of the modes and the functions that are achieved by sending the particular MOSI command. The following sections provide a full description of bit settings for each mode. All commands and responses use D13 to achieve odd parity. 30/49 DocID024714 Rev 2 L9660 Functional description Table 15. Command description summary Command/mode Mode bits Description D15 D14 D13 D12 D11 D10 D09 D08 D07 - D00 Configuration commands Config. Mode 1 Current limit programming and software reset 0 0 P - - 0 - - - Config. Mode 2 FEN latch time Programming 0 0 P - - 1 - - - Deployment Mode 1 Arming Command 0 1 P 1 1 0 0 1 - Deployment Mode 2 Firing Command 0 1 P 0 0 0 0 0 - Deployment commands Diagnostic commands Diagnostic Mode 1 Disable Diagnostic 1 0 P - 0 0 0 - - Diagnostic Mode 2 Short to battery & ground diagnostics Short between loop diagnostics 1 0 P - 0 0 1 - - Diagnostic Mode 3 VRESx voltage diagnostics 1 0 P - 0 1 0 - - Diagnostic Mode 4 High Side Safing diagnostics 1 0 P - 0 1 1 - - Diagnostic Mode 5 Squib Resistance Diagnostics 1 0 P - 1 0 0 - - Diagnostic Mode 6 High Squib Resistance Diagnostics 1 0 P - 1 0 1 - - Diagnostic Mode 7 LS driver diagnostics 1 0 P - 1 1 0 - - Diagnostic Mode 8 HS driver diagnostics 1 0 P - 1 1 1 - - Monitor Mode 1 Deployment status 1 1 P - 0 0 - - - Monitor Mode 2 Channel current limit measurement information 1 1 P - 0 1 - - - Monitor Mode 3 FENx function status and active current limit status 1 1 P - 1 0 - - - Monitor Mode 4 Revision and L9660 ID 1 1 P - 1 1 - - - Monitor commands P = Parity bit – all commands and responses use this bit to achieve odd parity The squib circuits can be reset over when sending the appropriate configuration commands via SPI. Configuration commands Configuration mode 1 Configuration mode 1 main functions are as follows:  Set Deployment current for all channels. All channels are either set to 1.2A/2ms, 1.5A/2ms (Maximum VRESx Voltage limited to 25V) 1.75A/1ms or 1.75A/0.65ms  Perform a software reset The SPI message definition for MOSI commands and MISO responses in this mode are defined below. DocID024714 Rev 2 31/49 48 Functional description L9660 MSB D15 LSB D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 0 MOSI Command for configuration Mode 1 0 0 P R/W SWR 0 CL Set bits Software Reset Sequence bits MISO Response for configuration Mode 1 (Except for Soft Reset/D11=1 and appropriate pattern) 0 0 P R/W SWR 0 CL Set bits 0 0 0 0 0 0 Table 16. Configuration mode 1 MOSI command MISO response Bit State D15 D14 D13 0 0 0 D12 1 0 D11 1 D10 D9 D8 D7 – D2 D1 D0 32/49 Description Mode bits Odd Parity – Includes all 16 bits Read (default) - When D12=’0’ bits D11 to D0 are ignored Write – Allows Soft reset and deployment programming Sets Deployment Condition for ALL channels - When D11=’0’ bits D7 to D0 are ignored Soft Reset Sequence – bits D8 and D9 are ignored 0 Sets Deployment Conditions 00 = 1.2A/2ms (Default) 01 = 1.5A/2ms 10 = 1.75A/0.65ms 11 = 1.75A/1ms Software Reset-sequence See above See above Odd Parity – Includes all 16 bits R/W bit See above See above Internal Stored Value CL bits - See above see above See above Bit [D9:D8] Bits used to set the firing current/time for all channels. The default state is ‘00’ (1.2A/2ms min.) Bits [D7:D0] The soft reset for the L9660, which includes deployment driver/diagnostics, is achieved by writing 0xAA and 0x55 within two subsequent 16-bit SPI transmissions. If the sequence is broken, the processor is required to re-transmit the sequence. The L9660 does not reset if the sequence is not completed within two subsequent 16- bit SPI transmissions. When soft reset command is received, the L9660 reset its deployment driver’s internal logic and timers, including all internal registers. The effects of a soft reset is the same as for a POR event, except MISO response. Bit [D1] For the first response after POR (or equivalent) the PU bit is set to ‘0’. For all responses following the bit is set to ‘1’. DocID024714 Rev 2 L9660 Functional description Bit [D0] Bit D0 used to report the soft reset sequence status. If valid soft reset sequences are received, bit D0 is set to ‘1.’ Otherwise, bit D0 is set to ‘0.’ When L9660 receives valid soft reset sequences, it sends a MISO configuration mode response containing 0x2003 in the next SPI transmission. Configuration mode 2 Configuration mode 2 main function is as follows:  Set the latch time for FENx input The SPI message definition for MOSI commands and MISO responses in this mode are defined below. MSB D15 LSB D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Latch bits 0 0 0 0 0 0 0 0 Latch bits 0 0 0 0 0 0 0 0 MOSI Command for configuration mode 2 0 0 P R/W 0 1 MISO Response for configuration mode 2 0 0 P R/W 0 1 Table 17. Configuration mode 2 MOSI command MISO response Bit State D15 D14 D13 0 0 0 D12 1 0 1 D11 D10 D9 D8 D7 – D0 - 0 Bits [D9:D8] Description Mode bits Odd Parity – Includes all 16 bits Read (default) - When D12=’0’ bits D11 to D0 are ignored Write – FEN latch programming FEN latch time 00 = 0ms (default) 01 = 128ms 10 = 256ms 11 = 512ms - See above See above Odd Parity – Includes all 16 bits R/W bit - Internal Stored Value FEN latch bits See above Bits are used to set the period of the FEN latch timer. The L9660 has 2 independent timers. A valid FENx input starts the pulse stretch timer. These bits set the timer duration. These values default to ‘00’ after a POR event. DocID024714 Rev 2 33/49 48 Functional description L9660 Deployment commands The deployment mode is used to activate the drivers. Two consecutive commands are required to activate the drivers. Any combination of channels can be fired as long as the prerequisite conditions are met as indicated in the previous section. The SPI message definition for MOSI commands and MISO responses in Deployment Mode are defined below. MSB D15 LSB D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 0 0 Arming Channel Select 0 1 0 0 0 0 Armed Channels 0 0 0 0 0 0 Firing Channel Select 0 0 0 0 0 0 Channels activated or channels waiting for FEN input MOSI Command for Deployment Mode 1 0 1 P 1 1 0 MISO Response for Deployment Mode 1 0 1 P 1 1 0 MOSI Command for Deployment Mode 2 0 1 P 0 0 0 MISO Response for Deployment Mode 2 0 1 P 0 0 0 Table 18. Deployment mode 1 bit definition MOSI command MISO response Bit State D15 Description 0 See above Mode bits D14 1 D13 D12 – D8 See above Odd Parity – Includes all 16 bits Odd Parity – Includes all 16 bits Arm pattern See above D7 0 - 0 D6 0 - 0 D5 0 - 0 D4 0 - 0 0 Channel 3 Idle (default) 1 Arm Channel 3 0 Channel 2 Idle (default) 1 Arm Channel 2 0 Channel 1 Idle (default) 1 Arm Channel 1 D3 Internal Stored Value Arm bit D2 Internal Stored Value Arm bit D1 34/49 Internal Stored Value Arm bit DocID024714 Rev 2 L9660 Functional description Table 18. Deployment mode 1 bit definition MOSI command MISO response Bit State Description 0 Channel 0 Idle (default) 1 Arm Channel 0 D0 Internal Stored Value Arm bit Table 19. Deployment mode 2 bit definition MOSI command MISO response Bit State Description D15 0 Mode bits See above D14 1 - See above Odd Parity – Includes all 16 bits Odd Parity – Includes all 16 bits Fire pattern See above D13 D12 – D8 D7 0 - 0 D6 0 - 0 D5 0 - 0 D4 0 - 0 0 Channel 3 Idle (default) 1 Deploy Channel 3 0 Channel 2 Idle (default) 1 Deploy Channel 2 0 Channel 1 Idle (default) 1 Deploy Channel 1 0 Channel 0 Idle (default) 1 Deploy Channel 0 D3 Internal Deploy Status D2 Internal Deploy Status D1 Internal Deploy Status D0 Internal Deploy Status The Deploy Status becomes ‘1’ when there is a valid fire sequence. Once active it becomes ‘0’ when the time out has expired waiting FEN activation or when squib driver has turned off for fire completion. The same information is available when receiving a response from Monitor Mode 1. For the drivers to be fire capable the command mode 1 (Arming) must be sent followed by command mode 2 (Firing). With this sequence valid and FEN active then firing begins. A break in the sequence requires the process to be restarted. All other bit patterns for D12-D0 are ignored and the L9660 responds with $D005. To begin a deployment 2 consecutive commands need to be sent along with the FEN active (external or internal latch). An example of a firing sequence for channel 0 would be as follows FENx active or inactive TX – 0x5901 – ARM Channel 0 RX – Based on previous command DocID024714 Rev 2 35/49 48 Functional description L9660 TX – 0x5901 – ARM Channel 0 RX – 0x5901 TX – 0x5901 – ARM Channel 0 RX – 0x5901 TX – 0x6001 – Firing on Channel 0 is started on if FEN is active RX – 0x5901 TX – 0x6001 – Command ignored – sequence is not allowed RX – 0x6001 TX – 0x6001 – Command ignored RX – 0xD005 Alternatively, if the sequence is broken the response is as in the following example FENx active TX – 0x5901 – ARM Channel 0 RX – Based on previous command TX – 0x2000 – Read of Register Mode 1 RX – 0x5901 TX – 0x6001 – Command ignored – sequence is not allowed RX – contents of register TX – 0x6001 – Command ignored – sequence is not allowed RX – 0xD005 If, for example, channel 0 and 1 bits are set in the Arm command and channel 0 and 2 bits are set in the fire command then the drivers on channel 0 are activated (assuming FEN function is active) and there are no effect on channel 2. During a deployment, any commands directed to the channel that is in deployment are ignored and the response shall be 0xD009. Diagnostic commands Diagnostic Mode Diagnostic mode main functions are as follows:  Squib short to battery/ground diagnostics  Loop to loop diagnostics  Normal Squib Resistance Diagnostics  High Squib Resistance Diagnostics  High side safing diagnostics  VRESx measurement  LS and HS FET Test The SPI message definition for MOSI commands and MISO responses in Diagnostic Mode are defined below. 36/49 DocID024714 Rev 2 L9660 Functional description Write commands definition MSB D15 LSB D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 0 0 SQ P D4 D3 D2 D1 D0 MOSI Command for Diagnostic Mode Execution 1 0 P 1 Diag. Selection bits 0 IPD_DIS AMC Channel selection MISO Response for Diagnostic Mode, Stop Diagnostic Selection (MOSI D11:D9=000) Diagnostic Mode 1 1 0 P 1 0 0 0 0 0 0 0 IPD_DIS 0 000 MISO Response for Short to Battery/Ground Selection (MOSI D11:D9=001) Diagnostic Mode 2 1 0 P 1 0 0 1 STB STG 0 SQP IPD_DIS 0 Channel selection MISO Response for Diagnostic Mode, Vresx Selection (MOSI D11:D9=010) Diagnostic Mode 3 1 0 P 1 0 1 0 VR1 VR0 0 0 IPD_DIS 0 Channel selection MISO Response for Diagnostic Mode, High Side Safing Selection (MOSI D11:D9=011) Diagnostic Mode 4 1 0 P 1 0 1 1 HSS1 HSS0 0 0 IPD_DIS 0 Channel selection MISO Response for Diagnostic Mode, Squib Resistance Selection (MOSI D11:D9=100) Diagnostic Mode 5 1 0 P 1 1 0 0 0 0 0 0 IPD_DIS AMC Channel selection MISO Response for Diagnostic Mode, High Squib Resistance Selection (MOSI D11:D9=101) Diag. Mode 6 1 0 P 1 1 0 1 HSR 0 0 0 IPD_DIS 0 Channel selection MISO Response for Diagnostic Mode, Low Side FET Test Selection (MOSI D11:D9=110) Diagnostic Mode 7 1 0 P 1 1 1 0 STB STG FP FT IPD_DIS 0 Channel selection MISO Response for Diagnostic Mode, High Side FET Test Selection (MOSI D11:D9=111) Diagnostic Mode 8 1 0 P 1 1 1 1 STB STG FP FT IPD_DIS 0 Channel selection Read commands definition MSB D15 LSB D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 0 000 X X IPD_DIS X Channel Selection Internal State MOSI Command for Diagnostic Mode, READ command 1 0 P 0 0 0 0 1 1 MISO Response for Diagnostic Mode, READ command 1 0 P 0 Diag. Selection bits internal state X X Bits D13 Parity bit. Command and response use odd parity Bits D12 R/W 1 = Write (execute command) 0 = Read For bits D11:D09 the following table shall be used for diagnostic selection. DocID024714 Rev 2 37/49 48 Functional description L9660 Table 20. Diagnostic selection Bits Diagnostic Current source active Comparator or amplifier D11 D10 D9 Stop Diagnostic 0 0 0 NO NO Short to Battery/Ground and short between loops 0 0 1 Y (VMRC) Y (Comp ISTB/ISTG) VRESx Diagnostic 0 1 0 N Y (Comp VRESx) High Side Safing Diagnostics 0 1 1 Y (IHSS) Y (Comp HSS) Squib Resistance Diagnostics 1 0 0 Y (ISRC/ISINK) Y (Amply) High Squib Resistance Diagnostics 1 0 1 Y (VMRC/ISINK) Y (Comp IHR) LS FET test 1 1 0 Y (VMRC) Y (Comp ISTB/ISTG) HS FET test 1 1 1 Y (VMRC) Y (Comp ISTB/ISTG) Bits D8:D7 The definition of the response bits changes as follows based on diagnostic select STB/STG bit Definition with MOSI D11:D9=001 (Leakage Test) STB bit Bit used for indicating leakage to battery. 0 = No leakage to battery 1 = Short to battery / HS Driver test pass STG bit Bit used for indicating leakage to ground. 0 = No leakage to battery 1 = Short to ground / LS Driver test pass STB/STG bit Definition with MOSI D11:D9=110 (LS FET) STB, STG bits see table below Table 21. Diagnostic mode LS FET selection 38/49 Condition STB STG Test in Process (FT=1); Fault present prior to run test (FP=1); or LS FET/GNDx open fault (FP=0,FT=0). Only Valid if test is in process or inactive. 0 0 Short to battery occurred during test. 1 0 Test Pass if leakage diagnostics did not indicate a short to Gnd. 0 1 DocID024714 Rev 2 L9660 Functional description STB/STG bit definition with MOSI D11:D9=111 (HS FET) STB, STG bits see table below Table 22. Diagnostic mode HS FET selection Condition STB STG Test in Process (FT=1); Fault present prior to run test (FP=1); or HS 0 FET/VRESx open fault (FP=0,FT=0). Only Valid if test is in process or inactive. 0 1 0 Test Pass if leakage diagnostics did not indicate a short to battery. Short to ground occurred during test. 0 1 HSS1:HSS0 bit definition with MOSI D11:D9=011 (High side safing) HSS1:HSS0 bits see table below Table 23. Diagnostic mode HSS selection Condition HSS1 HSS0 (VSDIAG-VRESx) < VHSSSHORT_th 0 0 VHSSSHORT_th < (VSDIAG-VRESx) < VHSSOPEN_th 0 1 VHSSOPEN_th < (VSDIAG-VRESx) 1 1 VR1:VR0 bit definition with MOSI D11:D9=010 (VRESx supply voltage) VR1:VR0 bits see table below Table 24. Diagnostic mode VRESx selection Condition VR1 VR0 VRESx < VVRESXLO_th 0 0 VVRESXLO_th < VRESx < VVRESXHI_th 0 1 VVRESXHI_th < VRESx 1 1 HSR Bit Definition with MOSI D11:D9=101 (High Squib Resistance) HSR bit Bit used for indicating a high squib resistance. 0 = Squib Resistance below RSQHIZ 1 = Squib Resistance above RSQHIZ Bits D6 FP Fault present prior to running LS FET or HS FET test (diagnostics aborted) 0 = Normal 1 = Test not run - Fault present (FEN in incorrect state, short to battery or ground) Bits D5 Bit definition based on diagnostic selection. FT bit Read Only - Used for LS FET or HS FET diagnostics and is the status of the FET timer 0 = FET timer not active 1 = FET timer active DocID024714 Rev 2 39/49 48 Functional description L9660 SQP bit: Squib Pin to be tested during short to battery/ground diagnostics 0 = SQBLx pin test 1 = SQBHx pin test Bits D4 Used to disable IPD on all channels 0 = IPD active as indicated; – Active for all channels except the one under test when running Short to Battery/Ground and short between loops Bits D3 For bits D2:D0 Diagnostics and LS/HS FET test – Active for all channels when running Stop Diagnostic, Resistance Diagnostics, High Squib Resistance Diagnostics, HSS Diagnostic and VRESx Diagnostics 1 = IPD disabled on all channels AMC Bit Bit used for resistance measurement amplifier calibration. Only valid when squib resistance diagnostics is selected, otherwise this is ignored and a 0 is reported in the response 0 = No calibration (Normal squib resistance measurements) 1 = Calibration The following table shall be used for channel selection. Table 25. Channel selection Channel Bit D2 Bit D1 Bit D0 0 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 All other combinations for MOSI bits D2:D0 produce an error response of 0xD000. Note: 40/49 Except for short to battery /ground diagnostics and loop to loop test the state of IPD (D4) does not affect the test. DocID024714 Rev 2 L9660 Functional description Monitor commands Monitor Mode 1 Monitor mode main information:  Deployment status The SPI message definition for MOSI commands and MISO responses in Monitor Mode 1 are defined below. MSB D15 LSB D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 0 0 DS Channel Selection Status Request 0 0 DS Channel Status D0 MOSI Command for Monitor Mode 1 1 1 P 0 0 MISO Response for Monitor Mode 1 1 1 P 0 0 Table 26. MOSI diagnostic mode 1 bit definition MOSI Command MISO Response Bit State Description D15 1 Mode bits See above for state D14 1 Mode bits See above for state Odd Parity – Includes all 16 bits Odd Parity – Includes all 16 bits D13 D12 0 - See above for state D11 0 Monitor Mode selection bits See above for state D10 0 Monitor Mode selection bits See above for state D9 0 - See above for state 0 Report Deploy Success Flag (default) 1 Report Deploy Status D7 0 - 0 D6 0 - 0 D5 0 - 0 D4 0 - 0 0 Keep Deploy Success Flag Channel 3 (default) Deploy Information for channel based on bit D8 is either DEPLOY_STATUS3 orDEPLOY_SUCCESS3 D8 D3 D2 D1 D0 1 Clear Deploy Success Flag Channel 3 0 Keep Deploy Success Flag Channel 2 (default) 1 Clear Deploy Success Flag Channel 2 0 Keep Deploy Success Flag Channel 1 (default) 1 Clear Deploy Success Flag Channel 1 0 Keep Deploy Success Flag Channel 0 (default) 1 Clear Deploy Success Flag Channel 0 DocID024714 Rev 2 Internal state of report setting Deploy Information for channel based on bit D8 is either DEPLOY_STATUS2 or DEPLOY_SUCCESS62 Deploy Information for channel based on bit D8 is either DEPLOY_STATUS1 or DEPLOY_SUCCESS1 Deploy Information for channel based on bit D8 is either DEPLOY_STATUS0 or DEPLOY_SUCCESS0 41/49 48 Functional description L9660 The DEPLOY_SUCCESSx flag indicates if the corresponding channel’s drivers were activated and the activation period completed. This bit is set when the activation period has expired. The DEPLOY_SUCCESSx flag is ‘1’ until it is cleared by writing a ‘1’ to the appropriate channel(s) (bits D3-D0). The DEPLOY_STATUSx bit becomes ‘1’ when there is a valid Arm and Fire sequence for the corresponding channel. The DEPLOY_STATUSx bit transitioning from a ‘0’ to a ‘1’ does not depend on the state of the FEN function. It becomes ‘0’ when time out has expired. Depending on the state of FEN the DEPLOY_STATUSx flag could be ‘1’ for a minimum of 1x tDEPLOY and a maximum of up to 2 x tDEPLOY (see Figure 8.). The Deployment status is captured on the falling edge of CS_D. Bit D8 is used to select the meaning of bit D3 through bit D0 in the status response message. When this bit is set to ‘1,’ bits D3 through D0 in the status response message report the state of the DEPLOY_STATUSx flag. When this bit is ‘0,’ bit D3 through bit D0 in the status response message report the DEPLOY_SUCCESSx flag. The following table shows the conditions for the DEPLOY_STATUSx flag and the DEPLOY_SUCCESSx flag. Table 27. DEPLOY_STATUSx flag and DEPLOY_SUCCESSx flag conditions DEPLOY_STATUSx flag DEPLOY_SUCCESSx flag 0 0 0 1 1 1 0 1 Description No Deployment in process or has been initiated since POR or since last Clear of Success flag Deployment has successfully completed Deployment in process Deployment terminated / LSD shutdown Once set, the Deploy Success Flag inhibits the subsequent deployment command until a SPI command to clear this deployment success flag is received. Bits D3 through bit D0 are used to clear/keep the deploy success flag. When these bits are set to ‘1,’ the flag can be cleared. Otherwise, the state of these flags is not affected. The Success flag must be cleared to allow re-activation of the drivers. 42/49 DocID024714 Rev 2 L9660 Functional description Monitor mode 2 Monitor mode main information:  Current limit measurement of channels The SPI message definition for MOSI commands and MISO responses in Monitor Mode 2 are defined below. MSB D15 LSB D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 MOSI Command for Monitor Mode 2 1 1 P CLR 0 1 Current Measurement Channel Select 1 Current Measurement Channel MISO Response for Monitor Mode 2 1 1 P 0 0 Current Measurement Data Table 28. MOSI monitor mode 2 Bit definition MOSI command MISO response Bit State Description D15 1 Mode bits See above for state D14 1 Mode bits See above for state Odd parity – Includes all 16 bits Odd Parity – Includes all 16 bits 0 Keep timer measurements See above for state 1 Clear “current measurement time” stored on the register of channel selected by See above for state D9:D7 D11 0 Monitor mode selection bits See above for state D10 1 Monitor mode selection bits See above for state Channel selected for current measurement See Table 29 Internal Stored channel selections bits - Current measurement of selected channel D13 D12 D9 D8 D7 D6:D0 0 Bits [D9:D7]. Used when sending the MOSI command to select the channel to be measured. The MISO response echoes the MOSI command. Table 29. Current measurement channel selections Channel Bit D9 Bit D08 Bit D07 0 1 2 3 0 0 0 0 0 0 1 1 0 1 0 1 DocID024714 Rev 2 43/49 48 Functional description L9660 All other combinations for MOSI bits D9:D7 produce an error response of 0xD000. Bits [D6:D0] Current measurement data of selected squib channel. Bit weight is nominally 25µs for a total measurement time 3.175ms. Monitor mode 3 Monitor mode main information:  Status of FENx Function - FENx pin OR’d with Internal FENx latch  Status of current for each channel The SPI message definition for MOSI commands and MISO responses in Monitor Mode 3 are defined below. MSB D15 LSB D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CFS 0 0 0 0 0 0 0 0 0 CF6 CF5 CF4 CF3 CF2 CF1 CF0 MOSI Command for Monitor Mode 3 1 1 P 0 1 0 MISO Response for Monitor Mode 3 1 1 P 0 1 0 CFS POR STA CF7 T Table 30. MOSI monitor mode 3 bit definition MOSI command MISO response Bit State D15 Description 1 See above for state Mode Bits D14 1 D13 - Odd Parity – Includes all 16 bits Odd Parity – Includes all 16 bits D12 0 - See above for state D11 1 - See above for state D10 0 - See above for state Status Type 0 = Current limit status 1 = FEN function status 0 = current measurement status reported in bit D7:D0 1 = FEN function status reported in D7:D0 D09 See above for state D08 0 - D7:D0 0 - POR status Current measurement status of channels or FEN status as indicated below Bit [D8] POR status 0= Reset occurred. Bit cleared when read 1= Normal With Bit D9=1 CFS Bit D7:D2‘000000’ 44/49 DocID024714 Rev 2 L9660 Functional description Bit D1: 0 = FEN2 input or FEN2 latch timer inactive 1 = FEN2 input or FEN2 latch timer active Bit D0: 0 = FEN1 input or FEN1 latch timer inactive 1 = FEN1 input or FEN1 latch timer active Note: The FEN status is the result of the state of the FEN input pin OR’d with the FEN latch timer. The FEN latch timer remains inactive until a transition of ‘1’ to ‘0’ on the FEN input (assuming the pin was high for a minimum of 16µs). At that time the FEN latch timer is active and keeps the internal FEN signal active based on the programmed time (0ms, 128ms, 256ms or 512ms) for that particular FEN function. With Bit D9=0 CFS Bit D7:D4:‘0000’ Bit D3: 0 = Current through channel 3 is below IMEAS 1 = Current through channel 3 is above IMEAS Bit D2: 0 = Current through channel 2 is below IMEAS 1 = Current through channel 2 is above IMEAS Bit D1: 0 = Current through channel 1 is below IMEAS 1 = Current through channel 1 is above IMEAS Bit D0: 0 = Current through channel 0 is below IMEAS 1 = Current through channel 0 is above IMEAS Note: Current status for channel is captured on the falling edge of chip select. Monitor mode 4 Monitor mode main information:  Revision  L9660 ID The SPI message definition for MOSI commands and MISO responses in Monitor Mode 4 are defined below: . MSB D15 LSB D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 0 0 0 0 0 0 0 1 ID3 ID2 ID1 ID0 R5 R4 R3 R2 R1 R0 MOSI Command for Monitor Mode 4 1 1 P 0 1 MISO Response for Monitor Mode 4 1 1 P 0 1 DocID024714 Rev 2 45/49 48 Functional description L9660 Table 31. MOSI monitor mode 4 bit definition MOSI command MISO response Bit State D15 Description 1 See above for state Mode Bits D14 1 D13 See above for state Odd Parity – Includes all 16 bits Odd Parity – Includes all 16 bits D12 0 - See above for state D11 1 Mode selection See above for state D10 1 Mode selection See above for state D9-D6 0 - ‘1000’ is device L9660 D5:D0 0 - Revision Information The MOSI response for the first pass L9660 is 0xCE09. 46/49 DocID024714 Rev 2 L9660 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 10. LQFP64 (10 x 10 x mm) mechanical data and package dimensions. MM INCH $)- -). 490 -!8 ! -). 490   !    !               "  #  $       $        $   E   %       %             %  , /54,).%!.$ -%#(!.)#!,$!4 ! -!8  ,  + ƒPLQƒPLQƒPD[  CCC  ,1&0XXMM  $ $ ! $ ! !     MM CCC " 3EATING0LANE % % % "     # E , , 4 Package information + 41&0 & '!0'03 DocID024714 Rev 2 47/49 48 Revision history 5 L9660 Revision history Table 32. Document revision history 48/49 Date Revision Changes 27-Jun-2013 1 Initial release. 19-Sep-2013 2 Updated Disclaimer. DocID024714 Rev 2 L9660 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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