LNBH23

LNBH23 LNBs supply and control IC with step-up and I²C interface Features ■ ■ Complete interface between LNB and I²C bus Built-in DC-DC converter for single 12 V supply operation and high efficiency (Typ. 93% @ 0.75 A), with integrated NMOS Selectable output current limit by external resistor Compliant with main satellite receiver systems specifications New accurate built-in 22 kHz tone generator suits widely accepted standards (patent pending) see Figure 1 and Figure 4 Fast oscillator start-up facilitates DiSEqCTM encoding Built-in 22 kHz tone detector supports bidirectional DiSEqCTM 2.0 Very low-drop post regulator and high efficiency step-up PWM with integrated power N-MOS allow low power losses Two output pins suitable to by-pass the output R-L filter and avoid any tone distortion (R-L filter as per DiSEqCTM 2.0 specs, see typ. application circuits) Overload and over-temperature internal protections with I²C diagnostic bits Output voltage and output current level diagnostic feedback by I²C bits LNB Short circuit dynamic protection +/- 4 kV ESD tolerant on output power pins PowerSSO-24 (Exposed pad) QFN32 (5x5mm) (Exposed pad) ■ ■ ■ ■ ■ Description Intended for analog and digital satellite receivers/Sat-TV, sat-PC cards, the LNBH23 is a monolithic voltage regulator and interface IC, assembled in PowerSSO-24 ePAD and QFN32 (5x5 mm) ePAD, specifically designed to provide the 13/18 V power supply and the 22 kHz tone signalling to the LNB down-converter in the antenna dish or to the multi-switch box. In this application field, it offers a complete solution with extremely low component count, low power dissipation together with simple design and I²C standard interfacing. ■ ■ ■ ■ ■ ■ Table 1. Device summary Order code LNBH23PPR LNBH23QTR (1) Package PowerSSO-24 (Exposed pad) QFN32 (Exposed pad) Packaging Tape and reel Tape and reel 1. Available on request. March 2008 Rev 4 1/32 www.st.com 32 Contents LNBH23 Contents 1 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 DiSEqCTM data encoding and decoding . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DiSEqCTM 2.0 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DiSEqCTM 1.X implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Data encoding by external tone generator (EXTM) . . . . . . . . . . . . . . . . . . 6 I²C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Diagnostic and protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Output voltage diagnostic - VMON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 22 kHz tone diagnostic - TMON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Minimum output current diagnostic - IMON . . . . . . . . . . . . . . . . . . . . . . . . 7 Output current limit selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Over-current and short circuit protection and diagnostic . . . . . . . . . . . . . . 8 Thermal protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 4 5 6 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 I²C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1 6.2 6.3 6.4 6.5 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Start and stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7 LNBH23 software description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.1 7.2 Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 System register (SR, 1 byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2/32 LNBH23 Contents 7.3 7.4 7.5 7.6 7.7 Transmitted data (I²C bus write mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Diagnostic received data (I²C read mode) . . . . . . . . . . . . . . . . . . . . . . . . 17 Power-ON I²C interface reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Address pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 DiSEqCTM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8 9 10 11 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3/32 Block diagram LNBH23 1 Figure 1. Block diagram Block diagram ISEL TTX ADDR SDA SDA SCL Vcc Byp Vcc-L LX PWM Controller Preregulator +U.V.lockout +P.ON reset EN VSEL VSEL TTX EN Rsense P-GND Vup ITEST VOUT Control I²C interface VoRX Linear Post-reg +Modulator +Protections +Diagnostics 22KHz Oscill. TEN I²C Diagnostics VoTX TTX EXTM 22KHz Tone Amp. Diagn. 22KHz Tone Freq. Detector DETIN DSQOUT DSQIN VCTRL LNBH23 A-GND 4/32 LNBH23 Application information 2 Application information This IC has a built-in DC-DC step-up converter with integrated NMOS that, from a single source from 8 V to 15 V, generates the voltages (VUP) that let the linear post-regulator to work at a minimum dissipated power of 0.375 W Typ. @ 500 mA load (the linear postregulator drop voltage is internally kept at VUP-VORX=0.75 V typ.). An under voltage lockout circuit will disable the whole circuit when the supplied VCC drops below a fixed threshold (6.7 V typically). Note: In this document the output voltage (VO) is intended as the voltage present at the linear post-regulator output (VORX pin). 2.1 DiSEqCTM data encoding and decoding The new internal 22 kHz tone generator (patent pending) is factory trimmed in accordance to the standards, and can be selected by I²C interface TTX bit (or TTX pin) and activated by a dedicated pin (DSQIN) that allows immediate DiSEqCTM data encoding, or through TEN I²C bit in case the 22 kHz presence is requested in continuous mode. In stand-by condition (EN bit LOW) The TTX function must be disabled setting TTX to LOW. 2.2 DiSEqCTM 2.0 implementation The built-in 22 kHz tone detector completes the fully bi-directional DiSEqCTM 2.0 interfacing (see Note: 1). It’s input pin (DETIN) must be AC coupled to the DiSEqCTM BUS, and extracted PWK data are available on the DSQOUT pin. To comply to the bi-directional DiSEqCTM 2.0 bus hardware requirements an output R-L filter is needed. The LNBH23 is provided with two output pins, one for the dc voltage output (VoRX) and one for the 22 kHz tone transmission (VoTX). The VoTX must be activated only during the tone transmission while the VoRX provides the 13/18 V output voltage. This allows the 22 kHz Tone to pass without any losses due to the R-L filter impedance (see Figure 4 typ. application circuit). During the 22 kHz transmission, in DiSEqCTM 2.0 applications, activated by DSQIN pin or by the TEN bit, the VoTX pin must be preventively set ON by the TTX function. This can be controlled both through the TTX pin and by I²C bit. As soon as the tone transmission is expired, the VoTX must be disabled by setting the TTX to LOW to set the device in the 22 kHz receiving mode. The 13/18 V power supply is always provided to the LNB from the VoRX pin through the R-L filter. 2.3 DiSEqCTM 1.X implementation When the LNBH23 is used in DiSEqCTM 1.x applications the R-L filter is always needed for the proper operation of the new 22 kHz tone generator (patent pending. See application circuit). Also in this case, the TTX function must be preventively enabled before to start the 22 kHz data transmission and disabled as soon as the data transmission has been expired. The tone can be activated both with the DSQIN pin or the TEN I²C bit. The DSQIN internal circuit activates the 22 kHz tone on the VoTX output with 0.5 cycles ±25 µs delay from the TTL signal presence on the DSQIN pin, and it stops with 1 cycles ±25 µs delay after the TTL signal is expired. 5/32 Application information LNBH23 2.4 Data encoding by external tone generator (EXTM) In order to improve design flexibility an external tone input pin is available (EXTM). The EXTM is a logic input pin which activates the 22 kHz tone output, on the VoTX pin, by using the LNBH23 integrated tone generator (similarly to the DSQIN pin function). As a matter of fact, the output tone waveform characteristics will be always internally controlled by the LNBH23 tone generator and the EXTM signal will be used just as a timing control of the DiSEqC tone data encoding on the VoTX output. A TTL compatible 22 kHz signal is required for the proper control of the EXTM pin function. Before to send the TTL signal on the EXTM pin, the VoTX tone generator must be previously enabled through the TTX function (TTX pin or TTX bit set HIGH). As soon as the EXTM internal circuit detects the 22 kHz TTL signal code, it activates the 22 kHz tone on the VoTX output with 1.5 cycles ±25 µs delay from the TTL signal presence on the EXTM pin, and it stops with 2 cycles ±25 µs delay after the TTL signal is expired. Refer to the below Figure 2 Figure 2. EXTM waveform 2.5 I²C interface The main functions of the IC are controlled via I²C bus by writing 8 bits on the system register (SR 8 bits in write mode). On the same register there are 8 bits that can be read back (SR 8 bits in read mode) to provide 8 diagnostic functions: five bits will report the diagnostic status of five internal monitoring functions (IMON, VMON, TMON, OTF, OLF) while, three will report the last output voltage register status (EN, VSEL, LLC) received by the IC (see below diagnostic functions section). 2.6 Output voltage selection When the IC sections are in stand-by mode (EN bit LOW), the power blocks are disabled. When the regulator blocks are active (EN bit HIGH), the output can be logic controlled to be 13 or 18 V by means of the VSEL bit (Voltage SELect) for remote controlling of non-DiSEqC LNBs. Additionally, the LNBH23 is provided with the LLC I²C bit that increases the selected voltage value by +1 V to compensate the excess of voltage drop along the coaxial cable. The LNBH23 is also compliant to the USA LNB power supply standards. In order to allow fast transition of the output voltage from 18 V to 13 V and vice versa, the LNBH23 is provided with the VCTRL TTL pin which keeps the output to 13 V when it is set LOW and to 18 V when it is set HIGH or floating. VSEL and, if required, LLC bits must be set HIGH before to use the VCTRL pin to switch the output voltage level. If VCTRL=1 or floating VoRX=18.5 V (or 19.5 V if LLC=1). With VCTRL=0 VoRX=13.4 V (LLC= either 0 or 1). Be aware that the VCTRL pin controls only the linear regulator VoRX stage while the step-up VUP voltage is controlled only through the VSEL and LLC I²C bits, that is: Even if VCTRL=0 (keeping 6/32 LNBH23 Application information VoRX=13.4 V) you will have VUP=19.25 V typ when VSEL=1 and 20.25 V with VSEL=LLC=1. This means that VCTRL=0 must be used only for short time to avoid the higher power dissipation. In stand-by condition (EN bit LOW) all the I²C bits and the TTX pin must be set LOW (if the TTX pin is not used it can be left floating but the TTX bit must be set LOW during the stand-by condition). 2.7 Diagnostic and protection functions The LNBH23 has 5 diagnostic internal functions provided via I²C bus by reading 5 bits on the system register (SR bits in read mode). All the diagnostic bits are, in normal operation (no failure detected), set to LOW. Two diagnostic bits are dedicated to the over-temperature and over-load protections status (OTF and OLF) while, the remaining 3 bits, are dedicated to the output voltage level (VMON), 22 kHz tone (TMON) and to the minimum load current diagnostic function (IMON). 2.8 Output voltage diagnostic - VMON When VSEL=0 or 1 and LLC=0, the output voltage pin (VoRX) is internally monitored and, as long as the output voltage level is below the guaranteed limits the VMON I²C bit is set to "1". The output voltage diagnostic is valid only with LLC=0. Any VMON information with LLC=1 must be disregarded by the MCU. 2.9 22 kHz tone diagnostic - TMON The 22 kHz tone can be internally detected and monitored if DETIN pin is connected to the LNB output bus (see typical application circuits Figure 4) through a decoupling capacitor. The tone diagnostic function is provided with the TMON I²C bit. If the 22 kHz Tone amplitude and/or the tone frequency is out of the guaranteed limits (see TMON limits in the electrical characteristics Table 13), the TMON I²C bit is set to "1". 2.10 Minimum output current diagnostic - IMON In order to detect the output load absence (no LNB connected on the bus or cable not connected to the IRD) the LNBH23 is provided with a minimum output current flag by the IMON I²C bit in read mode, which is set to "1" if the output current is lower than 12 mA typically with ITEST=1 and 6 mA with ITEST=0. The minimum current diagnostic function (IMON) is always active. In order to make it work even in a multi-IRD configuration (multiswitch), where the supply current could be sunk only from the higher supply voltage connected to the multi-switch box, the LNBH23 is provided with the AUX I²C bit which can be set HIGH, in write mode by the MCU, before to read the IMON I²C bit status, to force the LNBH23 output voltage as the highest voltage on the bus (22 V typ.) during the minimum current diagnostic phase. When the AUX bit is set to HIGH, the VoRX is set to 22 V (typ.) and VUP is set to 22.75 V (VUP = VoRX+0.75 V typ.) independently of the VSEL/LLC bits status. If the AUX function is used to force the VoRX to 22 V, it is recommended to set the AUX bit to LOW as soon as the minimum current test phase is expired, so that the VoRX voltage will be controlled again as per the VSEL/LLC bits status. In order to avoid false triggering, the IMON function must be used only with the 22 kHz tone transmission deactivated (TEN=TTX=0 and DSQIN=LOW), otherwise the IMON bit could be erroneously set to 0 even if the output current is below the minimum current thresholds (6 mA or 12 mA). Any TMON information with 22 kHz tone enabled must be disregarded by the MCU. 7/32 Application information LNBH23 2.11 Output current limit selection The linear regulator current limit threshold can be set by an external resistor connected to ISEL pin. The resistor value defines the output current limit by the equation: IMAX[A] = 10000/RSEL where RSEL is the resistor connected between ISEL and GND. The highest selectable current limit threshold is 1.0 A typ with RSEL=10 kΩ The above equation defines the typical . threshold value. 2.12 Over-current and short circuit protection and diagnostic In order to reduce the total power dissipation during an overload or a short circuit condition, the device is provided with a dynamic short circuit protection. It is possible to set the short circuit current protection either statically (simple current clamp) or dynamically by the PCL bit of the I²C SR. When the PCL (Pulsed Current Limiting) bit is set lo LOW, the over current protection circuit works dynamically: as soon as an overload is detected, the output current is provided for 90 ms (typ.), after that the output is set in shut-down for a time TOFF of typically 900 ms. Simultaneously the diagnostic OLF I²C bit of the system register is set to "1". After this time has elapsed, the output is resumed for a time TON=1/10 TOFF = 90 ms (typ.). At the end of TON, if the overload is still detected, the protection circuit will cycle again through TOFF and TON. At the end of a full TON in which no overload is detected, normal operation is resumed and the OLF diagnostic bit is reset to LOW. Typical TON +TOFF time is 990 ms and an internal timer determines it. This dynamic operation can greatly reduce the power dissipation in short circuit condition, still ensuring excellent power-on start-up in most conditions. However, there could be some cases in which a highly capacitive load on the output may cause a difficult start-up when the dynamic protection is chosen. This can be solved by initiating any power start-up in static mode (PCL=1) and, then, switching to the dynamic mode (PCL=0) after a chosen amount of time depending on the output capacitance. Also in static mode, the diagnostic OLF bit goes to "1" when the current clamp limit is reached and returns LOW when the overload condition is cleared. 2.13 Thermal protection and diagnostic The LNBH23 is also protected against overheating: when the junction temperature exceeds 150 °C (typ.), the step-up converter and the liner regulator are shut-off, and the diagnostic OTF SR bit is set to "1". Normal operation is resumed and the OTF bit is reset to LOW when the junction is cooled down to 135 °C (typ.). Note: 1 External components are needed to comply to bidirectional DiSEqCTM bus hardware requirements. Full compliance of the whole application with DiSEqCTM specifications is not implied by the use of this IC. NOTICE: DiSEqCTM is a trademark of EUTELSAT. I²C is trademark of Philips Semiconductors. 8/32 LNBH23 Pin configuration 3 Figure 3. Pin configuration Pin connections (top view for PowerSSO-24, bottom view for QFN32) DETIN VCTRL NC NC NC LX P-GND SDA SCL ADDR DSQOUT DSQIN 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 NC ISEL VUP NC VoTX VoRX A-GND VCC VCC-L BYP TTX EXTM PowerSSO-24 QFN32 (5x5 mm) Table 2. Pin description Symbol VCC VCC–L LX VUP Name Supply input Supply input N-MOS drain Step-Up voltage Function 8 to 15 V IC DC-DC power supply. 8 to 15 V analog power supply. Integrated N-Channel power MOSFET drain. Input of the linear post-regulator. The voltage on this pin is monitored by the internal step-up controller to keep a minimum dropout across the linear pass transistor. Output of the integrated low drop linear post-regulator. See truth tables for voltage selections and description. Pin n° for Pin n° for QFN32 PSSO-24 19 18 4 27 17 16 6 22 21 22 6 9 19 20 8 9 VoRX VoTX SDA SCL LDO output port Output port for 22 TX Output to the LNB. See truth tables for selection. kHz tone TX Serial data Serial clock Bi-directional data from/to I²C bus. Clock from I²C bus. This pin will accept the DiSEqC code from the main microcontroller. The LNBH23 will use this code to modulate the internally generated 22 kHz carrier. Set to ground if not used. This pin can be used, as well as the TTX I²C bit of the system register, to control the TTX function enable before to start the 22 kHz tone transmission. Set floating or to GND if not used. 22 kHz tone decoder Input, must be AC coupled to the DiSEqC 2.0 bus. 9/32 12 12 DSQIN DiSEqC input 14 14 TTX TTX enable Tone decoder input 29 1 DETIN Pin configuration Table 2. Pin description (continued) Symbol Name Function LNBH23 Pin n° for Pin n° for QFN32 PSSO-24 11 11 DSQOUT DiSEqC output External modulation By-pass capacitor Open drain output of the tone decoder to the main microcontroller for DiSEqC 2.0 data decoding. It is LOW when tone is detected on DETIN pin. External modulation logic input pin which activates the 22 kHz tone output on the VoTX pin. Set to ground if not used. Needed for internal pre-regulator filtering. The BYP pin is intended only to connect an external ceramic capacitor. Any connection of this pin to external current or voltage sources may cause permanent damage to the device. Two I²C bus addresses available by setting the Address pin level voltage. See address pin characteristics Table 10 13 13 EXTM 15 15 BYP 10 10 ADDR Address setting 28 23 ISEL The resistor “RSEL” connected between ISEL and GND Current selection defines the linear regulator current limit threshold by the equation: Imax(typ.)=10000/ RSEL. 13V-18V linear regulator VoRX switch control. To be used only with VSEL=1. If VCTRL=1 or floating VoRX=18.5V (or 19.5V if LLC=1). If VCTRL=0 than VoRX=13.4V (LLC=either 0 or 1). Leave floating if not used. Do not connect to ground if not used. DC-DC converter power ground. To be connected with power grounds and to the ground layer through vias to dissipate the heat. Analog circuits ground. 30 2 VCTRL Output voltage control 5 Epad 20 1, 2, 3, 7, 8, 16, 17, 23, 24, 25, 26, 31, 32 7 Epad 18 P-GND Epad A-GND Power ground Exposed pad Analog ground 3, 4, 5, 21, 24 N.C. Not connected Not internally connected pins. 10/32 LNBH23 Maximum ratings 4 Table 3. Symbol Maximum ratings Absolute maximum ratings Parameter Value -0.3 to 16 -0.3 to 24 Internally Limited -0.3 to 25 -0.3 to 25 -0.3 to 7 -0.3 to 24 2 -0.3 to 7 -0.3 to 4.6 -0.3 to 4.6 -50 to 150 -25 to 125 2 4 0.6 kV Unit V V mA V V V V VPP V V V °C °C VCC-L, VCC DC power supply input voltage pins VUP IO VoRX VoTX VI LX VDETIN VOH VBYP ISEL TSTG TJ DC input voltage Output current DC output pin voltage Tone output pin voltage Logic input voltage (TTX, SDA, SCL, DSQIN, EXTM, VCTRL, ADDR) LX input voltage Detector input signal amplitude Logic high output voltage (DSQOUT) Internal reference pin voltage (Note 2) Current selection pin voltage Storage temperature range Operating junction temperature range ESD rating with human body model (HBM) for all pins unless 6,19,20, ESD ESD rating with Human Body Model (HBM) for pins 19, 20 ESD rating with Human Body Model (HBM) for pin 6 Note: 1 Absolute maximum ratings are those values beyond which damage to the device may occur. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. The BYP pin is intended only to connect an external ceramic capacitor. Any connection of this pin to external current or voltage sources may cause permanent damage to the device. Thermal data Parameter Thermal resistance junction-case Thermal resistance junction-ambient (PowerSSO24) with device soldered on 2s2p PC Board QFN32 2 35 PowerSSO-24 2 30 Unit °C/W °C/W 2 Table 4. Symbol RthJC RthJA 11/32 Application circuit LNBH23 5 Figure 4. Application circuit Typical application circuit D3 1N4001 Ferrite Ferrite Bead Filter L2 suggested part number: MURATA BL01RN1-A62 Panasonic EXCELS A35 L2 Vup C5 100µF C3 100µF C6 470nF C9 10µF VoTX D4 BAT43 C13 10nF Ceramic C4 470nF D1 Ceramic STPS130A LNBH23 LX VoRX Vcc C10 220nF Ceramic L3 270µH to LNB L1=22µH D2 BAT43 Vin 12V R1 100Ohm R4 15 Ohm Vcc-L C1 100µF C2 100nF C7 100nF Ceramic DETIN Byp EXTM R3 10kOhm C11 220nF Ceramic C8 220nF Ceramic C12 10nF Ceramic I C Bus Tone Enable TTX Enable 2 { SDA SCL DSQIN TTX P-GND A-GND ADDR DSQOUT VCTRL ISEL 13/18 R2 (RSEL) 11kOhm Table 5. Bill of material Notes 1/4W Resistors. Refer to the typical application circuit for the relative values 1/4W Resistors. Refer to the typical application circuit for the relative values 25V Electrolytic Capacitor, 100µF or higher is suitable. 10µF, >35V Electrolytic Capacitor 100µF, >25V Electrolytic Capacitor, ESR in the 150mΩ to 350mΩ range Component R1, R4 R2 (RSEL), R3 C1 C9 C3, C5 C2, C4, C6, C7, C8, C10, >25V Ceramic Capacitors. Refer to the Typ. Appl. Circuit for the relative values C11, C12, C13 STPS130A or any similar schottky diode with VRRM>25V and IF(AV) higher than: D1 IF ( AV) > IOUT_MAX x VUP_MAX VIN MIN D2, D4 D3 BAT43, 1N5818, or any schottky diode with IF(AV)>0.2A, VRRM>25V, VFIpeak where Ipeak is the boost converter peak current: L1 L2 L3 FERRITE BEAD, Panasonic-EXCELS A35 or Murata-BL01RN1-A62 or Taiyo-YudenBKP1608HS600 or equivalent with similar or higher impedance and current rating higher than 2A 220µH-270µH Inductor with current rating higher than rated output current 13/32 I²C bus interface LNBH23 6 I²C bus interface Data transmission from main MCU to the LNBH23 and vice versa takes place through the 2 wires I²C bus Interface, consisting of the 2 lines SDA and SCL (pull-up resistors to positive supply voltage must be externally connected). 6.1 Data validity As shown in Figure 5, the data on the SDA line must be stable during the high semi-period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. 6.2 Start and stop condition As shown in Figure 6 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. A STOP condition must be sent before each START condition. 6.3 Byte format Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. 6.4 Acknowledge The master (MCU) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see Figure 7). The peripheral (LNBH23) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The peripheral which has been addressed has to generate acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. The LNBH23 won't generate acknowledge if the VCC supply is below the Under-voltage Lockout threshold (6.7 V typ.). 6.5 Transmission without acknowledge Avoiding to detect the acknowledges of the LNBH23, the MCU can use a simpler transmission: simply it waits one clock cycle without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking and decreases the noise immunity. 14/32 LNBH23 I²C bus interface Figure 5. Data validity on the I²C bus Figure 6. Timing diagram of I²C bus Figure 7. Acknowledge on the I²C bus 15/32 LNBH23 software description LNBH23 7 7.1 LNBH23 software description Interface protocol The interface protocol comprises: ● ● ● ● A start condition (S) A chip address byte (the LSB bit determines read(=1)/write(=0) transmission) A sequence of data (1 byte + acknowledge) A stop condition (P) Chip address Data LSB 0 1 0 1 X R/W ACK MSB LSB ACK P MSB S 0 0 ACK = Acknowledge S = Start P = Stop R/W = 1/0, Read/Write bit X = 0/1, two selectable addresses available through ADDR pin (see Address pin characteristics Table 10) 7.2 Mode Write Read System register (SR, 1 byte) MSB PCL IMON TTX VMON TEN TMON LLC LLC VSEL VSEL EN EN ITEST OTF LSB AUX OLF Write = control bits functions in write mode Read= diagnostic bits in read mode. All bits reset to 0 at power On 16/32 LNBH23 LNBH23 software description 7.3 Transmitted data (I²C bus write mode) When the R/W bit in the chip address is set to 0, the main MCU can write on the system register (SR) of the LNBH23 via I²C bus. All and 8 bits are available and can be written by the MCU to control the device functions as per the below truth table Truth table TEN LLC 0 0 1 1 X 0 1 0 1 1 VSEL 0 1 0 1 X EN 1 1 1 1 1 1 1 1 1 1 1 X X X X X 1 1 0 0 1 X X X ITEST AUX 0 0 0 0 1 Function VoRX= 13.4V, VUP=14.15V, (VUP-VoRX=0.75V) VoRX= 18.5V, VUP=19.25V, (VUP-VoRX=0.75V) VoRX= 14.4V, VUP=15.15V, (VUP-VoRX=0.75V) VoRX= 19.5V, VUP=20.25V, (VUP-VoRX=0.75V) VoRX= 22V, VUP=22.75V, (VUP-VoRX=0.75V) 22 kHz controlled by DSQIN pin (only if TTX=1) 22 kHz tone output is always activated VoRX output is ON, VoTX Tone generator output is OFF VoRX output is ON, VoTX Tone generator output is ON Pulsed (Dynamic) current limiting is selected Static current limiting is selected Minimum output current diagnostic threshold = 6mA typ. Minimum output current diagnostic threshold = 12mA typ. Power block disabled Table 6. PCL TTX 0 0 0 0 0 1 X X X X X = don't care All values are typical unless otherwise specified Valid with TTX pin floating or to GND 7.4 Diagnostic received data (I²C read mode) LNBH23 can provide to the MCU Master a copy of the diagnostic system register information via I²C bus in read mode. The read mode is master activated by sending the chip address with R/W bit set to 1. At the following master generated clocks bits, LNBH23 issues a byte on the SDA data bus line (MSB transmitted first). At the ninth clock bit the master can: ● ● Acknowledge the reception, starting in this way the transmission of another byte from the LNBH23 No acknowledge, stopping the read mode communication Three bits of the register are read back as a copy of the corresponding write output voltage register status (LLC, VSEL, EN), while, the other five bits convey diagnostic information about the over-temperature (OTF), output voltage level (VMON), output over-load (OLF), Minimum output current presence (IMON) and 22 kHz tone (TMON). In normal operation the diagnostic bits are set to zero, while, if a failure is occurring, the corresponding bit is set to one. At start-up all the bits are reset to zero. 17/32 LNBH23 software description Table 7. IMON LNBH23 Register VMON TMON LLC VSEL EN OTF 0 These bits are read exactly the same as they were left after last write operation 1 0 1 OLF Function TJ < 135°C, normal operation (1) TJ > 150°C, power blocks disabled (1) IO < IOMAX, normal operation IO > IOMAX, Overload Protection triggered These bits are set to 1 if the relative parameter is out of the specification limits. 0/1 (2) 0/1 (3) 0/1 1. Values are typical unless otherwise specified 2. IMON information must be disregarded if 22 kHz TONE output is enabled 3. VMON information must be disregarded if LLC=1 (valid only if LLC=0) 7.5 Power-ON I²C interface reset I²C interface built in LNBH23 is automatically reset at power-on. As long as the VCC stays below the undervoltage lockout (UVL) threshold (6.7 V), the interface does not respond to any I²C command and the system register (SR) is initialized to all zeroes, thus keeping the power blocks disabled. Once the VCC rises above 7.3 V typ. The I²C interface becomes operative and the SR can be configured by the main MCU. This is due to 500 mV of hysteresis provided in the UVL threshold to avoid false retriggering of the power-on reset circuit. 7.6 Address pin It is possible to select two I²C interface addresses by means of ADDR pin. This pin is TTL compatible and can be set as per hereafter address pin characteristics Table 10. 7.7 DiSEqCTM implementation LNBH23 helps system designer to implement bi-directional DiSEqC 2.0 protocol by allowing an easy PWK modulation/demodulation of the 22 kHz carrier. Between the LNBH23 and the main MCU the PWK data is exchanged using logic levels that are compatible with both 3.3 V and 5 V MCU. This data exchange is made through two dedicated pins, DSQIN and DSQOUT, in order to maintain the timing relationships between the PWK data and the PWK modulation as accurate as possible. These two pins should be directly connected to two I/O pins of the MCU, thus leaving to the firmware the task of encoding and decoding the PWK data in accordance to the DiSEqC protocol. Full compliance of the system to the specification is thus not implied by the bare use of the LNBH23. The system designer should also take in consideration the bus hardware requirements; that can be simply accomplished by the R-L termination connected between VoRX and VoTX pins of LNBH23, as shown in the typical application circuit in Figure 4. To avoid any losses due to the R-L impedance during the tone transmission, LNBH23 has dedicated Tone output (VoTX) that is connected after the filter and must be enabled by setting the TTX function to HIGH only during the tone transmission (see DiSEqC 2.0 operation implementation in section 2.2 and 2.3). Also unidirectional DiSEqC 1.x and nonDiSEqC systems need this termination connected through a bypass capacitor and after a RL filter with 15 Ω in parallel with a 220 µH-270 µH inductor but, there is no need of Tone Decoding, thus DETIN and DSQOUT pins can be left connected to GND. 18/32 LNBH23 Electrical characteristics 8 Table 8. Electrical characteristics Electrical characteristics (Refer to the typical application circuit, TJ = 0 to 85 °C, EN=1, , VSEL=LLC=TEN=PCL=ITEST=TTX=AUX=0, RSEL = 11 kΩ DSQIN = LOW, VI = 12 V, IO = 50 mA, unless otherwise stated. Typical values are referred to TJ = 25 °C. VO = VoRX pin voltage. See software description section for I²C access to the system register) Parameter Supply voltage Test conditions IO=750mA, VSEL=LLC=1 IO=0 II Supply current EN=TEN=TTX=1, IO=0 EN=0 AUX=1; IO=50mA LLC=0 VO Output voltage VSEL=1 IO=750mA LLC=1 LLC=0 VSEL=0 IO=750mA LLC=1 VSEL=0 VO VO Line regulation Load regulation 13/18V Rise and Fall transition time by VCTRL pin Output current limiting Output short circuit current Dynamic overload protection OFF time Dynamic overload protection ON time Tone frequency Tone amplitude Tone duty cycle Tone rise or fall time EXTM frequency DC-DC converter efficiency DC-DC converter switching frequency VI=8 to 15V VSEL=1 17.8 18.8 12.8 13.8 Min. 8 Typ. 12 7 20 2 22 18.5 19.5 13.4 14.4 5 5 19.2 20.2 14 15 40 mV 60 200 575 750 300 1000 900 ms TON FTONE ATONE DTONE tr, tf FEXTM PCL=0, Output shorted DSQIN=HIGH or TEN=1, TTX=1 DSQIN=HIGH or TEN=1, TTX=1 IO from 0 to750mA CO from 0 to 750nF DSQIN=HIGH or TEN=1, TTX=1 DSQIN=HIGH or TEN=1, TTX=1 VEXTM-H =3.3V, VEXTM-L =0V, IO=750mA (1) Symbol VI Max. 15 15 40 Unit V mA V VSEL=0 or 1, IO from 50 to750mA VSEL=LLC=1, VCTRL from LOW to HIGH and vice versa, IO from 6 to 450mA, CO from 10 to 330nF RSEL=11kΩ RSEL= 22kΩ VSEL=0/1, AUX=0/1 PCL=0, Output shorted mV µs 13/18 TR - T F IMAX ISC TOFF 1000 mA 600 mA TOFF/10 20 0.4 43 5 20 22 0.650 50 8 22 93 220 24 0.9 57 15 24 kHz VPP % µs kHz % kHz EffDC-DC FSW 19/32 Electrical characteristics Table 8. LNBH23 Electrical characteristics (continued) (Refer to the typical application circuit, TJ = 0 to 85 , °C, EN=1, VSEL=LLC=TEN=PCL=ITEST=TTX=AUX=0, RSEL = 11 kΩ DSQIN = LOW, VI = 12 V, IO = 50 mA, unless otherwise stated. Typical values are referred to TJ = 25 °C. VO = VoRX pin voltage. See software description section for I²C access to the system register) Parameter Tone detector frequency capture range Test conditions 0.4VPP sine wave(2) Min. 19 0.3 150 DETIN Tone present, IOL=2mA 0.3 0.5 10 0.8 2 15 -6 150 15 -15 Typ. 22 Max. 25 1.5 Unit kHz VPP kΩ V µA V V µA mA °C °C Symbol FDETIN VDETIN ZDETIN VOL IOZ VIL VIH IIH IOBK TSHDN Tone detector input amplitude Sine wave signal, 22 kHz Tone detector input impedance DSQOUT pin logic LOW DSQOUT pin leakage current DETIN Tone absent, VOH=6V DSQIN,TTX,13/18, EXTM pin logic Low DSQIN,TTX,13/18, EXTM pin logic High DSQIN,TTX,13/18, EXTM pin VIH=5V input current Output backward current Thermal shut-down threshold Thermal shut-down hysteresis EN=0, VOBK=21V ΔTSHDN 1. External signal frequency range in which the EXTM function is guaranteed. 2. Frequency range in which the DETIN function is guaranteed. The VPP level is intended on the LNB bus (before the C12 capacitor. See Figure 4) Table 9. Symbol VIL VIH II VOL fMAX I²C electrical characteristics (TJ from 0 to 85 °C, VI = 12 V) Parameter LOW Level input voltage HIGH Level input voltage Input current Low level output voltage Maximum clock frequency SDA, SCL SDA, SCL SDA, SCL, VI = 0.4 to 4.5V SDA (open drain), IOL = 6mA SCL 400 2 -10 10 0.6 Test conditions Min. Typ. Max. 0.8 Unit V V µA V kHz Table 10. Symbol VADDR-1 VADDR-2 Address pin characteristics (TJ from 0 to 85 °C, VI = 12 V) Parameter Test condition Min. 0 2 Typ. Max. 0.8 5 Unit V V "0001010(R/W)" Address pin R/W bit determines the transmission voltage range mode: read (R/W=1) write (R/W=0) "0001011(RW)" Address pin voltage range R/W bit determines the transmission mode: read (R/W=1) write (R/W=0) 20/32 LNBH23 Electrical characteristics Table 11. Output voltage diagnostic (VMON bit) characteristics (Refer to the typical application circuit, TJ from 0 to 85 °C, EN=1, VSEL=LLC=TEN=PCL=ITEST=TTX=AUX=0, RSEL=11 kΩ , DSQIN=LOW, VI = 12 V, IO = 50 mA, unless otherwise stated. Typical values are referred to TJ = 25 °C. VO=VoRX pin voltage. See software description section for I²C access to the system register) Symbol VTH-L VTH-L Parameter Diagnostic low threshold at VO=13.4V Diagnostic low threshold at VO=18.5V Test condition EN=1, VSEL=0 LLC=0 EN=VSEL=1 LLC=0 Min. 85 84 Typ. 90 90 Max. 95 96 Unit % % Note: If the output voltage is lower than the min. value the VMON I²C bit is set to 1. When VSEL=0: If VMON=0 then VoRX>85% of VoRX typical; If VMON=1 then VoRX84% of VoRX typical; If VMON=1 then VoRX