LSM6DSO32
iNEMO inertial module:
always-on 3D accelerometer and 3D gyroscope
Datasheet - production data
Description
LGA-14L
(2.5 x 3 x 0.83 mm) typ.
Features
Power consumption: 0.55 mA in combo highperformance mode
“Always-on" experience with low power
consumption for both accelerometer and gyroscope
Smart FIFO up to 9 kbytes
±4/±8/±16/±32 g full scale
±125/±250/±500/±1000/±2000 dps full scale
Analog supply voltage: 1.71 V to 3.6 V
Independent IO supply (1.62 V)
Compact footprint: 2.5 mm x 3 mm x 0.83 mm
SPI / I²C & MIPI I3CSM serial interface with main
processor data synchronization
Advanced pedometer, step detector and step
counter
Significant Motion Detection, Tilt detection
Standard interrupts: free-fall, wakeup, 6D/4D
orientation, click and double-click
Programmable finite state machine: accelerometer,
gyroscope and external sensors
Embedded temperature sensor
ECOPACK, RoHS and “Green” compliant
The LSM6DSO32 is a system-in-package featuring a
3D digital accelerometer and 3D digital gyroscope
boosting power performance to 0.55 mA in highperformance mode and enabling always-on low-power
features for an optimal motion experience for the
consumer.
The LSM6DSO32 supports main OS requirements,
offering real, virtual and batch sensors with 9 kbytes for
dynamic data batching. ST’s family of MEMS sensor
modules leverages the robust and mature
manufacturing processes already used for the
production of micromachined accelerometers and
gyroscopes. The various sensing elements are
manufactured using specialized micromachining
processes, while the IC interfaces are developed using
CMOS technology that allows the design of a dedicated
circuit which is trimmed to better match the
characteristics of the sensing element.
The LSM6DSO32 has a full-scale acceleration range of
±4/±8/±16±32 g and an angular rate range of
±125/±250/±500/±1000/±2000 dps.
High robustness to mechanical shock makes the
LSM6DSO32 the preferred choice of system designers
for the creation and manufacturing of reliable products.
The LSM6DSO32 is available in a plastic land grid
array (LGA) package.
Table 1. Device summary
Applications
Part number
Temp.
range [°C]
LSM6DSO32
-40 to +85
LSM6DSO32TR
-40 to +85
Wearables, smart watches, and sports equipment
Motion tracking and gesture detection
Hard fall detection
Sensor hub
Navigation
IoT and connected devices
Smart power saving for handheld devices
March 2020
This is information on a product in full production.
DocID032891 Rev 1
Package
LGA-14L
(2.5x3x0.83 mm)
Packing
Tray
Tape &
Reel
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Contents
LSM6DSO32
Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2
Embedded low-power features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3
2.1
Tilt detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2
Significant Motion Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3
Finite State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1
4
5
Module specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.1
Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.3
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.4
Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 30
SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.4.2
I²C - inter-IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.6
Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.6.1
Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.6.2
Zero-g and zero-rate level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.2
2/153
4.4.1
4.5
5.1
6
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
I²C/SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.1.1
I²C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.1.2
SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
MIPI I3CSM interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.2.1
MIPI I3CSM slave interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.2.2
MIPI I3CSM CCC supported commands . . . . . . . . . . . . . . . . . . . . . . . . 41
5.3
I²C/MIPI I3CSM coexistence in LSM6DSO32 . . . . . . . . . . . . . . . . . . . . . . 43
5.4
Master I²C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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6.1
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.2
Accelerometer power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.2.1
6.3
Gyroscope power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.4
Block diagram of filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.5
7
Accelerometer ultra-low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.4.1
Block diagrams of the accelerometer filters . . . . . . . . . . . . . . . . . . . . . . 46
6.4.2
Block diagrams of the gyroscope filters . . . . . . . . . . . . . . . . . . . . . . . . . 48
FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.5.1
Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.5.2
FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.5.3
Continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.5.4
Continuous-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.5.5
Bypass-to-Continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.5.6
Bypass-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.5.7
FIFO reading procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
7.1
LSM6DSO32 electrical connections in Mode 1 . . . . . . . . . . . . . . . . . . . . 53
7.2
LSM6DSO32 electrical connections in Mode 2 . . . . . . . . . . . . . . . . . . . . 54
8
Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
9
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.1
FUNC_CFG_ACCESS (01h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.2
PIN_CTRL (02h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.3
FIFO_CTRL1 (07h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.4
FIFO_CTRL2 (08h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.5
FIFO_CTRL3 (09h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.6
FIFO_CTRL4 (0Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
9.7
COUNTER_BDR_REG1 (0Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9.8
COUNTER_BDR_REG2 (0Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9.9
INT1_CTRL (0Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
9.10
INT2_CTRL (0Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
9.11
WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
9.12
CTRL1_XL (10h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
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9.13
CTRL2_G (11h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
9.14
CTRL3_C (12h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
9.15
CTRL4_C (13h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
9.16
CTRL5_C (14h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
9.17
CTRL6_C (15h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
9.18
CTRL7_G (16h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
9.19
CTRL8_XL (17h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
9.20
CTRL9_XL (18h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
9.21
CTRL10_C (19h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
9.22
ALL_INT_SRC (1Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
9.23
WAKE_UP_SRC (1Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
9.24
TAP_SRC (1Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
9.25
D6D_SRC (1Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
9.26
STATUS_REG (1Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
9.27
OUT_TEMP_L (20h), OUT_TEMP_H (21h) . . . . . . . . . . . . . . . . . . . . . . . 79
9.28
OUTX_L_G (22h) and OUTX_H_G (23h) . . . . . . . . . . . . . . . . . . . . . . . . 79
9.29
OUTY_L_G (24h) and OUTY_H_G (25h) . . . . . . . . . . . . . . . . . . . . . . . . 80
9.30
OUTZ_L_G (26h) and OUTZ_H_G (27h) . . . . . . . . . . . . . . . . . . . . . . . . . 80
9.31
OUTX_L_A (28h) and OUTX_H_A (29h) . . . . . . . . . . . . . . . . . . . . . . . . . 80
9.32
OUTY_L_A (2Ah) and OUTY_H_A (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . 81
9.33
OUTZ_L_A (2Ch) and OUTZ_H_A (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . 81
9.34
EMB_FUNC_STATUS_MAINPAGE (35h) . . . . . . . . . . . . . . . . . . . . . . . . 82
9.35
FSM_STATUS_A_MAINPAGE (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
9.36
FSM_STATUS_B_MAINPAGE (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
9.37
STATUS_MASTER_MAINPAGE (39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
9.38
FIFO_STATUS1 (3Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
9.39
FIFO_STATUS2 (3Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
9.40
TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h),
and TIMESTAMP3 (43h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
9.41
TAP_CFG0 (56h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
9.42
TAP_CFG1 (57h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
9.43
TAP_CFG2 (58h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
9.44
TAP_THS_6D (59h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
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9.45
INT_DUR2 (5Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
9.46
WAKE_UP_THS (5Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
9.47
WAKE_UP_DUR (5Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
9.48
FREE_FALL (5Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
9.49
MD1_CFG (5Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
9.50
MD2_CFG (5Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
9.51
I3C_BUS_AVB (62h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
9.52
INTERNAL_FREQ_FINE (63h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
9.53
X_OFS_USR (73h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
9.54
Y_OFS_USR (74h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
9.55
Z_OFS_USR (75h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
9.56
FIFO_DATA_OUT_TAG (78h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
9.57
FIFO_DATA_OUT_X_L (79h) and FIFO_DATA_OUT_X_H (7Ah) . . . . . . 96
9.58
FIFO_DATA_OUT_Y_L (7Bh) and FIFO_DATA_OUT_Y_H (7Ch) . . . . . 96
9.59
FIFO_DATA_OUT_Z_L (7Dh) and FIFO_DATA_OUT_Z_H (7Eh) . . . . . . 96
10
Embedded functions register mapping . . . . . . . . . . . . . . . . . . . . . . . . . 97
11
Embedded functions register description . . . . . . . . . . . . . . . . . . . . . . 99
11.1
PAGE_SEL (02h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
11.2
EMB_FUNC_EN_A (04h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
11.3
EMB_FUNC_EN_B (05h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
11.4
PAGE_ADDRESS (08h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
11.5
PAGE_VALUE (09h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
11.6
EMB_FUNC_INT1 (0Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
11.7
FSM_INT1_A (0Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
11.8
FSM_INT1_B (0Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
11.9
EMB_FUNC_INT2 (0Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
11.10 FSM_INT2_A (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
11.11 FSM_INT2_B (10h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
11.12 EMB_FUNC_STATUS (12h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
11.13 FSM_STATUS_A (13h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
11.14 FSM_STATUS_B (14h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
11.15 PAGE_RW (17h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
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11.16 EMB_FUNC_FIFO_CFG (44h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
11.17 FSM_ENABLE_A (46h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
11.18 FSM_ENABLE_B (47h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
11.19 FSM_LONG_COUNTER_L (48h) and
FSM_LONG_COUNTER_H (49h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
11.20 FSM_LONG_COUNTER_CLEAR (4Ah) . . . . . . . . . . . . . . . . . . . . . . . . .111
11.21 FSM_OUTS1 (4Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
11.22 FSM_OUTS2 (4Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
11.23 FSM_OUTS3 (4Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
11.24 FSM_OUTS4 (4Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
11.25 FSM_OUTS5 (50h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
11.26 FSM_OUTS6 (51h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
11.27 FSM_OUTS7 (52h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
11.28 FSM_OUTS8 (53h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
11.29 FSM_OUTS9 (54h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
11.30 FSM_OUTS10 (55h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
11.31 FSM_OUTS11 (56h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
11.32 FSM_OUTS12 (57h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
11.33 FSM_OUTS13 (58h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
11.34 FSM_OUTS14 (59h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
11.35 FSM_OUTS15 (5Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
11.36 FSM_OUTS16 (5Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
11.37 EMB_FUNC_ODR_CFG_B (5Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
11.38 STEP_COUNTER_L (62h) and STEP_COUNTER_H (63h) . . . . . . . . . 120
11.39 EMB_FUNC_SRC (64h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
11.40 EMB_FUNC_INIT_A (66h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
11.41 EMB_FUNC_INIT_B (67h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
12
Embedded advanced features pages . . . . . . . . . . . . . . . . . . . . . . . . . 122
13
Embedded advanced features register description . . . . . . . . . . . . . . 125
13.1
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13.1.1
MAG_SENSITIVITY_L (BAh) and MAG_SENSITIVITY_H (BBh) . . . . 125
13.1.2
MAG_OFFX_L (C0h) and MAG_OFFX_H (C1h) . . . . . . . . . . . . . . . . . 125
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13.1.3
MAG_OFFY_L (C2h) and MAG_OFFY_H (C3h) . . . . . . . . . . . . . . . . . 126
13.1.4
MAG_OFFZ_L (C4h) and MAG_OFFZ_H (C5h) . . . . . . . . . . . . . . . . . 126
13.1.5
MAG_SI_XX_L (C6h) and MAG_SI_XX_H (C7h) . . . . . . . . . . . . . . . . 127
13.1.6
MAG_SI_XY_L (C8h) and MAG_SI_XY_H (C9h) . . . . . . . . . . . . . . . . 127
13.1.7
MAG_SI_XZ_L (CAh) and MAG_SI_XZ_H (CBh) . . . . . . . . . . . . . . . . 128
13.1.8
MAG_SI_YY_L (CCh) and MAG_SI_YY_H (CDh) . . . . . . . . . . . . . . . 128
13.1.9
MAG_SI_YZ_L (CEh) and MAG_SI_YZ_H (CFh) . . . . . . . . . . . . . . . . 129
13.1.10 MAG_SI_ZZ_L (D0h) and MAG_SI_ZZ_H (D1h) . . . . . . . . . . . . . . . . 129
13.1.11 MAG_CFG_A (D4h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
13.1.12 MAG_CFG_B (D5h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
13.2
Page 1 - Embedded advanced features registers . . . . . . . . . . . . . . . . . 131
13.2.1
FSM_LC_TIMEOUT_L (7Ah) and FSM_LC_TIMEOUT_H (7Bh) . . . . 131
13.2.2
FSM_PROGRAMS (7Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
13.2.3
FSM_START_ADD_L (7Eh) and FSM_START_ADD_H (7Fh) . . . . . . 132
13.2.4
PEDO_CMD_REG (83h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
13.2.5
PEDO_DEB_STEPS_CONF (84h) . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
13.2.6
PEDO_SC_DELTAT_L (D0h) and PEDO_SC_DELTAT_H (D1h) . . . . 133
14
Sensor hub register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
15
Sensor hub register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
15.1
SENSOR_HUB_1 (02h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
15.2
SENSOR_HUB_2 (03h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
15.3
SENSOR_HUB_3 (04h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
15.4
SENSOR_HUB_4 (05h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
15.5
SENSOR_HUB_5 (06h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
15.6
SENSOR_HUB_6 (07h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
15.7
SENSOR_HUB_7 (08h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
15.8
SENSOR_HUB_8 (09h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
15.9
SENSOR_HUB_9 (0Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
15.10 SENSOR_HUB_10 (0Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
15.11 SENSOR_HUB_11 (0Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
15.12 SENSOR_HUB_12 (0Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
15.13 SENSOR_HUB_13 (0Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
15.14 SENSOR_HUB_14 (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
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15.15 SENSOR_HUB_15 (10h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
15.16 SENSOR_HUB_16 (11h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
15.17 SENSOR_HUB_17 (12h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
15.18 SENSOR_HUB_18 (13h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
15.19 MASTER_CONFIG (14h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
15.20 SLV0_ADD (15h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
15.21 SLV0_SUBADD (16h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
15.22 SLAVE0_CONFIG (17h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
15.23 SLV1_ADD (18h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
15.24 SLV1_SUBADD (19h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
15.25 SLAVE1_CONFIG (1Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
15.26 SLV2_ADD (1Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
15.27 SLV2_SUBADD (1Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
15.28 SLAVE2_CONFIG (1Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
15.29 SLV3_ADD (1Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
15.30 SLV3_SUBADD (1Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
15.31 SLAVE3_CONFIG (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
15.32 DATAWRITE_SLV0 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
15.33 STATUS_MASTER (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
16
Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
17
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
18
8/153
17.1
LGA-14L package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
17.2
LGA-14 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
DocID032891 Rev 1
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
SPI slave timing values (in mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
I²C slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
I²C terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
SAD+Read/Write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 36
Transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 36
MIPI I3CSM CCC commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Master I²C pin details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Gyroscope LPF2 bandwidth selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Internal pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Registers address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
FUNC_CFG_ACCESS register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
FUNC_CFG_ACCESS register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
PIN_CTRL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
PIN_CTRL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
FIFO_CTRL1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
FIFO_CTRL1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
FIFO_CTRL2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
FIFO_CTRL2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
FIFO_CTRL3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
FIFO_CTRL3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
FIFO_CTRL4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
FIFO_CTRL4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
COUNTER_BDR_REG1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
COUNTER_BDR_REG1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
COUNTER_BDR_REG2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
COUNTER_BDR_REG2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
INT1_CTRL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
INT1_CTRL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
INT2_CTRL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
INT2_CTRL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
WhoAmI register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
CTRL1_XL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
CTRL1_XL register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Accelerometer ODR register setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Accelerometer full-scale selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
CTRL2_G register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
CTRL2_G register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Gyroscope ODR configuration setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
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List of tables
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
Table 100.
10/153
LSM6DSO32
CTRL3_C register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
CTRL3_C register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
CTRL4_C register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
CTRL4_C register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
CTRL5_C register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
CTRL5_C register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Angular rate sensor self-test mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Linear acceleration sensor self-test mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
CTRL6_C register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
CTRL6_C register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Trigger mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Gyroscope LPF1 bandwidth selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
CTRL7_G register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
CTRL7_G register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
CTRL8_XL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
CTRL8_XL register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Accelerometer bandwidth configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
CTRL9_XL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
CTRL9_XL register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
CTRL10_C register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
CTRL10_C register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
ALL_INT_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
ALL_INT_SRC register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
WAKE_UP_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
WAKE_UP_SRC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
TAP_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
TAP_SRC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
D6D_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
D6D_SRC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
STATUS_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
STATUS_REG register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
OUT_TEMP_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
OUT_TEMP_H register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
OUT_TEMP register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
OUTX_L_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
OUTX_H_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
OUTX_H_G register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
OUTY_L_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
OUTY_H_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
OUTY_H_G register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
OUTZ_L_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
OUTZ_H_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
OUTZ_H_G register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
OUTX_L_A register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
OUTX_H_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
OUTX_H_A register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
OUTY_L_A register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
OUTY_H_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
OUTY_H_A register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
OUTZ_L_A register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
OUTZ_H_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
OUTZ_H_A register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
DocID032891 Rev 1
LSM6DSO32
Table 101.
Table 102.
Table 103.
Table 104.
Table 105.
Table 106.
Table 107.
Table 108.
Table 109.
Table 110.
Table 111.
Table 112.
Table 113.
Table 114.
Table 115.
Table 116.
Table 117.
Table 118.
Table 119.
Table 120.
Table 121.
Table 122.
Table 123.
Table 124.
Table 125.
Table 126.
Table 127.
Table 128.
Table 129.
Table 130.
Table 131.
Table 132.
Table 133.
Table 134.
Table 135.
Table 136.
Table 137.
Table 138.
Table 139.
Table 140.
Table 141.
Table 142.
Table 143.
Table 144.
Table 145.
Table 146.
Table 147.
Table 148.
Table 149.
Table 150.
Table 151.
Table 152.
List of tables
EMB_FUNC_STATUS_MAINPAGE register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
EMB_FUNC_STATUS_MAINPAGE register description . . . . . . . . . . . . . . . . . . . . . . . . . . 82
FSM_STATUS_A_MAINPAGE register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
FSM_STATUS_A_MAINPAGE register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
FSM_STATUS_B_MAINPAGE register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
FSM_STATUS_B_MAINPAGE register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
STATUS_MASTER_MAINPAGE register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
STATUS_MASTER_MAINPAGE register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
FIFO_STATUS1 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
FIFO_STATUS1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
FIFO_STATUS2 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
FIFO_STATUS2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
TIMESTAMP output registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
TIMESTAMP output register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
TAP_CFG0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
TAP_CFG0 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
TAP_CFG1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
TAP_CFG1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
TAP priority decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
TAP_CFG2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
TAP_CFG2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
TAP_THS_6D register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
TAP_THS_6D register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Threshold for D4D/D6D function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
INT_DUR2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
INT_DUR2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
WAKE_UP_THS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
WAKE_UP_THS register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
WAKE_UP_DUR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
WAKE_UP_DUR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
FREE_FALL register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
FREE_FALL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Threshold for free-fall function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
MD1_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
MD1_CFG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
MD2_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
MD2_CFG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
I3C_BUS_AVB register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
I3C_BUS_AVB register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
INTERNAL_FREQ_FINE register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
INTERNAL_FREQ_FINE register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
X_OFS_USR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
X_OFS_USR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Y_OFS_USR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Y_OFS_USR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Z_OFS_USR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Z_OFS_USR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
FIFO_DATA_OUT_TAG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
FIFO_DATA_OUT_TAG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
FIFO tag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
FIFO_DATA_OUT_X_H and FIFO_DATA_OUT_X_L registers . . . . . . . . . . . . . . . . . . . . . 96
FIFO_DATA_OUT_X_H and FIFO_DATA_OUT_X_L register description . . . . . . . . . . . . 96
DocID032891 Rev 1
11/153
153
List of tables
Table 153.
Table 154.
Table 155.
Table 156.
Table 157.
Table 158.
Table 159.
Table 160.
Table 161.
Table 162.
Table 163.
Table 164.
Table 165.
Table 166.
Table 167.
Table 168.
Table 169.
Table 170.
Table 171.
Table 172.
Table 173.
Table 174.
Table 175.
Table 176.
Table 177.
Table 178.
Table 179.
Table 180.
Table 181.
Table 182.
Table 183.
Table 184.
Table 185.
Table 186.
Table 187.
Table 188.
Table 189.
Table 190.
Table 191.
Table 192.
Table 193.
Table 194.
Table 195.
Table 196.
Table 197.
Table 198.
Table 199.
Table 200.
Table 201.
Table 202.
Table 203.
Table 204.
12/153
LSM6DSO32
FIFO_DATA_OUT_Y_H and FIFO_DATA_OUT_Y_L registers . . . . . . . . . . . . . . . . . . . . . 96
FIFO_DATA_OUT_Y_H and FIFO_DATA_OUT_Y_L register description . . . . . . . . . . . . 96
FIFO_DATA_OUT_Z_H and FIFO_DATA_OUT_Z_L registers . . . . . . . . . . . . . . . . . . . . . 96
FIFO_DATA_OUT_Z_H and FIFO_DATA_OUT_Z_L register description. . . . . . . . . . . . . 96
Register address map - embedded functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
PAGE_SEL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
PAGE_SEL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
EMB_FUNC_EN_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
EMB_FUNC_EN_A register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
EMB_FUNC_EN_B register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
EMB_FUNC_EN_B register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
PAGE_ADDRESS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
PAGE_ADDRESS register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
PAGE_VALUE register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
PAGE_VALUE register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
EMB_FUNC_INT1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
EMB_FUNC_INT1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
FSM_INT1_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
FSM_INT1_A register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
FSM_INT1_B register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
FSM_INT1_B register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
EMB_FUNC_INT2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
EMB_FUNC_INT2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
FSM_INT2_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
FSM_INT2_A register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
FSM_INT2_B register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
FSM_INT2_B register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
EMB_FUNC_STATUS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
EMB_FUNC_STATUS register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
FSM_STATUS_A register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
FSM_STATUS_A register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
FSM_STATUS_B register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
FSM_STATUS_B register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
PAGE_RW register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
PAGE_RW register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
EMB_FUNC_FIFO_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
EMB_FUNC_FIFO_CFG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
FSM_ENABLE_A register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
FSM_ENABLE_A register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
FSM_ENABLE_B register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
FSM_ENABLE_B register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
FSM_LONG_COUNTER_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
FSM_LONG_COUNTER_L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
FSM_LONG_COUNTER_H register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
FSM_LONG_COUNTER_H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
FSM_LONG_COUNTER_CLEAR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
FSM_LONG_COUNTER_CLEAR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
FSM_OUTS1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
FSM_OUTS1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
FSM_OUTS2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
FSM_OUTS2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
FSM_OUTS3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
DocID032891 Rev 1
LSM6DSO32
Table 205.
Table 206.
Table 207.
Table 208.
Table 209.
Table 210.
Table 211.
Table 212.
Table 213.
Table 214.
Table 215.
Table 216.
Table 217.
Table 218.
Table 219.
Table 220.
Table 221.
Table 222.
Table 223.
Table 224.
Table 225.
Table 226.
Table 227.
Table 228.
Table 229.
Table 230.
Table 231.
Table 232.
Table 233.
Table 234.
Table 235.
Table 236.
Table 237.
Table 238.
Table 239.
Table 240.
Table 241.
Table 242.
Table 243.
Table 244.
Table 245.
Table 246.
Table 247.
Table 248.
Table 249.
Table 250.
Table 251.
Table 252.
Table 253.
Table 254.
Table 255.
Table 256.
List of tables
FSM_OUTS3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
FSM_OUTS4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
FSM_OUTS4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
FSM_OUTS5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
FSM_OUTS5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
FSM_OUTS6 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
FSM_OUTS6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
FSM_OUTS7 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
FSM_OUTS7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
FSM_OUTS8 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
FSM_OUTS8 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
FSM_OUTS9 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
FSM_OUTS9 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
FSM_OUTS10 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
FSM_OUTS10 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
FSM_OUTS11 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
FSM_OUTS11 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
FSM_OUTS12 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
FSM_OUTS12 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
FSM_OUTS13 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
FSM_OUTS13 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
FSM_OUTS14 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
FSM_OUTS14 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
FSM_OUTS15 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
FSM_OUTS15 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
FSM_OUTS16 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
FSM_OUTS16 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
EMB_FUNC_ODR_CFG_B register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
EMB_FUNC_ODR_CFG_B register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
STEP_COUNTER_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
STEP_COUNTER_L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
STEP_COUNTER_H register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
STEP_COUNTER_H register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
EMB_FUNC_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
EMB_FUNC_SRC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
EMB_FUNC_INIT_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
EMB_FUNC_INIT_A register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
EMB_FUNC_INIT_B register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
EMB_FUNC_INIT_B register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Register address map - embedded advanced features page 0 . . . . . . . . . . . . . . . . . . . . 122
Register address map - embedded advanced features page 1 . . . . . . . . . . . . . . . . . . . . 123
MAG_SENSITIVITY_L register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
MAG_SENSITIVITY_L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
MAG_SENSITIVITY_H register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
MAG_SENSITIVITY_H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
MAG_OFFX_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
MAG_OFFX_L register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
MAG_OFFX_H register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
MAG_OFFX_H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
MAG_OFFY_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
MAG_OFFY_L register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
MAG_OFFY_H register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
DocID032891 Rev 1
13/153
153
List of tables
Table 257.
Table 258.
Table 259.
Table 260.
Table 261.
Table 262.
Table 263.
Table 264.
Table 265.
Table 266.
Table 267.
Table 268.
Table 269.
Table 270.
Table 271.
Table 272.
Table 273.
Table 274.
Table 275.
Table 276.
Table 277.
Table 278.
Table 279.
Table 280.
Table 281.
Table 282.
Table 283.
Table 284.
Table 285.
Table 286.
Table 287.
Table 288.
Table 289.
Table 290.
Table 291.
Table 292.
Table 293.
Table 294.
Table 295.
Table 296.
Table 297.
Table 298.
Table 299.
Table 300.
Table 301.
Table 302.
Table 303.
Table 304.
Table 305.
Table 306.
Table 307.
Table 308.
14/153
LSM6DSO32
MAG_OFFY_H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
MAG_OFFZ_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
MAG_OFFZ_L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
MAG_OFFZ_H register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
MAG_OFFZ_H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
MAG_SI_XX_L register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
MAG_SI_XX_L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
MAG_SI_XX_H register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
MAG_SI_XX_H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
MAG_SI_XY_L register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
MAG_SI_XY_L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
MAG_SI_XY_H register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
MAG_SI_XY_H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
MAG_SI_XZ_L register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
MAG_SI_XZ_L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
MAG_SI_XZ_H register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
MAG_SI_XZ_H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
MAG_SI_YY_L register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
MAG_SI_YY_L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
MAG_SI_YY_H register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
MAG_SI_YY_H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
MAG_SI_YZ_L register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
MAG_SI_YZ_L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
MAG_SI_YZ_H register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
MAG_SI_YZ_H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
MAG_SI_ZZ_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
MAG_SI_ZZ_L register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
MAG_SI_ZZ_H register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
MAG_SI_ZZ_H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
MAG_CFG_A register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
MAG_CFG_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
MAG_CFG_B register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
MAG_CFG_B description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
FSM_LC_TIMEOUT_L register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
FSM_LC_TIMEOUT_L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
FSM_LC_TIMEOUT_H register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
FSM_LC_TIMEOUT_H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
FSM_PROGRAMS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
FSM_PROGRAMS register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
FSM_START_ADD_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
FSM_START_ADD_L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
FSM_START_ADD_H register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
FSM_START_ADD_H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
PEDO_CMD_REG register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
PEDO_CMD_REG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
PEDO_DEB_STEPS_CONF register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
PEDO_DEB_STEPS_CONF register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
PEDO_SC_DELTAT_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
PEDO_SC_DELTAT_H register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
PEDO_SC_DELTAT_H/L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Register address map - sensor hub registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
SENSOR_HUB_1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
DocID032891 Rev 1
LSM6DSO32
Table 309.
Table 310.
Table 311.
Table 312.
Table 313.
Table 314.
Table 315.
Table 316.
Table 317.
Table 318.
Table 319.
Table 320.
Table 321.
Table 322.
Table 323.
Table 324.
Table 325.
Table 326.
Table 327.
Table 328.
Table 329.
Table 330.
Table 331.
Table 332.
Table 333.
Table 334.
Table 335.
Table 336.
Table 337.
Table 338.
Table 339.
Table 340.
Table 341.
Table 342.
Table 343.
Table 344.
Table 345.
Table 346.
Table 347.
Table 348.
Table 349.
Table 350.
Table 351.
Table 352.
Table 353.
Table 354.
Table 355.
Table 356.
Table 357.
Table 358.
Table 359.
Table 360.
List of tables
SENSOR_HUB_1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
SENSOR_HUB_2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
SENSOR_HUB_2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
SENSOR_HUB_3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
SENSOR_HUB_3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
SENSOR_HUB_4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
SENSOR_HUB_4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
SENSOR_HUB_5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
SENSOR_HUB_5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
SENSOR_HUB_6 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
SENSOR_HUB_6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
SENSOR_HUB_7 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
SENSOR_HUB_7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
SENSOR_HUB_8 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
SENSOR_HUB_8 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
SENSOR_HUB_9 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
SENSOR_HUB_9 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
SENSOR_HUB_10 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
SENSOR_HUB_10 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
SENSOR_HUB_11 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
SENSOR_HUB_11 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
SENSOR_HUB_12 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
SENSOR_HUB_12 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
SENSOR_HUB_13 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
SENSOR_HUB_13 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
SENSOR_HUB_14 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
SENSOR_HUB_14 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
SENSOR_HUB_15 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
SENSOR_HUB_15 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
SENSOR_HUB_16 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
SENSOR_HUB_16 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
SENSOR_HUB_17 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
SENSOR_HUB_17 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
SENSOR_HUB_17 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
SENSOR_HUB_17 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
MASTER_CONFIG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
MASTER_CONFIG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
SLV0_ADD register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
SLV_ADD register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
SLV0_SUBADD register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
SLV0_SUBADD register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
SLAVE0_CONFIG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
SLAVE0_CONFIG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
SLV1_ADD register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
SLV1_ADD register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
SLV1_SUBADD register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
SLV1_SUBADD register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
SLAVE1_CONFIG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
SLAVE1_CONFIG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
SLV2_ADD register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
SLV2_ADD register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
SLV2_SUBADD register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
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List of tables
Table 361.
Table 362.
Table 363.
Table 364.
Table 365.
Table 366.
Table 367.
Table 368.
Table 369.
Table 370.
Table 371.
Table 372.
Table 373.
Table 374.
Table 375.
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LSM6DSO32
SLV2_SUBADD register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
SLAVE2_CONFIG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
SLAVE2_CONFIG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
SLV3_ADD register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
SLV3_ADD register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
SLV3_SUBADD register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
SLV3_SUBADD register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
SLAVE3_CONFIG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
SLAVE3_CONFIG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
DATAWRITE_SLV0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
DATAWRITE_SLV0 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
STATUS_MASTER register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
STATUS_MASTER register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Reel dimensions for carrier tape of LGA-14 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
DocID032891 Rev 1
LSM6DSO32
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Generic state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
State machine in the LSM6DSO32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
LSM6DSO32 connection modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SPI slave timing diagram (in mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
I²C slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Read and write protocol (in mode 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
SPI read protocol (in mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Multiple byte SPI read protocol (2-byte example) (in mode 3) . . . . . . . . . . . . . . . . . . . . . . 38
SPI write protocol (in mode 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Multiple byte SPI write protocol (2-byte example) (in mode 3) . . . . . . . . . . . . . . . . . . . . . . 39
SPI read protocol in 3-wire mode (in mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
I²C and MIPI I3CSM both active (INT1 pin not connected) . . . . . . . . . . . . . . . . . . . . . . . . . 43
Only MIPI I3CSM active (INT1 pin connected to VDD_IO) . . . . . . . . . . . . . . . . . . . . . . . . . 43
Block diagram of filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Accelerometer chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Accelerometer composite filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Gyroscope digital chain - Mode 1 and Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
LSM6DSO32 electrical connections in Mode 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
LSM6DSO32 electrical connections in Mode 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Accelerometer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
LGA-14L 2.5x3x0.86 mm package outline and mechanical data . . . . . . . . . . . . . . . . . . . 149
Carrier tape information for LGA-14 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
LGA-14 package orientation in carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Reel information for carrier tape of LGA-14 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
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Overview
1
LSM6DSO32
Overview
The LSM6DSO32 is a system-in-package featuring a high-performance 3-axis digital
accelerometer and 3-axis digital gyroscope.
The LSM6DSO32 delivers best-in-class motion sensing that can detect orientation and
gestures in order to empower application developers and consumers with features and
capabilities that are more sophisticated than simply orienting their devices to portrait and
landscape mode.
The event-detection interrupts enable efficient and reliable motion tracking and contextual
awareness, implementing hardware recognition of free-fall events, 6D orientation, click and
double-click sensing, activity or inactivity, stationary/motion detection and wakeup events.
The LSM6DSO32 supports main OS requirements, offering real, virtual and batch mode
sensors. In addition, the LSM6DSO32 can efficiently run the sensor-related features
specified in Android, saving power and enabling faster reaction time. In particular, the
LSM6DSO32 has been designed to implement hardware features such as significant motion
detection, stationary/motion detection, tilt, pedometer functions, timestamping and to
support the data acquisition of an external magnetometer.
The LSM6DSO32 offers hardware flexibility to connect the pins with different mode
connections to external sensors to expand functionalities such as adding a sensor hub, etc.
Up to 9 kbytes of FIFO with compression and dynamic allocation of significant data (i.e.
external sensors, timestamp, etc.) allows overall power saving of the system.
Like the entire portfolio of MEMS sensor modules, the LSM6DSO32 leverages the robust
and mature in-house manufacturing processes already used for the production of
micromachined accelerometers and gyroscopes. The various sensing elements are
manufactured using specialized micromachining processes, while the IC interfaces are
developed using CMOS technology that allows the design of a dedicated circuit which is
trimmed to better match the characteristics of the sensing element.
The LSM6DSO32 is available in a small plastic land grid array (LGA) package of
2.5 x 3.0 x 0.83 mm to address ultra-compact solutions.
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2
Embedded low-power features
Embedded low-power features
The LSM6DSO32 has been designed to be fully compliant with Android, featuring the
following on-chip functions:
9 kbytes data buffering, data can be compressed two or three times
–
100% efficiency with flexible configurations and partitioning
–
Possibility to store timestamp
Event-detection interrupts (fully configurable):
–
Free-fall
–
Wakeup
–
6D orientation
–
Click and double-click sensing
–
Activity/inactivity recognition
–
Stationary/Motion detection
Specific IP blocks with negligible power consumption and high-performance:
–
Pedometer functions: step detector and step counters
–
Tilt
–
Significant Motion Detection
–
Finite State Machine (FSM) for accelerometer, gyroscope, and external sensors
Sensor hub
–
Up to 6 total sensors: 2 internal (accelerometer and gyroscope) and 4 external
sensors
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Embedded low-power features
2.1
LSM6DSO32
Tilt detection
The tilt function helps to detect activity change and has been implemented in hardware
using only the accelerometer to achieve targets of both ultra-low power consumption and
robustness during the short duration of dynamic accelerations.
The tilt function is based on a trigger of an event each time the device's tilt changes and can
be used with different scenarios, for example:
a) Triggers when phone is in a front pants pocket and the user goes from sitting to
standing or standing to sitting;
b) Doesn’t trigger when phone is in a front pants pocket and the user is walking,
running or going upstairs.
2.2
Significant Motion Detection
The Significant Motion Detection (SMD) function generates an interrupt when a ‘significant
motion’, that could be due to a change in user location, is detected. In the LSM6DSO32
device this function has been implemented in hardware using only the accelerometer.
SMD functionality can be used in location-based applications in order to receive a
notification indicating when the user is changing location.
2.3
Finite State Machine
The LSM6DSO32 can be configured to generate interrupt signals activated by user-defined
motion patterns. To do this, up to 16 embedded finite state machines can be programmed
independently for motion detection such as glance gestures, absolute wrist tilt, shake and
double-shake detection.
Definition of Finite State Machine
A state machine is a mathematical abstraction used to design logic connections. It is a
behavioral model composed of a finite number of states and transitions between states,
similar to a flow chart in which one can inspect the way logic runs when certain conditions
are met. The state machine begins with a start state, goes to different states through
transitions dependent on the inputs, and can finally end in a specific state (called stop state).
The current state is determined by the past states of the system. Figure 1: Generic state
machine shows a generic state machine.
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Embedded low-power features
Figure 1. Generic state machine
Finite State Machine in the LSM6DSO32
The LSM6DSO32 works as a combo accelerometer-gyroscope sensor, generating
acceleration and angular rate output data. It is also possible to connect an external sensor
(magnetometer) by using the Sensor Hub feature (Mode 2). These data can be used as
input of up to 16 programs in the embedded Finite State Machine (Figure 2: State machine
in the LSM6DSO32).
All 16 finite state machines are independent: each one has its dedicated memory area and it
is independently executed. An interrupt is generated when the end state is reached or when
some specific command is performed.
Figure 2. State machine in the LSM6DSO32
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Pin description
3
LSM6DSO32
Pin description
Figure 3. Pin connections
Z
X
SCL
SDA
CS
Y
(1)
ΩP
1. Leave pin electrically unconnected and soldered to PCB.
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VDDIO
GND
ΩR
SDO/SA0
SDx
SCx
INT1
GND
ΩY
NC
(1)
NC
INT2
VDD
LSM6DSO32
3.1
Pin description
Pin connections
The LSM6DSO32 offers flexibility to connect the pins in order to have two different mode
connections and functionalities. In detail:
Mode 1: I²C / MIPI I3CSM slave interface or SPI (3- and 4-wire) serial interface is
available;
Mode 2: I²C / MIPI I3CSM slave interface or SPI (3- and 4-wire) serial interface and I²C
interface master for external sensor connections are available.
Figure 4. LSM6DSO32 connection modes
0RGH
0RGH
+267
+267
, &
0,3,,&60
63, Z
, &
60
0,3,,&
63, Z
/60'62
/60'62
0DVWHU,&
/60'60
([WHUQDO
/60'60
VHQVRUV
In the following table each mode is described for the pin connections and function.
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Pin description
LSM6DSO32
Table 2. Pin description
Pin#
Name
Mode 1 function
Mode 2 function
SDO
SPI 4-wire interface serial data output (SDO) SPI 4-wire interface serial data output (SDO)
SA0
I²C least significant bit of the device address
(SA0)
MIPI I3CSM least significant bit of the static
address (SA0)
I²C least significant bit of the device address
(SA0)
MIPI I3CSM least significant bit of the static
address (SA0)
2
SDx
Connect to VDDIO or GND
I²C serial data master (MSDA)
3
SCx
Connect to VDDIO or GND
I²C serial clock master (MSCL)
4
INT1
Programmable interrupt 1 /
If device is used as MIPI I3CSM pure slave,
this pin must be set to ‘1’.
Programmable interrupt 1 /
If device is used as MIPI I3CSM pure slave, this
pin must be set to ‘1’.
5
VDDIO(1)
Power supply for I/O pins
6
GND
0 V supply
7
GND
0 V supply
8
VDD(1)
Power supply
1
Programmable interrupt 2
(INT2) / Data enable (DEN)
Programmable interrupt 2 (INT2)/ Data enable
(DEN)/
I²C master external synchronization signal
(MDRDY)
9
INT2
10
NC
Leave unconnected(2)
Leave unconnected(2)
11
NC
Leave unconnected(2)
Leave unconnected(2)
12
CS
I²C/MIPI I3CSM/SPI mode selection
(1: SPI idle mode / I²C/MIPI I3CSM
communication enabled;
0: SPI communication mode / I²C/MIPI
I3CSM disabled)
I²C/MIPI I3CSM/SPI mode selection
(1: SPI idle mode / I²C/MIPI I3CSM
communication enabled;
0: SPI communication mode / I²C/MIPI I3CSM
disabled)
13
SCL
I²C/MIPI I3CSM serial clock (SCL)
SPI serial port clock (SPC)
I²C/MIPI I3CSM serial clock (SCL)
SPI serial port clock (SPC)
SDA
I²C/MIPI I3CSM serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
I²C/MIPI I3CSM serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
14
1. Recommended 100 nF filter capacitor.
2. Leave pin electrically unconnected and soldered to PCB.
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Module specifications
4
Module specifications
4.1
Mechanical characteristics
@ Vdd = 1.8 V, T = 25 °C, unless otherwise noted.
Table 3. Mechanical characteristics
Symbol
Parameter
Test conditions
Min.
Typ.(1)
Max.
Unit
±4
LA_FS
±8
Linear acceleration measurement
range
±16
g
±32
±125
G_FS
±250
Angular rate
measurement range
±500
dps
±1000
±2000
LA_So
G_So
Linear acceleration sensitivity(2)
Angular rate sensitivity
(2)
FS = ±4 g
0.122
FS = ±8 g
0.244
FS = ±16 g
0.488
FS = ±32 g
0.976
FS = ±125 dps
4.375
FS = ±250 dps
8.75
FS = ±500 dps
17.50
FS = ±1000 dps
35
FS = ±2000 dps
70
mg/LSB
mdps/LSB
LA_So%
Linear acceleration sensitivity
tolerance(3)
at component level
±0.5
%
G_So%
Angular rate sensitivity tolerance(3)
at component level
±0.5
%
LA_SoDr
Linear acceleration sensitivity
change vs. temperature(4)
from -40° to +85°
±0.007
%/°C
G_SoDr
Angular rate sensitivity change vs.
temperature(4)
from -40° to +85°
±0.005
%/°C
LA_TyOff
Linear acceleration zero-g level
offset accuracy(5)
±20
mg
G_TyOff
Angular rate zero-rate level offset
accuracy(5)
±0.5
dps
LA_OffDr
Linear acceleration zero-g level
change vs. temperature(4)
±0.1
mg/ °C
G_OffDr
Angular rate typical zero-rate level
change vs. temperature(4)
±0.01
dps/°C
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Module specifications
LSM6DSO32
Table 3. Mechanical characteristics (continued)
Symbol
Parameter
Test conditions
Min.
Typ.(1)
Max.
Unit
Rn
Rate noise density in highperformance mode(6)
3.8
mdps/Hz
RnRMS
Gyroscope RMS noise in
normal/low-power mode(7)
75
mdps
An
RMS
Acceleration noise density
in high-performance mode(8)
Acceleration RMS noise
in normal/low-power mode(9)(10)
Acceleration RMS noise
in ultra-low-power mode(9)(10)
FS = ±4 g
120
FS = ±8 g
130
FS = ±16 g
160
FS = ±32 g
220
FS = ±4 g
3.2
FS = ±8 g
3.4
FS = ±16 g
4.0
FS = ±32 g
5.4
FS = ±4 g
9.5
Vst
Top
Linear acceleration
self-test output change(12)(13)(14)
50
1700
mg
FS = ±250 dps
20
80
dps
FS = ±2000 dps
150
700
dps
-40
+85
°C
Operating temperature range
1. Typical specifications are not guaranteed.
2. Sensitivity values after factory calibration test and trimming.
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Hz
12.5
26
52
104
208
416
833
1666
3332
6664
Angular rate output data rate
Angular rate
self-test output change(15)(16)
mg(RMS)
1.6(11)
12.5
26
52
104
208
416
833
1666
3332
6664
LA_ODR Linear acceleration output data rate
G_ODR
μg/√Hz
DocID032891 Rev 1
LSM6DSO32
Module specifications
3. Subject to change.
4. Measurements are performed in a uniform temperature setup and they are based on characterization data in a limited
number of samples. Not measured during final test for production.
5. Values after factory calibration test and trimming.
6. Gyroscope rate noise density in high-performance mode is independent of the ODR and FS setting.
7. Gyroscope RMS noise in normal/low-power mode is independent of the ODR and FS setting.
8. Accelerometer noise density in high-performance mode is independent of the ODR.
9. Accelerometer RMS noise in normal/low-power/ultra-low-power mode is independent of the ODR.
10. Noise RMS related to BW = ODR/2.
11. This ODR is available when the accelerometer is in low-power mode.
12. The sign of the linear acceleration self-test output change is defined by the STx_XL bits in a dedicated register for all axes.
13. The linear acceleration self-test output change is defined with the device in stationary condition as the absolute value of:
OUTPUT[LSb] (self-test enabled) - OUTPUT[LSb] (self-test disabled). 1LSb = 0.122 mg at ±4 g full scale.
14. Accelerometer self-test limits are full-scale independent.
15. The sign of the angular rate self-test output change is defined by the STx_G bits in a dedicated register for all axes.
16. The angular rate self-test output change is defined with the device in stationary condition as the absolute value of:
OUTPUT[LSb] (self-test enabled) - OUTPUT[LSb] (self-test disabled). 1LSb = 70 mdps at ±2000 dps full scale.
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Module specifications
4.2
LSM6DSO32
Electrical characteristics
@ Vdd = 1.8 V, T = 25 °C, unless otherwise noted.
Table 4. Electrical characteristics
Vdd
Vdd_IO
Test
conditions
Min.
Typ.(1)
Max.
Unit
Supply voltage
1.71
1.8
3.6
V
Power supply for I/O
1.62
3.6
V
Symbol
Parameter
Gyroscope and accelerometer
current consumption
in high-performance mode
0.55
mA
LA_IddHP
Accelerometer current consumption
in high-performance mode
170
μA
LA_IddLP
Accelerometer current consumption
in low-power mode
ODR = 52 Hz
ODR = 1.6 Hz
26
4.5
μA
LA_IddULP
Accelerometer current consumption
in ultra-low-power mode
ODR = 52 Hz
ODR = 1.6 Hz
9.5
4.4
μA
IddPD
Gyroscope and accelerometer
current consumption during powerdown
3
μA
Ton
Turn-on time
35
ms
VIH
Digital high-level input voltage
VIL
Digital low-level input voltage
VOH
High-level output voltage
IOH = 4 mA(2)
VOL
Low-level output voltage
IOL = 4 mA(2)
Top
Operating temperature range
IddHP
0.7 *
VDD_IO
V
0.3 *
VDD_IO
VDD_IO 0.2
-40
V
V
0.2
V
+85
°C
1. Typical specifications are not guaranteed.
2. 4 mA is the maximum driving capability, i.e. the maximum DC current that can be sourced/sunk by the digital pin in order to
guarantee the correct digital output voltage levels VOH and VOL.
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4.3
Module specifications
Temperature sensor characteristics
@ Vdd = 1.8 V, T = 25 °C unless otherwise noted.
Table 5. Temperature sensor characteristics
Symbol
TODR(2)
Toff
Parameter
Test condition
Min.
Temperature refresh rate
(3)
Temperature offset
TSen
Temperature sensitivity
TST
Temperature stabilization
time(4)
Operating temperature range
Max.
52
-15
+15
°C
LSB/°C
500
16
-40
Unit
Hz
256
T_ADC_res Temperature ADC resolution
Top
Typ.(1)
μs
bit
+85
°C
1. Typical specifications are not guaranteed.
2. When the accelerometer is in low-power mode or ultra-low-power mode and the gyroscope part is turned
off, the TODR value is equal to the accelerometer ODR.
3. The output of the temperature sensor is 0 LSB (typ.) at 25 °C.
4. Time from power ON to valid data based on characterization data.
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Module specifications
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4.4
Communication interface characteristics
4.4.1
SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top.
Table 6. SPI slave timing values (in mode 3)
Value(1)
Symbol
Parameter
Unit
Min
tc(SPC)
SPI clock cycle
fc(SPC)
SPI clock frequency
tsu(CS)
CS setup time
5
th(CS)
CS hold time
20
tsu(SI)
SDI input setup time
5
th(SI)
SDI input hold time
15
tv(SO)
SDO valid output time
th(SO)
SDO output hold time
tdis(SO)
SDO output disable time
Max
100
ns
10
MHz
ns
50
5
50
1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not
tested in production
Figure 5. SPI slave timing diagram (in mode 3)
Note:
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Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output
ports.
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LSM6DSO32
4.4.2
Module specifications
I²C - inter-IC control interface
Subject to general operating conditions for Vdd and Top.
Table 7. I²C slave timing values
Symbol
f(SCL)
I²C standard mode(1)
Parameter
SCL clock frequency
I²C fast mode (1)
Min
Max
Min
Max
0
100
0
400
tw(SCLL)
SCL clock low time
4.7
1.3
tw(SCLH)
SCL clock high time
4.0
0.6
tsu(SDA)
SDA setup time
250
100
th(SDA)
SDA data hold time
0
th(ST)
START condition hold time
4
0.6
tsu(SR)
Repeated START condition
setup time
4.7
0.6
tsu(SP)
STOP condition setup time
4
0.6
4.7
1.3
tw(SP:SR)
Bus free time between STOP
and START condition
3.45
Unit
kHz
μs
ns
0
0.9
μs
μs
1. Data based on standard I²C protocol requirement, not tested in production.
Figure 6. I²C slave timing diagram
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WZ 6&//
WZ 6&/+
Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.
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Module specifications
4.5
LSM6DSO32
Absolute maximum ratings
Stresses above those listed as “Absolute maximum ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 8. Absolute maximum ratings
Symbol
Vdd /
Vdd_IO
TSTG
Sg
ESD
Vin
Note:
Ratings
Maximum value
Unit
Supply voltage
-0.3 to 4.8
V
Storage temperature range
-40 to +125
°C
20,000
g
2
kV
-0.3 to Vdd_IO +0.3
V
Acceleration g for 0.2 ms
Electrostatic discharge protection (HBM)
Input voltage on any control pin
(including CS, SCL/SPC, SDA/SDI/SDO, SDO/SA0)
Supply voltage on any pin should never exceed 4.8 V.
This device is sensitive to mechanical shock, improper handling can cause
permanent damage to the part.
This device is sensitive to electrostatic discharge (ESD), improper handling can
cause permanent damage to the part.
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4.6
Terminology
4.6.1
Sensitivity
Module specifications
Linear acceleration sensitivity can be determined, for example, by applying 1 g acceleration
to the device. Because the sensor can measure DC accelerations, this can be done easily
by pointing the selected axis towards the ground, noting the output value, rotating the
sensor 180 degrees (pointing towards the sky) and noting the output value again. By doing
so, ±1 g acceleration is applied to the sensor. Subtracting the larger output value from the
smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This
value changes very little over temperature and over time. The sensitivity tolerance describes
the range of sensitivities of a large number of sensors (see Table 3).
An angular rate gyroscope is a device that produces a positive-going digital output for
counterclockwise rotation around the axis considered. Sensitivity describes the gain of the
sensor and can be determined by applying a defined angular velocity to it. This value
changes very little over temperature and time (see Table 3).
4.6.2
Zero-g and zero-rate level
Linear acceleration zero-g level offset (TyOff) describes the deviation of an actual output
signal from the ideal output signal if no acceleration is present. A sensor in a steady state on
a horizontal surface will measure 0 g on both the X-axis and Y-axis, whereas the Z-axis will
measure 1 g. Ideally, the output is in the middle of the dynamic range of the sensor (content
of OUT registers 00h, data expressed as 2’s complement number). A deviation from the
ideal value in this case is called zero-g offset.
Offset is to some extent a result of stress to MEMS sensor and therefore the offset can
slightly change after mounting the sensor onto a printed circuit board or exposing it to
extensive mechanical stress. Offset changes little over temperature, see “Linear
acceleration zero-g level change vs. temperature” in Table 3. The zero-g level tolerance
(TyOff) describes the standard deviation of the range of zero-g levels of a group of sensors.
Zero-rate level describes the actual output signal if there is no angular rate present. The
zero-rate level of precise MEMS sensors is, to some extent, a result of stress to the sensor
and therefore the zero-rate level can slightly change after mounting the sensor onto a
printed circuit board or after exposing it to extensive mechanical stress. This value changes
very little over temperature and time (see Table 3).
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5
Digital interfaces
5.1
I²C/SPI interface
The registers embedded inside the LSM6DSO32 may be accessed through both the I²C and
SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire
interface mode. The device is compatible with SPI modes 0 and 3.
The serial interfaces are mapped onto the same pins. To select/exploit the I²C interface, the
CS line must be tied high (i.e connected to Vdd_IO).
Table 9. Serial interface pin description
Pin name
CS
SCL/SPC
SDA/SDI/SDO
SDO/SA0
5.1.1
Pin description
SPI enable
I²C/SPI mode selection (1: SPI idle mode / I²C communication enabled;
0: SPI communication mode / I²C disabled)
I²C Serial Clock (SCL)
SPI Serial Port Clock (SPC)
I²C Serial Data (SDA)
SPI Serial Data Input (SDI)
3-wire Interface Serial Data Output (SDO)
SPI Serial Data Output (SDO)
I²C less significant bit of the device address
I²C serial interface
The LSM6DSO32 I²C is a bus slave. The I²C is employed to write the data to the registers,
whose content can also be read back.
The relevant I²C terminology is provided in the table below.
Table 10. I²C terminology
Term
Transmitter
Receiver
Description
The device which sends data to the bus
The device which receives data from the bus
Master
The device which initiates a transfer, generates clock signals and terminates a
transfer
Slave
The device addressed by the master
There are two signals associated with the I²C bus: the serial clock line (SCL) and the Serial
DAta line (SDA). The latter is a bidirectional line used for sending and receiving the data
to/from the interface. Both the lines must be connected to Vdd_IO through external pull-up
resistors. When the bus is free, both the lines are high.
The I²C interface is implemented with fast mode (400 kHz) I²C standards as well as with the
standard mode.
In order to disable the I²C block, (I2C_disable) = 1 must be written in CTRL4_C (13h).
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Digital interfaces
I²C operation
The transaction on the bus is started through a START (ST) signal. A START condition is
defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After
this has been transmitted by the master, the bus is considered busy. The next byte of data
transmitted after the start condition contains the address of the slave in the first 7 bits and
the eighth bit tells whether the master is receiving data from the slave or transmitting data to
the slave. When an address is sent, each device in the system compares the first seven bits
after a start condition with its address. If they match, the device considers itself addressed
by the master.
The Slave ADdress (SAD) associated to the LSM6DSO32 is 110101xb. The SDO/SA0 pin
can be used to modify the less significant bit of the device address. If the SDO/SA0 pin is
connected to the supply voltage, LSb is ‘1’ (address 1101011b); else if the SDO/SA0 pin is
connected to ground, the LSb value is ‘0’ (address 1101010b). This solution permits to
connect and address two different inertial modules to the same I²C bus.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line
during the acknowledge pulse. The receiver must then pull the data line LOW so that it
remains stable low during the HIGH period of the acknowledge clock pulse. A receiver
which has been addressed is obliged to generate an acknowledge after each byte of data
received.
The I²C embedded inside the LSM6DSO32 behaves like a slave device and the following
protocol must be adhered to. After the start condition (ST) a slave address is sent, once a
slave acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) is transmitted.
The increment of the address is configured by the CTRL3_C (12h) (IF_INC).
The slave address is completed with a Read/Write bit. If the bit is ‘1’ (Read), a repeated
START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (Write)
the master will transmit to the slave with direction unchanged. Table 11 explains how the
SAD+Read/Write bit pattern is composed, listing all the possible configurations.
Table 11. SAD+Read/Write patterns
Command
SAD[6:1]
SAD[0] = SA0
R/W
SAD+R/W
Read
110101
0
1
11010101 (D5h)
Write
110101
0
0
11010100 (D4h)
Read
110101
1
1
11010111 (D7h)
Write
110101
1
0
11010110 (D6h)
Table 12. Transfer when master is writing one byte to slave
Master
ST
SAD + W
Slave
SUB
DATA
SAK
SAK
SP
SAK
Table 13. Transfer when master is writing multiple bytes to slave
Master
Slave
ST
SAD + W
SUB
SAK
DATA
SAK
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SAK
SP
SAK
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Digital interfaces
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Table 14. Transfer when master is receiving (reading) one byte of data from slave
Master
ST
SAD + W
Slave
SUB
SAK
SR
SAD + R
SAK
NMAK
SAK
SP
DATA
Table 15. Transfer when master is receiving (reading) multiple bytes of data from slave
Master
Slave
ST
SAD+W
SUB
SAK
SR SAD+R
SAK
MAK
SAK
DATA
MAK
DAT
A
NMAK
SP
DATA
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number
of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit
(MSb) first. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to
receive because it is performing some real-time function) the data line must be left HIGH by
the slave. The master can then abort the transfer. A LOW to HIGH transition on the SDA line
while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be
terminated by the generation of a STOP (SP) condition.
In the presented communication format MAK is Master acknowledge and NMAK is No
Master Acknowledge.
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5.1.2
Digital interfaces
SPI bus interface
The LSM6DSO32 SPI is a bus slave. The SPI allows writing and reading the registers of the
device.
The serial interface communicates to the application using 4 wires: CS, SPC, SDI and SDO.
Figure 7. Read and write protocol (in mode 3)
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CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of
the transmission and goes back high at the end. SPC is the serial port clock and it is
controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and
SDO are, respectively, the serial port data input and output. Those lines are driven at the
falling edge of SPC and should be captured at the rising edge of SPC.
Both the read register and write register commands are completed in 16 clock pulses or in
multiples of 8 in case of multiple read/write bytes. Bit duration is the time between two falling
edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling edge
of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the
rising edge of CS.
bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0)
from the device is read. In latter case, the chip will drive SDO at the start of bit 8.
bit 1-7: address AD(6:0). This is the address field of the indexed register.
bit 8-15: data DI(7:0) (write mode). This is the data that is written into the device (MSb first).
bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
In multiple read/write commands further blocks of 8 clock periods will be added. When the
CTRL3_C (12h) (IF_INC) bit is ‘0’, the address used to read/write data remains the same for
every block. When the CTRL3_C (12h) (IF_INC) bit is ‘1’, the address used to read/write
data is increased at every block.
The function and the behavior of SDI and SDO remain unchanged.
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Digital interfaces
LSM6DSO32
SPI read
Figure 8. SPI read protocol (in mode 3)
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The SPI Read command is performed with 16 clock pulses. A multiple byte read command
is performed by adding blocks of 8 clock pulses to the previous one.
bit 0: READ bit. The value is 1.
bit 1-7: address AD(6:0). This is the address field of the indexed register.
bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb
first).
bit 16-...: data DO(...-8). Further data in multiple byte reads.
Figure 9. Multiple byte SPI read protocol (2-byte example) (in mode 3)
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Digital interfaces
SPI write
Figure 10. SPI write protocol (in mode 3)
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The SPI Write command is performed with 16 clock pulses. A multiple byte write command
is performed by adding blocks of 8 clock pulses to the previous one.
bit 0: WRITE bit. The value is 0.
bit 1 -7: address AD(6:0). This is the address field of the indexed register.
bit 8-15: data DI(7:0) (write mode). This is the data that is written inside the device (MSb
first).
bit 16-... : data DI(...-8). Further data in multiple byte writes.
Figure 11. Multiple byte SPI write protocol (2-byte example) (in mode 3)
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Digital interfaces
LSM6DSO32
SPI read in 3-wire mode
A 3-wire mode is entered by setting the CTRL3_C (12h) (SIM) bit equal to ‘1’ (SPI serial
interface mode selection).
Figure 12. SPI read protocol in 3-wire mode (in mode 3)
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The SPI read command is performed with 16 clock pulses:
bit 0: READ bit. The value is 1.
bit 1-7: address AD(6:0). This is the address field of the indexed register.
bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
A multiple read command is also available in 3-wire mode.
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Digital interfaces
5.2
MIPI I3CSM interface
5.2.1
MIPI I3CSM slave interface
The LSM6DSO32 interface includes a MIPI I3CSM SDR only slave interface (compliant with
release 1.0 of the specification) with MIPI I3CSM SDR embedded features:
CCC command
Direct CCC communication (SET and GET)
Broadcast CCC communication
Private communications
Private read and write for single byte
Multiple read and write
In-Band Interrupt request
Error Detection and Recovery Methods (S0-S6)
Note:
Refer to Section 5.3: I²C/MIPI I3CSM coexistence in LSM6DSO32 for details concerning the
choice of the interface when powering up the device.
5.2.2
MIPI I3CSM CCC supported commands
The list of MIPI I3CSM CCC commands supported by the device is detailed in the following
table.
Table 16. MIPI I3CSM CCC commands
Command
Command
code
Default
Description
ENTDAA
0x07
DAA procedure
SETDASA
0x87
Assign Dynamic Address using Static Address 0x6B/0x6A
depending on SDO pin
ENEC
0x80 / 0x00
Slave activity control (direct and broadcast)
DISEC
0x81/ 0x01
Slave activity control (direct and broadcast)
ENTAS0
0x82 / 0x02
Enter activity state (direct and broadcast)
ENTAS1
0x83 / 0x03
Enter activity state (direct and broadcast)
ENTAS2
0x84 / 0x04
Enter activity state (direct and broadcast)
ENTAS3
0x85 / 0x05
Enter activity state (direct and broadcast)
SETXTIME
0x98 / 0x28
Timing information exchange
GETXTIME
0x99
0x07
0x00
0x05
0x92
Timing information exchange
RSTDAA
0x86 / 0x06
Reset the assigned dynamic address (direct and broadcast)
SETMWL
0x89 / 0x08
Define maximum write length during private write (direct and
broadcast)
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Digital interfaces
LSM6DSO32
Table 16. MIPI I3CSM CCC commands
Command
SETMRL
Command
code
Default
Description
Define maximum read length during private read (direct and
broadcast)
0x8A / 0x09
SETNEWDA
0x88
GETMWL
0x8B
0x00
0x08
(2 byte)
Get maximum write length during private write
0x8C
0x00
0x10
0x09
(3 byte)
Get maximum read length during private read
GETPID
0x8D
0x02
0x08
0x00
0x6C
0x10
0x0B
GETBCR
0x8E
0x07
(1 byte)
GETDCR
0x8F
0x44 default
GETSTATUS
0x90
0x00
0x00
(2 byte)
Status register
GETMXDS
0x94
0x00
0x20
(2 byte)
Return max data speed
GETMRL
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Change dynamic address
Device ID register
Bus characteristics register
MIPI I3CSM Device Characteristic Register
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5.3
Digital interfaces
I²C/MIPI I3CSM coexistence in LSM6DSO32
In the LSM6DSO32, the SDA and SCL lines are common to both I²C and MIPI I3CSM. The
I²C bus requires anti-spike filters on the SDA and SCL pins that are not compatible with MIPI
I3CSM timing.
The device can be connected to both I²C and MIPI I3CSM or only to the MIPI I3CSM bus
depending on the connection of the INT1 pin when the device is powered up:
INT1 pin floating (internal pull-down): I²C/MIPI I3CSM both active, see Figure 13
INT1 pin connected to VDD_IO: only MIPI I3CSMactive, see Figure 14
Figure 13. I²C and MIPI I3CSM both active (INT1 pin not connected)
INT1 pin not connected
I²C/I3C both active
I²C/I3C
(both active)
I3C bus case
I²C bus case
Master sends
I²C r/w
Slave performs
requested r/w
Master assigns DA
to the slave(1)
Master resets
DA
I3C private R/W with and without 7Eh
CCC commands
Slave event management
Error detection and recovery
1. Address assignment (DAA or ENTDA) must be performed with I²C Fast Mode Plus Timing. When the slave
is addressed, the I²C slave is disabled and the timing is compatible with MIPI I3CSM specifications.
Figure 14. Only MIPI I3CSM active (INT1 pin connected to VDD_IO)
INT1 pin connected to VDD_IO
Only I3C active
I²C/I3C
I3C bus case
Dynamic
Address
Assignment (1)
Master resets
DA
I3C private R/W with and without 7Eh
CCC commands
Slave event management
Error detection and recovery
1. When the slave is MIPI I3CSM only, the I²C slave is always disabled. The address can be assigned using
MIPI I3CSM SDR timing.
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Digital interfaces
5.4
LSM6DSO32
Master I²C interface
If the LSM6DSO32 is configured in Mode 2, a master I²C line is available. The master serial
interface is mapped in the following dedicated pins.
Table 17. Master I²C pin details
Pin name
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Pin description
MSCL
I²C serial clock master
MSDA
I²C serial data master
MDRDY
I²C master external synchronization signal
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6
Functionality
6.1
Operating modes
Functionality
In the LSM6DSO32, the accelerometer and the gyroscope can be turned on/off
independently of each other and are allowed to have different ODRs and power modes.
The LSM6DSO32 has three operating modes available:
only accelerometer active and gyroscope in power-down
only gyroscope active and accelerometer in power-down
both accelerometer and gyroscope sensors active with independent ODR
The accelerometer is activated from power-down by writing ODR_XL[3:0] in CTRL1_XL
(10h) while the gyroscope is activated from power-down by writing ODR_G[3:0] in
CTRL2_G (11h). For combo-mode the ODRs are totally independent.
6.2
Accelerometer power modes
In the LSM6DSO32, the accelerometer can be configured in five different operating modes:
power-down, ultra-low-power, low-power, normal mode and high-performance mode. The
operating mode selected depends on the value of the XL_HM_MODE bit in CTRL6_C (15h).
If XL_HM_MODE is set to '0', high-performance mode is valid for all ODRs (from 12.5 Hz up
to 6.66 kHz).
To enable the low-power and normal mode, the XL_HM_MODE bit has to be set to '1'. Lowpower mode is available for lower ODRs (1.6, 12.5, 26, 52 Hz) while normal mode is
available for ODRs equal to 104 and 208 Hz.
6.2.1
Accelerometer ultra-low-power mode
The LSM6DSO32 can be configured in ultra-low-power (ULP) mode by setting the
XL_ULP_EN bit to 1 in CTRL5_C (14h) register. This mode can be used in accelerometeronly mode (gyroscope sensor must be configured in power-down mode) and for ODR_XL
values between 1.6 Hz and 208 Hz.
When ULP mode is intended to be used, the bit XL_HM_MODE must be set to 0.
When ULP mode is switched ON/OFF, the accelerometer must be configured in powerdown condition.
The embedded functions based on accelerometer data (free-fall, 6D/4D, tap, double-tap,
wake-up, activity/inactivity, stationary/motion, step-counter, step-detection, significant
motion, tilt) and the FIFO batching functionality are still supported when ULP mode is
enabled.
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Functionality
6.3
LSM6DSO32
Gyroscope power modes
In the LSM6DSO32, the gyroscope can be configured in four different operating modes:
power-down, low-power, normal mode and high-performance mode. The operating mode
selected depends on the value of the G_HM_MODE bit in CTRL7_G (16h). If G_HM_MODE
is set to '0', high-performance mode is valid for all ODRs (from 12.5 Hz up to 6.66 kHz).
To enable the low-power and normal mode, the G_HM_MODE bit has to be set to '1'. Lowpower mode is available for lower ODRs (12.5, 26, 52 Hz) while normal mode is available
for ODRs equal to 104 and 208 Hz.
6.4
Block diagram of filters
Figure 15. Block diagram of filters
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Block diagrams of the accelerometer filters
In the LSM6DSO32, the filtering chain for the accelerometer part is composed of the
following:
Analog filter (anti-aliasing)
Digital filter (LPF1)
Composite filter
Details of the block diagram appear in the following figure.
Figure 16. Accelerometer chain
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Functionality
Figure 17. Accelerometer composite filter
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1. The cutoff value of the LPF1 output is ODR/2 when the accelerometer is in high-performance mode. This
value is equal to 700 Hz when the accelerometer is in low-power or normal mode.
Note:
Advanced functions include pedometer, step detector and step counter, significant motion
detection, tilt functions and Finite State Machine.
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Functionality
6.4.2
LSM6DSO32
Block diagrams of the gyroscope filters
Figure 18. Gyroscope digital chain - Mode 1 and Mode 2
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The digital LPF2 filter cannot be configured by the user and its cutoff frequency depends on
the selected gyroscope ODR, as indicated in the following table.
Table 18. Gyroscope LPF2 bandwidth selection
Gyroscope ODR [Hz]
LPF2 cutoff [Hz]
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Data can be acquired from the output registers and FIFO over the primary I²C/I³C/SPI
interface.
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6.5
Functionality
FIFO
The presence of a FIFO allows consistent power saving for the system since the host
processor does not need continuously poll data from the sensor, but It can wake up only
when needed and burst the significant data out from the FIFO.
The LSM6DSO32 embeds 3 kbytes of data in FIFO (up to 9 kbytes with the compression
feature enabled) to store the following data:
Gyroscope
Accelerometer
External sensors (up to 4)
Step counter
Timestamp
Temperature
Writing data in the FIFO can be configured to be triggered by the:
Accelerometer / gyroscope data-ready signal
Sensor hub data-ready signal
Step detection signal
The applications have maximum flexibility in choosing the rate of batching for physical
sensors with FIFO-dedicated configurations: accelerometer, gyroscope and temperature
sensor batching rates can be selected by the user. External sensor writing in FIFO can be
triggered by the accelerometer data-ready signal or by an external sensor interrupt. The
step counter can be stored in FIFO with associated timestamp each time a step is detected.
It is possible to select decimation for timestamp batching in FIFO with a factor of 1, 8, or 32.
The reconstruction of a FIFO stream is a simple task thanks to the FIFO_DATA_OUT_TAG
byte that allows recognizing the meaning of a word in FIFO.
FIFO allows correct reconstruction of the timestamp information for each sensor stored in
FIFO. If a change in the ODR or BDR (Batching Data Rate) configuration is performed, the
application can correctly reconstruct the timestamp and know exactly when the change was
applied without disabling FIFO batching. FIFO stores information of the new configuration
and timestamp in which the change was applied in the device.
Finally, FIFO embeds a compression algorithm that the user can enable in order to have up
to 9 kbyte data stored in FIFO and take advantage of interface communication length for
FIFO flushing and communication power consumption.
The programmable FIFO watermark threshold can be set in FIFO_CTRL1 (07h) and
FIFO_CTRL2 (08h) using the WTM[8:0] bits. To monitor the FIFO status, dedicated
registers (FIFO_STATUS1 (3Ah), FIFO_STATUS2 (3Bh)) can be read to detect FIFO
overrun events, FIFO full status, FIFO empty status, FIFO watermark status and the number
of unread samples stored in the FIFO. To generate dedicated interrupts on the INT1 and
INT2 pins of these status events, the configuration can be set in INT1_CTRL (0Dh) and
INT2_CTRL (0Eh).
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Functionality
LSM6DSO32
The FIFO buffer can be configured according to six different modes:
Bypass mode
FIFO mode
Continuous mode
Continuous-to-FIFO mode
Bypass-to-continuous mode
Bypass-to-FIFO mode
Each mode is selected by the FIFO_MODE_[2:0] bits in the FIFO_CTRL4 (0Ah) register.
6.5.1
Bypass mode
In Bypass mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = 000), the FIFO is not operational
and it remains empty. Bypass mode is also used to reset the FIFO when in FIFO mode.
6.5.2
FIFO mode
In FIFO mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = 001) data from the output
channels are stored in the FIFO until it is full.
To reset FIFO content, Bypass mode should be selected by writing FIFO_CTRL4
(0Ah)(FIFO_MODE_[2:0]) to '000'. After this reset command, it is possible to restart FIFO
mode by writing FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0]) to '001'.
The FIFO buffer memorizes up to 9 kbytes of data (with compression enabled) but the depth
of the FIFO can be resized by setting the WTM [8:0] bits in FIFO_CTRL1 (07h) and
FIFO_CTRL2 (08h). If the STOP_ON_WTM bit in FIFO_CTRL2 (08h) is set to '1', FIFO
depth is limited up to the WTM [8:0] bits in FIFO_CTRL1 (07h) and FIFO_CTRL2 (08h).
6.5.3
Continuous mode
Continuous mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = 110) provides a continuous
FIFO update: as new data arrives, the older data is discarded.
A FIFO threshold flag FIFO_STATUS2 (3Bh)(FIFO_WTM_IA) is asserted when the number
of unread samples in FIFO is greater than or equal to FIFO_CTRL1 (07h) and FIFO_CTRL2
(08h)(WTM [8:0]).
It is possible to route the FIFO_WTM_IA flag to the INT1 pin by writing in register
INT1_CTRL (0Dh)(INT1_FIFO_TH) = '1' or to the INT2 pin by writing in register INT2_CTRL
(0Eh)(INT2_FIFO_TH) = '1'.
A full-flag interrupt can be enabled, INT1_CTRL (0Dh)(INT1_FIFO_FULL) = '1' or
INT2_CTRL (0Eh)(INT2_FIFO_FULL) = '1', in order to indicate FIFO saturation and
eventually read its content all at once.
If an overrun occurs, at least one of the oldest samples in FIFO has been overwritten and
the FIFO_OVR_IA flag in FIFO_STATUS2 (3Bh) is asserted.
In order to empty the FIFO before it is full, it is also possible to pull from FIFO the number of
unread samples available inFIFO_STATUS1 (3Ah) and FIFO_STATUS2
(3Bh)(DIFF_FIFO_[9:0]).
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6.5.4
Functionality
Continuous-to-FIFO mode
In Continuous-to-FIFO mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = 011), FIFO
behavior changes according to the trigger event detected in one of the following interrupt
events:
Single tap
Double tap
Wake-up
Free-fall
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When the selected trigger bit is equal to '1', FIFO operates in FIFO mode.
When the selected trigger bit is equal to '0', FIFO operates in Continuous mode.
6.5.5
Bypass-to-Continuous mode
In Bypass-to-Continuous mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = '100'), data
measurement storage inside FIFO operates in Continuous mode when selected triggers are
equal to '1', otherwise FIFO content is reset (Bypass mode).
FIFO behavior changes according to the trigger event detected in one of the following
interrupt events:
Single tap
Double tap
Wake-up
Free-fall
D6D
6.5.6
Bypass-to-FIFO mode
In Bypass-to-FIFO mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = '111'), data
measurement storage inside FIFO operates in FIFO mode when selected triggers are equal
to '1', otherwise FIFO content is reset (Bypass mode).
FIFO behavior changes according to the trigger event detected in one of the following
interrupt events:
Single tap
Double tap
Wake-up
Free-fall
D6D
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Functionality
6.5.7
LSM6DSO32
FIFO reading procedure
The data stored in FIFO are accessible from dedicated registers and each FIFO word is
composed of 7 bytes: one tag byte (FIFO_DATA_OUT_TAG (78h), in order to identify the
sensor, and 6 bytes of fixed data (FIFO_DATA_OUT registers from (79h) to (7Eh)).
The DIFF_FIFO_[9:0] field in the FIFO_STATUS1 (3Ah) and FIFO_STATUS2 (3Bh)
registers contains the number of words (1 byte TAG + 6 bytes DATA) collected in FIFO.
In addition, it is possible to configure a counter of the batch events of accelerometer or
gyroscope sensors. The flag COUNTER_BDR_IA in FIFO_STATUS2 (3Bh) alerts that the
counter reaches a selectable threshold (CNT_BDR_TH_[10:0] field in
COUNTER_BDR_REG1 (0Bh) and COUNTER_BDR_REG2 (0Ch)). This allows triggering
the reading of FIFO with the desired latency of one single sensor. The sensor is selectable
using the TRIG_COUNTER_BDR bit in COUNTER_BDR_REG1 (0Bh). As for the other
FIFO status events, the flag COUNTER_BDR_IA can be routed on the INT1 or INT2 pins by
asserting the corresponding bits (INT1_CNT_BDR of INT1_CTRL (0Dh) and
INT2_CNT_BDR of INT2_CTRL (0Eh)).
In order to maximize the amount of accelerometer and gyroscope data in FIFO, the user can
enable the compression algorithm by setting to 1 both the FIFO_COMPR_EN bit in
EMB_FUNC_EN_B (05h) (embedded functions registers bank) and the
FIFO_COMPR_RT_EN bit in FIFO_CTRL2 (08h). When compression is enabled, it is also
possible to force writing non-compressed data at a selectable rate using the
UNCOPTR_RATE_[1:0] field in FIFO_CTRL2 (08h).
Meta information about accelerometer and gyroscope sensor configuration changes can be
managed by enabling the ODR_CHG_EN bit in FIFO_CTRL2 (08h).
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Application hints
7
Application hints
7.1
LSM6DSO32 electrical connections in Mode 1
Figure 19. LSM6DSO32 electrical connections in Mode 1
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1. Leave pin electrically unconnected and soldered to PCB.
The device core is supplied through the Vdd line. Power supply decoupling capacitors (C1,
C2 = 100 nF ceramic) should be placed as near as possible to the supply pin of the device
(common design practice).
The functionality of the device and the measured acceleration/angular rate data is
selectable and accessible through the SPI/I²C/MIPI I3CSM interface.
The functions, the threshold and the timing of the two interrupt pins for each sensor can be
completely programmed by the user through the SPI/I²C/MIPI I3CSM interface.
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7.2
LSM6DSO32
LSM6DSO32 electrical connections in Mode 2
Figure 20. LSM6DSO32 electrical connections in Mode 2
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Package information
17.2
LSM6DSO32
LGA-14 packing information
Figure 23. Carrier tape information for LGA-14 package
Figure 24. LGA-14 package orientation in carrier tape
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Package information
Figure 25. Reel information for carrier tape of LGA-14 package
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Table 374. Reel dimensions for carrier tape of LGA-14 package
Reel dimensions (mm)
A (max)
330
B (min)
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C
13 ±0.25
D (min)
20.2
N (min)
60
G
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T (max)
18.4
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Revision history
18
LSM6DSO32
Revision history
Table 375. Document revision history
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Date
Revision
13-Mar-2020
1
Changes
Initial release
DocID032891 Rev 1
LSM6DSO32
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