M24M01-R M24M01-DF
1-Mbit serial I²C bus EEPROM
Datasheet - production data
Features
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
• Compatible with all I2C bus modes:
– 1 MHz
– 400 kHz
– 100 kHz
• Memory array:
– 1 Mbit (128 Kbyte) of EEPROM
– Page size: 256 byte
– Additional Write lockable page (M24M01-D
order codes)
• Single supply voltage and high speed:
– 1 MHz clock from 1.7 V to 5.5 V
•
WLCSP (CS, CX)
Write:
– Byte Write within 5 ms
– Page Write within 5 ms
• Operating temperature range:
– from -40 °C up to +85 °C
• Random and sequential Read modes
• Write protect of the whole memory array
• Enhanced ESD/Latch-Up protection
• More than 4 million Write cycles
Unsawn wafer
• More than 200-years data retention
Packages
• SO8 ECOPACK2®
• TSSOP8 ECOPACK2®
• WLCSP ECOPACK2®
• Unsawn wafer (each die is tested)
October 2017
This is information on a product in full production.
DocID12943 Rev 14
1/47
www.st.com
Contents
M24M01-R M24M01-DF
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
Chip Enable (E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4
Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5
VSS (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6
Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.1
Operating supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.2
Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.3
Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.4
Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4
Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5
4.1
Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2
Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3
Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.4
Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.5
Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1
5.2
Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1.1
Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1.2
Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1.3
Write Identification Page (M24M01-D only) . . . . . . . . . . . . . . . . . . . . . . 17
5.1.4
Lock Identification Page (M24M01-D only) . . . . . . . . . . . . . . . . . . . . . . 17
5.1.5
ECC (Error Correction Code) and Write cycling . . . . . . . . . . . . . . . . . . 17
5.1.6
Minimizing Write delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 18
Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2.1
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Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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Contents
5.2.2
Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2.3
Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.3
Read Identification Page (M24M01-D only) . . . . . . . . . . . . . . . . . . . . . . . 20
5.4
Read the lock status (M24M01-D only) . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.1
TSSOP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.2
SO8N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.3
WLCSP8 ultra thin package information . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.4
WLCSP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
10
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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3
List of tables
M24M01-R M24M01-DF
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
4/47
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Most significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Least significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Operating conditions (voltage range R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Operating conditions (voltage range F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Cycling performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DC characteristics (M24M01-R, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DC characteristics (M24M01-DF, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
400 kHz AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1 MHz AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
TSSOP8 – 3 x 4.4 mm, 0.65 mm pitch, 8-lead thin shrink small outline,
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
SO8N – 3.9x4.9 mm, 8-lead plastic small outline, 150 mils body width,
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
WLCSP - 8 balls, 2.578x1.716 mm, 0.5 mm pitch, wafer level chip scale
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
WLCSP- 8-bump, without BSC, 2.578 x 1.716 mm, wafer level chip scale
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
WLCSP- 8-bump, with BSC, 2.578 x 1.716 mm, wafer level chip scale
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Ordering information scheme (unsawn wafer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
DocID12943 Rev 14
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List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
8-pin package connections, top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
WLCSP connections (top view, marking side,
with balls on the underside) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chip enable inputs connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Maximum Rbus value versus bus parasitic capacitance (Cbus) for
an I2C bus at maximum frequency fC = 400 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Maximum Rbus value versus bus parasitic capacitance Cbus) for
an I2C bus at maximum frequency fC = 1MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
TSSOP8 – 3x4.4 mm, 0.65 mm pitch, 8-lead thin shrink small outline,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
SO8N – 3.9x4.9 mm, 8-lead plastic small outline, 150 mils body width, package outline . 34
SO8N – 3.9x4.9 mm, 8-lead plastic small outline, 150 mils body width,
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
WLCSP - 8 balls, 2.578x1.716 mm, 0.5 mm pitch, wafer level chip scale
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
WLCSP - 8 balls, 2.578x1.716 mm, 0.5 mm pitch, wafer level chip scale
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
WLCSP- 8-bump, without BSC, 2.578 x 1.716 mm, wafer level chip scale
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
WLCSP- 8-bump, with BSC, 2.578 x 1.716 mm, wafer level chip scale
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
WLCSP- 8-bump, 2.578 x 1.716 mm, wafer level chip scale
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
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5
Description
1
M24M01-R M24M01-DF
Description
The M24M01 is a 1 Mbit I2C-compatible EEPROM (Electrically Erasable PROgrammable
Memory) organized as 128 K × 8 bits.
The M24M01-R can operate with a supply voltage from 1.8 V to 5.5 V, and the M24M01-DF
can operate with a supply voltage from 1.7 V to 5.5 V, over an ambient temperature range of
–40 °C / +85 °C.
The M24M01-D offers an additional page, named the Identification Page (256 byte). The
Identification Page can be used to store sensitive application parameters which can be
(later) permanently locked in Read-only mode.
Figure 1. Logic diagram
6##
%
%
3$!
-XXX
3#,
7#
633
.47
Table 1. Signal names
Signal name
6/47
Function
Direction
E1, E2
Chip Enable
Input
SDA
Serial Data
I/O
SCL
Serial Clock
Input
WC
Write Control
Input
VCC
Supply voltage
-
VSS
Ground
-
DocID12943 Rev 14
M24M01-R M24M01-DF
Description
Figure 2. 8-pin package connections, top view
'8
9&&
(
:&
(
6&/
966
6'$
06 9
1. DU: Don’t use (no signal should be applied on this pin; if connected, must be connected to VSS)
2. See Section 9: Package information for package dimensions, and how to identify pin 1
Figure 3. WLCSP connections (top view, marking side,
with balls on the underside)
&
%
$
9 &&
6'$
6&/
(
:&
(
9 66
'8
06 9
1. DU: Don't Use (if connected, must be connected to VSS)
2. See Section 9: Package mechanical data for package dimensions, and how to identify pin 1.
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Signal description
M24M01-R M24M01-DF
2
Signal description
2.1
Serial Clock (SCL)
The signal applied on the SCL input is used to strobe the data available on SDA(in) and to
output the data on SDA(out).
2.2
Serial Data (SDA)
SDA is an input/output used to transfer data in or data out of the device. SDA(out) is an
open drain output that may be wire-OR’ed with other open drain or open collector signals on
the bus. A pull-up resistor must be connected (Figure 12 indicates how to calculate the
value of the pull-up resistor).
2.3
Chip Enable (E1, E2)
These input signals are used to set the value that is to be looked for on the two bits (b3, b2)
of the 7-bit device select code. These inputs must be tied to VCC or VSS, to establish the
device select code as shown in Figure 4. When not connected (left floating), These inputs
are read as low (0,0).
Figure 4. Chip enable inputs connection
9&&
9&&
0[[[
0[[[
(L
(L
966
2.4
966
$L
Write Control (WC)
This input signal is useful for protecting the entire contents of the memory from inadvertent
write operations. Write operations are disabled to the entire memory array when Write
Control (WC) is driven high. Write operations are enabled when Write Control (WC) is either
driven low or left floating.
When Write Control (WC) is driven high, device select and address bytes are
acknowledged, Data bytes are not acknowledged.
2.5
VSS (ground)
VSS is the reference for the VCC supply voltage.
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Signal description
2.6
Supply voltage (VCC)
2.6.1
Operating supply voltage (VCC)
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions
in Section 8: DC and AC parameters). In order to secure a stable DC supply voltage, it is
recommended to decouple the VCC line with a suitable capacitor (usually of the order of
10 nF to 100 nF) close to the VCC/VSS package pins.
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a write instruction, until the completion of the internal write cycle (tW).
2.6.2
Power-up conditions
The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage
(see Operating conditions in Section 8: DC and AC parameters).
2.6.3
Device reset
In order to prevent inadvertent write operations during power-up, a power-on-reset (POR)
circuit is included.
At power-up, the device does not respond to any instruction until VCC has reached the
internal reset threshold voltage. This threshold is lower than the minimum VCC operating
voltage (see Operating conditions in Section 8: DC and AC parameters). When VCC passes
over the POR threshold, the device is reset and enters the Standby Power mode; however,
the device must not be accessed until VCC reaches a valid and stable DC voltage within the
specified [VCC(min), VCC(max)] range (see Operating conditions in Section 8: DC and AC
parameters).
In a similar way, during power-down (continuous decrease in VCC), the device must not be
accessed when VCC drops below VCC(min). When VCC drops below the internal reset
threshold voltage, the device stops responding to any instruction sent to it.
2.6.4
Power-down conditions
During power-down (continuous decrease in VCC), the device must be in the Standby Power
mode (mode reached after decoding a Stop condition, assuming that there is no internal
write cycle in progress).
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46
Memory organization
3
M24M01-R M24M01-DF
Memory organization
The memory is organized as shown below.
Figure 5. Block diagram
7#
%
%
(IGHVOLTAGE
GENERATOR
#ONTROLLOGIC
3#,
3$!
)/SHIFTREGISTER
$ATA
REGISTER
9DECODER
!DDRESSREGISTER
ANDCOUNTER
PAGE
)DENTIFICATIONPAGE
8DECODER
-36
10/47
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4
Device operation
Device operation
The device supports the I2C protocol. This is summarized in Figure 6. Any device that sends
data on to the bus is defined to be a transmitter, and any device that reads the data to be a
receiver. The device that controls the data transfer is known as the bus master, and the
other as the slave device. A data transfer can only be initiated by the bus master, which will
also provide the serial clock for synchronization. The device is always a slave in all
communications.
Figure 6. I2C bus protocol
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46
Device operation
4.1
M24M01-R M24M01-DF
Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the high state. A Start condition must precede any data transfer instruction. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition.
4.2
Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and
driven high. A Stop condition terminates communication between the device and the bus
master. A Read instruction that is followed by NoAck can be followed by a Stop condition to
force the device into the Standby mode.
A Stop condition at the end of a Write instruction triggers the internal Write cycle.
4.3
Data input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven low.
4.4
Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) low to
acknowledge the receipt of the eight data bits.
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M24M01-R M24M01-DF
4.5
Device operation
Device addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, shown
in Table 2 (most significant bit first).
Table 2. Device select code
Chip Enable
address(2)
Device type identifier(1)
When accessing
the memory
When accessing
the Identification
page
Address
bit
RW
b7
b6
b5
b4
b3
b2
b1
b0
1
0
1
0
E2
E1
A16
RW
1
0
1
1
E2
E1
X(3)
RW
1. The most significant bit, b7, is sent first.
2. E2,E1 are compared against the external pin on the memory device.
3. X = don’t care.
When the device select code is received, the device only responds if the Chip Enable
address is the same as the value on its Chip Enable E2,E1 inputs.
The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
If a match occurs on the device select code, the corresponding device gives an
acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match
the device select code, the device deselects itself from the bus, and goes into Standby
mode.
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Instructions
M24M01-R M24M01-DF
5
Instructions
5.1
Write operations
Following a Start condition the bus master sends a device select code with the R/W bit (RW)
reset to 0. The device acknowledges this, as shown in Figure 7, and waits for two address
bytes. The device responds to each address byte with an acknowledge bit, and then waits
for the data byte.
Table 3. Most significant address byte
A15
A14
A13
A12
A11
A10
A9
A8
A1
A0
Table 4. Least significant address byte
A7
A6
A5
A4
A3
A2
The 128 Kbytes (1 Mb) are addressed with 17 address bits, the 16 lower address bits being
defined by the two address bytes and the most significant address bit (A16) being included
in the Device Select code (see Table 2).
When the bus master generates a Stop condition immediately after a data byte Ack bit (in
the “10th bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write
cycle tW is triggered. A Stop condition at any other time slot does not trigger the internal
Write cycle.
After the Stop condition and the successful completion of an internal Write cycle (tW), the
device internal address counter is automatically incremented to point to the next byte after
the last modified byte.
During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does
not respond to any requests.
If the Write Control input (WC) is driven High, the Write instruction is not executed and the
accompanying data bytes are not acknowledged, as shown in Figure 8.
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5.1.1
Instructions
Byte Write
After the device select code and the address bytes, the bus master sends one data byte. If
the addressed location is Write-protected, by Write Control (WC) being driven high, the
device replies with NoAck, and the location is not modified. If, instead, the addressed
location is not Write-protected, the device replies with Ack. The bus master terminates the
transfer by generating a Stop condition, as shown in Figure 7.
Figure 7. Write mode sequences with WC = 0 (data write enabled)
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Instructions
5.1.2
M24M01-R M24M01-DF
Page Write
The Page Write mode allows up to 256 byte to be written in a single Write cycle, provided
that they are all located in the same page in the memory: that is, the most significant
memory address bits, b16-b8, are the same. If more bytes are sent than will fit up to the end
of the page, a “roll-over” occurs, i.e. the bytes exceeding the page end are written on the
same page, from location 0.
The bus master sends from 1 to 256 byte of data, each of which is acknowledged by the
device if Write Control (WC) is low. If Write Control (WC) is high, the contents of the
addressed memory location are not modified, and each data byte is followed by a NoAck, as
shown in Figure 8. After each transferred byte, the internal page address counter is
incremented.
The transfer is terminated by the bus master generating a Stop condition.
Figure 8. Write mode sequences with WC = 1 (data write inhibited)
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5.1.3
Instructions
Write Identification Page (M24M01-D only)
The Identification Page (256 byte) is an additional page which can be written and (later)
permanently locked in Read-only mode. It is written by issuing the Write Identification Page
instruction. This instruction uses the same protocol and format as Page Write (into memory
array), except for the following differences:
•
Device type identifier = 1011b
•
MSB address bits A16/A8 are don't care except for address bit A10 which must be ‘0’.
LSB address bits A7/A0 define the byte address inside the Identification page.
If the Identification page is locked, the data bytes transferred during the Write Identification
Page instruction are not acknowledged (NoAck).
5.1.4
Lock Identification Page (M24M01-D only)
The Lock Identification Page instruction (Lock ID) permanently locks the Identification page
in Read-only mode. The Lock ID instruction is similar to Byte Write (into memory array) with
the following specific conditions:
5.1.5
•
Device type identifier = 1011b
•
Address bit A10 must be ‘1’; all other address bits are don't care
•
The data byte must be equal to the binary value xxxx xx1x, where x is don't care
ECC (Error Correction Code) and Write cycling(1)
The Error Correction Code (ECC) is an internal logic function which is transparent for the
I2C communication protocol.
The ECC logic is implemented on each group of four EEPROM bytes(2). Inside a group, if a
single bit out of the four bytes happens to be erroneous during a Read operation, the ECC
detects this bit and replaces it with the correct value. The read reliability is therefore much
improved.
Even if the ECC function is performed on groups of four bytes, a single byte can be
written/cycled independently. In this case, the ECC function also writes/cycles the three
other bytes located in the same group(2). As a consequence, the maximum cycling budget is
defined at group level and the cycling can be distributed over the 4 bytes of the group: the
sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain
below the maximum value defined Table 10: Cycling performance.
1. Only for devices identified with process letter K
2.A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer.
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Instructions
5.1.6
M24M01-R M24M01-DF
Minimizing Write delays by polling on ACK
The maximum Write time (tw) is shown in AC characteristics tables in Section 8: DC and AC
parameters, but the typical time is shorter. To make use of this, a polling sequence can be
used by the bus master.
The sequence, as shown in Figure 9, is:
•
Initial condition: a Write cycle is in progress.
•
Step 1: the bus master issues a Start condition followed by a device select code (the
first byte of the new instruction).
•
Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
Figure 9. Write cycle polling flowchart using ACK
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