M29F200BT
M29F200BB
2 Mbit (256Kb x8 or 128Kb x16, Boot Block)
Single Supply Flash Memory
Features
■
Single 5V±10% supply voltage for Program,
Erase and Read operations
■
Access time: 45, 50, 70, 90ns
■
Programming time
– 8µs per Byte/Word typical
■
7 memory blocks
– 1 Boot Block (Top or Bottom location)
– 2 parameter and 4 main blocks
■
Program/Erase controller
– Embedded Byte/Word Program algorithm
– Embedded Multi-Block/Chip Erase
algorithm
– Status Register polling and toggle bits
– Ready/Busy output pin
■
TSOP48 (N)
12 x 20mm
44
Erase Suspend and Resume modes
– Read and Program another block during
Erase Suspend
■
Unlock Bypass Program command
– Faster Production/Batch Programming
■
Temporary Block Unprotection mode
■
Low power consumption
– Standby and Automatic Standby
■
100,000 Program/Erase cycles per block
■
20 years data retention
– Defectivity below 1 ppm/year
■
Electronic Signature
– Manufacturer code: 0020h
– Top Device code M29F200BT: 00D3h
– Bottom Device code: M29F200BB: 00D4h
■
ECOPACK® packages available
March 2007
1
SO44 (M)
Rev 5
1/39
www.st.com
1
Contents
M29F200BT, M29F200BB
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
4
2/39
2.1
Address Inputs (A0-A16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2
Data Inputs/Outputs (DQ0-DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3
Data Inputs/Outputs (DQ8-DQ14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4
Data Input/Output or Address Input (DQ15A-1) . . . . . . . . . . . . . . . . . . . . 10
2.5
Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.6
Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.7
Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.8
Reset/Block Temporary Unprotect (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.9
Ready/Busy Output (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.10
Byte/Word Organization Select (BYTE) . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.11
VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.12
Vss Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1
Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2
Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3
Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5
Automatic Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.6
Special Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.6.1
Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.6.2
Block Protection and Blocks Unprotection . . . . . . . . . . . . . . . . . . . . . . . 14
Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.0.1
Read/Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.0.2
Auto Select command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.0.3
Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.0.4
Unlock Bypass command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.0.5
Unlock Bypass Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
M29F200BT, M29F200BB
5
Contents
4.0.6
Unlock Bypass Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.0.7
Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.0.8
Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.0.9
Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.0.10
Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1
Data Polling Bit (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.2
Toggle Bit (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.3
Error Bit (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.4
Erase Timer Bit (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.5
Alternative Toggle Bit (DQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7
DC and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8
Package Mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Appendix A Block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3/39
List of tables
M29F200BT, M29F200BB
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
4/39
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Bus operations, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Bus operations, BYTE = VIH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Commands, 16-bit mode, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Commands, 8-bit mode, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Program, Erase times and Program, Erase endurance cycles
(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Capacitance (TA = 25 °C, f = 1 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DC characteristics (TA = 0 to 70°C, –40 to 85°C or –40 to 125°C). . . . . . . . . . . . . . . . . . . 29
Read ac characteristics (TA = 0 to 70°C, –40 to 85°C or –40 to 125°C) . . . . . . . . . . . . . . 30
Write ac characteristics, Write Enable controlled (TA = 0 to 70 °C,
–40 to 85 °C or –40 to 125 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Write AC Characteristics, Chip Enable Controlled
(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Reset/Block Temporary Unprotect AC Characteristics
(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data . . . 34
SO44 - 44 lead Plastic Small Outline, 500 mils body width, package mechanical data . . . 35
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Top Boot block addresses, M29F200BT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Bottom Boot Block Addresses, M29F200BB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
M29F200BT, M29F200BB
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SO connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
TSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Data polling flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Data toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
AC testing input output waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
AC testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Read Mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Write ac waveforms, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Write ac waveforms, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Reset/Block Temporary Unprotect ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, package outline . . . . . . . . . . . 34
SO44 - 44 lead Plastic Small Outline, 500 mils body width, package outline . . . . . . . . . . . 35
5/39
Description
1
M29F200BT, M29F200BB
Description
The M29F200B is a 2 Mbit (256Kb x8 or 128Kb x16) non-volatile memory that can be read,
erased and reprogrammed. These operations can be performed using a single 5V supply.
On power-up the memory defaults to its Read mode where it can be read in the same way
as a ROM or EPROM. The M29F200B is fully backward compatible with the M29F200.
The memory is divided into blocks that can be erased independently so it is possible to
preserve valid data while old data is erased. Each block can be protected independently to
prevent accidental Program or Erase commands from modifying the memory. Program and
Erase commands are written to the Command Interface of the memory. An on-chip
Program/Erase Controller simplifies the process of programming or erasing the memory by
taking care of all of the special operations that are required to update the memory contents.
The end of a program or erase operation can be detected and any error conditions
identified. The command set required to control the memory is consistent with JEDEC
standards.
The blocks in the memory are asymmetrically arranged, see Table 19 and Table 20, Block
Addresses. The first or last 64 KBytes have been divided into four additional blocks. The 16
KByte Boot Block can be used for small initialization code to start the microprocessor, the
two 8 KByte Parameter Blocks can be used for parameter storage and the remaining 32K is
a small Main Block where the application may be stored.
Chip Enable, Output Enable and Write Enable signals control the bus operation of the
memory. They allow simple connection to most microprocessors, often without additional
logic.
The memory is offered in TSOP48 (12 x 20mm) and SO44 packages and it is supplied with
all the bits erased (set to ’1’).
In order to meet environmental requirements, ST offers the M29F200B in ECOPACK®
packages.
ECOPACK packages are Lead-free. The category of second Level Interconnect is marked
on the package and on the inner box label, in compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
6/39
M29F200BT, M29F200BB
Table 1.
Description
Signal names
Name
Description
A0-A16
Direction
Address Inputs
Inputs
DQ0-DQ7
Data Inputs/Outputs
Input/Outputs
DQ8-DQ14
Data Inputs/Outputs
Input/Outputs
Data Input/Output or Address Input
Input/Output
DQ15A–1
E
Chip Enable
Input
G
Output Enable
Input
W
Write Enable
Input
RP
Reset/Block Temporary Unprotect
Input
RB
Ready/Busy Output
BYTE
Output
Byte/Word Organization Select
Input
VCC
Supply Voltage
VSS
Ground
-
NC
Not Connected Internally
-
Figure 1.
Supply
Logic diagram
VCC
17
15
A0-A16
DQ0-DQ14
DQ15A–1
W
E
M29F200BT
M29F200BB
G
BYTE
RB
RP
VSS
AI02912
7/39
Description
M29F200BT, M29F200BB
Figure 2.
SO connections
NC
RB
NC
A7
A6
A5
A4
A3
A2
A1
A0
E
VSS
G
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
1
44
2
43
3
42
4
41
5
40
6
39
7
38
8
37
9
36
10
35
11 M29F200BT 34
12 M29F200BB 33
13
32
14
31
15
30
16
29
28
17
27
18
26
19
25
20
21
24
22
23
AI02914
8/39
RP
W
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
VSS
DQ15A–1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
M29F200BT, M29F200BB
Figure 3.
Description
TSOP connections
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
W
RP
NC
NC
RB
NC
NC
A7
A6
A5
A4
A3
A2
A1
1
12
13
24
48
M29F200BT
M29F200BB
37
36
25
A16
BYTE
VSS
DQ15A–1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
VSS
E
A0
AI02913
9/39
Signal descriptions
2
M29F200BT, M29F200BB
Signal descriptions
See Figure 1: Logic diagram, and Table 1: Signal names, for a brief overview of the signals
connected to this device.
2.1
Address Inputs (A0-A16)
The Address Inputs select the cells in the memory array to access during Bus Read
operations. During Bus Write operations they control the commands sent to the Command
Interface of the internal state machine.
2.2
Data Inputs/Outputs (DQ0-DQ7)
The Data Inputs/Outputs output the data stored at the selected address during a Bus Read
operation. During Bus Write operations they represent the commands sent to the Command
Interface of the internal state machine.
2.3
Data Inputs/Outputs (DQ8-DQ14)
The Data Inputs/Outputs output the data stored at the selected address during a Bus Read
operation when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used and are
high impedance. During Bus Write operations the Command Register does not use these
bits. When reading the Status Register these bits should be ignored.
2.4
Data Input/Output or Address Input (DQ15A-1)
When BYTE is High, VIH, this pin behaves as a Data Input/Output pin (as DQ8-DQ14).
When BYTE is Low, VIL, this pin behaves as an address pin; DQ15A–1 Low will select the
LSB of the Word on the other addresses, DQ15A–1 High will select the MSB. Throughout
the text consider references to the Data Input/Output to include this pin when BYTE is High
and references to the Address Inputs to include this pin when BYTE is Low except when
stated explicitly otherwise.
2.5
Chip Enable (E)
The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to
be performed. When Chip Enable is High, VIH, all other pins are ignored.
2.6
Output Enable (G)
The Output Enable, G, controls the Bus Read operation of the memory.
10/39
M29F200BT, M29F200BB
2.7
Signal descriptions
Write Enable (W)
The Write Enable, W, controls the Bus Write operation of the memory’s Command Interface.
2.8
Reset/Block Temporary Unprotect (RP)
The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the
memory or to temporarily unprotect all Blocks that have been protected.
A Hardware Reset is achieved by holding Reset/Block Temporary Unprotect Low, VIL, for at
least tPLPX. After Reset/Block temporary unprotect goes High, VIH, the memory will be ready
for Bus Read and Bus Write operations after tPHEL or tRHEL, whichever occurs last. See the
Ready/Busy Output section, Table 15: Reset/Block Temporary Unprotect AC Characteristics
(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C) and Figure 11: Reset/Block Temporary
Unprotect ac waveforms, for more details.
Holding RP at VID will temporarily unprotect the protected Blocks in the memory. Program
and Erase operations on all blocks will be possible. The transition from VIH to VID must be
slower than tPHPHH.
2.9
Ready/Busy Output (RB)
The Ready/Busy pin is an open-drain output that can be used to identify when the memory
array can be read. Ready/Busy is high-impedance during Read mode, Auto Select mode
and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy
becomes high-impedance. See Table 15: Reset/Block Temporary Unprotect AC
Characteristics (TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C) and Figure 11: Reset/Block
Temporary Unprotect ac waveforms.
During Program or Erase operations Ready/Busy is Low, VOL. Ready/Busy will remain Low
during Read/Reset commands or Hardware Resets until the memory is ready to enter Read
mode.
The use of an open-drain output allows the Ready/Busy pins from several memories to be
connected to a single pull-up resistor. A Low will then indicate that one, or more, of the
memories is busy.
2.10
Byte/Word Organization Select (BYTE)
The Byte/Word Organization Select pin is used to switch between the 8-bit and 16-bit Bus
modes of the memory. When Byte/Word Organization Select is Low, VIL, the memory is in 8bit mode, when it is High, VIH, the memory is in 16-bit mode.
2.11
VCC Supply Voltage
The VCC Supply Voltage supplies the power for all operations (Read, Program, Erase etc.).
The Command Interface is disabled when the VCC Supply Voltage is less than the Lockout
Voltage, VLKO. This prevents Bus Write operations from accidentally damaging the data
during power up, power down and power surges. If the Program/Erase Controller is
11/39
Signal descriptions
M29F200BT, M29F200BB
programming or erasing during this time then the operation aborts and the memory contents
being altered will be invalid.
A 0.1µF capacitor should be connected between the VCC Supply Voltage pin and the VSS
Ground pin to decouple the current surges from the power supply. The PCB track widths
must be sufficient to carry the currents required during program and erase operations, ICC4.
2.12
Vss Ground
The VSS Ground is the reference for all voltage measurements.
12/39
M29F200BT, M29F200BB
3
Bus operations
Bus operations
There are five standard bus operations that control the device. These are Bus Read, Bus
Write, Output Disable, Standby and Automatic Standby. See Table 2 and Table 3, Bus
Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write
Enable are ignored by the memory and do not affect bus operations.
3.1
Bus Read
Bus Read operations read from the memory cells, or specific registers in the Command
Interface. A valid Bus Read operation involves setting the desired address on the Address
Inputs, applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write
Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 8: Read Mode
ac waveforms, and Table 12: Read ac characteristics (TA = 0 to 70°C, –40 to 85°C or –40 to
125°C), for details of when the output becomes valid.
3.2
Bus Write
Bus Write operations write to the Command Interface. A valid Bus Write operation begins by
setting the desired address on the Address Inputs. The Address Inputs are latched by the
Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs
last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of
Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH,
during the whole Bus Write operation. See Figure 9 and Figure 10, Write ac waveforms, and
Table 13 and Table 14, Write ac characteristics, for details of the timing requirements.
3.3
Output Disable
The Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH.
3.4
Standby
When Chip Enable is High, VIH, the Data Inputs/Outputs pins are placed in the highimpedance state and the Supply Current is reduced to the Standby level.
When Chip Enable is at VIH the Supply Current is reduced to the TTL Standby Supply
Current, ICC2. To further reduce the Supply Current to the CMOS Standby Supply Current,
ICC3, Chip Enable should be held within VCC ± 0.2V. For Standby current levels see
Table 11: DC characteristics (TA = 0 to 70°C, –40 to 85°C or –40 to 125°C).
During program or erase operations the memory will continue to use the Program/Erase
Supply Current, ICC4, for Program or Erase operations until the operation completes.
13/39
Bus operations
3.5
M29F200BT, M29F200BB
Automatic Standby
If CMOS levels (VCC ± 0.2V) are used to drive the bus and the bus is inactive for 150ns or
more the memory enters Automatic Standby where the internal Supply Current is reduced to
the CMOS Standby Supply Current, ICC3. The Data Inputs/Outputs will still output data if a
Bus Read operation is in progress.
3.6
Special Bus operations
Additional bus operations can be performed to read the Electronic Signature and also to
apply and remove Block Protection. These bus operations are intended for use by
programming equipment and are not usually used in applications. They require VID to be
applied to some pins.
3.6.1
Electronic Signature
The memory has two codes, the manufacturer code and the device code, that can be read
to identify the memory. These codes can be read by applying the signals listed in Table 2
and Table 3, Bus operations.
3.6.2
Block Protection and Blocks Unprotection
Each block can be separately protected against accidental Program or Erase. Protected
blocks can be unprotected to allow data to be changed.
There are two methods available for protecting and unprotecting the blocks, one for use on
programming equipment and the other for in-system use. For further information refer to
Application Note AN1122, Applying Protection and Unprotection to M29 Series Flash.
Table 2.
Bus operations, BYTE = VIL(1)
Data Inputs/Outputs
Operation
G
W
DQ14DQ8
DQ7-DQ0
Bus Read
VIL
VIL
VIH
Cell Address
Hi-Z
Data Output
Bus Write
VIL
VIH
VIL
Command Address
Hi-Z
Data Input
X
VIH
VIH
X
Hi-Z
Hi-Z
Standby
VIH
X
X
X
Hi-Z
Hi-Z
Read
Manufacturer
Code
VIL
VIL
VIH
A0 = VIL, A1 = VIL, A9 =
VID, Others VIL or VIH
Hi-Z
20h
VIH
A0 = VIH, A1 = VIL, A9 =
VID, Others VIL or VIH
Hi-Z
D3h
(M29F200BT)
D4h
(M29F200BB)
Output Disable
Read Device
Code
1. X = VIL or VIH.
14/39
E
Address Inputs
DQ15A–1, A0-A16
VIL
VIL
M29F200BT, M29F200BB
Table 3.
Bus operations
Bus operations, BYTE = VIH(1)
Operation
Address Inputs
A0-A16
Data Inputs/Outputs
DQ15A–1, DQ14-DQ0
E
G
W
Bus Read
VIL
VIL
VIH
Cell Address
Bus Write
VIL
VIH
VIL
Command Address
X
VIH
VIH
X
Hi-Z
Standby
VIH
X
X
X
Hi-Z
Read
Manufacturer
Code
VIL
VIL
VIH
A0 = VIL, A1 = VIL, A9 =
VID, Others VIL or VIH
0020h
Read Device
Code
VIL
VIL
VIH
A0 = VIH, A1 = VIL, A9 =
VID, Others VIL or VIH
00D3h (M29F200BT)
00D4h (M29F200BB)
Output Disable
Data Output
Data Input
1. X = VIL or VIH.
15/39
Command interface
4
M29F200BT, M29F200BB
Command interface
All Bus Write operations to the memory are interpreted by the Command Interface.
Commands consist of one or more sequential Bus Write operations. Failure to observe a
valid sequence of Bus Write operations will result in the memory returning to Read mode.
The long command sequences are imposed to maximize data security.
The address used for the commands changes depending on whether the memory is in 16bit or 8-bit mode. See either Table 4, or Table 5, depending on the configuration that is being
used, for a summary of the commands.
4.0.1
Read/Reset command
The Read/Reset command returns the memory to its Read mode where it behaves like a
ROM or EPROM. It also resets the errors in the Status Register. Either one or three Bus
Write operations can be used to issue the Read/Reset command.
If the Read/Reset command is issued during a Block Erase operation or following a
Programming or Erase error then the memory will take up to 10µs to abort. During the abort
period no valid data can be read from the memory. Issuing a Read/Reset command during a
Block Erase operation will leave invalid data in the memory.
4.0.2
Auto Select command
The Auto Select command is used to read the Manufacturer Code, the Device Code and the
Block Protection Status. Three consecutive Bus Write operations are required to issue the
Auto Select command. Once the Auto Select command is issued the memory remains in
Auto Select mode until another command is issued.
From the Auto Select mode the Manufacturer Code can be read using a Bus Read operation
with A0 = VIL and A1 = VIL. The other address bits may be set to either VIL or VIH. The
Manufacturer Code for STMicroelectronics is 0020h.
The Device Code can be read using a Bus Read operation with A0 = VIH and A1 = VIL. The
other address bits may be set to either VIL or VIH. The Device Code for the M29F200BT is
00D3h and for the M29F200BB is 00D4h.
The Block Protection Status of each block can be read using a Bus Read operation with A0
= VIL, A1 = VIH, and A12-A16 specifying the address of the block. The other address bits
may be set to either VIL or VIH. If the addressed block is protected then 01h is output on
Data Inputs/Outputs DQ0-DQ7, otherwise 00h is output.
4.0.3
Program command
The Program command can be used to program a value to one address in the memory array
at a time. The command requires four Bus Write operations, the final write operation latches
the address and data in the internal state machine and starts the Program/Erase Controller.
If the address falls in a protected block then the Program command is ignored, the data
remains unchanged. The Status Register is never read and no error condition is given.
During the program operation the memory will ignore all commands. It is not possible to
issue any command to abort or pause the operation. Typical program times are given in
Table 6. Bus Read operations during the program operation will output the Status Register
on the Data Inputs/Outputs. See the section on the Status Register for more details.
16/39
M29F200BT, M29F200BB
Command interface
After the program operation has completed the memory will return to the Read mode, unless
an error has occurred. When an error occurs the memory will continue to output the Status
Register. A Read/Reset command must be issued to reset the error condition and return to
Read mode.
Note that the Program command cannot change a bit set at ’0’ back to ’1’. One of the Erase
Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’.
4.0.4
Unlock Bypass command
The Unlock Bypass command is used in conjunction with the Unlock Bypass Program
command to program the memory. When the access time to the device is long (as with
some EPROM programmers) considerable time saving can be made by using these
commands. Three Bus Write operations are required to issue the Unlock Bypass command.
Once the Unlock Bypass command has been issued the memory will only accept the Unlock
Bypass Program command and the Unlock Bypass Reset command. The memory can be
read as if in Read mode.
4.0.5
Unlock Bypass Program command
The Unlock Bypass Program command can be used to program one address in memory at
a time. The command requires two Bus Write operations, the final write operation latches
the address and data in the internal state machine and starts the Program/Erase Controller.
The Program operation using the Unlock Bypass Program command behaves identically to
the Program operation using the Program command. A protected block cannot be
programmed; the operation cannot be aborted and the Status Register is read. Errors must
be reset using the Read/Reset command, which leaves the device in Unlock Bypass Mode.
See the Program command for details on the behavior.
4.0.6
Unlock Bypass Reset command
The Unlock Bypass Reset command can be used to return to Read/Reset mode from
Unlock Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass
Reset command.
4.0.7
Chip Erase command
The Chip Erase command can be used to erase the entire chip. Six Bus Write operations
are required to issue the Chip Erase Command and start the Program/Erase Controller.
If any blocks are protected then these are ignored and all the other blocks are erased. If all
of the blocks are protected the Chip Erase operation appears to start but will terminate
within about 100µs, leaving the data unchanged. No error condition is given when protected
blocks are ignored.
During the erase operation the memory will ignore all commands. It is not possible to issue
any command to abort the operation. Typical chip erase times are given in Table 6. All Bus
Read operations during the Chip Erase operation will output the Status Register on the Data
Inputs/Outputs. See the section on the Status Register for more details.
After the Chip Erase operation has completed the memory will return to the Read Mode,
unless an error has occurred. When an error occurs the memory will continue to output the
Status Register. A Read/Reset command must be issued to reset the error condition and
return to Read Mode.
17/39
Command interface
M29F200BT, M29F200BB
The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ’1’. All
previous data is lost.
4.0.8
Block Erase command
The Block Erase command can be used to erase a list of one or more blocks. Six Bus Write
operations are required to select the first block in the list. Each additional block in the list can
be selected by repeating the sixth Bus Write operation using the address of the additional
block. The Block Erase operation starts the Program/Erase Controller about 50µs after the
last Bus Write operation. Once the Program/Erase Controller starts it is not possible to
select any more blocks. Each additional block must therefore be selected within 50µs of the
last block. The 50µs timer restarts when an additional block is selected. The Status Register
can be read after the sixth Bus Write operation. See the Status Register for details on how
to identify if the Program/Erase Controller has started the Block Erase operation.
If any selected blocks are protected then these are ignored and all the other selected blocks
are erased. If all of the selected blocks are protected the Block Erase operation appears to
start but will terminate within about 100µs, leaving the data unchanged. No error condition is
given when protected blocks are ignored.
During the Block Erase operation the memory will ignore all commands except the Erase
Suspend and Read/Reset commands. Typical block erase times are given in Table 6. All
Bus Read operations during the Block Erase operation will output the Status Register on the
Data Inputs/Outputs. See the section on the Status Register for more details.
After the Block Erase operation has completed the memory will return to the Read Mode,
unless an error has occurred. When an error occurs the memory will continue to output the
Status Register. A Read/Reset command must be issued to reset the error condition and
return to Read mode.
The Block Erase Command sets all of the bits in the unprotected selected blocks to ’1’. All
previous data in the selected blocks is lost.
4.0.9
Erase Suspend command
The Erase Suspend Command may be used to temporarily suspend a Block Erase
operation and return the memory to Read mode. The command requires one Bus Write
operation.
The Program/Erase Controller will suspend within 15µs of the Erase Suspend Command
being issued. Once the Program/Erase Controller has stopped the memory will be set to
Read mode and the Erase will be suspended. If the Erase Suspend command is issued
during the period when the memory is waiting for an additional block (before the
Program/Erase Controller starts) then the Erase is suspended immediately and will start
immediately when the Erase Resume Command is issued. It will not be possible to select
any further blocks for erasure after the Erase Resume.
During Erase Suspend it is possible to Read and Program cells in blocks that are not being
erased; both Read and Program operations behave as normal on these blocks. Reading
from blocks that are being erased will output the Status Register. It is also possible to enter
the Auto Select mode: the memory will behave as in the Auto Select mode on all blocks until
a Read/Reset command returns the memory to Erase Suspend mode.
18/39
M29F200BT, M29F200BB
4.0.10
Command interface
Erase Resume command
The Erase Resume command must be used to restart the Program/Erase Controller from
Erase Suspend. An erase can be suspended and resumed more than once.
Table 4.
Commands, 16-bit mode, BYTE = VIH
Command
Length
Bus Write operations
1st
2nd
3rd
4th
5th
6th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
1
X
F0
3
555
AA
2AA
55
X
F0
Auto Select
3
555
AA
2AA
55
555
90
Program
4
555
AA
2AA
55
555
A0
Unlock Bypass
3
555
AA
2AA
55
555
20
Unlock Bypass
Program
2
X
A0
PA
PD
Unlock Bypass Reset
2
X
90
X
00
Chip Erase
6
555
AA
2AA
55
555
Block Erase
6+
555
AA
2AA
55
555
Erase Suspend
1
X
B0
Erase Resume
1
X
30
Read/Reset
PA
PD
80
555
AA
2AA
55
555
10
80
555
AA
2AA
55
BA
30
19/39
Command interface
M29F200BT, M29F200BB
Commands, 8-bit mode, BYTE = VIL(1)(2)(3)
Table 5.
Command
Length
Bus Write operations
1st
2nd
3rd
4th
5th
6th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
1
X
F0
3
AAA
AA
555
55
X
F0
3
AAA
AA
555
55
AAA
90
4
AAA
AA
555
55
AAA
A0
Unlock Bypass
3
AAA
AA
555
55
AAA
20
Unlock Bypass
Program(6)
2
X
A0
PA
PD
Unlock Bypass Reset(8)
2
X
90
X
00
(6)
6
AAA
AA
555
55
AAA
555
55
AAA
Read/Reset(4)
(5)
Auto Select
Program(6)
(7)
Chip Erase
(6)
6+ AAA
AA
(9)
Erase Suspend
1
X
B0
Erase Resume(10)
1
X
30
Block Erase
PA
PD
80
AAA
AA
555
55
AAA
10
80
AAA
AA
555
55
BA
30
1. X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block.
2. All values in the table are in hexadecimal.
3. The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A16, DQ8-DQ14 and DQ15
are Don’t Care. DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH.
4. After a Read/Reset command, read the memory as normal until another command is issued.
5. After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status.
6. After a Program, Unlock Bypass Program, Chip Erase, or Block Erase command, read the Status Register until the
Program/Erase Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase
Command with additional Bus Write Operations until the Timeout Bit is set.
7. After the Unlock Bypass command, issue Unlock Bypass Program or Unlock Bypass Reset commands.
8. After the Unlock Bypass Reset command read the memory as normal until another command is issued.
9. After the Erase Suspend command, read non-erasing memory blocks as normal, issue Auto Select and Program
commands on non-erasing blocks as normal.
10. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the
Program/Erase Controller completes and the memory returns to Read Mode.
20/39
M29F200BT, M29F200BB
Table 6.
Command interface
Program, Erase times and Program, Erase endurance cycles
(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C)
Typ(1)
Typical after
100k W/E Cycles(1)
Chip Erase (All bits in the memory set to ‘0’)
0.8
0.8
Chip Erase
2.5
2.5
10
s
Block Erase (64 Kbytes)
0.6
0.6
4
s
Program (Byte or Word)
8
8
150
µs
Chip Program (Byte by Byte)
2.3
2.3
9
s
Chip Program (Word by Word)
1.2
1.2
4.5
s
Parameter
Program/Erase Cycles (per Block)
Min
100,000
Max
Unit
s
cycles
1. TA = 25°C, VCC = 5V.
21/39
Status register
5
M29F200BT, M29F200BB
Status register
Bus Read operations from any address always read the Status Register during Program and
Erase operations. It is also read during Erase Suspend when an address within a block
being erased is accessed.
The bits in the Status Register are summarized in Table 7: Status Register Bits.
5.1
Data Polling Bit (DQ7)
The Data Polling Bit can be used to identify whether the Program/Erase Controller has
successfully completed its operation or if it has responded to an Erase Suspend. The Data
Polling Bit is output on DQ7 when the Status Register is read.
During Program operations the Data Polling Bit outputs the complement of the bit being
programmed to DQ7. After successful completion of the Program operation the memory
returns to Read mode and Bus Read operations from the address just programmed output
DQ7, not its complement.
During Erase operations the Data Polling Bit outputs ’0’, the complement of the erased state
of DQ7. After successful completion of the Erase operation the memory returns to Read
Mode.
In Erase Suspend mode the Data Polling Bit will output a ’1’ during a Bus Read operation
within a block being erased. The Data Polling Bit will change from a ’0’ to a ’1’ when the
Program/Erase Controller has suspended the Erase operation.
Figure 4: Data polling flowchart, gives an example of how to use the Data Polling Bit. A Valid
Address is the address being programmed or an address within the block being erased.
5.2
Toggle Bit (DQ6)
The Toggle Bit can be used to identify whether the Program/Erase Controller has
successfully completed its operation or if it has responded to an Erase Suspend. The Toggle
Bit is output on DQ6 when the Status Register is read.
During Program and Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with
successive Bus Read operations at any address. After successful completion of the
operation the memory returns to Read mode.
During Erase Suspend mode the Toggle Bit will output when addressing a cell within a block
being erased. The Toggle Bit will stop toggling when the Program/Erase Controller has
suspended the Erase operation.
Figure 5: Data toggle flowchart, gives an example of how to use the Data Toggle Bit.
5.3
Error Bit (DQ5)
The Error Bit can be used to identify errors detected by the Program/Erase Controller. The
Error Bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to write the
correct data to the memory. If the Error Bit is set a Read/Reset command must be issued
22/39
M29F200BT, M29F200BB
Status register
before other commands are issued. The Error bit is output on DQ5 when the Status Register
is read.
Note that the Program command cannot change a bit set at ’0’ back to ’1’ and attempting to
do so may or may not set DQ5 at ‘1’. In both cases, a successive Bus Read operation will
show the bit is still ’0’. One of the Erase commands must be used to set all the bits in a block
or in the whole memory from ’0’ to ’1’.
5.4
Erase Timer Bit (DQ3)
The Erase Timer Bit can be used to identify the start of Program/Erase Controller operation
during a Block Erase command. Once the Program/Erase Controller starts erasing the
Erase Timer Bit is set to ’1’. Before the Program/Erase Controller starts the Erase Timer Bit
is set to ’0’ and additional blocks to be erased may be written to the Command Interface.
The Erase Timer Bit is output on DQ3 when the Status Register is read.
5.5
Alternative Toggle Bit (DQ2)
The Alternative Toggle Bit can be used to monitor the Program/Erase controller during
Erase operations. The Alternative Toggle Bit is output on DQ2 when the Status Register is
read.
During Chip Erase and Block Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’,
etc., with successive Bus Read operations from addresses within the blocks being erased.
Once the operation completes the memory returns to Read mode.
During Erase Suspend the Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with
successive Bus Read operations from addresses within the blocks being erased. Bus Read
operations to addresses within blocks not being erased will output the memory cell data as if
in Read mode.
After an Erase operation that causes the Error Bit to be set the Alternative Toggle Bit can be
used to identify which block or blocks have caused the error. The Alternative Toggle Bit
changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read Operations from addresses
within blocks that have not erased correctly. The Alternative Toggle Bit does not change if
the addressed block has erased correctly.
23/39
Status register
M29F200BT, M29F200BB
Table 7.
Status Register Bits(1)
Operation
Address
DQ7
DQ6
DQ5
DQ3
DQ2
RB
Program
Any Address
DQ7
Toggle
0
–
–
0
Program during
Erase Suspend
Any Address
DQ7
Toggle
0
–
–
0
Program Error
Any Address
DQ7
Toggle
1
–
–
0
Chip Erase
Any Address
0
Toggle
0
1
Toggle
0
Erasing Block
0
Toggle
0
0
Toggle
0
Non-Erasing Block
0
Toggle
0
0
No
Toggle
0
Erasing Block
0
Toggle
0
1
Toggle
0
Non-Erasing Block
0
Toggle
0
1
No
Toggle
0
Erasing Block
1
No
Toggle
0
–
Toggle
1
Block Erase before
timeout
Block Erase
Erase Suspend
Non-Erasing Block
Data read as normal
1
Good Block
Address
0
Toggle
1
1
No
Toggle
0
Faulty Block
Address
0
Toggle
1
1
Toggle
0
Erase Error
1. Unspecified data bits should be ignored.
24/39
M29F200BT, M29F200BB
Figure 4.
Status register
Data polling flowchart
START
READ DQ5 & DQ7
at VALID ADDRESS
DQ7
=
DATA
YES
NO
NO
DQ5
=1
YES
READ DQ7
at VALID ADDRESS
DQ7
=
DATA
YES
NO
FAIL
PASS
AI03598
25/39
Status register
Figure 5.
M29F200BT, M29F200BB
Data toggle flowchart
START
READ
DQ5 & DQ6
READ DQ6
DQ6
=
TOGGLE
NO
YES
NO
DQ5
=1
YES
READ DQ6
TWICE
DQ6
=
TOGGLE
NO
YES
FAIL
PASS
AI01370B
26/39
M29F200BT, M29F200BB
6
Maximum rating
Maximum rating
Stressing the device above the rating listed in the Absolute Maximum Ratings table may
cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions
for extended periods may affect device reliability. These are stress ratings only and
operation of the device at these or any other conditions above those indicated in the
Operating sections of this specification is not implied. Refer also to the STMicroelectronics
SURE Program and other relevant quality documents.
Table 8.
Absolute maximum ratings(1)
Symbol
Value
Unit
Ambient operating temperature (temperature range
option 1)
0 to 70
°C
Ambient operating temperature (temperature range
option 6)
–40 to 85
°C
Ambient Operating Temperature (Temperature Range
Option 3)
–40 to 125
°C
TBIAS
Temperature under bias
–50 to 125
°C
TSTG
Storage temperature
–65 to 150
°C
VIO(2)
Input or output voltage
–0.6 to 6
V
VCC
Supply Voltage
–0.6 to 6
V
VID
Identification voltage
–0.6 to 13.5
V
TA
Parameter
1. Except for the Operating Temperature Range, stresses above those listed in the Table 8: Absolute
maximum ratings may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods
may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant
quality documents.
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.
27/39
DC and ac parameters
7
M29F200BT, M29F200BB
DC and ac parameters
This section summarizes the operating measurement conditions, and the dc and ac
characteristics of the device. The parameters in the dc and ac characteristics Tables that
follow, are derived from tests performed under the Measurement Conditions summarized in
Table 9: Operating and ac measurement conditions. Designers should check that the
operating conditions in their circuit match the operating conditions when relying on the
quoted parameters.
Table 9.
Operating and ac measurement conditions
M29F200B
Parameter
45 / 50
70 / 90
High Speed
Standard
30pF
100pF
Input Rise and Fall Times
≤ 10ns
≤ 10ns
Input Pulse Voltages
0 to 3V
0.45 to 2.4V
1.5V
0.8V and 2.0V
AC Test Conditions
Load Capacitance (CL)
Input and Output Timing Ref. Voltages
Table 10.
Symbol
CIN
COUT
Capacitance (TA = 25 °C, f = 1 MHz)(1)
Parameter
Input Capacitance
Output Capacitance
Test condition
Min
Max
Unit
VIN = 0V
6
pF
VOUT = 0V
12
pF
1. Sampled only, not 100% tested.
Figure 6.
AC testing input output waveform
High Speed
3V
1.5V
0V
Standard
2.4V
0.45V
2.0V
0.8V
AI01275B
28/39
M29F200BT, M29F200BB
Figure 7.
DC and ac parameters
AC testing load circuit
1.3V
1N914
3.3kΩ
DEVICE
UNDER
TEST
OUT
CL = 30pF or 100pF
CL includes JIG capacitance
Table 11.
Symbol
AI03027
DC characteristics (TA = 0 to 70°C, –40 to 85°C or –40 to 125°C)
Parameter
Test Condition
Min
Typ(1)
Max
Unit
0V ≤ VIN ≤ VCC
±1
µA
±1
µA
20
mA
1
mA
100
µA
20
mA
ILI
Input Leakage Current
ILO
Output Leakage Current
0V ≤ VOUT ≤ VCC
ICC1
Supply Current (Read)
E = VIL, G = VIH,
f = 6MHz
ICC2
Supply Current (Standby) TTL
ICC3
Supply Current (Standby)
CMOS
E = VCC ±0.2V,
RP = VCC ±0.2V
ICC4(2)
Supply Current
(Program/Erase)
Program/Erase
Controller active
VIL
Input Low Voltage
–0.5
0.8
V
VIH
Input High Voltage
2
VCC +0.5
V
VOL
Output Low Voltage
0.45
V
VOH
E = VIH
30
IOL = 5.8mA
Output High Voltage TTL
IOH = –2.5mA
2.4
V
Output High Voltage CMOS
IOH = –100µA
VCC –0.4
V
VID
Identification Voltage
IID
Identification Current
VLKO(2)
6
Program/Erase Lockout Supply
Voltage
11.5
A9 = VID
3.2
12.5
V
100
µA
4.2
V
1. TA = 25°C, VCC = 5V.
2. Sampled only, not 100% tested.
29/39
DC and ac parameters
Table 12.
M29F200BT, M29F200BB
Read ac characteristics (TA = 0 to 70°C, –40 to 85°C or –40 to 125°C)
M29F200B
Symbol
Alt
Parameter
Test Condition
Unit
45
50
70 / 90
tAVAV
tRC
Address Valid to Next Address
Valid
E = VIL,
G = VIL
Min
45
50
70
ns
tAVQV
tACC
Address Valid to Output Valid
E = VIL,
G = VIL
Max
45
50
70
ns
tELQX(1)
tLZ
Chip Enable Low to Output
Transition
G = VIL
Min
0
0
0
ns
tELQV
tCE
Chip Enable Low to Output Valid
G = VIL
Max
45
50
70
ns
tGLQX(1)
tOLZ
Output Enable Low to Output
Transition
E = VIL
Min
0
0
0
ns
tGLQV
tOE
Output Enable Low to Output Valid
E = VIL
Max
25
30
30
ns
tEHQZ(1)
tHZ
Chip Enable High to Output Hi-Z
G = VIL
Max
15
18
20
ns
tGHQZ(1)
tDF
Output Enable High to Output Hi-Z
E = VIL
Max
15
18
20
ns
tEHQX
tGHQX
tAXQX
tOH
Chip Enable, Output Enable or
Address Transition to Output
Transition
Min
0
0
0
ns
tELBL
tELBH
tELFL
tELFH
Chip Enable to BYTE Low or High
Max
5
5
5
ns
tBLQZ
tFLQZ
BYTE Low to Output Hi-Z
Max
15
15
20
ns
tBHQV
tFHQV
BYTE High to Output Valid
Max
30
30
30
ns
1. Sampled only, not 100% tested.
Figure 8.
Read Mode ac waveforms
tAVAV
A0-A16/
A–1
VALID
tAVQV
tAXQX
E
tELQV
tEHQX
tELQX
tEHQZ
G
tGLQX
tGHQX
tGLQV
tGHQZ
DQ0-DQ7/
DQ8-DQ15
VALID
tBHQV
BYTE
tELBL/tELBH
30/39
tBLQZ
AI02915
M29F200BT, M29F200BB
Table 13.
DC and ac parameters
Write ac characteristics, Write Enable controlled (TA = 0 to 70 °C,
–40 to 85 °C or –40 to 125 °C)
M29F200B
Symbol
Alt
Parameter
Unit
45
50
70 / 90
tAVAV
tWC
Address Valid to Next Address Valid
Min
45
50
70
ns
tELWL
tCS
Chip Enable Low to Write Enable Low
Min
0
0
0
ns
tWLWH
tWP
Write Enable Low to Write Enable High
Min
40
40
45
ns
tDVWH
tDS
Input Valid to Write Enable High
Min
25
25
30
ns
tWHDX
tDH
Write Enable High to Input Transition
Min
0
0
0
ns
tWHEH
tCH
Write Enable High to Chip Enable High
Min
0
0
0
ns
tWHWL
tWPH
Write Enable High to Write Enable Low
Min
20
20
20
ns
tAVWL
tAS
Address Valid to Write Enable Low
Min
0
0
0
ns
tWLAX
tAH
Write Enable Low to Address Transition
Min
40
40
45
ns
Output Enable High to Write Enable Low
Min
0
0
0
ns
tOEH
Write Enable High to Output Enable Low
Min
0
0
0
ns
tBUSY
Program/Erase Valid to RB Low
Max
30
30
30
ns
tVCS
VCC High to Chip Enable Low
Min
50
50
50
µs
tGHWL
tWHGL
tWHRL
(1)
tVCHEL
1. Sampled only, not 100% tested.
Figure 9.
Write ac waveforms, Write Enable controlled
tAVAV
A0-A16/
A–1
VALID
tWLAX
tAVWL
tWHEH
E
tELWL
tWHGL
G
tGHWL
tWLWH
W
tWHWL
tDVWH
DQ0-DQ7/
DQ8-DQ15
tWHDX
VALID
VCC
tVCHEL
RB
tWHRL
AI01991
31/39
DC and ac parameters
Table 14.
M29F200BT, M29F200BB
Write AC Characteristics, Chip Enable Controlled
(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C)
M29F200B
Symbol
Alt
Parameter
Unit
45
50
70 / 90
tAVAV
tWC
Address Valid to Next Address Valid
Min
45
50
70
ns
tWLEL
tWS
Write Enable Low to Chip Enable Low
Min
0
0
0
ns
tELEH
tCP
Chip Enable Low to Chip Enable High
Min
40
40
45
ns
tDVEH
tDS
Input Valid to Chip Enable High
Min
25
25
30
ns
tEHDX
tDH
Chip Enable High to Input Transition
Min
0
0
0
ns
tEHWH
tWH
Chip Enable High to Write Enable High
Min
0
0
0
ns
tEHEL
tCPH
Chip Enable High to Chip Enable Low
Min
20
20
20
ns
tAVEL
tAS
Address Valid to Chip Enable Low
Min
0
0
0
ns
tELAX
tAH
Chip Enable Low to Address Transition
Min
40
40
45
ns
Output Enable High Chip Enable Low
Min
0
0
0
ns
tGHEL
tEHGL
tOEH
Chip Enable High to Output Enable Low
Min
0
0
0
ns
tEHRL(1)
tBUSY
Program/Erase Valid to RB Low
Max
30
30
30
ns
tVCHWL
tVCS
VCC High to Write Enable Low
Min
50
50
50
µs
1. Sampled only, not 100% tested.
Figure 10. Write ac waveforms, Chip Enable controlled
tAVAV
A0-A16/
A–1
VALID
tELAX
tAVEL
tEHWH
W
tWLEL
tEHGL
G
tGHEL
tELEH
E
tEHEL
tDVEH
DQ0-DQ7/
DQ8-DQ15
tEHDX
VALID
VCC
tVCHWL
RB
tEHRL
32/39
AI01992
M29F200BT, M29F200BB
Table 15.
DC and ac parameters
Reset/Block Temporary Unprotect AC Characteristics
(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C)
M29F200B
Symbol
Alt
Parameter
Unit
45
50
70 / 90
tPHWL(1)
tPHEL
tPHGL(1)
tRH
RP High to Write Enable Low, Chip Enable
Low, Output Enable Low
Min
50
50
50
ns
tRHWL(1)
tRHEL(1)
tRHGL(1)
tRB
RB High to Write Enable Low, Chip Enable
Low, Output Enable Low
Min
0
0
0
ns
tPLPX
tRP
RP Pulse Width
Min
500
500
500
ns
RP Low to Read Mode
Max
10
10
10
µs
RP Rise Time to VID
Min
500
500
500
ns
tPLYH
(1)
tPHPHH(1)
tREADY
tVIDR
1. Sampled only, not 100% tested.
Figure 11. Reset/Block Temporary Unprotect ac waveforms
W, E, G
tPHWL, tPHEL, tPHGL
RB
tRHWL, tRHEL, tRHGL
RP
tPLPX
tPHPHH
tPLYH
AI02931
33/39
Package Mechanical
8
M29F200BT, M29F200BB
Package Mechanical
Figure 12. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, package outline
1
48
e
D1
B
24
L1
25
A2
E1
E
A
A1
DIE
α
L
C
CP
TSOP-G
1. Drawing is not to scale.
Table 16.
TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
A
Typ
Min
1.200
Max
0.0472
A1
0.100
0.050
0.150
0.0039
0.0020
0.0059
A2
1.000
0.950
1.050
0.0394
0.0374
0.0413
B
0.220
0.170
0.270
0.0087
0.0067
0.0106
0.100
0.210
0.0039
0.0083
C
CP
34/39
Max
0.100
0.0039
D1
12.000
11.900
12.100
0.4724
0.4685
0.4764
E
20.000
19.800
20.200
0.7874
0.7795
0.7953
E1
18.400
18.300
18.500
0.7244
0.7205
0.7283
e
0.500
–
–
0.0197
–
–
L
0.600
0.500
0.700
0.0236
0.0197
0.0276
L1
0.800
α
3
0
5
0.0315
0
5
3
M29F200BT, M29F200BB
Package Mechanical
Figure 13. SO44 - 44 lead Plastic Small Outline, 500 mils body width, package outline
D
44
23
c
E1 E
θ
1
22
A1
A2
b
A
L
L1
ddd
e
SO-F
1. Drawing is not to scale.
Table 17.
SO44 - 44 lead Plastic Small Outline, 500 mils body width, package mechanical data
millimeters
inches
Symbol
Typ
Min
A
Max
Min
3.00
A1
0.10
A2
2.69
2.79
b
0.35
c
28.50
Max
0.118
0.004
2.56
D
Typ
0.101
0.110
0.50
0.014
0.020
0.18
0.28
0.007
0.011
28.37
28.63
1.117
1.127
ddd
0.106
1.122
0.10
0.004
E
16.03
15.77
16.28
0.631
0.621
0.641
E1
12.60
12.47
12.73
0.496
0.491
0.501
e
1.27
–
–
0.050
–
–
L
0.79
0.031
L1
1.73
0.068
Θ
N
8
44
8
44
35/39
Part numbering
9
M29F200BT, M29F200BB
Part numbering
Table 18.
Ordering information scheme
Example:
M29F200BB
50
N
1
T
Device Type
M29
Operating Voltage
F = VCC = 5V ± 10%
Device Function
200B = 2 Mbit (256Kb x8 or 128Kb x16), Boot Block
Array Matrix
T = Top Boot
B = Bottom Boot
Speed
45 = 45 ns
50 = 50 ns(1)
70 = 70 ns
90 = 90 ns
Package
N = TSOP48: 12 x 20 mm
M = SO44 500mm width
Temperature Range
1 = 0 to 70 °C
3 = –40 to 125 °C
6 = –40 to 85 °C
Option
Blank = Standard Packing
T = Tape & Reel Packing
E = ECOPACK Package, Standard Packing
F = ECOPACK Package, Tape & Reel Packing
1. 50ns speed devices are only available in M29F200BB in Temperature Range option 3.
The last two characters of the ordering code may be replaced by a letter code for
preprogrammed parts, otherwise devices are shipped from the factory with the memory
content bits erased to ’1’.
For a list of available options (Speed, Package, etc...) or for further information on any
aspect of this device, please contact the ST Sales Office nearest to you.
36/39
M29F200BT, M29F200BB
Appendix A
Table 19.
Block addresses
Block addresses
Top Boot block addresses, M29F200BT
#
Size
(Kbytes)
Address Range
(x8)
Address Range
(x16)
6
16
3C000h-3FFFFh
1E000h-1FFFFh
5
8
3A000h-3BFFFh
1D000h-1DFFFh
4
8
38000h-39FFFh
1C000h-1CFFFh
3
32
30000h-37FFFh
18000h-1BFFFh
2
64
20000h-2FFFFh
10000h-17FFFh
1
64
10000h-1FFFFh
08000h-0FFFFh
0
64
00000h-0FFFFh
00000h-07FFFh
Table 20.
Bottom Boot Block Addresses, M29F200BB
#
Size
(Kbytes)
Address Range
(x8)
Address Range
(x16)
6
64
30000h-3FFFFh
18000h-1FFFFh
5
64
20000h-2FFFFh
10000h-17FFFh
4
64
10000h-1FFFFh
08000h-0FFFFh
3
32
08000h-0FFFFh
04000h-07FFFh
2
8
06000h-07FFFh
03000h-03FFFh
1
8
04000h-05FFFh
02000h-02FFFh
0
16
00000h-03FFFh
00000h-01FFFh
37/39
Revision history
10
M29F200BT, M29F200BB
Revision history
Table 21.
Document revision history
Date
Revision
July 1999
1.0
First Issue
2.0
Chip Erase Max. specification added (Table 6)
Block Erase Max. specification added (Table 6)
Program Max. specification added (Table 6)
Chip Program Max. specification added (Table 6)
ICC1 and ICC3 Typ. specification added (Table 11)
ICC3 Test Condition changed (Table 11)
3.0
New document template
Document type: from Preliminary Data to Data Sheet
Status Register bit DQ5 clarification
Data Polling Flowchart diagram change (Figure 4)
Data Toggle Flowchart diagram change (Figure 5)
19-Sep-2005
4.0
Document restructured.
Table 18: Ordering information scheme: standard package added and
ECOPACK version added for both standard package and Tape & Reel
packing. Note 1 modified.
55ns speed class replaced by 50ns.
TSOP48 mechanical data updated, and SO44 525mm body width
changed to SO44 500mm body width.
22-Mar-2007
5
10/08/99
07/28/00
38/39
Changes
Document restructured.
SO44 package code changed to ‘M’ inSection : Features and in Table 18:
Ordering information scheme.
M29F200BT, M29F200BB
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