S4DNF30L

STS4DNF30L Dual N-channel 30V - 0.039Ω - 4A SO-8 STripFET™ Power MOSFET General features Type STS4DNF30L ■ ■ VDSS 30V RDS(on) ID(on) x RDS(on)max,, ID= 4 A Min. 1 Typ. 3 330 90 40 6.5 3.6 2 9 Max. Unit S pF pF pF nC nC nC 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 . Table 5. Symbol td(on) tr td(off) tf Switching times Parameter Turn-on delay time Rise time Turn-off Delay Time Fall Time Test conditions VDD=15 V, ID=2A, RG=4.7Ω, VGS= 4.5V (see Figure 12) VDD=15 V, ID=2A, RG=4.7Ω, VGS= 4.5V (see Figure 12) Min. Typ. 11 100 25 22 Max. Unit ns ns ns ns 4/12 STS4DNF30L Table 6. Symbol ISD ISDM VSD (1) (2) Electrical characteristics Source drain diode Parameter Source-drain current Source-drain current (pulsed) Forward on voltage Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 4A, VGS = 0 ISD = 4A, VDD = 20V di/dt = 100A/µs, Tj = 150°C (see Figure 14) 30 18 1.2 Test conditions Min Typ. Max 4 16 1.2 Unit A A V ns nC A trr Qrr IRRM 1. Pulse width limited by safe operating area. 2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % 5/12 Electrical characteristics STS4DNF30L 2.1 Figure 1. Electrical characteristics (curves) Safe operating area Figure 2. Thermal impedance Figure 3. Output characterisics Figure 4. Transfer characteristics Figure 5. Transconductance Figure 6. Static drain-source on resistance 6/12 STS4DNF30L Figure 7. Gate charge vs gate-source voltage Figure 8. Electrical characteristics Capacitance variations Figure 9. Normalized gate threshold voltage vs temperature Figure 10. Normalized on resistance vs temperature Figure 11. Source-drain diode forward characteristics 7/12 Test circuit STS4DNF30L 3 Test circuit Figure 13. Gate charge test circuit Figure 12. Switching times test circuit for resistive load Figure 14. Test circuit for inductive load Figure 15. Unclamped Inductive load test switching and diode recovery times circuit Figure 16. Unclamped inductive waveform Figure 17. Switching time waveform 8/12 STS4DNF30L Package mechanical data 4 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at : www.st.com 9/12 Package mechanical data STS4DNF30L SO-8 MECHANICAL DATA DIM. A a1 a2 a3 b b1 C c1 D E e e3 F L M S 3.8 0.4 4.8 5.8 1.27 3.81 4.0 1.27 0.6 8 (max.) 0.14 0.015 5.0 6.2 0.65 0.35 0.19 0.25 0.1 mm. MIN. TYP MAX. 1.75 0.25 1.65 0.85 0.48 0.25 0.5 45 (typ.) 0.188 0.228 0.050 0.150 0.157 0.050 0.023 0.196 0.244 0.025 0.013 0.007 0.010 0.003 MIN. inch TYP. MAX. 0.068 0.009 0.064 0.033 0.018 0.010 0.019 10/12 STS4DNF30L Revision history 5 Revision history Table 7. Date 11-Sep-2006 15-Nov-2006 Revision history Revision 1 2 First version The document has been reformated Changes 11/12 STS4DNF30L Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. 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