ST1L05DPUR

ST1L05 Very low quiescent current BiCMOS voltage regulator Datasheet - production data Description The ST1L05 is a low drop linear voltage regulator, which supplies up to 1.3 A output current. DFN6 (3x3 mm) DFN8 (4x4 mm) Features • Fixed output voltage: 1.8 V, 2.5 V, 3.3 V and ADJ • Output voltage tolerance: ± 2% at 25 °C • Output current capability: 1.3 A • Very low quiescent current: max. 650 µA • Typ. dropout 0.3 V (@ IO = 1.3 A) • Enable function for B, C and D versions • Power Good function for B and D versions • Stable with low ESR ceramic capacitors • Thermal shutdown protection with hysteresis The output voltage is fixed at 1.8 V, 2.5 V, 3.3 V and it is adjustable. It is available in three different versions with different pinouts. Thanks to BiCMOS technology, the quiescent current is controlled and maintained below 650 µA over the entire allowed junction temperature range. The ST1L05 is stable with low ESR output ceramic capacitors. Internal protection circuitry includes thermal protection with hysteresis and overcurrent limiting. The ST1L05 is suitable for data storage applications such as HDDs, where it can supply 3.3 V required by read channel and memory chips. The regulator is available in the small and thin DFN6 (3x3 mm) and DFN8 (4x4 mm) packages. • Overcurrent protection • Operating junction temperature range: from 0 to 125 °C Table 1. Device summary Order codes Package Output voltage ST1L05PU25R DFN6 (3x3 mm) 2.5 V ST1L05APU33R DFN6 (3x3 mm) 3.3 V ST1L05BPUR DFN6 (3x3 mm) ADJ ST1L05CPU33R DFN6 (3x3 mm) 3.3 V ST1L05DPUR DFN8 (4x4 mm) ADJ May 2014 This is information on a product in full production. DocID14492 Rev 3 1/30 www.st.com Contents ST1L05 Contents 1 Schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.1 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.2 Enable function (ST1L05B, ST1L05C and ST1L05D only) . . . . . . . . . . . 20 6.3 Power Good function (ST1L05B and ST1L05D only) . . . . . . . . . . . . . . . . 20 7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2/30 DocID14492 Rev 3 ST1L05 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ESD data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ST1L05PU25R electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 ST1L05APU33R electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 ST1L05CPU33R electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ST1L05BPUR and ST1L05DPUR electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 12 DFN6 (3x3 mm) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DFN8 (4x4 mm) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 DFN6 (3x3 mm) tape and reel mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 DFN8 (4x4 mm) reel mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 DocID14492 Rev 3 3/30 30 List of figures ST1L05 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. 4/30 ST1L05 schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ST1L05A schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ST1L05B and ST1L05D schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ST1L05C schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Output voltage vs temperature VO = 1.22 V, IO = 10 mA . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Output voltage vs temperature VO = 1.22 V, IO = 1.3 A . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Output voltage vs temperature VO = 2.5 V, IO = 10 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Output voltage vs temperature VO = 2.5 V, IO = 1.3 A . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Line regulation vs temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Load regulation vs temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Dropout voltage vs temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 ESR required for stability with ceramic capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Quiescent current vs temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Quiescent current vs output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Enable voltage vs temperature VI = 3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Enable voltage vs temperature VI = 5.25 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Supply voltage rejection vs temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Supply voltage rejection vs frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Load transient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Short-circuit removal transient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Line transient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Enable transient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 ST1L05 application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 ST1L05A application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ST1L05B and ST1L05D application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ST1L05C application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 DFN6 (3x3 mm) drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DFN6 (3x3 mm) recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DFN8 (4x4 mm) drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 DFN8 (4x4 mm) recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 DFN6 (3x3 mm) tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 DFN6 (3x3 mm) reel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 DFN8 (4x4 mm) carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DFN8 (4x4 mm) reel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 DocID14492 Rev 3 ST1L05 1 Schematic diagram Schematic diagram Figure 1. ST1L05 schematic diagram VI VI BandGap reference Current limit OpAmp VO Thermal protection VO_SENSE R1 R2 GND Figure 2. ST1L05A schematic diagram VI VI BandGap reference Current limit OpAmp VO Thermal protection R1 R2 GND DocID14492 Rev 3 5/30 30 Schematic diagram ST1L05 Figure 3. ST1L05B and ST1L05D schematic diagram VI Power-good signal PG VI BandGap reference Current limit OpAmp VO Thermal protection VI ADJ RP EN Internal enable GND Figure 4. ST1L05C schematic diagram VI Power-good signal PG VI BandGap reference Current limit OpAmp Thermal protection VO VI ADJ RP EN Internal enable GND 6/30 DocID14492 Rev 3 ST1L05 2 Pin configuration Pin configuration Figure 5. Pin connections (top view) ST1L05 ST1L05B ST1L05A ST1L05D ST1L05C Table 2. Pin description Pin Symbol Function ST1L05 ST1L05A ST1L05B ST1L05C ST1L05D VI 6 3 6 6 8 Supply voltage input pin. Bypass with a 4.7 µF capacitor to GND VO 4 2 4 4 6 Output voltage pin. Bypass with a 4.7 µF capacitor to GND GND 2 6 2 2 2 Ground pin ADJ - - 5 - 7 Adjust pin VO_SENSE 5 - - 5 - VO sense PG - - 3 - 3 Power Good pin EN - - 1 1 1 Enable pin. Internal pull-up to VI N.C. 1-3 1-4-5 - 3 4-5 GND Exposed Not connected Exposed pad has to be connected to GND DocID14492 Rev 3 7/30 30 Maximum ratings 3 ST1L05 Maximum ratings Table 3. Absolute maximum ratings Symbol Parameter Value Unit VI DC supply voltage -0.3 to 7 V VO DC output voltage -0.3 to 7 V PG Power Good -0.3 to 7 V EN Enable pin -0.3 to 7 V 4 V ADJ/VOUT_SENSE Adjust pin or VO sense PD Power dissipation Internally limited W IO Output current Internally limited A 0 to 150 °C -65 to 150 °C 260 °C TOP Operating junction temperature range range(1) TSTG Storage temperature TLEAD Lead temperature (soldering) 10 seconds 1. Storage temperature > 125 °C is acceptable only if the regulator is soldered to a PCBA. Note: Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Table 4. Thermal data Symbol Parameter DFN6 DFN8 Unit RthJC Thermal resistance junction-case 10 4 °C/W RthJA Thermal resistance junction-ambient 55 40 °C/W Table 5. ESD data Symbol 8/30 Parameter HBM Human body model MM Machine model DocID14492 Rev 3 Value Unit 2 kV 150 V ST1L05 4 Electrical characteristics Electrical characteristics Refer to the typical application schematic, VI = 3.3 V to 4.5 V, IO = 5 mA to 1.3 A, CI = CO = 4.7 µF, TJ = 0 to 125 °C, unless otherwise specified. Intended typical value is TJ = 25 °C unless otherwise specified. Table 6. ST1L05PU25R electrical characteristics Symbol Parameter Test conditions VO Output voltage VI = 3.3 V to 5.25 V, T = 25 °C VO Output voltage VI = 3.3 V to 5.25 V ΔVO Line regulation VI = 4.75 V to 5.25 V ΔVO Load regulation VI = 4.75 V, IO = 10 mA to 1.3 A Output current limit VI = 5.5 V IS IOMIN Vd IQ SVR Max. Unit 2.45 2.5 2.55 V 2.4375 2.5 2.5625 V 15 mV 30 mV 15 1.3 A Dropout voltage Quiescent current Supply voltage rejection(1) 0 mA IO = 0.8 A 0.2 0.4 V IO = 1 A 0.25 0.45 V IO = 1.3 A 0.3 0.5 V VI = 5 V, IO = 2 mA to 1.3 A, T = 25 °C 350 500 VI = 5.5 V, IO = 2 mA to 1.3 A 350 VI = 5 ± 0.5 V, IO = 5 mA, f = 120 Hz B = 10 Hz to 10 kHz, VI = 5 V, IO = 5 mA ΔVO/ΔIO Load transient (rising)(1)(2) VI = 5 V, any 200 mA step from 100 mA to 1.3 A, tR ≥ 1 µs ΔVO/ΔIO Load transient (falling)(1)(2) ΔVO/ΔVI ΔVO/ΔIO TSH Typ. Minimum output current for regulation RMS output noise(1) eN Min. µA 50 650 68 dB 0.003 %VO 5 %VO VI = 5 V, IO = 1.3 A to 10 mA, tF ≥ 1 µs 2.75 V Start-up transient(1)(2) VI = 0 V to 5 V, IO = 10 mA to 1.3 A, tR ≥ 1 µs 2.75 V Short-circuit removal response(1)(2) VI = 5 V, IO = short to 10 mA 2.75 V Thermal shutdown trip point(1) VI = 5 V 165 °C 1. Guaranteed by design. Not tested in production. 2. CI = 10 µF, CO = 10 µF, all X7R ceramic capacitors. DocID14492 Rev 3 9/30 30 Electrical characteristics ST1L05 Refer to the typical application schematic, VI = 4.5 V to 5.5 V, IO = 5 mA to 1.3 A, CI = CO = 4.7 µF, TJ = 0 to 125 °C, unless otherwise specified. Intended typical value is TJ = 25 °C unless otherwise specified. Table 7. ST1L05APU33R electrical characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit VO Output voltage VI = 4.75 V to 5.25 V, T = 25 °C 3.234 3.3 3.366 V VO Output voltage VI = 4.75 V to 5.25 V 3.2175 3.3 3.3825 V ΔVO Line regulation VI = 4.75 V to 5.25 V 15 mV ΔVO Load regulation VI = 4.75 V, IO = 10 mA to 1.3 A 30 mV Output current limit VI = 5.5 V IS IOMIN Vd IQ SVR Dropout voltage Quiescent current Supply voltage rejection (1) 0 mA 0.2 0.4 V IO = 1 A 0.25 0.45 V IO = 1.3 A 0.3 0.5 V VI = 5 V, IO = 2 mA to 1.3 A, T = 25 °C 350 500 VI = 5.5 V, IO = 2 mA to 1.3 A 350 VI = 5 ± 0.5 V, IO = 5 mA, f = 120 Hz ΔVO/ΔIO Load transient (rising)(1)(2) VI = 5 V, any 200 mA step from 100 mA to 1.3 A, tR ≥ 1 µs ΔVO/ΔIO Load transient (falling)(1)(2) ΔVO/ΔVI ΔVO/ΔIO µA 50 650 65 dB 0.003 %VO 5 %VO VI = 5 V, IO = 1.3 A to 10 mA, tF ≥ 1 µs 3.6 V Start-up transient(1)(2) VI = 0 V to 5 V, IO = 10 mA to 1.3 A, tR ≥ 1 µs 3.5 V Short-circuit removal response (1)(2) VI = 5 V, IO = short to 10 mA 3.5 V Thermal shutdown trip point(1) VI = 5 V 1. Guaranteed by design. Not tested in production. 2. CI = 10µF, CO = 10µF, all X7R ceramic capacitors. 10/30 A IO = 0.8 A B = 10 Hz to 10 kHz, VI = 5 V, IO = 5 mA TSH 1.3 Minimum output current for regulation RMS output noise(1) eN 15 DocID14492 Rev 3 165 °C ST1L05 Electrical characteristics Refer to the typical application schematic, VI = 4.5 V to 5.5 V, VEN = 2 V, IO = 5 mA to 1.3 A, CI = CO = 4.7 µF, TJ = 0 to 125 °C, unless otherwise specified. Intended typical value is TJ = 25 °C unless otherwise specified. Table 8. ST1L05CPU33R electrical characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit VO Output voltage VI = 4.75 V to 5.25 V, T = 25 °C 3.234 3.3 3.366 V VO Output voltage VI = 4.75 V to 5.25 V 3.2175 3.3 3.3825 V ΔVO Line regulation VI = 4.75 V to 5.25 V 15 mV ΔVO Load regulation VI = 4.75 V, IO = 10 mA to 1.3 A 30 mV Output current limit VI = 5.5 V IS IOMIN Vd IQ Dropout voltage Quiescent current V IO = 1 A 0.25 0.45 V IO = 1.3 A 0.3 0.5 V VI = 5 V, IO = 2 mA to 1.3 A, T = 25 °C 350 500 VI = 5.5 V, IO = 2 mA to 1.3 A 350 Enable threshold low VI = 4.5 V to 5.25, IO = 50 mA Enable pin current VEN = VI = 5 V Supply voltage rejection(1) VI = 5 ± 0.5 V, IO = 5 mA, f = 120 Hz RMS output noise(1) B = 10 Hz to 10 kHz, VI = 5 V, IO = 5 mA ΔVO/ΔIO Load transient (rising) (1)(2) VI = 5 V, any 200 mA step from 100 mA to 1.3 A, tR ≥ 1 µs ΔVO/ΔIO Load transient (falling)(1)(2) ΔVO/ΔVI Start-up transient (1)(2) TSH mA 0.4 VEN_L ΔVO/ΔIO 0 0.2 VI = 4.5 V to 5.25, IO = 50 mA eN A IO = 0.8 A Enable threshold high SVR 1.3 Minimum output current for regulation VEN_H IEN 15 µA 650 2 V 0.8 2 50 µA 65 dB 0.003 %VO 5 %VO VI = 5 V, IO = 1.3 A to 10 mA, tF ≥ 1 µs 3.6 V VI = 0 V to 5 V, IO = 10 mA to 1.3 A, tR ≥ 1 µs 3.5 V Short-circuit removal response (1)(2) VI = 5 V, IO = short to 10 mA 3.5 V Thermal shutdown trip point(1) VI = 5 V 165 °C 1. Guaranteed by design. Not tested in production. 2. CI =10 µF, CO =10 µF, all X7R ceramic capacitors. DocID14492 Rev 3 11/30 30 Electrical characteristics ST1L05 Refer to the typical application schematic, VI = 3 V to 5.5 V, VEN = 2 V, IO = 5 mA to 1.3 A, CI = CO = 4.7 µF, TJ = 0 to 125 °C, unless otherwise specified. Intended typical value is TJ = 25 °C unless otherwise specified. Table 9. ST1L05BPUR and ST1L05DPUR electrical characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit VO Output voltage VI = 3 V to 5.25 V, T = 25 °C 1.195 1.22 1.245 V VO Output voltage VI = 3 V to 5.25 V 1.18 1.22 1.256 V ΔVO Line regulation VI = 4.75 V to 5.25 V 15 mV ΔVO Load regulation VI = 4.75 V, IO = 10 mA to 1.3 A 15 30 mV IADJ Adjust pin current VI = 3 V to 5.25 V 1 Output current limit VI = 5.5 V IS IOMIN Vd IQ 1.3 A Minimum output current for regulation Dropout voltage (1) Quiescent current 1 0.2 V IO = 1 A, VO = 3.3 V 0.25 V IO = 1.3 A, VO = 3.3 V 0.3 V VI = 5 V, IO = 2 mA to 1.3 A, T = 25 °C 300 500 VI = 5.5 V, IO = 2 mA to 1.3 A 350 650 VEN_H Enable threshold high VI = 3 V to 5.25, IO = 50 mA VEN_L Enable threshold low VI = 3 V to 5.25, IO= 50 mA Enable pin current VEN = VI = 5 V 2 V 0.8 2 Rising edge 0.92 VO Falling edge 0.8 VO SVR eN Power Good output voltage low(3) ISINK = 6 mA open drain output Supply voltage rejection(3) VI = 5 ± 0.5 V, IO = 5 mA, f = 120 Hz RMS output noise(3) B = 10 Hz to 10 kHz, VI = 5 V, IO = 5 mA ΔVO/ΔIO Load transient (rising)(3)(4) VI = 5 V, any 200 mA step from 100 mA to 1.3 A, tR ≥ 1 µs ΔVO/ΔIO Load transient (falling)(3)(4) ΔVO/ΔVI Start-up transient(3)(4) 12/30 µA 1 Power Good output threshold PG mA IO = 0.8 A, VO = 3.3 V Device OFF(2) IEN nA V 0.4 50 µA V 72 dB 0.003 %VO 5 %VO VI = 5 V, IO = 1.3 A to 10 mA, tF ≥ 1 µs 1.38 V VI = 0 V to 5 V, IO = 10 mA to 1 A, tR ≥ 1 µs 1.38 V DocID14492 Rev 3 ST1L05 Electrical characteristics Table 9. ST1L05BPUR and ST1L05DPUR electrical characteristics (continued) Symbol Parameter ΔVO/ΔIO Short-circuit removal response(3)(4) VI = 5 V, IO = short to 10 mA Thermal shutdown trip point (3) VI = 5 V TSH Test conditions Min. Typ. 165 Max. Unit 1.38 V °C 1. See minimum start-up voltage, VI = 2.9 V. 2. PG pin floating. 3. Guaranteed by design. Not tested in production. 4. CI = 10 µF, CO = 10 µF, all X7R ceramic capacitors. DocID14492 Rev 3 13/30 30 Typical characteristics 5 ST1L05 Typical characteristics 1.30 1.28 1.26 1.24 1.22 1.20 1.18 1.16 1.14 1.12 1.10 Figure 7. Output voltage vs temperature VO = 1.22 V, IO = 1.3 A VO [V] VO [V] Figure 6. Output voltage vs temperature VO = 1.22 V, IO = 10 mA VEN = VI = 5 V, IO = 0.01 A, CI = CO = 4.7 µF -30 -5 20 45 70 95 120 1.30 1.28 1.26 1.24 1.22 1.20 1.18 1.16 1.14 1.12 1.10 145 VEN = VI = 5 V, IO = 1.3 A, CI = CO = 4.7 µF -30 -5 20 45 T [°C] Figure 8. Output voltage vs temperature VO = 2.5 V, IO = 10 mA 2.70 120 145 VI = 5 V, IO = 1.3 A, CI = CO = 4.7 µF 2.65 2.60 2.60 2.55 2.55 VO [V] VO [V] 2.70 2.50 2.45 2.50 2.45 2.40 2.40 2.35 2.35 2.30 2.30 -30 -5 20 45 70 95 120 -30 145 -5 20 45 70 95 120 145 T [°C] T [°C] Figure 10. Line regulation vs temperature Figure 11. Load regulation vs temperature 20 50 VEN = VI = from 4.75 to 5.25 V, IO = 0.005 A, CIN = CO = 4.7 µF 15 VEN = VI = 4.75 V, IO = from 0.01 to 1.3 A, CI = CO = 4.7 µF 40 Load [mV] 10 Line [mV] 95 Figure 9. Output voltage vs temperature VO = 2.5 V, IO = 1.3 A VI = 5 V, IO = 0.01 A, CI = CO = 4.7 µF 2.65 70 T [°C] 5 0 -5 30 20 -10 10 -15 -20 0 -30 -5 20 45 T [°C] 14/30 70 95 120 -30 -5 20 45 T [°C] DocID14492 Rev 3 70 95 120 145 ST1L05 Typical characteristics Figure 12. Dropout voltage vs temperature CI = CO = 4.7 µF, VO @ 3.3 V 0.7 IO = 1 A 0.6 Dropout [V] 0.4 IO = 800 mA ESR @ 100kHz [ohm] 0.8 Figure 13. ESR required for stability with ceramic capacitors IO = 1.3 A 0.5 0.4 0.3 0.2 CI = 4.7 µF, VEN = VI = from 3 V to 5.5 V, IO = from 5 mA to 1.3 A 0.35 0.3 0.25 0.2 0.15 0.1 Stable zone 0.05 0.1 0 0 0 -30 -5 20 45 70 95 120 2 4 6 145 T [°C] Figure 14. Quiescent current vs temperature 400 VEN = VI = 5 V, IO = 1.3 A, CI = CO = 4.7 µF 300 400 250 IQ [µA] IQ [µA] 500 200 14 16 18 20 22 200 150 100 100 50 0 -30 -5 20 45 70 95 120 0 145 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 I O [A] T [°C] Figure 16. Enable voltage vs temperature VI = 3 V Figure 17. Enable voltage vs temperature VI = 5.25 V 2.5 2.5 VI = 3 V, IO = 50 mA, CI = CO = 4.7 µF ON VI = 5.25 V, IO = 50 mA, CI = CO = 4.7 µF ON OFF 2 OFF 2 1.5 VEN [V] VEN [V] 12 VEN = VI = 5.5 V, CI = CO = 4.7 µF 350 300 10 Figure 15. Quiescent current vs output current 700 600 8 CO [µF] (nominal value) 1 0.5 1.5 1 0.5 0 0 -30 -5 20 45 70 95 120 145 -30 T [°C] -5 20 45 70 95 120 145 T [°C] DocID14492 Rev 3 15/30 30 Typical characteristics ST1L05 Figure 19. Supply voltage rejection vs frequency 80 80 75 70 70 60 SVR [dB] SVR [dB] Figure 18. Supply voltage rejection vs temperature 65 60 VEN = VI = from 3 to 5.5 V, IO = 5 mA, VO = 1.22 V, CI = CO = 4.7 µF, F = 120 Hz 55 50 40 30 VEN = VI = 3 to 5.5 V, IO = 5 mA, VO = 1.22 V, CI = CO = 4.7 µF 50 20 -30 -5 20 45 70 95 120 145 10 T [°C] 100 1000 10000 100000 Figure 20. Load transient Figure 21. Short-circuit removal transient IO=10 mA to 1.3 A, CI=CO=10 µF, VEN=VI=5 V, VO@3.3 V IO=10 mA to short, CI=CO=10 µF, VEN=VI=5.5 V Figure 22. Line transient Figure 23. Enable transient VEN VI VO CI=CO=4.7 µF, VI=3 to 5.5V, IO=5 mA 16/30 1000000 Frequency [Hz] VO CO=CI=4.7 µF, VEN=0 to 2 V, VI=5.5 V, IO=5 mA DocID14492 Rev 3 ST1L05 6 Application information Application information The ST1L05 is a low-dropout linear regulator. It provides up to 1.3 A with a low 300 mV dropout. The input voltage range is from 3 V to 5.5 V. The device is available in fixed and adjustable output versions. The regulator is equipped with internal protection circuitry, such as short-circuit current limiting and thermal protection. The regulator is designed to be stable with ceramic capacitors on the input and the output. The expected values of the input and output ceramic capacitors are from 1 µF to 22 µF with 4.7 µF typical. The input capacitor has to be connected within 1 cm from VI terminal. The output capacitor has also to be connected 1 cm far from output pin. There isn’t any upper limit to the value of the input capacitor. Figure 24, Figure 25, Figure 26 and Figure 27 illustrate the typical application schematics: Figure 24. ST1L05 application schematic VI VI CI ST1L05 GND VO VO VO_SENSE G ND GN DocID14492 Rev 3 CO GIPG3005141059LM 17/30 30 Application information ST1L05 Figure 25. ST1L05A application schematic VI VI CI ST1L05A VO VO CO GND G ND GN GIPG3004141216LM Figure 26. ST1L05B and ST1L05D application schematic VI VI OFF ON CI PG VO S T 1 L 0 5B S T 1 L 0 5D VO EN ADJ GND R1 CO R2 GND GIPG3004141246LM 18/30 DocID14492 Rev 3 ST1L05 Application information Figure 27. ST1L05C application schematic VI VO VO VI ST1L05C CI OFF ON VO_SENSE EN GND CO GND Regarding to the adjustable version, the output voltage can be adjusted from 1.22 V up to the input voltage, minus the voltage drop across PMOS (dropout voltage), by connecting a resistor divider between ADJ pin and the output, thus allowing remote voltage sensing. The resistor divider should be selected according to the following equation: Equation 1 VO = VADJ (1 + R1 / R2) with VADJ = 1.22 V (typ.) Resistors should be used with values in the range from 10 kΩ to 100 kΩ. Lower values can also be suitable, but they increase current consumption. 6.1 Power dissipation An internal thermal feedback loop disables the output voltage if the die temperature rises to approximately 165 °C. This feature protects the device from excessive temperature and allows the user to push the limits of the power handling capability of a given circuit board without risk of damaging the device. A good PC board layout should be used to maximize the power dissipation. Thermal path goes from the die to the copper lead frame through the package leads and exposed pad to the PC board copper. The PC board copper works as a heatsink. Footprint copper pads should be as wider as possible to spread and dissipate the heat to the surrounding ambient. Feed-through vias to inner or backside copper layers are also useful to improve the overall thermal performance of the device. Power dissipation of the device depends on the input voltage, output voltage and output current, and is given by: Equation 2 PD = (VI -VO) IO DocID14492 Rev 3 19/30 30 Application information ST1L05 The junction temperature of the device is: TJ_MAX = TA + RthJA x PD where: TJ_MAX is the maximum junction of the die, 125 °C TA is the ambient temperature RthJA is the thermal resistance junction-to-ambient 6.2 Enable function (ST1L05B, ST1L05C and ST1L05D only) The ST1L05 features the enable function. When EN voltage is higher than 2 V the device is ON, and if it is lower than 0.8 V the device is OFF. In shutdown mode, consumption is lower than 1 µA. EN pin has an internal pull-up, so it can be left floating if it is not used. 6.3 Power Good function (ST1L05B and ST1L05D only) Most applications require a flag showing that the output voltage is in the correct range. Power Good threshold depends on the adjust voltage. When the adjust is higher than 0.92*VADJ, Power Good (PG) pin goes to high impedance. If the adjust is below 0.92*VADJ PG pin goes to low impedance. If the device works correctly, Power Good pin is at high impedance. If the output voltage is fixed using an external or internal resistor divider, Power Good threshold is 0.92*VO. To use Power Good function, an external pull-up resistor is required, and it has to be connected between PG pin and VI or VO. PG pin typical current capability is up to 6 mA. A pull-up resistor in the range of 100 kΩ to 1 MΩ is recommended. If Power Good function is not used, PG pin has to remain floating. 20/30 DocID14492 Rev 3 ST1L05 7 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 28. DFN6 (3x3 mm) drawings DocID14492 Rev 3 21/30 30 Package mechanical data ST1L05 Table 10. DFN6 (3x3 mm) mechanical data mm Dim. Min. A 0.80 A1 0 Typ. Max. 1 0.02 A3 0.05 0.20 b 0.23 D 2.90 D2 2.23 E 2.90 E2 1.50 0.45 3 3.10 2.50 3 3.10 1.75 0.95 L 0.30 0.40 Figure 29. DFN6 (3x3 mm) recommended footprint 22/30 DocID14492 Rev 3 0.50 ST1L05 Package mechanical data Figure 30. DFN8 (4x4 mm) drawings DocID14492 Rev 3 23/30 30 Package mechanical data ST1L05 Table 11.DFN8 (4x4 mm) mechanical data mm Dim. Min. Typ. Max. A 0.80 0.90 1 A1 0 0.02 0.05 A3 0,20 b 0.23 0.30 0.38 D 3.90 4 4.10 D2 2.82 3 3.23 E 3.90 4 4.10 E2 2.05 2.20 2.30 e L 0.80 0.40 0.50 Figure 31. DFN8 (4x4 mm) recommended footprint 24/30 DocID14492 Rev 3 0.60 ST1L05 8 Packaging mechanical data Packaging mechanical data Figure 32. DFN6 (3x3 mm) tape B1 DocID14492 Rev 3 25/30 30 Packaging mechanical data ST1L05 Figure 33. DFN6 (3x3 mm) reel B1 Table 12. DFN6 (3x3 mm) tape and reel mechanical data mm Dim. 26/30 Min. Typ. Max. A0 3.20 3.30 3.40 B0 3.20 3.30 3.40 K0 1 1.10 1.20 DocID14492 Rev 3 ST1L05 Packaging mechanical data Figure 34. DFN8 (4x4 mm) carrier tape 7279936 DocID14492 Rev 3 27/30 30 Packaging mechanical data ST1L05 Figure 35. DFN8 (4x4 mm) reel Table 13. DFN8 (4x4 mm) reel mechanical data mm Dim. Min. Typ. A 330 C 12.8 D 20.2 N 60 T 28/30 Max. 13.0 13.2 22.4 DocID14492 Rev 3 ST1L05 9 Revision history Revision history Table 14. Document revision history Date Revision 29-Feb-2008 1 First release. 07-Jul-2009 2 Added: package DFN8 (4 x 4 mm). 3 Part numbers: ST1L05A, ST1L05B, ST1L05C, ST1L05D have been included in the ST1L05 for product rationalization. Changed title of Figure 6, Figure 7, Figure 8, Figure 9, Figure 16 and Figure 17. Updated package mechanical data. Added Section 8. 05-May-2014 Changes DocID14492 Rev 3 29/30 30 ST1L05 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2014 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 30/30 DocID14492 Rev 3