ST1S40IPUR

ST1S40 3 A DC step-down switching regulator Datasheet - production data Applications  P/ASIC/DSP/FPGA core and I/O supplies  Point of load for: STB, TVs, DVD HSOP-8  Optical storage, hard disk drive, printers, audio/graphic cards SO8 VFQFPN 4 x 4 Description Features The ST1S40 device is an internally compensated 850 kHz fixed-frequency PWM synchronous stepdown regulator. The ST1S40 operates from 4.0 V to 18 V input, while it regulates an output voltage as low as 0.8 V and up to VIN.  3 A DC output current  4.0 V to 18 V input voltage  Output voltage adjustable from 0.8 V  850 kHz switching frequency  Internal soft-start  Integrated 95 m and 69 m Power MOSFETs  All ceramic capacitor The ST1S40 integrates a 95 m high side switch and 69 m synchronous rectifier allowing very high efficiency with very low output voltages. The peak current mode control with internal compensation delivers a very compact solution with a minimum component count.  Enable  Cycle-by-cycle current limiting  Current fold back short-circuit protection  Available in HSOP-8, VFQFPN4x4-8L, and SO8 packages The ST1S40 is available in HSOP-8, VFQFPN 4 mm x 4 mm - 8 lead, and standard SO8 package. Figure 1. Application circuit / —+ 9,1 9 9,16: 92879 6: 9,1$ &LQBD (13* 5 676, —) )% &LQBVZ &RXW 3*1'$*1'H3DG —) August 2019 This is information on a product in full production. DocID17928 Rev 6 5 —) 1/30 www.st.com Contents ST1S40 Contents 1 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 5.1 Internal soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.2 Error amplifier and control loop stability . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.3 Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.4 Enable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.5 Hysteretic thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1 Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.2 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.3 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.4 Thermal dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.5 Layout consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 Demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8 Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 10 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2/30 DocID17928 Rev 6 ST1S40 Pin settings 1 Pin settings 1.1 Pin connection Figure 2. Pin connection (top view) VINA 1 EN 2 FB 3 GND 4 9 VINA 1 SW EN 2 6 VINSW FB 3 5 NC GND 4 8 PGND 7 PGND 7 SW 6 VINSW 5 NC 8 SW VINSW PGND HSOP-8 HSOP8 VFQFPN 1.2 9 1 8 GND VINA EN AGND 4 5 FB SO8-BW Pin description Table 1. Pin description N° VFQFPN S08-BW and HSOP-8 Type Description 1 3 VINA 2 4 EN Enable input. With EN higher than 1.2 V the device in ON and with EN lower than 0.4 V the device is OFF (ST1S40Ixx). 3 5 FB Feedback input. Connecting the output voltage directly to this pin the output voltage is regulated at 0.8 V. To have higher regulated voltages an external resistor divider is required from Vout to the FB pin. 4 6 5 - 6 8 7 1 8 2 - 7 9 - Unregulated DC input voltage AGND Ground NC It can be connected to ground VINSW Power input voltage SW Regulator output switching pin PGND Power ground Ground ePad Exposed pad mandatory connected to ground DocID17928 Rev 6 3/30 30 Maximum ratings 2 ST1S40 Maximum ratings Table 2. Absolute maximum ratings Symbol Value Power input voltage -0.3 to 20 VINA Input voltage -0.3 to 20 VEN Enable voltage VINSW 3 Parameter -0.3 to VINA VSW Output switching voltage VFB Feedback voltage IFB FB current Unit V -1 to VIN -2 V to -1 V for 50 nsec -0.3 to 2.5 -1 to +1 mA 2.25 (HSOP-8/DFN4x4); 1.6 SO8-BW W PTOT Power dissipation at TA < 60 °C TOP Operating junction temperature range -40 to 150 °C Tstg Storage temperature range -55 to 150 °C Thermal data Table 3. Thermal data Symbol RthJA Parameter Maximum thermal resistance junction-ambient(1) 1. Package mounted on the demonstration board. 4/30 DocID17928 Rev 6 Value VFQFPN 40 HSOP-8 40 SO8-BW 55 Unit °C/W ST1S40 4 Electrical characteristics Electrical characteristics TJ = 25 °C, VCC= 12 V, unless otherwise specified. Table 4. Electrical characteristics Values Symbol Parameter Test condition Unit Min. Typ. VIN Operating input voltage range (1) VINON Turn-on VCC threshold (1) 2.9 VINHYS Threshold hysteresis (1) 0.250 RDSON-P High side switch ON resistance ISW = 750 mA 95 RDSON-N Low side switch ON resistance ISW = 750 mA 69 ILIM Maximum limiting current (2) 4 Max. 18 4.0 V m m 6.0 A 1 MHz Oscillator FSW DMAX Switching frequency Maximum duty cycle 0.7 (2) 0.85 100 % Dynamic characteristics VFB Feedback voltage (1) 0.784 0.8 0.816 0.776 0.8 0.824 V %VOUT/ IOUT Reference load regulation Isw = 10 mA to ILIM(2) 0.5 % %VOUT/ VIN Reference line regulation VIN = 4.0 V to 18 V(2) 0.4 % DC characteristics IQ IQST-BY IFB Quiescent current Duty cycle = 0, no load VFB = 1.2 V Total standby quiescent current OFF FB bias current 1.5 2.5 mA 2 15 A 50 Enable Device ON level VEN EN threshold voltage IEN EN current 1.2 V Device OFF level 0.4 2 DocID17928 Rev 6 A 5/30 30 Electrical characteristics ST1S40 Table 4. Electrical characteristics (continued) Values Symbol Parameter Test condition Unit Min. Typ. Max. Soft start TSS Soft-start duration 1 ms Protection TSHDN Thermal shutdown 150 Hysteresis 15 °C 1. Specification referred to TJ from -40 to +125 °C. Specifications in the -40 to +125 °C temperature range are assured by design, characterization and statistical correlation. 2. Guaranteed by design. 6/30 DocID17928 Rev 6 ST1S40 5 Functional description Functional description The ST1S40 device is based on a “peak current mode”, constant frequency control. The output voltage VOUT is sensed by the feedback pin (FB) compared to an internal reference (0.8 V) providing an error signal that, compared to the output of the current sense amplifier, controls the ON and OFF time of the power switch. The main internal blocks are shown in the block diagram in Figure 3. They are:  A fully integrated oscillator that provides the internal clock and the ramp for the slope compensation avoiding sub-harmonic instability  The soft-start circuitry to limit inrush current during the startup phase  The transconductance error amplifier with integrated compensation network  The pulse width modulator and the relative logic circuitry necessary to drive the internal power switches  The drivers for embedded P-channel and N-channel Power MOSFET switches  The high side current sensing block  The low side current sense to implement diode emulation  A voltage monitor circuitry (UVLO) that checks the input and internal voltages  A thermal shutdown block, to prevent thermal run-away. Figure 3. Block diagram VINA VINSW OCP REF OSC I2V COMP I_SENSE RSENSE REGULATOR UVLO OCP Vdrv_p MOSFET CONTROL LOGIC Vsum COMP DRIVER Vdrv_n Vc SW OTP DMD E/A SHUT-DOWN DRIVER SOFTSTART 0.8V FB EN DocID17928 Rev 6 GNDA GNDP 7/30 30 Functional description 5.1 ST1S40 Internal soft-start The soft-start is essential to assure correct and safe startup of the step-down converter. It avoids inrush current surge and causes the output voltage to increase monothonically. The soft-start is performed by ramping the non-inverting input (VREF) of the error amplifier from 0 V to 0.8 V in around 1 ms. 5.2 Error amplifier and control loop stability The error amplifier compares the FB pin voltage with the internal 0.8 V reference and it provides the error signal to be compared with the output of the current sense circuitry, that is the high side Power MOSFET current. Comparing the output of the error amplifier and the peak inductor current implements the peak current mode control loop. The error amplifier is a transconductance amplifier (OTA). The uncompensated characteristics are listed inTable 5. Table 5. Error amplifier characteristics Parameter Value DC Gain 95 dB Gm 251 µA/V Ro 240 M The ST1S40 device embeds the compensation network that assures the stability of the loop in the whole operating range. All the tools needed to check the loop stability are shown below. 8/30 DocID17928 Rev 6 ST1S40 Functional description Figure 4 shows the simple small signal model for the peak current mode control loop. Figure 4. Block diagram of the loop for the small signal analysis VIN GCO(s) Slope Compensation High side Switch L Current sense Logic And Driver VOUT GDIV (s) Cout Low side Switch PWM comparator 0.8V R1 VC Rc VFB Error Amp R2 Cc G EA(s) Three main terms can be identified to obtain the loop transfer function: 1. from control (output of E/A) to output, GCO(s) 2. from output (Vout) to the FB pin, GDIV(s) 3. from the FB pin to control (output of E/A), GEA(s). The transfer function from control to output GCO(s) results: Equation 1 s  1 + -----   R LOAD 1 z G CO  s  = ------------------  ---------------------------------------------------------------------------------------------  ----------------------  F H  s  Ri R out  T SW s  ------ 1 + ----------------------------   m C   1 – D  – 0.5   1 +   L p where RLOAD represents the load resistance, Ri (0.3 ) the equivalent sensing resistor of the current sense circuitry, p the single pole introduced by the LC filter and z the zero given by the ESR of the output capacitor. FH(s) accounts for the sampling effect performed by the PWM comparator on the output of the error amplifier that introduces a double pole at one half of the switching frequency. Equation 2 1  Z = ------------------------------ESR  C OUT DocID17928 Rev 6 9/30 30 Functional description ST1S40 Equation 3 m C   1 – D  – 0.5 1  p = -------------------------------------- + --------------------------------------------L  C OUT  f SW R LOAD  C OUT where: Equation 4 Se   m C = 1 + -----Sn  S = V  f pp SW  e  V IN – V OUT  S = -----------------------------  Ri  n L Sn represents the ON time slope of the sensed inductor current, Se the slope of the external ramp (VPP peak-to-peak amplitude 1.25 V) that implements the slope compensation to avoid sub-harmonic oscillations at duty cycle over 50%. The sampling effect contribution FH(s) is: Equation 5 1 F H  s  = -----------------------------------------2 s s 1 + ------------------- + ------2 n  QP  n where: Equation 6 1 Q P = ---------------------------------------------------------   m C   1 – D  – 0.5  and Equation 7  n =   f SW The resistor to adjust the output voltage gives the term from output voltage to the FB pin. GDIV(s) is: R2 G DIV  s  = -------------------R1 + R2 The transfer function from FB to Vcc (output of E/A) introduces the singularities (poles and zeros) to stabilize the loop. Figure 5 shows the small signal model of the error amplifier with the internal compensation network. 10/30 DocID17928 Rev 6 ST1S40 Functional description Figure 5. Small signal model for the error amplifier 9 )% 5R 9G &R *P 9G 5F &S &F 95() RC and CC introduce a pole and a zero in the open loop gain. CP does not significantly affect system stability and can be neglected. So GEA(s) results: Equation 8 G EA0   1 + s  R c  C c  G EA  s  = ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------2 s  R0   C0 + Cp   Rc  Cc + s   R0  Cc + R0   C0 + Cp  + Rc  Cc  + 1 where GEA= Gm · Ro The poles of this transfer function are (if Cc >> C0+CP): Equation 9 1 f P LF = ---------------------------------2    R0  Cc Equation 10 1 f P HF = ---------------------------------------------------2    Rc   C0 + Cp  whereas the zero is defined as: Equation 11 1 f Z = --------------------------------2    Rc  Cc The embedded compensation network is RC = 70 k, CC = 195 pF while CP and CO can be considered as negligible. The error amplifier output resistance is 240 Mso the relevant singularities are: Equation 12 f Z = 11 6 kHz DocID17928 Rev 6 f P LF = 3 4 Hz 11/30 30 Functional description ST1S40 so by closing the loop, the loop gain GLOOP(s) is: Equation 13 G LOOP  s  = G CO  s   G DIV  s   G EA  s  Example: VIN = 12 V, VOUT = 1.2 V, Iomax = 3 A, L = 1.5 µH, Cout = 47 µF (MLCC), R1 = 10 k, R2 = 20 k(see Section 6.2 and Section 6.3 for inductor and output capacitor selection guidelines). The module and phase Bode plot are reported in Figure 6. The bandwidth is 100 kHz and the phase margin is 45 degrees. Figure 6. Module and phase Bode plot 12/30 DocID17928 Rev 6 ST1S40 5.3 Functional description Overcurrent protection The ST1S40 device implements the pulse-by-pulse overcurrent protection. The peak current is sensed through the high side Power MOSFET and when it exceeds the first overcurrent threshold (OCP1) the high side is immediately turned off and the low side conducts the inductor current for the rest of the clock period. During overload condition, since the duty cycle is not set by the control loop but is limited by the overcurrent threshold, the output voltage drops out of regulation. If the feedback falls below 0.3 V the switching frequency is reduced to one fourth and the current limit threshold is folded back to around 2 A. Thanks to the current and frequency fold back the stress on the device and on the external power components is reduced in case of severe overload or dead-short to ground of the output. The current fold back is disabled during the startup, in order to allow the Vout to rise up properly in case of the big output capacitor requiring high extra current to be charged. An additional mechanism is protecting the device in case of short-circuit on the output and high input voltage. A further threshold (OCP2, 1A higher than OCP1) is compared to the inductor current. If the inductor current exceeds OCP2, the device stops switching and restarts with a soft-start cycle. 5.4 Enable function The enable feature allows the device to be put into standby mode. With the EN pin lower than 0.4 V, the device is disabled and the power consumption is reduced to less than 15 µA. With the EN pin higher than 1.2 V, the device is enabled. High level signal enables the device. An external 100 k pulldown resistor is suggested to ensure device disabled when the pin is left floating. Connect to VIN if not used. 5.5 Hysteretic thermal shutdown The thermal shutdown block generates a signal that turns off the power stage if the junction temperature goes above 150 C. Once the junction temperature goes back to about 130 C, the device restarts in normal operation. DocID17928 Rev 6 13/30 30 Application information ST1S40 6 Application information 6.1 Input capacitor selection The capacitor connected to the input must be capable of supporting the maximum input operating voltage and the maximum RMS input current required by the device. The input capacitor is subject to a pulsed current, the RMS value of which is dissipated over its ESR, affecting the overall system efficiency. So the input capacitor must have an RMS current rating higher than the maximum RMS input current and an ESR value compliant with the expected efficiency. The maximum RMS input current flowing through the capacitor can be calculated as: Equation 14 2 2 2D D I RMS = I O  D – --------------- + ------2  where Io is the maximum DC output current, D is the duty cycle, is the efficiency. Considering , this function has a maximum at D = 0.5 and is equal to Io/2. The peak-to-peak voltage across the input capacitor can be calculated as: Equation 15 IO D D V PP = -------------------------   1 – ----  D + ----   1 – D  + ESR  I O C IN  F SW    where ESR is the equivalent series resistance of the capacitor. Given the physical dimension, ceramic capacitors can well meet the requirements of the input filter sustaining a higher input RMS current than electrolytic / tantalum types. In this case the equation of CIN as a function of the target peak-to-peak voltage ripple (VPP) can be written as follows: Equation 16 IO D D C IN = ---------------------------   1 – ----  D + ----   1 – D  V PP  F SW    neglecting the small ESR of ceramic capacitors. Considering = 1, this function has its maximum in D = 0.5, therefore, given the maximum peak-to-peak input voltage (VPP_MAX), the minimum input capacitor (CIN_MIN) value is: Equation 17 IO C IN_MIN = -----------------------------------------------2  V PP_MAX  F SW Typically, CIN is dimensioned to keep the maximum peak-to-peak voltage ripple in the order of 1% of VINMAX. 14/30 DocID17928 Rev 6 ST1S40 Application information In Table 6 some multi layer ceramic capacitors suitable for this device are reported. Table 6. Input MLCC capacitors Manufacturer Series Cap value (F) Rated voltage (V) GRM31 10 25 GRM55 10 25 C3225 10 25 Murata TDK A ceramic bypass capacitor, as close as possible to the VINA pin, so that additional parasitic ESR and ESL are minimized, is suggested in order to prevent instability on the output voltage due to noise. The value of the bypass capacitor can go from 330 nF to 1 µF. 6.2 Inductor selection The inductance value fixes the current ripple flowing through the output capacitor. So the minimum inductance value, to have the expected current ripple, must be selected. The rule to fix the current ripple value is to have a ripple at 20% to 40% of the output current. In continuous current mode (CCM), the inductance value can be calculated by Equation 18 Equation 18 V IN – V OUT V OUT I L = ------------------------------  T ON = --------------  T OFF L L where TON is the conduction time of the high side switch and TOFF is the conduction time of the low side switch (in CCM, FSW = 1/(TON + TOFF)). The maximum current ripple, given the Vout, is obtained at maximum TOFF, that is at minimum duty cycle. So by fixing IL = 20% to 30% of the maximum output current, the minimum inductance value can be calculated: Equation 19 V OUT 1 – D MIN L MIN = ----------------  ----------------------I MAX F SWMIN where FSWMIN is the minimum switching frequency, according to Table 4 The peak current through the inductor is given by: Equation 20 I L I L PK = I O + -------2 so if the inductor value decreases, the peak current (that must be lower than the current limit of the device) increases. The higher the inductor value, the higher the average output current that can be delivered, without reaching the current limit. DocID17928 Rev 6 15/30 30 Application information ST1S40 In Table 7 below some inductor part numbers are listed. Table 7. Inductors Manufacturer Series Inductor value (H) Saturation current (A) XPL7030 2.2 to 4.7 6.8 to 10.5 MSS1048 2.2 to 6.8 4.14 to 6.62 MSS1260 10 5.5 WE-HC/HCA 3.3 to 4.7 7 to 11 WE-TPC typ XLH 3.6 to 6.2 4.5 to 6.4 WE-PD type L 10 5.6 RLF7030T 2.2 to 4.7 4 to 6 Coilcraft Wurth TDK 6.3 Output capacitor selection The current in the output capacitor has a triangular waveform which generates a voltage ripple across it. This ripple is due to the capacitive component (charge or discharge of the output capacitor) and the resistive component (due to the voltage drop across its ESR). So the output capacitor must be selected in order to have a voltage ripple compliant with the application requirements. The amount of the voltage ripple can be calculated starting from the current ripple obtained by the inductor selection. Equation 21 I MAX V OUT = ESR  I MAX + ------------------------------------8  C OUT  f SW For ceramic (MLCC) capacitors the capacitive component of the ripple dominates the resistive one. Whilst for electrolytic capacitors the opposite is true. Since the compensation network is internal, the output capacitor should be selected in order to have a proper phase margin and then a stable control loop. The equations of Section 5.2 help to check loop stability given the application conditions, the value of the inductor, and of the output capacitor. In Table 8 some capacitor series are listed. Table 8. Output capacitors Manufacturer Series Cap value (F) Rated voltage (V) ESR (m) GRM32 22 to 100 6.3 to 25