STD9NM50N

STD9NM50N N-channel 500 V, 0.73 Ω, 5 A MDmesh™II Power MOSFET in DPAK Features Order code VDSS@TJMAX RDS(on)max. STD9NM50N 550 V ID < 0.79 Ω 5A ■ 100% avalanche tested ■ Low input capacitances and gate charge ■ Low gate input resistance 3 1 DPAK Applications ■ Switching applications ■ Automotive Description Figure 1. These N-channel Power MOSFETs are developed using STMicroelectronics’ revolutionary MDmesh™ technology, which associates the multiple drain process with the company's PowerMESH™ horizontal layout. These devices offer extremely low on-resistance, high dv/dt and excellent avalanche characteristics. Utilizing ST's proprietary strip technique, these Power MOSFETs boast an overall dynamic performance which is superior to similar products on the market. Internal schematic diagram $ ' 3 !-V Table 1. Device summary Order code Marking Packages Packaging STD9NM50N 9NM50N DPAK Tape and reel September 2011 Doc ID 022254 Rev 1 1/15 www.st.com 15 Contents STD9NM50N Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Test circuits 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2/15 .............................................. 8 Doc ID 022254 Rev 1 STD9NM50N 1 Electrical ratings Electrical ratings Table 2. Symbol VGS Absolute maximum ratings Parameter Gate-source voltage Value Unit ± 25 V ID Drain current (continuous) at TC = 25 °C 5 A ID Drain current (continuous) at TC = 100 °C 3 A IDM (1) Drain current (pulsed) 20 A PTOT Total dissipation at TC = 25 °C 45 W Peak diode recovery voltage slope 15 V/ns - 55 to 150 °C 150 °C Value Unit Rthj-case Thermal resistance junction-case max 2.78 °C/W Rthj-pcb Thermal resistance junction-pcb max 50 °C/W dv/dt (2) Tstg Tj Storage temperature Max. operating junction temperature 1. Pulse width limited by safe operating area 2. ISD ≤ 5 A, di/dt ≤ 400 A/µs, VPeak < V(BR)DSS, VDS=80% V(BR)DSS Table 3. Symbol Table 4. Thermal data Parameter Avalanche characteristics Symbol Parameter Value Unit IAR Avalanche current, repetitive or not-repetitive (pulse width limited by Tj max) 2 A EAS Single pulse avalanche energy (starting Tj = 25°C, ID = IAR, VDD = 50 V) 140 mJ Doc ID 022254 Rev 1 3/15 Electrical characteristics 2 STD9NM50N Electrical characteristics (TC = 25 °C unless otherwise specified) Table 5. Symbol V(BR)DSS On /off states Parameter Test conditions Drain-source breakdown voltage (VGS = 0) ID = 1 mA Min. Typ. Max. Unit 500 V IDSS VDS = 500 V Zero gate voltage drain current (VGS = 0) VDS = 500 V, TC=125 °C 1 100 µA µA IGSS Gate-body leakage current (VDS = 0) 100 nA 3 4 V 0.73 0.79 Ω Min. Typ. Max. Unit VDS = 50 V, f = 1 MHz, VGS = 0 - 364 33 1.2 - pF pF pF VDS = 0 to 50 V, VGS = 0 - 147.5 - pF VGS = ± 25 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source on resistance Table 6. Symbol Ciss Coss Crss 2 VGS = 10 V, ID = 2.5 A Dynamic Parameter Input capacitance Output capacitance Reverse transfer capacitance Equivalent output Coss(eq)(1) capacitance time related Test conditions RG Intrinsic gate resistance f = 1 MHz open drain - 5.4 - Ω Qg Qgs Qgd Total gate charge Gate-source charge Gate-drain charge VDD = 400 V, ID = 5 A, VGS = 10 V (see Figure 13) - 14 3 7 - nC nC nC 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 4/15 Doc ID 022254 Rev 1 STD9NM50N Electrical characteristics Table 7. Symbol td(on) tr td(off) tf Table 8. Switching times Parameter Test conditions Turn-on delay time Rise time Turn-off-delay time Fall time VDD = 250 V, ID = 5 A, RG = 4.7 Ω, VGS = 10 V (see Figure 12) Parameter ISD ISDM (1) Source-drain current Source-drain current (pulsed) VSD (2) Forward on voltage IRRM trr Qrr IRRM Typ. - 7 4.4 25 8.8 Min. Typ. Max Unit - ns ns ns ns Source drain diode Symbol trr Qrr Min. Test conditions Max. Unit - 5 20 A A ISD = 5 A, VGS = 0 - 1.5 V Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 5 A, di/dt = 100 A/µs VDD = 60 V (see Figure 17) - 187 1.3 14 ns µC A Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 5 A, di/dt = 100 A/µs VDD = 60 V, Tj = 150 °C (see Figure 17) - 224 1.5 13 ns µC A 1. Pulse width limited by safe operating area. 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% Doc ID 022254 Rev 1 5/15 Electrical characteristics STD9NM50N 2.1 Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance Figure 5. Transfer characteristics AM07915v1 ID (A) on ) 10µs 100µs D S( O Li per m at ite io d ni by n m this ax a R rea is 10 1 1ms 10ms 0.1 Tj=150°C Tc=25°C Single pulse 0.01 0.1 Figure 4. 10 1 100 VDS(V) Output characteristics AM07917v1 ID (A) VGS=10V 10 AM07918v1 ID (A) VDS= 20 V 10 7V 8 8 6V 6 6 4 4 5V 2 2 0 0 Figure 6. 20 10 30 Static drain-source on resistance AM07919v1 RDS(on) (Ω) 0.77 0 0 VDS(V) Figure 7. 2 4 AM03195v1 VDD=400 V 12 400 ID=5 A 350 VDS 10 0.76 VGS(V) Gate charge vs gate-source voltage VGS (V) VGS=10V 8 6 300 0.75 8 250 6 200 0.74 0.73 150 0.72 4 100 0.71 2 0.7 0.69 0 6/15 1 2 3 4 5 ID(A) Doc ID 022254 Rev 1 50 0 0 5 10 15 0 Qg(nC) STD9NM50N Figure 8. Electrical characteristics Capacitance variations Figure 9. AM07921v1 C (pF) Normalized BVdss vs temperature AM07925v1 BVDSS (norm) ID = 1 mA 1000 1.05 Ciss 1.03 1.01 100 Coss 0.99 0.97 10 Crss 1 0 1 10 100 0.95 VDS(V) Figure 10. Normalized gate threshold voltage vs temperature AM07923v1 VGS(th) (norm) ID = 250 µA 0.93 -50 -25 1.3 0.80 0.9 50 75 100 75 100 TJ(°C) AM07924v1 ID = 2.5 A 0.90 25 50 RDS(on) (norm) 2.1 1.7 0 25 Figure 11. Normalized on resistance vs temperature 1.00 0.70 -50 -25 0 TJ(°C) Doc ID 022254 Rev 1 0.5 -50 -25 0 25 50 75 100 TJ(°C) 7/15 Test circuits 3 STD9NM50N Test circuits Figure 12. Switching times test circuit for resistive load Figure 13. Gate charge test circuit VDD 12V 47kΩ 1kΩ 100nF 3.3 μF 2200 RL μF VGS IG=CONST VDD 100Ω Vi=20V=VGMAX VD RG 2200 μF D.U.T. D.U.T. VG 2.7kΩ PW 47kΩ 1kΩ PW AM01468v1 AM01469v1 Figure 14. Test circuit for inductive load Figure 15. Unclamped inductive load test switching and diode recovery times circuit A A D.U.T. FAST DIODE B B L A D G VD L=100μH S 3.3 μF B 25 Ω 1000 μF D VDD 2200 μF 3.3 μF VDD ID G RG S Vi D.U.T. Pw AM01470v1 Figure 16. Unclamped inductive waveform AM01471v1 Figure 17. Switching time waveform ton V(BR)DSS tdon VD toff tr tdoff tf 90% 90% IDM 10% ID VDD 10% 0 VDD VDS 90% VGS AM01472v1 8/15 0 10% Doc ID 022254 Rev 1 AM01473v1 STD9NM50N 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Doc ID 022254 Rev 1 9/15 Package mechanical data Table 9. STD9NM50N DPAK (TO-252) mechanical data mm Dim. Min. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 E 5.10 6.40 6.60 E1 4.70 e 2.28 e1 4.40 4.60 H 9.35 10.10 L 1 1.50 L1 2.80 L2 0.80 L4 0.60 R V2 10/15 Typ. 1 0.20 0° 8° Doc ID 022254 Rev 1 STD9NM50N Package mechanical data Figure 18. DPAK (TO-252) drawing 0068772_H Figure 19. DPAK footprint(a) 6.7 3 3 1.6 2.3 6.7 2.3 1.6 AM08850v1 a. All dimension are in millimeters Doc ID 022254 Rev 1 11/15 Packaging mechanical data 5 STD9NM50N Packaging mechanical data Table 10. DPAK (TO-252) tape and reel mechanical data Tape Reel mm mm Dim. Dim. Min. Max. A0 6.8 7 A B0 10.4 10.6 B 1.5 12.1 C 12.8 1.6 D 20.2 G 16.4 50 B1 12/15 Min. Max. 330 13.2 D 1.5 D1 1.5 E 1.65 1.85 N F 7.4 7.6 T K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3 Doc ID 022254 Rev 1 18.4 22.4 STD9NM50N Packaging mechanical data Figure 20. Tape for DPAK (TO-252) 10 pitches cumulative tolerance on tape +/- 0.2 mm T P0 Top cover tape P2 D E F B1 W K0 B0 For machine ref. only including draft and radii concentric around B0 A0 P1 D1 User direction of feed R Bending radius User direction of feed AM08852v1 Figure 21. Reel for DPAK (TO-252) T REEL DIMENSIONS 40mm min. Access hole At sl ot location B D C N A Full radius Tape slot in core for tape start 25 mm min. width G measured at hub AM08851v2 Doc ID 022254 Rev 1 13/15 Revision history 6 STD9NM50N Revision history Table 11. 14/15 Document revision history Date Revision 21-Sep-2011 1 Changes First release. Doc ID 022254 Rev 1 STD9NM50N Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. 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