STDRIVE601

STDRIVE601 Datasheet Triple half-bridge high-voltage gate driver Features • • • • • • • • • • • • • SO-28 High voltage rail up to 600 V Driver current capability: – 200 mA source current @ 25 °C – 350 mA sink current @ 25 °C dV/dt transient immunity ±50 V/ns Gate driving voltage range from 9 V to 20 V Overall input-output propagation delay: 85 ns Matched propagation delay for all channels 3.3 V, 5 V TTL/CMOS inputs with hysteresis Integrated bootstrap diodes Comparator for fast overcurrent protection Smart shutdown function Interlocking and deadtime function Dedicated Enable pin UVLO function on low-side and high-sides Applications • • 3-phase motor drives Inverters Product status link Description STDRIVE601 Product summary Order code STDRIVE601 Package Packing STDRIVE601TR SO-28 Tube Product label Tape & Reel The STDRIVE601 is a high voltage device manufactured with BCD6s offline technology. It is a single-chip with three half-bridge gate drivers for N-channel power MOSFETs or IGBTs suitable for 3-phase applications. All device outputs can sink and source 350 mA and 200 mA respectively. Prevention from cross conduction is ensured by interlocking and deadtime function. The device has dedicated input pins for each output and a shutdown pin. The logic inputs are CMOS/TTL compatible down to 3.3 V for easy interfacing with control devices. Matched delays between low-side and high-side sections guarantee no cycle distortion and allow high frequency operation. The STDRIVE601 embeds a comparator featuring advanced SmartSD function also integrated in the device, ensuring fast and effective protection against fault events like overcurrent, overtemperature, etc. Dedicated UVLO protection on the low-sides and each of the high-side driving sections allow to prevent the power switches from operating in low efficiency or dangerous conditions. The integrated bootstrap diodes as well as all of the integrated features of this IC make the application PCB design easier, more compact and simpler, thus reducing the overall bill of material. The device is available in SO-28 package. DS12949 - Rev 2 - April 2021 For further information contact your local STMicroelectronics sales office. www.st.com STDRIVE601 Block diagram 1 Block diagram Figure 1. Block diagram VCC VCC D1 VCC UVLO VCC UVLO DETECTION +5V BOOT1 VBO UVLO & Level Shifter Input noise filter HIN1 +5V Floating structure VCC VBO UVLO & Level Shifter +5V HVG2 Floating structure Input noise filter HlN3 OUT1 D2 BOOT2 Input noise filter HIN2 HVG1 VCC OUT2 D3 LOGIC +5V Input noise filter LIN1 +5V SHOOT THROUGH PREVENTION DEADTIME BOOT3 VBO UVLO & Level Shifter HVG3 Floating structure OUT3 VCC Input noise filter LIN2 LVG1 +5V VCC Input noise filter LlN3 LVG2 EN Input noise filter EN VCC LVG3 FAULT VCC UVLO +5V IOD OD SMART SD PGND +5V CIN + - + Comparator input filter VREF SGND DS12949 - Rev 2 page 2/26 STDRIVE601 Pin description and connection diagram 2 Pin description and connection diagram Figure 2. Pin connection (top view) 1 28 BOOT1 HIN1 2 27 HVG1 HIN2 3 26 OUT1 HIN3 4 25 NC LIN1 5 24 BOOT2 LIN2 6 23 HVG2 LIN3 7 22 OUT2 FAULT 8 21 NC CIN 9 20 BOOT3 EN 10 19 HVG3 OD 11 18 OUT3 SGND 12 17 NC PGND 13 16 LVG1 LVG3 14 15 LVG2 VCC Table 1. Pin description DS12949 - Rev 2 Pin # Pin Name Type 1 VCC Power Supply 2 HIN1 Logic Input High-side driver logic input 1 3 HIN2 Logic Input High-side driver logic input 2 4 HIN3 Logic Input High-side driver logic input 3 5 LIN1 Logic Input Low-side driver logic input 1 6 LIN2 Logic Input Low-side driver logic input 2 7 LIN3 Logic Input Low-side driver logic input 3 8 FAULT OD Output Fault output 9 CIN Analog Input Comparator positive input 10 EN Logic Input Enable input, active high 11 OD OD Output SmartSD timing Open Drain output, unlatch and restart input 12 SGND Power Supply Signal ground 13 PGND Power Supply Low-side driver ground 14 LVG3(1) Analog Output Low-side driver output 3 15 LVG2(1) Analog Output Low-side driver output 2 16 LVG1(1) Analog Output Low-side driver output 1 17, 21 25 N.C. - 18 OUT3 Power Supply High-side (floating) common voltage driver 3 19 HVG3(1) Analog Output High-side driver output 3 20 BOOT3 Power Supply Bootstrap supply voltage 3 22 OUT2 Power Supply High-side (floating) common voltage driver 2 Function Low-side and logic supply voltage Not Connected page 3/26 STDRIVE601 Pin description and connection diagram Pin # Pin Name Type Function 23 HVG2(1) Analog Output High-side driver output 2 24 BOOT2 Power Supply Bootstrap supply voltage 2 26 OUT1 Power Supply High-side (floating) common voltage driver 1 27 HVG1(1) Analog Output High-side driver output 1 28 BOOT1 Power Supply Bootstrap supply voltage 1 1. The circuit guarantees less than 1 V on the LVG and HVG pins (at Isink = 10 mA), with VCC > 3 V. This allows omitting the “bleeder” resistor connected between the gate and the source of the external MOSFETs normally used to hold the pin low. DS12949 - Rev 2 page 4/26 STDRIVE601 Electrical data 3 Electrical data 3.1 Absolute maximum ratings Table 2. Absolute maximum ratings Note: Each voltage referred to SGND unless otherwise specified. Symbol Min. Max. Unit -0.3 21 V Low-side driver ground VCC - 21 VCC + 0.3 V VPS Low-side drivers ground -21 21 V VOUT Output voltage VBOOT - 21 VBOOT + 0.3 V VBOOT Bootstrap voltage - 0.3 620 V VHVG High-side gate output voltage VOUT - 0.3 VBOOT + 0.3 V VLVG Low-side gate output voltage VPGND - 0.3 VCC + 0.3 V VCIN Comparator input voltage - 0.3 20 V Logic input voltage(2) - 0.3 15 V OD pin voltage - 0.3 21 V FAULT pin voltage - 0.3 21 V 50 V/ns VCC VPGND (1) Vi VOD VFAULT dVOUT/dt Parameter Logic supply voltage Common mode transient Immunity TJ Junction temperature -40 150 °C TS Storage temperature -50 150 °C ESD Human body model 2(3) kV 1. VPS = PGND - SGND. 2. EN, LINx, HINx. 3. Pins 18 to 28 have HBM ESD rating 1C conforming to ANSI/ESDA/JEDEC JS-001-2014. 3.2 Thermal data Table 3. Thermal data Symbol Parameter Value Unit Rth(JA) Thermal resistance junction to ambient(1) 52 °C/W 1. JEDEC 2s2p PCB in still air. DS12949 - Rev 2 page 5/26 STDRIVE601 Recommended operating conditions 3.3 Recommended operating conditions Table 4. Recommended operating conditions Note: Each voltage referred to SGND unless otherwise specified. Symbol VCC (1) VLS VPS(2) (3) Parameter Test conditions Min. Max. Unit Logic supply voltage - 9 20 V Low-side drivers supply voltage - 4 20 V Low-side drivers ground - -5 5 V - 8.5 20 V VBO Floating supply VOUT DC Output voltage - -10(4) 580 V VCIN Comparator input voltage - 0 15 V Logic input voltage - 0 15 V OD pin voltage - 0 20 V FAULT pin voltage - 0 20 V Maximum switching frequency - - 800 kHz Minimum input pulse width - 100 - ns Junction temperature - -40 125 °C Vi VOD VFAULT FSW (5) PW(6) TJ voltage(3) 1. VLS = VCC - PGND 2. VPS = PGND - SGND. 3. VBO = BOOT - OUT. 4. VCC = 9 V, LVG off. Logic is operational if VBOOT > 5 V. 5. Actual maximum FSW depends on power dissipation. 6. Pulse width on LIN or HIN pins. See Figure 3. Propagation delay timing definition. DS12949 - Rev 2 page 6/26 STDRIVE601 Electrical characteristics 4 Electrical characteristics Table 5. Electrical characteristics Note: VCC = 15 V; PGND = SGND; TJ = +25 °C, unless otherwise specified. HIN is referred to channels HIN1, HIN2, HIN3; LIN is referred to channels LIN1, LIN2, LIN3. Symbol Pin Parameter Test conditions Min. Typ. Max. Unit Low-side section supply VCCTHON VCC UVLO turn-on threshold - 8 8.5 9 V VCCTHOFF VCC UVLO turn-off threshold - 7.5 8 8.5 V VCC UVLO hysteresis - 0.4 0.5 0.6 V IQCCU VCC undervoltage quiescent supply current VCC = 7 V; EN = 5 V; CIN = SGND LVG & HVG: OFF - 430 744 μA IQCC VCC quiescent supply current EN = 5 V; CIN = SGND LVG & HVG: OFF - 950 1450 μA VCCHYS - High-side floating section supply(1) VBOTHON VBO UVLO turn-on threshold - 7.5 8 8.5 V VBOTHOFF VBO UVLO turn-off threshold - 7 7.5 8 V - 0.4 0.5 0.6 V VCC = VBO = 6.5 V; EN = 5 V; CIN = SGND LVG OFF; HVG = ON - 25 62 μA VBOquiescent supply current VBO = 15 V EN = 5 V; CIN = SGND LVG OFF; HVG = ON - 84 150 μA VBOHYS IQBOU VBO UVLO hysteresis 20 - 18 24 - 22 28 - 26 VBO undervoltage quiescent supply current IQBO ILK - High voltage leakage current BOOT = HVG = OUT = 620V - - 15 μA RDboot - Bootstrap Diode on resistance - - 215 - Ω 160 200 300 mA 130 - 350 - TJ = 25°C 230 350 430 mA Full temperature range(2) 200 - 500 - Output driving buffers ISO ISI High/Low-side source peak current TJ = 25°C Full temperature 14, 15, 16, 19, 23, 27 High/Low-side sink peak current range(2) RDSonON High/Low-side source RDSon I = 10 mA 24 35 46 Ω RDSonOFF High/Low-side sink RDSon I = 10 mA 11 16 21 Ω Low level logic threshold voltag - 0.8 - 1.4 V High level logic threshold voltage - 1.8 - 2.3 V Logic input threshold hysteresis - 0.8 - 1.2 V SmartSD restart threshold - 3.5 4 4.3 V SmartSD unlatch threshold - - 0.56 0.75 V LIN logic “1” input bias current VLINx = 15 V - - 1 μA LIN logic “0” input bias current VLINx = 0 V 28 43 58 μA Logic Inputs Vil Vih Vhyst VSSDh VSSDl ILINh ILINl DS12949 - Rev 2 2, 3, 4, 5, 6, 7, 10 2, 3, 4, 5, 6, 7, 10 11 5, 6, 7 page 7/26 STDRIVE601 Electrical characteristics Symbol IHINh IHINl RPU_IN IENh IENl RPD_EN Pin 2, 3, 4 2, 3, 4, 5, 6, 7 10 10 Parameter Test conditions HIN logic “1” input bias current VHINx = 15 V HIN logic “0” input bias current Min. Typ. Max. Unit - - 1 μA VHINx = 0 28 43 58 μA Logic input pull-up resistor - 75 100 125 kΩ EN logic “1” input bias current VEN = 15 V 110 150 200 μA EN logic "0" input bias current VEN = 0 V - - 1 μA EN pull-down resistor - 75 100 125 kΩ Sense comparator(3) and FAULT VREF - Internal voltage reference - 410 460 510 mV CINhyst 9 Comparator input hysteresis - 40 70 - mV CIN_PD 9 Comparator input pull- down current VCIN = 1 V 7 10 13 μA IOD 11 OD internal current source - 2.5 5 7.5 μA RON_OD 11 OD On resistance IOD = 16 mA 19 25 36 Ω IOL_OD 11 OD low level sink current VOD = 400 mV 11 16 21 mA ISAT_OD 11 OD saturation current VOD = 5 V - 95 - mA VFLOAT_OD 11 OD floating voltage level OD connected only to an external capacitance 4.4 4.8 5.2 V RON_F 8 FAULT ON resistance IFAULT = 8 mA - 50 100 Ω IOL_F 8 FAULT low level sink current VFAULT = 400 mV 4 8 12 mA tOD 11 Comparator propagation delay Rpu = 100 kΩ to 5 V; voltage step on CIN = 0 to 3.3 V; 50% CIN to 90% OD - 350 500 ns tCIN-F 11 Comparator triggering to FAULT voltage step on CIN = 0 to 3.3 V; 50% CIN to 90% FAULT - 350 500 ns tCINoff 11 Comparator triggering to high/lowside driver propagation delay voltage step on CIN = 0 to 3.3 V; 50% CIN to 90% LVG/HVG - 360 510 ns tFCIN 11 Comparator input filter time - 200 300 400 ns SR 11 OD Slew rate CL = 1 nF; Rpu = 33 kΩ to 5 V; 90% to 10% OD 20 60 100 V/μs 45 85 120 ns 45 85 120 ns 245 385 520 ns Dynamic characteristics DS12949 - Rev 2 ton 2 vs. 27 High/Low-side driver turn-on vs 23 propagation delay vs 19 toff 5 vs. 16 High/Low-side driver turn-off 6 vs. 15 propagation delay 7 vs. 14 tEN 10 vs. 14, 15, 16, 19, 23, 27 Enable to high/low- side driver propagation delay tFIN 2,3,4, 5,6,7 LIN HIN input filter time - 30 40 50 ns tFEN 10 EN input filter time - 200 300 400 ns OUT = 0 V BOOT = VCC CL = 1 nF Vin = 0 to 3.3 V page 8/26 STDRIVE601 Electrical characteristics Symbol Pin tr tf 14, 15, 16, 19, 23, 27 MT Parameter Test conditions Min. Typ. Max. Unit Rise time CL= 1 nF - 120 160 ns Fall time CL= 1 nF - 50 75 ns - Delay matching high/low side turnon/off(4) - - 0 30 ns DT - Deadtime CL= 1 nF 200 300 400 ns MDT - Matching deadtime(5) CL= 1 nF - 0 50 ns 1. VBO = BOOT - OUT. 2. Values provided by characterization, not tested. 3. Comparator is disabled when VCC is in UVLO condition. 4. MT = max. (|ton(LVG) - toff(LVG)|, |ton(HVG) - toff(HVG)|, |toff(LVG) - ton(HVG)|, |toff(HVG) - ton(LVG)|). 5. MDT = | DTLH - DTHL |, refer to Section 4 Electrical characteristics Figure 3. Propagation delay timing definition LIN 50% 50% t > DT t > DT HIN 50% 50% 50% tr tf 90% LVG 10% 10% t on tr 90% 10% 10% t on t off 50% 50% 90% LVG/HVG 10% t EN DS12949 - Rev 2 t off tf 90% HVG EN 90% t EN page 9/26 STDRIVE601 Electrical characteristics Figure 4. Deadtime timing definitions t > DT LIN 50% 50% HIN 50% 50% tr tf 90% HVG 90% 10% 10% t off tf 90% LVG 10% t off DS12949 - Rev 2 DTLH 10% DTHL page 10/26 STDRIVE601 Electrical characteristics Figure 5. Deadtime and interlocking waveforms definition LIN INTERLOCKING CONTROL SIGNAL EDGES OVERLAPPED FOR MORE THAN DEAD TIME: INTERLOCKING INTERLOCKING HIN LVG DTHL DTLH HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) OCK ING ERL OCK HIN LVG INT INT ERL CONTROL SIGNAL EDGES OVERLAPPED: INTERLOCKING + DEAD TIME ING LIN DTHL DTLH HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) LIN CONTROL SIGNALS EDGES SYNCHRONOUS (*): DEAD TIME HIN LVG DTLH DTHL HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) LIN CONTROL SIGNALS EDGES NOT OVERLAPPED, BUT INSIDE THE DEAD TIME: DEAD TIME HIN LVG DTLH DTHL HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) LIN CONTROL SIGNALS EDGES NOT OVERLAPPED, OUTSIDE THE DEAD TIME: DIRECT DRIVING HIN LVG DTLH DTHL HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) DS12949 - Rev 2 gate driver outputs OFF (HALF-BRIDGE TRI-STATE) page 11/26 STDRIVE601 Functional description 5 Functional description 5.1 Inputs and outputs The devices are controlled through the following logic inputs: • EN: Enable input, active high; • LIN: low-side driver inputs, active low; • HIN: high-side driver inputs, active low. Table 6. Inputs truth table Note: Applicable when device is not in UVLO or SmartSD protection Input pins Output pins EN LIN HIN LVG HVG L X X Low Low H H H Low Low H L H High Low H H L Low High Low Low Interlocking H L L The FAULT and OD pins are open-drain outputs. The FAULT signal is set low in case VCC UVLO is detected, or in case the SmartShutDown comparator triggers an event. It is only used to signal a UVLO or SmartSD activation to external circuits, and its state does not affect the behavior of other functions or circuits inside the driver. The OD behavior is explained in Section 5.5 Comparator and smart shutdown. When EN is set low, gate driver outputs are forced low and assure low impedance. 5.2 Deadtime The deadtime feature, in companion with interlocking feature, guarantees that driver outputs of the same channel are not high simultaneously and at least a DT time passes between the turn-off of one driver's output and the turn-on of the companion output of the same channel. If a deadtime longer than the internal DT is applied to LIN and HIN inputs by the external controller, the internal DT is ignored, and the outputs follow the deadtime determined by the inputs. Refer to Figure 4. Deadtime timing definitions for the dead time and interlocking waveforms. 5.3 VCC UVLO protection Undervoltage protection is available on VCC and BOOT supply pins. In order to avoid intermittent operation, a hysteresis set the turn-off threshold with respect to the turn-on threshold. When VCC voltage goes below VCCTHOFF threshold all the outputs are switched off, both LVG and HVG. When VCC voltage reaches VCCTHON threshold the driver returns to normal operation and sets the LVG outputs according to actual input pins status; HVG is also set according to input pin status if the corresponding VBO section is not in UVLO condition. The FAULT output is kept low when VCC is in UVLO condition. The following figures show some examples of typical operation conditions. DS12949 - Rev 2 page 12/26 STDRIVE601 VBO UVLO protection Figure 6. VCC power ON and UVLO, LVG timing Fault pin connected to external pull-up. VCCthON VCCthOFF VCC 0V FAULT 0V UVLO VCC LIN 0V LVG 0V Figure 7. VCC power ON and UVLO, HVG timing Fault pin connected to external pull-up. VCCthON VCCthOFF VCC 0V FAULT UVLO VCC HIN 0V 0V VBOthON VBOthOFF VBO 0V HVG-OUT 5.4 VBO UVLO protection Dedicated undervoltage protection is available on each bootstrap section between BOOTx and OUTx supply pins. In order to avoid intermittent operation, a hysteresis sets the turn-off threshold with respect to the turn-on threshold. When VBO voltage goes below VBOTHOFF threshold, the HVG output of corresponding bootstrap section is switched off. When VBO voltage reaches VBOTHON threshold device returns to normal operation and the output remains off up to the next input pins transition that requests HVG to turn on. DS12949 - Rev 2 page 13/26 STDRIVE601 Comparator and smart shutdown Figure 8. VBO power-ON and UVLO timing VCCthON VCCthOFF VCC 0V FAULT 0V HIN 0V VBOthON VBOthOFF VBO HVG-OUT 5.5 0V 0V Comparator and smart shutdown This device integrates a comparator committed to the fault protection function, thanks to the SmartShutDown (SmartSD) circuit. The SmartSD architecture allows immediate turn-off of the gate driver outputs in the case of overload or overcurrent condition, by minimizing the propagation delay between the fault detection event and the actual output switch-off. In fact, the time delay between the fault detection and the output turn-off is not dependent on the value of the external components connected to the OD pin, which are only used to set the duration of disable time after the fault. This provides the possibility to increase the duration of the output disable time after the fault event up to very large values without increasing the delay time of the protection. The duration of the disable time is determined by the values of the external capacitor COD and of the optional pull-up resistor connected to OD pin. The comparator has an internal voltage reference VREF connected to the inverting input, while the non-inverting input is available on the CIN pin. The comparator CIN input can be connected to an external shunt resistor in order to implement a fast and simple overcurrent protection function. The output signal of the comparator is filtered from glitches shorter than tFCIN and then fed to the SmartSD logic. If the impulse on CIN pin is higher than VREF and wider than tFCIN, the SmartSD logic is triggered and immediately sets all of the driver outputs to low-level (OFF). At the same time, FAULT is forced low to signal the event (for example to an MCU input) and OD starts to discharge the external COD capacitor used to set the duration of the output disable time of the fault event. The FAULT pin is released and driver outputs restart following the input pins as soon as the output disable time expires. The overall disable time is composed of two phases: • The OD unlatch time (t1 in Figure 9. Smart shutdown timing waveforms), which is the time required to discharge COD capacitor down to VSSDl threshold. The discharge starts as soon as the SmartSD comparator is triggered. • The OD restart time (t2 in Figure 9. Smart shutdown timing waveforms, which is the time required to recharge the COD capacitor up to the VSSDh threshold. The recharge of COD starts when the OD internal MOSFET is turned-off, which happens when the fault condition has been removed (CIN < VREF - CINhyst) and the voltage on OD reaches the VSSDl threshold. This time normally covers most of the overall output disable time. DS12949 - Rev 2 page 14/26 STDRIVE601 Comparator and smart shutdown If no external pull-up is connected to OD, the external COD capacitor is discharged with a time constant defined by COD and the internal MOSFET's characteristic (Eq. (1)), and the Restart time is determined by the internal current source IOD and by COD (Eq. (2)). t1 ≅ RON _ OD ⋅ COD ⋅ ln VOD VSSDl C ⋅V V −V t2 ≅ OD SSDℎ ⋅ ln SSDl − VOD IOD VSSDℎ OD (1) (2) In case the OD pin is connected to VCC by an external pull-up resistor ROD_ext, the OD discharge time is determined by the external network ROD_ext COD and by the internal MOSFET's RON_OD (Eq. (3)), while the Restart time is determined by current in ROD_ext (Eq. (4)). VOD − Von t1 ≅ COD ⋅ ROD _ ext / / RON _ OD ⋅ ln VSSDl − Von Where: t1 ≅ COD ⋅ ROD _ ext ⋅ ln VSSDl − VOD VSSDℎ − VOD (3) (4) RON _ OD Von = R ;V = VCC ON _ ext + RON _ OD OD DS12949 - Rev 2 page 15/26 STDRIVE601 Comparator and smart shutdown Figure 9. Smart shutdown timing waveforms VREF CIN t FCIN t FCIN Fast shut down t CINoff the driver outputs are switched off immediately after the comparator triggering LVG/HVG VOD OD VSSDh VSSDl 1 OD gate (internal) 2 t1 t2 disable time FAULT SMART SHUTDOWN CIRCUIT external pull-up VCC 5V 5V ROD_ext IOD OD OD SMART SD LOGIC COD RON_OD DS12949 - Rev 2 IOD SMART SD LOGIC COD RON_OD page 16/26 STDRIVE601 Typical application diagram 6 Typical application diagram Figure 10. Typical application diagram VCC VCC VCC + VCC UVLO DETECTION +5V CVCC1 BOOT1 VBO UVLO & Level Shifter Input noise filter HIN1 +5V HV OUT1 D2 BOOT BOOT2 Input noise filter HIN2 HVG1 Floating structure VCC + VBO UVLO & Level Shifter +5V FROM CONTROLLER D1 VCC UVLO HVG2 Input noise filter HlN3 VCC LIN Input noise filter LIN1 +5V SHOOT THROUGH PREVENTION DEADTIME HVG OUT2 DH BOOT3 VBO UVLO & Level Shifter HVG3 Floating structure IGBT DL EN RS VCC LVG3 VCC UVLO ROD 3x Power Half-Bridge LVG2 FAULT Vcc RGL_OFF VCC EN input noise filter CSD TO RFAULT CONTROLLER LS LVG1 Input noise filter LlN3 FROM CONTROLLER RGL_ON LVG +5V VDD THREE-PHASE MOTOR M OUT3 Input noise filter LIN2 IGBT RGH_OFF OUT VCC 3x Half-Bridge Inputs RGH_ON HS D3 LOGIC +5V FROM CONTROLLER Floating structure CHV CBOOT HIN IOD VCC OD SMART SD COD +5V CIN + CLP - + CVCC2 PGND Comparator input filter VREF RLP SGND DS12949 - Rev 2 page 17/26 STDRIVE601 Package information 7 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 7.1 SO-28 package information Table 7. SO-28 package dimensions Dim. DS12949 - Rev 2 Mm Min. Typ. Max. A 2.35 - 2.65 A1 0.10 - 0.30 B 0.33 - 0.51 C 0.23 - 0.32 D 17.70 - 18.10 E 7.40 - 7.60 e - 1.27 - H 10.00 - 10.65 h 0.25 - 0.75 L 0.40 - 1.27 k 0° - 8° ddd - - 0.10 page 18/26 STDRIVE601 SO-28 package information Figure 11. SO-28 mechanical data hx45° D A C A1 B SEATING PLANE 15 E H PIN 1 IDENTIFIER 28 k 14 A1 1 L e DS12949 - Rev 2 page 19/26 STDRIVE601 SO-28 package information Figure 12. SO-28 suggested land pattern 11.50 7.50 DS12949 - Rev 2 1.27 0.60 (x28) 2.00 page 20/26 STDRIVE601 Ordering information 8 Ordering information Table 8. Order codes DS12949 - Rev 2 Order code Package Package marking Packaging STDRIVE601 SO-28 STDRV601 Tube STDRIVE601TR SO-28 STDRV601 Tape and reel page 21/26 STDRIVE601 Revision history Table 9. Document history Date Revision 21-May-2019 1 Changes Initial release. Throughout document: - updated template - minor text edits 02-Apr-2021 2 In Table 2. Absolute maximum ratings: - updated ESD value and added footnote In Table 5. Electrical characteristics: - updated VSSDh Typ. and Max. values - updated VFLOAT_OD Min., Typ., and Max. values DS12949 - Rev 2 page 22/26 STDRIVE601 Contents Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Pin description and connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3.1 Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 5.1 Inputs and outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2 Deadtime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.3 VCC UVLO protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.4 VBO UVLO protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.5 Comparator and smart shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 7 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 7.1 8 SO-28 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 DS12949 - Rev 2 page 23/26 STDRIVE601 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. DS12949 - Rev 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . Pin connection (top view) . . . . . . . . . . . . . . . . Propagation delay timing definition . . . . . . . . . Deadtime timing definitions . . . . . . . . . . . . . . Deadtime and interlocking waveforms definition VCC power ON and UVLO, LVG timing . . . . . . VCC power ON and UVLO, HVG timing . . . . . . VBO power-ON and UVLO timing . . . . . . . . . . Smart shutdown timing waveforms . . . . . . . . . Typical application diagram . . . . . . . . . . . . . . SO-28 mechanical data . . . . . . . . . . . . . . . . . SO-28 suggested land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 3 . 9 10 11 13 13 14 16 17 19 20 page 24/26 STDRIVE601 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Pin description. . . . . . . . . . . . . . . . Absolute maximum ratings . . . . . . . Thermal data. . . . . . . . . . . . . . . . . Recommended operating conditions. Electrical characteristics . . . . . . . . . Inputs truth table . . . . . . . . . . . . . . SO-28 package dimensions . . . . . . Order codes . . . . . . . . . . . . . . . . . Document history. . . . . . . . . . . . . . DS12949 - Rev 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 . 5 . 5 . 6 . 7 12 18 21 22 page 25/26 STDRIVE601 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2021 STMicroelectronics – All rights reserved DS12949 - Rev 2 page 26/26