STG6684QTR

STG6684 High isolation dual SPDT analog switch Features ■ Ultra high off-isolation: -80 dB (typ) at 1 Mhz ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o Description ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O ■ Ultra low power dissipation: ICC = 0.2 μA (max.) at TA = 85 °C ■ RPEAK on Tn = 1.30 Ω max (TA = 25 °C) at VCC = 4.3 V ■ RPEAK on Sn = 0.55 Ω max (TA = 25 °C) at VCC = 4.3 V ■ Wide operating voltage range: VCC (opr) = 1.65 to 4.3 V single supply ■ 4.3 V tolerant and 1.8 V compatible threshold on digital control input at VCC = 1.65 to 4.3 V ■ Typical bandwidth (-3 dB) at 65 MHz on Sn channel, 58 MHz on the Tn channel ■ Latch-up performance exceeds 100 mA per JESD 78, Class II ■ ESD performance exceeds JESD22 2000-V Human body model (A114-A) QFN10L (1.8 x 1.4 mm) The switch Tn is “on” (connected to common port Dn) when the SELn input is held high and “off” (high impedance state exists between the two ports) when SELn is held low. Additional key features are fast switching speed, break-before-make delay time and ultra low power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them ESD immunity and transient excess voltage. The STG6684 is a high-speed CMOS low voltage dual analog SPDT (single pole dual throw) switch or 2:1 multiplexer/de-multiplexer switch fabricated in silicon gate C2MOS technology. The STG6684 is designed to operate from 1.65 to 4.3 V, making this device ideal for portable applications. The SELn inputs are provided to control the switch operation. The switch Sn is ON (connected to common ports Dn) when the SELn input is held low and OFF (high impedance state exists between the two ports) when SELn is held high. Table 1. Device summary Order code Package Packaging STG6684QTR QFN10L (1.8 x 1.4 mm) Tape and reel January 2008 Rev 1 1/24 www.st.com 24 Table of contents STG6684 Table of contents 1 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2/24 STG6684 Pin settings Pin connection (top through view) SEL1 Figure 1. D1 1 Pin settings 10 9 S1 1 8 GND T1 2 7 T2 ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O Table 2. 3 5 D2 6 4 SEL2 VCC S2 Pin description Pin number Symbol Name and function 1 S1 Independent channel 2 T1 Independent channel 3 VCC 4 SEL2 Selection control 5 D2 Common channel 6 S2 Independent channel 7 T2 Independent channel 8 GND Ground (0 V) 9 SEL1 Selection control 10 D1 Common channel Positive supply voltage 3/24 Logic diagram 2 STG6684 Logic diagram Figure 2. Logic block diagram SEL1 S1 D 1 ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O T1 S2 D 2 T2 SEL2 Table 3. Truth table SELn Switch Sn Switch Tn L Sn is connected to Dn OFF(1) H OFF(1) Tn is connected to Dn 1. High impedance 4/24 STG6684 3 Maximum rating Maximum rating Stressing the device above the rating listed in the “Absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 4. Absolute maximum ratings Symbol VCC Parameter Value Supply voltage VIC DC control input voltage VO DC output voltage IIKC DC input diode current on control pin (VSEL < 0 V) IIK DC input diode current (VSEL < 0 V) IOK DC output diode current IO DC output current IOP DC output current peak (pulse at 1 ms, 10% duty cycle) e t e l so b O TL b O - Power dissipation at TA=70 °C(1) u d o Pr (s) V -0.5 to 5.5 V Lead temperature (10 sec) Pr ) s t( -0.5 to VCC + 0.5 V − 50 mA c u d ± 50 ro P e let so ICC or IGND DC VCC or ground current Storage temperature -0.5 to VCC + 0.5 u d o )- s ( t c V ct DC input voltage TSTG (s) -0.5 to 5.5 VI PD Unit mA ± 20 mA ± 300 mA ± 500 mA ± 100 mA 1120 mW -65 to 150 °C 300 °C t c u 1. Derate above 70 °C by 18.5 mW/°C ete l o s b O d o r P e t e l o s b O 5/24 Maximum rating 3.1 STG6684 Recommended operating conditions Table 5. Recommended operating conditions Symbol VCC Parameter Supply voltage Value Unit 1.65 to 4.3 V VI Input voltage 0 to VCC V VIC Control input voltage 0 to 4.3 V VO Output voltage 0 to VCC V Top Operating temperature -40 to 85 °C VCC = 1.65 V to 2.7 V ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O dt/dv 6/24 Input rise and fall time control input 0 to 20 ns/V VCC = 3.0 V to 4.3 V 0 to 10 STG6684 4 Electrical characteristics Electrical characteristics Table 6. DC specifications Value Symbol VCC (V) Parameter TA = 25 °C Test condition Min VIH High level input voltage Typ Max 0.65 VCC 0.65 VCC 2.3 −2.5 1.2 1.2 2.7 −3.0 1.3 1.3 3.3 −3.6 1.4 4.3 1.5 3.3 −3.6 o s b 4.3 e t e l RPEAK, Sn o s b O 1.3 1.5 1.15 1.4 1.6 1.25 1.5 1.8 1.35 1.6 1.9 2.20 2.9 3.5 0.45 0.55 0.62 0.48 0.58 0.65 0.51 0.62 0.70 2.7 0.54 0.70 0.80 1.8 0.84 1.10 1.30 4.3 10 O ) 3.0 Switch SnON resistance ΔRON, Tn ΔRON, Sn 2.7 1.8 ct (s) u d o ON resistance match between Tn channels(1) ON resistance match between Sn channels(1) 4.3 VS = 0 V to VCC IS = 100 mA e t le so b O - 3.6 3.0 VS = 0 V to VCC IS = 100 mA 3.6 3.0 Ω Ω 14 VS at RPEAK IS = 100 mA 14 2.7 15 1.8 30 4.3 7 3.6 3.0 V 0.30 1.10 t(s r P e t e l o s b O o r P od 0.25 0.40 3.6 c u d uc 0.40 4.3 RPEAK, Switch Tn ON Tn resistance ) s t( 0.25 0.25 Pr V 0.25 0.25 0.30 (s) 1.5 d o r P e let 2.7 −3.0 Max t c u 1.4 0.25 2.3 −2.5 Low level input voltage Min 1.65 −1.95 1.65 −1.95 VIL -40 to 85 °C Unit mΩ 7 VS at RPEAK IS = 100 mA 8 2.7 9 1.8 12 mΩ 7/24 Electrical characteristics Table 6. STG6684 DC specifications Value Symbol Parameter VCC (V) Test condition TA = 25 °C Min Typ Max 0.45 0.50 0.55 0.45 0.50 0.55 0.50 0.55 0.60 2.7 0.55 0.60 0.70 1.8 1.10 1.70 2.00 4.3 RFLAT, Tn ON resistance flatness for Tn channels(2) -40 to 85 °C Unit 3.6 3.0 VS = 0 to VCC IS = 100 mA Min Max Ω ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O RFLAT, ON resistance flatness for Sn channels(2) 4.3 0.15 0.20 0.20 3.6 0.15 0.20 0.20 0.15 0.20 0.20 2.7 0.15 0.20 0.20 1.8 0.35 0.55 0.66 VS = 0.3 or 4 V ±0.1 ±1 μA VSEL = 0 to 4.3 V ±0.05 ±1 μA VSEL = VCC or GND ±0.05 ±0.2 μA 3.0 Sn IOFF OFF state leakage current (Tn), (Sn), (Dn) ISEL SEL leakage current ICC Quiescent supply current ICCLV Quiescent supply current low voltage driving 4.3 0 −4.3 1.65 −4.3 4.3 VS = 0 to VCC IS = 100 mA VSEL = 1.65 V ±37 ±50 ±100 VSEL = 1.80 V ±33 ±40 ±50 VSEL = 2.60 V ±12 ±20 ±30 1. ΔRON = RON(max) - RON(min). 2. Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the specified analog signal ranges. 8/24 Ω μA STG6684 Electrical characteristics Table 7. AC electrical characteristics (CL = 35 pF, RL = 50 Ω, tr = tf ≤5 ns) Value Symbol Parameter VCC (V) TA = 25 °C Test condition Min tPLH, tPHL Propagation delay Typ 1.65 −−1.95 0.45 2.3 −−2.7 0.45 3.0 −−3.3 0.30 3.6 −−4.3 0.30 -40 to 85 °C Max Min Unit Max ns ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O 1.65 −−1.95 VS = 0.8 V tON Turn-ON time 120 2.3 −−2.7 3.0 −−3.3 1.65 −−1.95 VS = 0.8 V Turn-OFF time 1.65 −−1.95 Break-beforemake time delay 2.3 −−2.7 3.0 −−3.3 CL = 35 pF RL = 50 Ω VS = 1.5 V 3.6 −−4.3 1.65 −−1.95 Q Charge injection 2.3 −−2.7 3.0 −−3.3 3.6 −−4.3 42 55 65 40 55 65 18 30 40 16 30 40 15 30 40 ns VS = 1.5 V 3.6 −−4.3 tD 90 45 2.3 −−2.7 3.0 −−3.3 85 ns VS = 1.5 V 3.6 −−4.3 tOFF 65 2 18 2 10 2 8 2 6 ns 43 CL = 100 pF RL = 1 MΩ VGEN = 0 V RGEN = 0 Ω 51 pC 51 49 9/24 Electrical characteristics Table 8. STG6684 Analog switch characteristics (CL = 5 pF, RL = 50 Ω, TA = 25 °C) Value Symbol Parameter VCC (V) Test condition TA = 25 °C Min Off isolation OIRRTn for switch T1,T2 1.65 −−4.3 Typ VS=1 VRMS, f=1 MHz, RL = 50 Ω -80 VS=1 VRMS, f = 10 MHz, RL = 50 Ω -60 Max -40 to 85 °C Min Unit Max dB ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O Off isolation OIRRSn for switch S1, S2 XtalkSn XtalkTn 10/24 Crosstalk between S1 and S2 Crosstalk between T1 and T2 1.65 −−4.3 1.65 −− 4.3 1.65 −− 4.3 VS =1 VRMS, f = 100 kHz RL = 50 Ω -66 VS=1 VRMS, f = 1 MHz RL = 50 Ω -45 VS=1 VRMS, f = 1 MHz Signal = 0 dBm -90 dB VS=1 VRMS, f = 10 MHz Signal = 0 dBm -69 dB VS=1 VRMS, f = 1 MHz Signal = 0 dBm -85 dB dB VS=1 VRMS, f = 10 MHz Signal = 0 dBm -74 0.01 % THDSn Total harmonic distortion 2.3 −− 4.3 f = 20 Hz to 20 kHz RL= 600 Ω, CL = 50 pF VIN = 2 VP-P VDC = VCC/2 BWTn -3dB bandwidth for switch T1, T2 1.65 −− 4.3 RL = 50 Ω Signal = 0 dBm 58 MHz BWSn -3dB bandwidth for switch S1,S2 1.65 −− 4.3 RL = 50 Ω Signal = 0 dBm 65 MHz STG6684 Electrical characteristics Value Symbol Parameter VCC (V) Test condition TA = 25 °C Min Typ CSEL Control pin input capacitance CON,Tn Tn port capacitance when the switch is enabled 3.3 Sn port capacitance when the switch is enabled 3.3 Tn port capacitance COFF,Tn when the switch is disabled 3.3 f = 1 MHz 85 Sn port capacitance COFF,Sn when the switch is disabled 3.3 f = 1 MHz 40 VCC = 0 V 9 f = 1 MHz 113 Max -40 to 85 °C Min Unit Max ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O CON,Sn f = 1 MHz 88 pF 11/24 Test circuit 5 STG6684 Test circuit Figure 3. ON resistance I DS V ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O V CC D S1 VS S2 IN GND GND CS14071 12/24 STG6684 Test circuit Figure 4. OFF leakage V CC I I S(OFF) D(OFF) D A A V SS V D ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O S2 IN V CC GND CS14081 Figure 5. OFF isolation V CC S1 V OUT 50 Ω S2 IN GND VS GND CS00381 13/24 Test circuit STG6684 Figure 6. Bandwidth V CC D S1 V OUT S2 ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O V IN CC GND CS00371 Figure 7. Switch-to-switch crosstalk CS14091 14/24 STG6684 Test circuit Figure 8. Test circuit ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O 1. CL = 5/35 pF or equivalent (includes jig and probe capacitance) 2. RL = 50 Ω or equivalent 3. RT = ZOUT of pulse generator (typically 50 Ω) 15/24 Test circuit STG6684 Figure 9. Break-before-make time delay ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O Figure 10. Switching time and charge injection (VGEN = 0, RGEN = 0 Ω, RL = 1 MΩ, CL = 100 pF) Figure 11. Turn on, turn off delay time VCC S1 D VOUT RL S2 IN V IN 16/24 GND CL STG6684 6 Application diagram Application diagram Figure 12. Application diagram SEL1 = High Class-D output S1 R D1 L T1 BB ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O S2 D2 T2 SEL2 = High Figure 13. Application diagram SEL1 = High R S1 BB Class-D output D1 L T1 S2 D2 T2 SEL2 = High 17/24 Package mechanical data 7 STG6684 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 14. QFN10L (1.8 x 1.4 mm) package outline ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O 7936408 Rev.D 18/24 STG6684 Package mechanical data Table 2. QFN10L(1.8 x 1.4 mm) mechanical data Symbol Millimeters Min Typ Max A 0.45 0.50 0.55 A1 0 0.02 0.05 A3 b 0.127 0.15 0.20 0.25 D 1.75 1.80 1.85 E 1.35 1.40 1.45 e L 0.40 0.35 0.40 0.45 ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O Figure 15. QFN10L (1.8 x 1.4 mm) footprint recommendations 19/24 Package mechanical data STG6684 Figure 16. QFN10L (1.8 x 1.4 mm) carrier tape ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O 20/24 STG6684 Package mechanical data Figure 17. QFN10L (1.8 x 1.4 mm) reel information - front side ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O 21/24 Package mechanical data STG6684 Figure 18. QFN10L(1.8 x 1.4 mm) reel information - back view ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O 22/24 STG6684 8 Revision history Revision history Table 9. Document revision history Date Revision 9-Jan-2008 1 Changes Initial release. ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O 23/24 STG6684 ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. 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