STGIPL14K60-S

STGIPL14K60, STGIPL14K60-S SLLIMM™ (small low-loss intelligent molded module) IPM, 3-phase inverter, 15 A, 600 V short-circuit rugged IGBT Datasheet - production data • 5 kΩ NTC for temperature control • UL Recognized: UL1557 file E81734 Applications • 3-phase inverters for motor drives • Home appliances, such as washing machines, refrigerators, air conditioners and sewing machines Description SDIP-38L option A AM01193v1 Features • IPM 15 A, 600 V 3-phase IGBT inverter bridge including control ICs for gate driving and freewheeling diodes • Short-circuit rugged IGBTs These intelligent power modules provides a compact, high performance AC motor drive in a simple, rugged design. Combining ST proprietary control ICs with the most advanced short-circuitrugged IGBT system technology, this device is ideal for 3-phase inverters in applications such as home appliances and air conditioners. SLLIMM™ is a trademark of STMicroelectronics. • VCE(sat) negative temperature coefficient • 3.3 V, 5 V, 15 V CMOS/TTL inputs comparators with hysteresis and pull down/pull up resistors • Undervoltage lockout • Internal bootstrap diode • Interlocking function • Smart shut down function • Comparators for fault protection against overtemperature and overcurrent • Op amps for advanced current sensing • DBC substrate leading to low thermal resistance • Isolation rating of 2500 Vrms/min Table 1. Device summary Order code Marking Package Packaging STGIPL14K60 GIPL14K60 SDIP-38L option A Tube STGIPL14K60-S GIPL14K60-S SDIP-38L option B Tube October 2013 This is information on a product in full production. DocID15589 Rev 11 1/26 www.st.com Contents STGIPL14K60, STGIPL14K60-S Contents 1 Internal block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . 3 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 Control part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1.1 3.2 NTC thermistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Waveforms definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 Smart shutdown function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2/26 DocID15589 Rev 11 STGIPL14K60, STGIPL14K60-S 1 Internal block diagram and pin configuration Internal block diagram and pin configuration Figure 1. Internal block diagram DocID15589 Rev 11 3/26 26 Internal block diagram and pin configuration STGIPL14K60, STGIPL14K60-S Table 2. Pin description 4/26 Pin Symbol Description 1 OUTU High side reference output for U phase 2 Vboot U Bootstrap voltage for U phase 3 LINU Low side logic input for U phase 4 HINU High side logic input for U phase 5 OP-U Op amp inverting input for U phase 6 OPOUT U 7 OP+U Op amp non inverting input for U phase 8 CINU Comparator input for U phase 9 OUTV High side reference output for V phase 10 Vboot V Bootstrap voltage for V phase 11 LINV Low side logic input for V phase 12 HINV High side logic input for V phase 13 OP-V Op amp inverting input for V phase 14 OPOUT V 15 OP+V Op amp non inverting input for V phase 16 CINV Comparator input for V phase 17 OUTW High side reference output for W phase 18 Vboot W Bootstrap voltage for W phase 19 LINW Low side logic input for W phase 20 HINW High side logic input for W phase 21 OP-W Op amp inverting input for W phase 22 OPOUT W 23 OP+W Op amp non inverting input for W phase 24 CINW Comparator input for W phase 25 VCC 26 SD / OD 27 GND 28 T2 NTC thermistor terminal 2 29 T1 NTC thermistor terminal 1 30 NW Negative DC input for W phase 31 W W phase output 32 P Positive DC input 33 NV Negative DC input for V phase 34 V V phase output Op amp output for U phase Op amp output for V phase Op amp output for W phase Low voltage power supply Shut down logic input (active low) / open drain (comparator output) Ground DocID15589 Rev 11 STGIPL14K60, STGIPL14K60-S Internal block diagram and pin configuration Table 2. Pin description (continued) Pin Symbol Description 35 P 36 NU Negative DC input for U phase 37 U U phase output 38 P Positive DC input Positive DC input Figure 2. Pin layout (bottom view) Marking area DocID15589 Rev 11 5/26 26 Electrical ratings STGIPL14K60, STGIPL14K60-S 2 Electrical ratings 2.1 Absolute maximum ratings Table 3. Inverter part Symbol Parameter Value Unit VPN Supply voltage applied between P-NU, NV, NW 450 V VPN(surge) Supply voltage (surge) applied between P-NU, NV, NW 500 V VCES Each IGBT collector emitter voltage (VIN(1) = 0) 600 V ± IC(2) Each IGBT continuous collector current at TC = 25°C 15 A Each IGBT pulsed collector current 30 A Each IGBT total dissipation at TC = 25°C 44 W Short circuit withstand time, VCE = 0.5 V(BR)CES Tj = 125 °C, VCC = Vboot= 15 V, VIN (1)= 0÷5 V 5 µs ± ICP (3) PTOT tscw 1. Applied between HINi, LINi and GND for i = U, V, W 2. Calculated according to the iterative formula: T j ( max ) – TC IC ( T C ) = ------------------------------------------------------------------------------------------------------R thj – c × V CE ( sat ) ( max ) ( Tj ( max ), I C ( TC ) ) 3. Pulse width limited by max junction temperature Table 4. Control part Symbol Min. Max. Unit Vboot - 21 Vboot + 0.3 V VOUT Output voltage applied between OUTU, OUTV, OUTW - GND VCC Low voltage power supply - 0.3 21 V VCIN Comparator input voltage - 0.3 VCC + 0.3 V Vop+ OPAMP non-inverting input - 0.3 VCC + 0.3 V Vop- OPAMP inverting input - 0.3 VCC + 0.3 V Vboot Bootstrap voltage - 0.3 620 V Logic input voltage applied between HIN, LIN and GND - 0.3 15 V Open drain voltage - 0.3 15 V 50 V/ns VIN VSD/OD dVOUT/dt 6/26 Parameter Allowed output slew rate DocID15589 Rev 11 STGIPL14K60, STGIPL14K60-S Electrical ratings Table 5. Total system Symbol VISO 2.2 Parameter Isolation withstand voltage applied between each pin and heatsink plate (AC voltage, t = 60sec.) Value Unit 2500 V Tj Power chips operating junction temperature -40 to 150 °C TC Module case operation temperature -40 to 125 °C Value Unit Thermal resistance junction-case single IGBT 2.8 °C/W Thermal resistance junction-case single diode 5 °C/W Thermal data Table 6. Thermal data Symbol Rth(j-c) Parameter DocID15589 Rev 11 7/26 26 Electrical characteristics 3 STGIPL14K60, STGIPL14K60-S Electrical characteristics Tj = 25 °C unless otherwise specified. Table 7. Inverter part Value Symbol VCE(sat) ICES VF Parameter Test condition Unit Min. Typ. Max. VCC = VBoot = 15 V, VIN(1)= 0 ÷ 5 V, IC = 7 A - 2.1 2.5 VCC = VBoot = 15 V, VIN(1)= 0 ÷ 5 V, IC = 7 A, Tj= 125 °C - Collector-cut off current (VIN(1)=0 “logic state”) VCE = 550 V VCC = Vboot = 15 V - 150 µA Diode forward voltage VIN(1) = 0 “logic state”, IC = 7 A - 2.1 V Collector-emitter saturation voltage V 1.8 Inductive load switching time and energy ton tc(on) toff tc(off) trr Turn-on time Crossover time (on) Turn-off time Crossover time (off) Reverse recovery time Eon Turn-on switching losses Eoff Turn-off switching losses VDD = 300 V, VCC = Vboot = 15 V, VIN(1)= 0 ÷ 5 V, IC = 7 A (see Figure 3) - 270 - 130 - 320 - 110 - 130 - 150 - 90 ns µJ 1. Applied between HINi LINi and GND for i = U, V, W (LIN inputs are active-low). Note: 8/26 ton and toff include the propagation delay time of the internal drive. tC(ON) and tC(OFF) are the switching time of IGBT itself under the internally given gate driving condition. DocID15589 Rev 11 STGIPL14K60, STGIPL14K60-S Electrical characteristics Figure 3. Switching time test circuit INPUT BOOT /Lin BUS VBOOT>VCC +5V HVG /SD RSD Hin L OUT VCC Vcc IC DT LVG GND CP+ VCE 0 1 AM06019v2 Figure 4. Switching time definition 100% IC 100% IC t rr IC VCE VCE IC VIN VIN t ON t OFF t C(OFF) t C(ON) VIN(ON) 10% IC 90% IC 10% VCE (a) turn-on VIN(OFF) 10% VCE (b) turn-off 10% IC AM09223V1 Figure 4 "Switching time definition" refers to HIN inputs (active high). For LIN inputs (active low), VIN polarity must be inverted for turn-on and turn-off. DocID15589 Rev 11 9/26 26 Electrical characteristics 3.1 STGIPL14K60, STGIPL14K60-S Control part Table 8. Low voltage power supply (VCC = 15 V unless otherwise specified) Symbol Min. Typ. Max. Unit Vcc UV hysteresis 1.2 1.5 1.8 V Vcc_thON Vcc UV turn ON threshold 11.5 12 12.5 V Vcc_thOFF Vcc UV turn OFF threshold 10 10.5 11 V Vcc_hys Parameter Test conditions Iqccu Undervoltage quiescent supply current VCC = 10 V SD/OD = 5 V; LIN = 5 V; HIN = 0, CIN = 0 450 µA Iqcc Quiescent current VCC = 15 V SD/OD = 5 V; LIN = 5 V HIN = 0, CIN = 0 3.5 mA Vref Internal comparator (CIN) reference voltage 0.58 V 0.5 0.54 Table 9. Bootstrapped voltage (VCC = 15 V unless otherwise specified) Symbol Min. Typ. Max. Unit VBS UV hysteresis 1.2 1.5 1.8 V VBS_thON VBS UV turn ON threshold 11.1 11.5 12.1 V VBS_thOFF VBS UV turn OFF threshold 9.8 10 10.6 V IQBSU Undervoltage VBS quiescent current VBS < 9 V SD/OD = 5 V; LIN and HIN = 5 V; CIN = 0 70 110 µA IQBS VBS quiescent current VBS = 15 V SD/OD = 5 V; LIN and HIN = 5 V; CIN = 0 200 300 µA Bootstrap driver on resistance LVG ON 120 VBS_hys RDS(on) Parameter Test conditions W Table 10. Logic inputs (VCC = 15 V unless otherwise specified) Symbol Parameter Test conditions Min. Typ. Max. Unit Vil Low logic level voltage 0.8 1.1 V Vih High logic level voltage 1.9 2.25 V 260 µA 1 µA 20 µA 1 µA 300 µA IHINh HIN logic “1” input bias current HIN = 15 V IHINl HIN logic “0” input bias current HIN = 0 V ILINl LIN logic “1” input bias current LIN = 0 V ILINh LIN logic “0” input bias current LIN = 15 V ISDh SD logic “0” input bias current SD = 15 V 10/26 DocID15589 Rev 11 110 3 30 175 6 120 STGIPL14K60, STGIPL14K60-S Electrical characteristics Table 10. Logic inputs (VCC = 15 V unless otherwise specified) (continued) Symbol Parameter Test conditions ISDl SD logic “1” input bias current SD = 0 V Dt Dead time see Figure 9 Min. Typ. Max. Unit 3 µA 600 ns Table 11. OPAMP characteristics (VCC = 15 V unless otherwise specified) Symbol Parameter Vio Input offset voltage Iio Input offset current Input bias current Iib (1) Test condition Min. Typ. Max. Unit 6 mV 4 40 nA 100 200 nA Vic = 0 V, Vo = 7.5 V Vic = 0 V, Vo = 7.5 V ςicm Input common mode voltage range ςOL Low level output voltage RL = 10 kΩ to VCC ςOH High level output voltage RL = 10 kΩ to GND 14 14.7 V Σουρχε, ςιδ = +1; ςο = 0 ς 16 30 mA Sink, ςιδ = -1; ςο = ςΧΧ 50 80 mA Slew rate Vi = 1 ÷ 4 V; CL = 100 pF; unity gain 2.5 3.8 V/μs GBWP Gain bandwidth product Vo = 7.5 V 8 12 MHz Avd Large signal voltage gain RL = 2 kΩ 70 85 dB SVR Supply voltage rejection ratio vs. VCC 60 75 dB CMRR Common mode rejection ratio 55 70 dB Io Output short circuit current SR 0 V 75 150 mV 1. The direction of input current is out of the IC. Table 12. Sense comparator characteristics (VCC = 15 V unless otherwise specified) Symbol Parameter Test conditions Min. Typ. Max. Unit Iib(i) Input bias current VCIN(i) =1 V, i= U, V o W - 3 µA Vol Open-drain low-level output voltage Iod = 3 mA - 0.5 V Comparator delay SD/OD pulled to 5 V through 100 kΩ resistor - 90 130 ns SR Slew rate CL = 180 pF; Rpu = 5 kΩ - 60 tsd Shut down to high / low side driver propagation delay VOUT = 0, Vboot = VCC, VIN = 0 to 3.3 V 50 125 tisd Comparator triggering to high / low side driver turn-off propagation delay Measured applying a voltage step from 0 V to 3.3 V to pin CINi td_comp DocID15589 Rev 11 V/µsec 200 ns 50 200 250 11/26 26 Electrical characteristics STGIPL14K60, STGIPL14K60-S Table 13. Truth table Logic input (VI) Output Condition SD/OD LIN HIN LVG HVG Shutdown enable half-bridge 3-state L X X L L Interlocking half-bridge 3-state H L H L L 0 ‘’logic state” half-bridge 3-state H H L L L 1 “logic state” low side direct driving H L L H L 1 “logic state” high side direct driving H H H L H Note: X: don’t care . Figure 5. Maximum IC(RMS) current vs. switching frequency (1) Figure 6. Maximum IC(RMS) current vs. fsine(1) AM07839v1 20 AM07840v1 12 18 11 VPN = 300 V, Modulation index = 0.8, PF = 0.6, Tj = 150 °C, TC = 10 °C 16 10 Ic(RMS) [A] Ic(RMS) [A] TC = 80 °C 14 TC = 100 °C 12 9 8 fSW = 16 kHz VPN = 300 V, Modulation index = 0.8, PF = 0.6, Tj = 150 °C, fSINE = 60 Hz 10 fSW = 12 kHz 7 fSW = 20 kHz 8 6 4 6 8 10 12 14 16 18 20 1 10 100 fSINE [Hz] fSW [kHz] 1. Simulated curves refer to typical IGBT parameters and maximum Rthj-c. 3.1.1 NTC thermistor Table 14. NTC thermistor Symbol 12/26 Parameter Test conditions Min. Typ. Max. Unit. R25 Resistance T = 25°C 5 kΩ R125 Resistance T = 125°C 300 Ω B B-constant T = 25°C to 85°C 3340 K T Operating temperature DocID15589 Rev 11 -40 125 °C STGIPL14K60, STGIPL14K60-S Electrical characteristics Equation 1: resistance variation vs. temperature R ( T ) = R 25 ⋅ e 1 1 B  --- – ---------- T 298 Where T are temperatures in Kelvin. Figure 7. NTC resistance vs. temperature AM03795v2 NTC (kΩ) Figure 8. NTC resistance vs. temperature zoom AM03795_2v3 NTC (kΩ) 1.8 100 1.6 1.4 80 Max Min 1.2 60 1.0 0.8 40 Typ 0.6 0.4 20 0.2 0 -40 -20 0 20 40 60 80 100 T (°C) DocID15589 Rev 11 0 50 60 70 80 90 100 110 120 T (°C) 13/26 26 Electrical characteristics 3.2 STGIPL14K60, STGIPL14K60-S Waveforms definitions Figure 9. Dead time and interlocking waveforms definitions RLO CK ING INTE RLO CK HIN INTE CONTROL SIGNAL EDGES OVERLAPPED: INTERLOCKING + DEAD TIME ING LIN LVG DTHL DTLH HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) LIN CONTROL SIGNALS EDGES SYNCHRONOUS (*): DEAD TIME HIN LVG DTLH DTHL HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) LIN CONTROL SIGNALS EDGES NOT OVERLAPPED, BUT INSIDE THE DEAD TIME: DEAD TIME HIN LVG DTLH DTHL HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) LIN CONTROL SIGNALS EDGES NOT OVERLAPPED, OUTSIDE THE DEAD TIME: DIRECT DRIVING HIN LVG DTLH DTHL HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) 14/26 DocID15589 Rev 11 gate driver outputs OFF (HALF-BRIDGE TRI-STATE) STGIPL14K60, STGIPL14K60-S 4 Smart shutdown function Smart shutdown function The devices integrate a comparator for fault sensing purposes. The comparator has an internal voltage reference VREF connected to the inverting input, while the non-inverting input, available on pin (CIN), can be connected to an external shunt resistor in order to implement a simple over-current protection function. When the comparator triggers, the device is set in shutdown state and both its outputs are set to low-level leading the halfbridge in tri-state. In the common overcurrent protection architectures the comparator output is usually connected to the shutdown input through a RC network, in order to provide a mono-stable circuit, which implements a protection time that follows the fault condition. Our smart shutdown architecture allows to immediately turn-off the output gate driver in case of overcurrent, the fault signal has a preferential path which directly switches off the outputs. The time delay between the fault and the outputs turn-off is no more dependent on the RC values of the external network connected to the shutdown pin. At the same time the DMOS connected to the open-drain output (pin SD/OD) is turned on by the internal logic which holds it on until the shutdown voltage is lower than the logic input lower threshold (Vil). Finally, the smart shutdown function provides the possibility to increase the real disable time without increasing the constant time of the external RC network. DocID15589 Rev 11 15/26 26 Smart shutdown function STGIPL14K60, STGIPL14K60-S Figure 10. Smart shutdown timing waveforms comp Vref CP+ HIN/LIN PROTECTION HVG/LVG SD/OD open drain gate (internal) disable time Fast shut down: the driver outputs are set in SD state immediately after the comparator triggering even if the SD signal has not yet reach the lower input threshold An approximation of the disable time is given by: SHUT DOWN CIRCUIT VBIAS where: RSD SD/OD FROM/TO CONTROLLER CSD RON_OD SMART SD LOGIC RPD_SD AM12947v1 Please refer to Table 12 for internal propagation delay time details. 16/26 DocID15589 Rev 11 STGIPL14K60, STGIPL14K60-S 5 Applications information Applications information Figure 11. Typical application circuit DocID15589 Rev 11 17/26 26 Applications information 5.1 STGIPL14K60, STGIPL14K60-S Recommendations • Input signal HIN is active high logic. A 85kΩ (typ.) pull down resistor is built-in for each high side input. If an external RC filter is used, for noise immunity, pay attention to the variation of the input signal level. • Input signal LIN is active low logic. A 720 kΩ (typ.) pull-up resistor, connected to an internal 5 V regulator through a diode, is built-in for each low side input. • To prevent the input signals oscillation, the wiring of each input should be as short as possible. • By integrating an application specific type HVIC inside the module, direct coupling to MCU terminals without any opto-coupler is possible. • Each capacitor should be located as nearby the pins of IPM as possible. • Low inductance shunt resistors should be used for phase leg current sensing. • Electrolytic bus capacitors should be mounted as close to the module bus terminals as possible. Additional high frequency ceramic capacitor mounted close to the module pins will further improve performance. • The SD/OD signal should be pulled up to 5 V / 3.3 V with an external resistor (see Section 4: Smart shutdown function for detailed info). Table 15. Recommended operating conditions Value Symbol Parameter Conditions Unit Min. VPN Supply Voltage Applied between P-Nu, Nv, Nw VCC Control supply voltage Applied between VCC-GND VBS High side bias voltage Applied between VBOOTi-OUTi for i = U, V, W 13 tdead Blanking time to prevent Arm-short For each input signal 1 fPWM PWM input signal -40°C < Tc < 100°C -40°C < Tj < 125°C TC Note: 18/26 Case operation temperature For further details refer to AN3338. DocID15589 Rev 11 13.5 Typ. Max. 300 400 V 15 18 V 18 V µs 20 kHz 100 °C STGIPL14K60, STGIPL14K60-S 6 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Please refer to dedicated technical note TN0107 for mounting instructions. Table 16. SDIP-38L option A mechanical data mm. Dimensions Min. Typ. Max. A 49.10 49.60 50.10 A1 1.10 1.30 1.50 A2 1.40 1.60 1.80 A3 44.10 44.60 45.10 B 24.00 24.50 25.00 B1 11.25 11.85 12.45 B2 27.10 27.60 28.10 B3 28.60 29.10 29.60 C 5.00 5.40 6.00 C1 6.50 7.00 7.50 C2 10.35 10.85 11.35 e 1.10 1.30 1.50 e1 3.20 3.40 3.60 e2 5.80 6.00 6.20 e3 4.60 4.80 5.00 e4 5.60 5.80 6.00 e5 6.30 6.50 6.70 e6 4.50 4.70 4.90 D 38.10 D1 5.75 E 11.80 E1 2.15 F 0.85 1.00 1.15 F1 0.35 0.50 0.65 R 1.55 1.75 1.95 T 0.45 0.55 0.65 V 0° DocID15589 Rev 11 6° 19/26 26 Package information STGIPL14K60, STGIPL14K60-S Figure 12. SDIP-38L option A drawing dimensions 8142868_G 20/26 DocID15589 Rev 11 STGIPL14K60, STGIPL14K60-S Package information Table 17. SDIP-38L option B mechanical data mm. Dimensions Min. Typ. Max. A 49.10 49.60 50.10 A1 1.10 1.30 1.50 A2 1.40 1.60 1.80 A3 44.10 44.60 45.10 B 24.00 24.50 25.00 B1 11.25 11.85 12.45 B2 27.10 27.60 28.10 B3 29.65 30.15 30.65 C 5.00 5.40 6.00 C2 8.15 8.35 8.55 e 1.10 1.30 1.50 e1 3.20 3.40 3.60 e2 5.80 6.00 6.20 e3 4.60 4.80 5.00 e4 5.60 5.80 6.00 e5 6.30 6.50 6.70 e6 4.50 4.70 4.90 D 38.10 D1 5.75 E 11.80 E1 2.15 F 0.85 1.00 1.15 F1 0.35 0.50 0.65 R 1.55 1.75 1.95 T 0.45 0.55 0.65 V 0° DocID15589 Rev 11 6° 21/26 26 Package information STGIPL14K60, STGIPL14K60-S Figure 13. SDIP-38L option B drawing dimensions 8434993_A 22/26 DocID15589 Rev 11 STGIPL14K60, STGIPL14K60-S Packaging mechanical data Figure 14. SDIP-38L shipping tube type A (dimensions are in mm.) 8147106_E 7 Packaging mechanical data DocID15589 Rev 11 23/26 26 Packaging mechanical data STGIPL14K60, STGIPL14K60-S 8147106_E Figure 15. SDIP-38L shipping tube type B (dimensions are in mm.) 24/26 DocID15589 Rev 11 STGIPL14K60, STGIPL14K60-S 8 Revision history Revision history Table 18. Document revision history Date Revision 16-Apr-2009 1 Initial release 2 Inserted Figure 5, Figure 6 and Section 4: Smart shutdown function. Updated Section 3.1: Control part and package mechanical data, Section 6. Minor text changes to improve readability. 14-Jun-2010 3 Document status promoted from preliminary data to datasheet. Updated Table 7: Inverter part, Figure 5: Maximum IC(RMS) current vs. switching frequency and Figure 6: Maximum IC(RMS) current vs. fsine(1). 21-Sep-2010 4 Updated: Table 3, 5, 8, 9, 10 and 12. Modified: Figure 5 and Figure 6. 09-Mar-2011 5 Updated title with SLLIMM™ in cover page, added SDIP-38L tube dimensions Figure 14. 04-Nov-2011 6 Updated title with SLLIMM™ (small low-loss intelligent molded module) IPM, 3-phase inverter - 15 A, 600 V short-circuit rugged IGBT in cover page and SDIP-38L mechanical data Table 16 on page 19, Figure 12. 28-Aug-2012 7 Modified: Min. and Max. value Table 4 on page 6. Updated: Figure 14. Added: Figure 15. 04-Mar-2013 8 Added: Figure 7 and Figure 8 13-Mar-2013 9 Modified: Figure 8 on page 13 17-Jun-2013 10 Updated: Figure 9: Dead time and interlocking waveforms definitions. 11 Added device STGIPL14K60-S and modified Table 1: Device summary accordingly. Updated Section 6: Package information and Section 7: Packaging mechanical data. Minor text changes. 29-Mar-2010 17-Oct-2013 Changes DocID15589 Rev 11 25/26 26 STGIPL14K60, STGIPL14K60-S Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2013 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 26/26 DocID15589 Rev 11