STM32F030F4P6

STM32F030x4 STM32F030x6 STM32F030x8 Value-line ARM-based 32-bit MCU with 16 to 64-KB Flash, timers, ADC, communication interfaces, 2.4-3.6 V operation Datasheet target specification Features  Core: ARM® 32-bit Cortex™-M0 CPU, frequency up to 48 MHz  Memories – 16 to 64 Kbytes of Flash memory – 4 to 8 Kbytes of SRAM with HW parity checking  CRC calculation unit  Reset and power management – Voltage range: 2.4 V to 3.6 V – Power-on/Power down reset (POR/PDR) – Low power modes: Sleep, Stop, Standby  Clock management – 4 to 32 MHz crystal oscillator – 32 kHz oscillator for RTC with calibration – Internal 8 MHz RC with x6 PLL option – Internal 40 kHz RC oscillator  Up to 55 fast I/Os – All mappable on external interrupt vectors – Up to 36 I/Os with 5 V tolerant capability LQFP64 10x10 mm LQFP48 7x7 mm LQFP32 7x7 mm – One 16-bit basic timer – Independent and system watchdog timers – SysTick timer: 24-bit downcounter  Calendar RTC with alarm and periodic wakeup from Stop/Standby  Communication interfaces – Up to two I2C interfaces: one supporting Fast Mode Plus (1 Mbit/s) with 20 mA current sink – Up to two USARTs supporting master synchronous SPI and modem control; one with auto baud rate detection – Up to two SPIs (18 Mbit/s) with 4 to 16 programmable bit frame  Serial wire debug (SWD)  5-channel DMA controller  1 x 12-bit, 1.0 µs ADC (up to 16 channels) – Conversion range: 0 to 3.6 V – Separate analog supply from 2.4 up to 3.6 V  Up to 10 timers – One 16-bit 7-channel advanced-control timer for 6 channels PWM output, with deadtime generation and emergency stop – One 16-bit timer, with up to 4 IC/OC, usable for IR control decoding – One 16-bit timer, with 2 IC/OC, 1 OCN, deadtime generation and emergency stop – Two 16-bit timers, each with IC/OC and OCN, deadtime generation, emergency stop and modulator gate for IR control – One 16-bit timer with 1 IC/OC July 2013 TSSOP20 Table 1. Device summary Reference Part number STM32F030x4 STM32F030F4 STM32F030x6 STM32F030C6, STM32F030K6 STM32F030x8 STM32F030C8, STM32F030R8 DocID024849 Rev 1 1/88 www.st.com Contents STM32F030x4 STM32F030x6 STM32F030x8 Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 ARM® CortexTM-M0 core with embedded Flash and SRAM . . . . . . . . . 12 3.2 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 13 3.5 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5.2 Power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.6 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.7 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.8 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.9 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.10 3.11 2/88 3.5.1 3.9.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 16 3.9.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 16 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.10.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.10.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.11.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.11.2 General-purpose timers (TIM3, TIM14..17) . . . . . . . . . . . . . . . . . . . . . . 19 3.11.3 Basic timer TIM6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.11.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.11.5 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.11.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.12 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.13 Inter-integrated circuit interfaces (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.14 Universal synchronous/asynchronous receiver transmitters (USART) . . 22 DocID024849 Rev 1 STM32F030x4 STM32F030x6 STM32F030x8 Contents 3.15 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.16 Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4 Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 41 6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 41 6.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.3.6 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.3.10 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.3.16 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.3.17 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.3.18 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.3.19 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 DocID024849 Rev 1 3/88 4 Contents 7 STM32F030x4 STM32F030x6 STM32F030x8 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.2.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . 83 8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 4/88 DocID024849 Rev 1 STM32F030x4 STM32F030x6 STM32F030x8 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM32F030x device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 STM32F030x I2C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 STM32F030x USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 STM32F030x SPI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Alternate functions selected through GPIOA_AFR registers for port A . . . . . . . . . . . . . . . 31 Alternate functions selected through GPIOB_AFR registers for port B . . . . . . . . . . . . . . . 32 STM32F030x peripheral register boundary addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 41 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Typical and maximum current consumption from VDD supply at VDD = 3.6 . . . . . . . . . . . 43 Typical and maximum current consumption from the VDDA supply . . . . . . . . . . . . . . . . . . 43 Typical and maximum VDD consumption in Stop and Standby modes. . . . . . . . . . . . . . . . 44 Typical and maximum VDDA consumption in Stop and Standby modes. . . . . . . . . . . . . . . 44 Typical current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 HSI14 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 DocID024849 Rev 1 5/88 6 List of tables Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. 6/88 STM32F030x4 STM32F030x6 STM32F030x8 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 IWDG min/max timeout period at 40 kHz (LSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 WWDG min-max timeout value @48 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 I2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data . . . . . . . . . . 75 LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . . 77 LQFP32 – 7 x 7mm 32-pin low-profile quad flat package mechanical data . . . . . . . . . . . . 79 TSSOP20 – 20-pin thin shrink small outline package mechanical data . . . . . . . . . . . . . . . 81 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 DocID024849 Rev 1 STM32F030x4 STM32F030x6 STM32F030x8 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 LQFP64 64-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 LQFP48 48-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 LQFP32 32-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 TSSOP20 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 STM32F030x memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 TC and TTa I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Five volt tolerant (FT and FTf) I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 75 LQFP64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 LQFP48 – 7 x 7 mm, 48 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 77 LQFP48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 LQFP32 – 7 x 7mm 32-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . 79 LQFP32 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 TSSOP20 - 20-pin thin shrink small outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 TSSOP20 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 LQFP64 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 DocID024849 Rev 1 7/88 7 Introduction 1 STM32F030x4 STM32F030x6 STM32F030x8 Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F030x microcontrollers. This STM32F030x4, STM32F030x6, and STM32F030x8 datasheet should be read in conjunction with the STM32F0xxxx reference manual (RM0091). The reference manual is available from the STMicroelectronics website www.st.com. For information on the ARM Cortex™-M0 core, please refer to the Cortex™-M0 Technical Reference Manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0432c/index.html. 8/88 DocID024849 Rev 1 STM32F030x4 STM32F030x6 STM32F030x8 2 Description Description The STM32F030x microcontroller incorporates the high-performance ARM Cortex™-M0 32bit RISC core operating at a 48 MHz frequency, high-speed embedded memories (up to 64 Kbytes of Flash memory and up to 8 Kbytes of SRAM), and an extensive range of enhanced peripherals and I/Os. All devices offer standard communication interfaces (up to two I2Cs, up to two SPIs, and up to two USARTs), one 12-bit ADC, up to 6 general-purpose 16-bit timers and an advanced-control PWM timer. The STM32F030x microcontroller operates in the -40 to +85 °C temperature range, from a 2.4 to 3.6 V power supply. A comprehensive set of power-saving modes allows the design of low-power applications. The STM32F030x microcontroller includes devices in four different packages ranging from 20 pins to 64 pins. Depending on the device chosen, different sets of peripherals are included. The description below provides an overview of the complete range of STM32F030x peripherals proposed. These features make the STM32F030x microcontroller suitable for a wide range of applications such as application control and user interfaces, handheld equipment, A/V receivers and digital TV, PC peripherals, gaming platforms, e-bikes, consumer appliances, printers, scanners, alarm systems, video intercoms, and HVACs. DocID024849 Rev 1 9/88 11 Description STM32F030x4 STM32F030x6 STM32F030x8 Table 2. STM32F030x device features and peripheral counts Peripheral STM32F030F4 STM32F030K6 Flash (Kbytes) 16 32 32 64 64 SRAM (Kbytes) 4 4 4 8 8 4 (16-bit)(1) 5 (16-bit) 5 (16-bit) Advanced control Timers Comm. interfaces General purpose STM32F030C6/C8 1 (16-bit) 4 (16-bit)(1) 4 (16-bit)(1) Basic - - - 1 (16-bit) 1 (16-bit) SPI (2) 1 (2) 1 1 (2) 2 2 I2C 1(3) 1(3) 1(3) 2 2 (4) 1(4) 1(4) 2 2 USART 12-bit synchronized ADC (number of channels) GPIOs 1 1 (11 channels) 1 (12 channels) 1 (12 channels) 1 (18 channels) 15 26 39 55 Max. CPU frequency 48 MHz Operating voltage 2.4 to 3.6 V Operating temperature Packages Ambient operating temperature: -40 °C to 85 °C TSSOP20 LQFP32 1. TIM15 is not present. 2. SPI2 is not present. 3. I2C2 is not present. 4. USART2 is not present. 10/88 STM32F030R8 DocID024849 Rev 1 LQFP48 LQFP64 STM32F030x4 STM32F030x6 STM32F030x8 Description Figure 1. Block diagram Serial Wire Debug VDD18 Obl Flash interface SWCLK SWDIO as AF SRAM controller NVIC Bus matrix CORTEX-M0 CPU fHCLK = 48 MHz Flash up to 64 KB, 32 bits SRAM 4 / 8 KB POWER VOLT.REG 3.3 V TO 1.8 V VDD = 2.4 to 3.6 V VSS @ VDD POR Reset Int SUPPLY SUPERVISION POR/PDR @ VDDA NRST VDDA VDD RC HS 14 MHz RC HS 8 MHz @ VDDA GP DMA 5 channels RC LS PLL GPIO port A PB[15:0] GPIO port B PC[15:0] GPIO port C PD2 GPIO port D PF[1:0] PF[7:4] GPIO port F AHB decoder PA[15:0] RESET & CLOCK CONTROL AHBPCLK APBPCLK ADCCLK USARTCLK HCLK FCLK CRC AHB @ VDD XTAL OSC 4-32 MHz IWDG Power Controller @ VDD XTAL32 kHz OSC32_IN (PC14) OSC32_OUT (PC15) RTC TAMPER-RTC (ALARM OUT) RTC interface TIMER 1 4 channels 3 compl. channels BRK, ETR input as AF TIMER 3 4 ch., ETR as AF TIMER 14 1 channel as AF TIMER 15 2 channels 1 compl, BRK as AF TIMER 16 1 channel 1 compl, BRK as AF TIMER 17 1 channel 1 compl, BRK as AF APB 55 AF EXT. IT WKUP WWDG MOSI, MISO, SCK, NSS as AF MOSI/MISO, SCK/NSS, as AF SPI1 OSC_IN (PF0) OSC_OUT (PF1) IR_OUT as AF DBGMCU USART1 SPI2 USART2 RX, TX,CTS, RTS, CK as AF RX, TX,CTS, RTS, CK as AF SYSCFG IF @ VDDA Temp. sensor 16 AD inputs 12-bit ADC1 I2C 1 SCL, SDA, SMBA (20 mA for FM+) as AF I2C2 SCL, SDA as AF IF TIMER 6 VDDA VSSA MSv32137V1 1. TIMER6, TIMER15, SPI2, USART2 and I2C2 are available on STM32F030x8 devices only. DocID024849 Rev 1 11/88 11 Functional overview STM32F030x4 STM32F030x6 STM32F030x8 3 Functional overview 3.1 ARM® CortexTM-M0 core with embedded Flash and SRAM The ARM Cortex™-M0 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. The ARM Cortex™-M0 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. The STM32F0xx family has an embedded ARM core and is therefore compatible with all ARM tools and software. Figure 1 shows the general block diagram of the device family. 3.2 Memories The device has the following features:  Up to 8 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states and featuring embedded parity checking with exception generation for failcritical applications.  The non-volatile memory is divided into two arrays: – 16 to 64 Kbytes of embedded Flash memory for programs and data – Option bytes The option bytes are used to write-protect the memory (with 4 KB granularity) and/or readout-protect the whole memory with the following options: 3.3 – Level 0: no readout protection – Level 1: memory readout protection, the Flash memory cannot be read from or written to if either debug features are connected or boot in RAM is selected – Level 2: chip readout protection, debug features (Cortex-M0 serial wire) and boot in RAM selection disabled Boot modes At startup, the boot pin and boot selector option bit are used to select one of three boot options:  Boot from User Flash  Boot from System Memory  Boot from embedded SRAM The boot loader is located in System Memory. It is used to reprogram the Flash memory by using USART on pins PA14/PA15 or PA9/PA10. 12/88 DocID024849 Rev 1 STM32F030x4 STM32F030x6 STM32F030x8 3.4 Functional overview Cyclic redundancy check calculation unit (CRC) The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a CRC-32 (Ethernet) polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. 3.5 Power management 3.5.1 Power supply schemes  VDD = 2.4 to 3.6 V: external power supply for I/Os and the internal regulator. Provided externally through VDD pins.  VDDA = 2.4 to 3.6 V: external analog power supply for ADC, Reset blocks, RCs and PLL. The VDDA voltage level must be always greater or equal to the VDD voltage level and must be provided first. For more details on how to connect power pins, refer to Figure 10: Power supply scheme. 3.5.2 Power supply supervisors The device has integrated power-on reset (POR) and power-down reset (PDR) circuits. They are always active, and ensure proper operation above a threshold of 2 V. The device remains in reset mode when the monitored supply voltage is below a specified threshold, VPOR/PDR, without the need for an external reset circuit. 3.5.3  The POR monitors only the VDD supply voltage. During the startup phase it is required that VDDA should arrive first and be greater than or equal to VDD.  The PDR monitors both the VDD and VDDA supply voltages, however the VDDA power supply supervisor can be disabled (by programming a dedicated Option bit) to reduce the power consumption if the application design ensures that VDDA is higher than or equal to VDD. Voltage regulator The regulator has three operating modes: main (MR), low power (LPR) and power down.  MR is used in normal operating mode (Run)  LPR can be used in Stop mode where the power demand is reduced  Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost) This regulator is always enabled after reset. It is disabled in Standby mode, providing high impedance output. DocID024849 Rev 1 13/88 22 Functional overview 3.5.4 STM32F030x4 STM32F030x6 STM32F030x8 Low-power modes The STM32F030x microcontroller supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:  Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.  Stop mode Stop mode achieves very low power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low power mode. The device can be woken up from Stop mode by any of the EXTI lines. The EXTI line source can be one of the 16 external lines or the RTC alarm.  Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and register contents are lost except for the Standby circuitry. The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pins, or an RTC alarm occurs. Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode. 3.6 Clocks and startup System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example on failure of an indirectly used external crystal, resonator or oscillator). Several prescalers allow the application to configure the frequency of the AHB and the APB domains. The maximum frequency of the AHB and the APB domains is 48 MHz. 14/88 DocID024849 Rev 1 STM32F030x4 STM32F030x6 STM32F030x8 Functional overview Figure 2. Clock tree FLITFCLK to Flash programming interface HSI to I2C1 SYSCLK LSE 8 MHz HSI HSI RC /244 /2 HCLK PLLSRC PLLMUL PLL x2,x3,.. x16 SW HSI PLLCLK HSE /8 AHB AHB prescaler /1,2,..512 SYSCLK CSS /1,2, 3,..16 OSC_OUT OSC_IN 4-32 MHz HSE OSC 14 MHz HSI14 HSI14 RC /32 OSC32_IN OSC32_OUT LSE OSC 32.768kHz LSE RTCCLK to RTC APB prescaler /1,2,4,8,16 to AHB bus, core, memory and DMA to cortex System timer FHCLK Cortex free running clock PCLK If (APB1 prescaler =1) x1 else x2 ADC Prescaler /2,4 PCLK SYSCLK HSI LSE to APB peripherals to TIM1,3,6, 14,15,16,17 to ADC 14 MHz max to USART1 RTCSEL[1:0] LSI LSI RC 40kHz to IWDG /2 PLLCLK MCO Main clock output HSI HSI14 HSE SYSCLK LSI (1) LSE (1) MCO MS32138V1 1. LSI/LSE is not available on STM32F030x8 devices. DocID024849 Rev 1 15/88 22 Functional overview 3.7 STM32F030x4 STM32F030x6 STM32F030x8 General-purpose inputs/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. The I/O configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. 3.8 Direct memory access controller (DMA) The 5-channel general-purpose DMAs manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA supports circular buffer management, removing the need for user code intervention when the controller reaches the end of the buffer. Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent. DMA can be used with the main peripherals: SPI, I2C, USART, all TIMx timers (except TIM14) and ADC. 3.9 Interrupts and events 3.9.1 Nested vectored interrupt controller (NVIC) The STM32F0xx family embeds a nested vectored interrupt controller able to handle up to 32 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M0) and 4 priority levels.  Closely coupled NVIC gives low latency interrupt processing  Interrupt entry vector table address passed directly to the core  Closely coupled NVIC core interface  Allows early processing of interrupts  Processing of late arriving higher priority interrupts  Support for tail-chaining  Processor state automatically saved  Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimal interrupt latency. 3.9.2 Extended interrupt/event controller (EXTI) The extended interrupt/event controller consists of 24 edge detector lines used to generate interrupt/event requests and wake-up the system. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the internal clock period. Up to 55 GPIOs can be connected to the 16 external interrupt lines. 16/88 DocID024849 Rev 1 STM32F030x4 STM32F030x6 STM32F030x8 3.10 Functional overview Analog to digital converter (ADC) The 12-bit analog to digital converter has up to 16 external and 2 internal (temperature sensor/voltage reference measurement) channels and performs conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs. The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. 3.10.1 Temperature sensor The temperature sensor (TS) generates a voltage VSENSE that varies linearly with temperature. The temperature sensor is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value. The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode. Table 3. Temperature sensor calibration values Calibration value name 3.10.2 Description Memory address TS_CAL1 TS ADC raw data acquired at temperature of 30 °C, VDDA= 3.3 V 0x1FFF F7B8 - 0x1FFF F7B9 TS_CAL2 TS ADC raw data acquired at temperature of 110 °C VDDA= 3.3 V 0x1FFF F7C2 - 0x1FFF F7C3 Internal voltage reference (VREFINT) The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the ADC. VREFINT is internally connected to the ADC_IN17 input channel. The precise voltage of VREFINT is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode. Table 4. Internal voltage reference calibration values Calibration value name VREFINT_CAL Description Raw data acquired at temperature of 30 °C VDDA= 3.3 V DocID024849 Rev 1 Memory address 0x1FFF F7BA - 0x1FFF F7BB 17/88 22 Functional overview 3.11 STM32F030x4 STM32F030x6 STM32F030x8 Timers and watchdogs Devices of the STM32F0xx family include up to six general-purpose timers, one basic timer and an advanced control timer. Table 5 compares the features of the advanced-control, general-purpose and basic timers. Table 5. Timer feature comparison Timer type Timer Counter resolution Counter type Prescaler factor DMA request generation Capture/ compare channels Complementary outputs Advanced control TIM1 16-bit Up, down, up/down Any integer between 1 and 65536 Yes 4 Yes TIM3 16-bit Up, down, up/down Any integer between 1 and 65536 Yes 4 No TIM14 16-bit Up Any integer between 1 and 65536 No 1 No TIM15(1) 16-bit Up Any integer between 1 and 65536 Yes 2 Yes TIM16, TIM17 16-bit Up Any integer between 1 and 65536 Yes 1 Yes TIM6(1) 16-bit Up Any integer between 1 and 65536 Yes 0 No General purpose Basic 1. Available on STM32F030x8 devices only. 3.11.1 Advanced-control timer (TIM1) The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable inserted dead times. It can also be seen as a complete general-purpose timer. The 4 independent channels can be used for:  Input capture  Output compare  PWM generation (edge or center-aligned modes)  One-pulse mode output If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If configured as the 16-bit PWM generator, it has full modulation capability (0-100%). The counter can be frozen in debug mode. Many features are shared with those of the standard timers which have the same architecture. The advanced control timer can therefore work together with the other timers via the Timer Link feature for synchronization or event chaining. 18/88 DocID024849 Rev 1 STM32F030x4 STM32F030x6 STM32F030x8 3.11.2 Functional overview General-purpose timers (TIM3, TIM14..17) There are five synchronizable general-purpose timers embedded in the STM32F030x devices (see Table 5 for differences). Each general-purpose timer can be used to generate PWM outputs, or as simple time base. TIM3 STM32F030x devices feature a synchronizable 4-channel general-purpose timer based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. TIM3 features 4 independent channels for input capture/output compare, PWM or one-pulse mode output. This gives up to 12 input captures/output compares/PWMs on the largest packages. The TIM3 general-purpose timer can work with the TIM1 advanced-control timer via the Timer Link feature for synchronization or event chaining. It provides independent DMA request generation. The TIM3 timer is capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. Its counter can be frozen in debug mode. TIM14 This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM14 features one single channel for input capture/output compare, PWM or one-pulse mode output. Its counter can be frozen in debug mode. TIM15, TIM16 and TIM17 These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM15 has two independent channels, whereas TIM16 and TIM17 feature one single channel for input capture/output compare, PWM or one-pulse mode output. The TIM15, TIM16 and TIM17 timers can work together, and TIM15 can also operate with TIM1 via the Timer Link feature for synchronization or event chaining. TIM15 can be synchronized with TIM16 and TIM17. TIM15, TIM16, and TIM17 have a complementary output with dead-time generation and independent DMA request generation. Their counters can be frozen in debug mode. 3.11.3 Basic timer TIM6 This timer is mainly used as a generic 16-bit time base. 3.11.4 Independent watchdog (IWDG) The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with user-defined refresh window. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free DocID024849 Rev 1 19/88 22 Functional overview STM32F030x4 STM32F030x6 STM32F030x8 running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode. 3.11.5 System window watchdog (WWDG) The system window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the APB clock (PCLK). It has an early warning interrupt capability and the counter can be frozen in debug mode. 3.11.6 SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features: 3.12  A 24-bit down counter  Autoreload capability  Maskable system interrupt generation when the counter reaches 0  Programmable clock source (HCLK or HCLK/8) Real-time clock (RTC) The RTC is an independent BCD timer/counter. Its main features are the following:  Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format  Automatically correction for 28, 29 (leap year), 30, and 31 day of the month  Programmable alarm with wake up from Stop and Standby mode capability  On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master clock.  Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal inaccuracy  2 anti-tamper detection pins with programmable filter. The MCU can be woken up from Stop and Standby modes on tamper event detection.  Timestamp feature which can be used to save the calendar content. This function can triggered by an event on the timestamp pin, or by a tamper event. The MCU can be woken up from Stop and Standby modes on timestamp event detection.  Periodic wakeup from Stop/Standby  Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision. The RTC clock sources can be: 20/88  A 32.768 kHz external crystal  A resonator or oscillator  The internal low-power RC oscillator (typical frequency of 40 kHz)  The high-speed external clock divided by 32 DocID024849 Rev 1 STM32F030x4 STM32F030x6 STM32F030x8 3.13 Functional overview Inter-integrated circuit interfaces (I2C) Up to two I2C interfaces (I2C1 and I2C2) can operate in multimaster or slave modes. Both can support Standard mode (up to 100 kbit/s) or Fast mode (up to 400 kbit/s). I2C1 also supports Fast Mode Plus (up to 1 Mbit/s) with 20 mA output drive. Both support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2 addresses, 1 with configurable mask). They also include programmable analog and digital noise filters. Table 6. Comparison of I2C analog and digital filters Analog filter Digital filter Pulse width of suppressed spikes  50 ns Programmable length from 1 to 15 I2C peripheral clocks Benefits Available in Stop mode 1. Extra filtering capability vs. standard requirements. 2. Stable length Drawbacks Variations depending on temperature, voltage, process Wakeup from Stop on address match is not available when digital filter is enabled. In addition, I2C1 provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts verifications and ALERT protocol management. The I2C interfaces can be served by the DMA controller. Refer to Table 7 for the differences between I2C1 and I2C2. Table 7. STM32F030x I2C implementation I2C features(1) I2C1 I2C2 7-bit addressing mode X X 10-bit addressing mode X X Standard mode (up to 100 kbit/s) X X Fast mode (up to 400 kbit/s) X X Fast Mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s) X - SMBus X - 1. X = supported. DocID024849 Rev 1 21/88 22 Functional overview 3.14 STM32F030x4 STM32F030x6 STM32F030x8 Universal synchronous/asynchronous receiver transmitters (USART) The device embeds up to two universal synchronous/asynchronous receiver transmitters (USART1 and USART2), which communicate at speeds of up to 6 Mbit/s. They provide hardware management of the CTS and RTS signals, multiprocessor communication mode, master synchronous communication and single-wire half-duplex communication mode. The USART1 supports also auto baud rate feature. The USART interfaces can be served by the DMA controller. Refer to Table 8 for the differences between USART1 and USART2. Table 8. STM32F030x USART implementation USART modes/features(1) USART1 USART2 Hardware flow control for modem X X Continuous communication using DMA X X Multiprocessor communication X X Synchronous mode X X Single-wire half-duplex communication X X Receiver timeout interrupt X - Auto baud rate detection X - 1. X = supported. 3.15 Serial peripheral interface (SPI) Up to two SPIs are able to communicate up to 18 Mbits/s in slave and master modes in fullduplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits. Refer to Table 9 for the differences between SPI1 and SPI2. Table 9. STM32F030x SPI implementation SPI features(1) SPI1 SPI2 Hardware CRC calculation X X Rx/Tx FIFO X X NSS pulse mode X X TI mode X X 1. X = supported. 3.16 Serial wire debug port (SW-DP) An ARM SW-DP interface is provided to allow a serial wire debugging tool to be connected to the MCU. 22/88 DocID024849 Rev 1 STM32F030x4 STM32F030x6 STM32F030x8 Pinouts and pin descriptions PC13 PC14/OSC32_IN PC15/OSC32_OUT PF0/OSC_IN PF1/OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VDDA PA0 PA1 PA2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 LQFP64 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PF7 PF6 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VSS VDD VDD PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 VDD VSS Figure 3. LQFP64 64-pin package pinout PA3 PF4 PF5 4 Pinouts and pin descriptions MS32729V1 1. The above figure shows the package top view. DocID024849 Rev 1 23/88 32 Pinouts and pin descriptions STM32F030x4 STM32F030x6 STM32F030x8 VDD 1 PC13 PC14/OSC32_IN 2 PC15/OSC32_OUT PF0/OSC_IN PF1/OSC_OUT 4 NRST 7 VSSA 8 VDDA PA0 PA1 9 PA14 PB3 PA15 PB4 PB6 PB5 PB7 PB8 BOOT0 48 47 46 45 44 43 42 41 40 39 38 37 36 3 5 6 LQFP48 10 35 34 33 32 31 30 29 28 27 26 25 PF7 PF6 PA13 PA12 PA11 PA10 PA9 PA8 PB15 PB14 PB13 PB12 VDD PB11 VSS PB10 PB1 PB2 PB0 PA5 PA6 PA7 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PA3 PA4 PA2 PB9 VDD VSS Figure 4. LQFP48 48-pin package pinout MS32730V1 1. The above figure shows the package top view. PB3 PA15 PB4 PB6 PB5 PB7 VSS BOOT0 Figure 5. LQFP32 32-pin package pinout 32 31 30 29 28 27 26 25 VDD PF0/OSC_IN 1 PF1/OSC_OUT 3 NRST VDDA PA0 PA1 4 PA2 24 23 22 2 21 20 19 18 17 LQFP32 5 6 7 8 PA14 PA13 PA12 PA11 PA10 PA9 PA8 VDD PB1 VSS PB0 PA6 PA7 PA5 PA3 PA4 9 10 11 12 13 14 15 16 MS32144V1 1. The above figure shows the package top view. 24/88 DocID024849 Rev 1 STM32F030x4 STM32F030x6 STM32F030x8 Pinouts and pin descriptions Figure 6. TSSOP20 package pinout 20 19 BOOT0 1 PF0/OSC_IN 2 PF1/OSC_OUT 3 4 18 PA14 PA13 PA10 17 PA 9 5 16 VDD 6 15 7 8 9 10 14 VSS PB1 13 12 11 PA7 PA6 PA5 NRST VDDA PA0 PA1 PA2 PA3 PA4 MS32731V1 1. The above figure shows the package top view. Table 10. Legend/abbreviations used in the pinout table Name Pin name Pin type Abbreviation Definition Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name S Supply pin I Input only pin I/O Input / output pin FT 5 V tolerant I/O FTf 5 V tolerant I/O, FM+ capable TTa 3.3 V tolerant I/O directly connected to ADC TC Standard 3.3V I/O I/O structure B RST Notes Pin functions Dedicated BOOT0 pin Bidirectional reset pin with embedded weak pull-up resistor Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset. Alternate functions Functions selected through GPIOx_AFR registers Additional functions Functions directly selected/enabled through peripheral registers DocID024849 Rev 1 25/88 32 Pinouts and pin descriptions STM32F030x4 STM32F030x6 STM32F030x8 Table 11. Pin definitions TSSOP20 1 - - VDD S I/O structure LQFP32 1 Pin name (function after reset) Pin type LQFP48 Pin functions LQFP64 Pin number Notes Alternate functions Additional functions Complementary power supply 2 2 - - PC13 I/O TC (1) - RTC_TAMP1, RTC_TS, RTC_OUT, WKUP2 3 3 - - PC14-OSC32_IN (PC14) I/O TC (1) - OSC32_IN 4 4 - - PC15-OSC32_OUT (PC15) I/O TC (1) - OSC32_OUT 5 5 2 2 PF0-OSC_IN (PF0) I/O FT - OSC_IN 6 6 3 3 PF1-OSC_OUT (PF1) I/O FT - OSC_OUT 7 7 4 4 NRST I/O RST 8 - - - PC0 I/O TTa EVENTOUT ADC_IN10 9 - - - PC1 I/O TTa EVENTOUT ADC_IN11 10 - - - PC2 I/O TTa EVENTOUT ADC_IN12 11 - - - PC3 I/O TTa EVENTOUT ADC_IN13 12 8 - - VSSA S Analog ground 13 9 5 5 VDDA S Analog power supply 14 10 6 6 PA0 I/O 15 16 11 12 7 8 7 8 PA1 PA2 I/O I/O Device reset input / internal reset output (active low) TTa USART1_CTS(2), USART2_CTS(3) ADC_IN0, RTC_TAMP2, WKUP1 TTa USART1_RTS(2), USART2_RTS(3), EVENTOUT ADC_IN1 TTa USART1_TX(2), USART2_TX(3), TIM15_CH1(3) ADC_IN2 ADC_IN3 17 13 9 9 PA3 I/O TTa USART1_RX(2), USART2_RX(3), TIM15_CH2(3) 18 - - - PF4 I/O FT EVENTOUT - 19 - - - PF5 I/O FT EVENTOUT - 26/88 DocID024849 Rev 1 STM32F030x4 STM32F030x6 STM32F030x8 Pinouts and pin descriptions Table 11. Pin definitions (continued) I/O structure Pin name (function after reset) Pin type Pin functions TSSOP20 LQFP32 LQFP48 LQFP64 Pin number Notes Alternate functions Additional functions ADC_IN4 20 14 10 10 PA4 I/O TTa SPI1_NSS, USART1_CK(2) USART2_CK(3), TIM14_CH1 21 15 11 11 PA5 I/O TTa SPI1_SCK ADC_IN5 TTa SPI1_MISO, TIM3_CH1, TIM1_BKIN, TIM16_CH1, EVENTOUT ADC_IN6 ADC_IN7 22 16 12 12 PA6 I/O 23 17 13 13 PA7 I/O TTa SPI1_MOSI, TIM3_CH2, TIM14_CH1, TIM1_CH1N, TIM17_CH1, EVENTOUT 24 - - - PC4 I/O TTa EVENTOUT ADC_IN14 25 - - - PC5 I/O TTa - ADC_IN15 26 18 14 - PB0 I/O TTa TIM3_CH3, TIM1_CH2N, EVENTOUT ADC_IN8 27 19 15 14 PB1 I/O TTa TIM3_CH4, TIM14_CH1, TIM1_CH3N ADC_IN9 28 20 - - PB2 I/O FT - - 29 21 - - PB10 I/O FT I2C1_SCL(2), I2C2_SCL(3) - 30 22 - - PB11 I/O FT I2C1_SDA(2), I2C2_SDA(3), EVENTOUT - 31 23 16 - VSS S Ground 32 24 17 16 VDD S Digital power supply 33 25 - - PB12 I/O (4) FT DocID024849 Rev 1 SPI1_NSS(2), SPI2_NSS(3), TIM1_BKIN, EVENTOUT - 27/88 32 Pinouts and pin descriptions STM32F030x4 STM32F030x6 STM32F030x8 Table 11. Pin definitions (continued) TSSOP20 26 - - 35 27 - - PB13 PB14 I/O structure LQFP32 34 Pin name (function after reset) Pin type LQFP48 Pin functions LQFP64 Pin number Alternate functions Additional functions I/O FT SPI1_SCK(2), SPI2_SCK(3), TIM1_CH1N - FT SPI1_MISO(2), SPI2_MISO(3), TIM1_CH2N, TIM15_CH1(3) - RTC_REFIN I/O Notes 36 28 - - PB15 I/O FT SPI1_MOSI(2), SPI2_MOSI(3), TIM1_CH3N, TIM15_CH1N(3), TIM15_CH2(3) 37 - - - PC6 I/O FT TIM3_CH1 - 38 - - - PC7 I/O FT TIM3_CH2 - 39 - - - PC8 I/O FT TIM3_CH3 - 40 - - - PC9 I/O FT TIM3_CH4 - FT USART1_CK, TIM1_CH1, EVENTOUT, MCO - FT USART1_TX, TIM1_CH2, TIM15_BKIN(3) I2C1_SCL(2) - - 41 42 29 30 18 19 - 17 PA8 PA9 I/O I/O 43 31 20 18 PA10 I/O FT USART1_RX, TIM1_CH3, TIM17_BKIN I2C1_SDA(2) 44 32 21 - PA11 I/O FT USART1_CTS, TIM1_CH4, EVENTOUT - 45 33 22 - PA12 I/O FT USART1_RTS, TIM1_ETR, EVENTOUT - 46 34 23 19 PA13 (SWDIO) I/O FT IR_OUT, SWDIO - 47 35 - - PF6 I/O FT I2C1_SCL(2), I2C2_SCL(3) - 28/88 (5) DocID024849 Rev 1 STM32F030x4 STM32F030x6 STM32F030x8 Pinouts and pin descriptions Table 11. Pin definitions (continued) LQFP48 LQFP32 TSSOP20 Pin type I/O structure Pin functions LQFP64 Pin number 48 36 - - PF7 I/O FT 49 37 24 20 PA14 (SWCLK) I/O FT Pin name (function after reset) Notes Alternate functions Additional functions I2C1_SDA(2), I2C2_SDA(3) - USART1_TX(2), USART2_TX(3), SWCLK - - (5) 50 38 25 - PA15 I/O FT SPI1_NSS, USART1_RX(2), USART2_RX(3), EVENTOUT 51 - - - PC10 I/O FT - - 52 - - - PC11 I/O FT - - 53 - - - PC12 I/O FT - - 54 - - - PD2 I/O FT TIM3_ETR - 55 39 26 - PB3 I/O FT SPI1_SCK, EVENTOUT - 56 40 27 - PB4 I/O FT SPI1_MISO, TIM3_CH1, EVENTOUT - - 57 41 28 - PB5 I/O FT SPI1_MOSI, I2C1_SMBA, TIM16_BKIN, TIM3_CH2 58 42 29 - PB6 I/O FTf I2C1_SCL, USART1_TX, TIM16_CH1N - 59 43 30 - PB7 I/O FTf I2C1_SDA, USART1_RX, TIM17_CH1N - 60 44 31 1 BOOT0 I B 61 45 - - PB8 I/O FTf 62 46 - - PB9 I/O Boot memory selection (5) FTf DocID024849 Rev 1 I2C1_SCL, TIM16_CH1 - I2C1_SDA, IR_OUT, TIM17_CH1, EVENTOUT - 29/88 32 Pinouts and pin descriptions STM32F030x4 STM32F030x6 STM32F030x8 Table 11. Pin definitions (continued) LQFP64 LQFP48 LQFP32 TSSOP20 Pin name (function after reset) I/O structure Pin functions Pin type Pin number 63 47 32 15 VSS S Ground 64 48 1 16 VDD S Digital power supply Notes Alternate functions Additional functions 1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: - The speed should not exceed 2 MHz with a maximum load of 30 pF. - These GPIOs must not be used as current sources (e.g. to drive an LED). 2. This feature is available on STM32F030x6 and STM32F030x4 devices only. 3. This feature is available on STM32F030x8 devices only. 4. On LQFP32 package, PB2 and PB8 should be treated as unconnected pins (even when they are not available on the package, they are not forced to a defined level by hardware). 5. After reset, these pins are configured as SWDIO and SWCLK alternate functions, and the internal pull-up on SWDIO pin and internal pull-down on SWCLK pin are activated. 30/88 DocID024849 Rev 1 Pin name AF0 AF1 AF2 AF3 AF4 AF5 AF6 PA0 - - - - - - PA1 EVENTOUT - - - - - PA2 TIM15_CH1(2) - - - - - PA3 TIM15_CH2(2) - - - - - PA4 SPI1_NSS - - TIM14_CH1 - - PA5 SPI1_SCK - - - - - - PA6 SPI1_MISO TIM3_CH1 TIM1_BKIN - - TIM16_CH1 EVENTOUT PA7 SPI1_MOSI TIM3_CH2 TIM1_CH1N - TIM14_CH1 TIM17_CH1 EVENTOUT PA8 MCO USART1_CK TIM1_CH1 EVENTOUT - - - - - USART1_CTS(1) USART2_CTS(2) USART1_RTS(1) USART2_RTS(2) USART1_TX(1) USART2_TX(2) USART1_RX(1) USART2_RX(2) USART1_CK(1) DocID024849 Rev 1 PA9 (2) TIM15_BKIN USART2_CK(2) USART1_TX TIM1_CH2 - I2C1_SCL(1) TIM17_BKIN USART1_RX TIM1_CH3 - I2C1_SDA(1) - - PA11 EVENTOUT USART1_CTS TIM1_CH4 - - - - PA12 EVENTOUT USART1_RTS TIM1_ETR - - - - PA13 SWDIO IR_OUT - - - - - PA14 SWCLK - - - - - PA15 SPI1_NSS - EVENTOUT - - - USART1_TX(1) USART2_TX(2) USART1_RX(1) USART2_RX(2) 31/88 1. This feature is available on STM32F030x6 and STM32F030x4 devices only. 2. This feature is available on STM32F030x8 devices only. Pinouts and pin descriptions PA10 STM32F030x4 STM32F030x6 STM32F030x8 Table 12. Alternate functions selected through GPIOA_AFR registers for port A AF0 AF1 AF2 AF3 PB0 EVENTOUT TIM3_CH3 TIM1_CH2N - PB1 TIM14_CH1 TIM3_CH4 TIM1_CH3N - PB2 - - - - PB3 SPI1_SCK EVENTOUT - - PB4 SPI1_MISO TIM3_CH1 EVENTOUT - PB5 SPI1_MOSI TIM3_CH2 TIM16_BKIN I2C1_SMBA PB6 USART1_TX I2C1_SCL TIM16_CH1N - PB7 USART1_RX I2C1_SDA TIM17_CH1N - PB8 - I2C1_SCL TIM16_CH1 - PB9 IR_OUT I2C1_SDA TIM17_CH1 EVENTOUT - - - - EVENTOUT TIM1_BKIN - - TIM1_CH1N - TIM15_CH1(2) TIM1_CH2N - TIM15_CH2(2) TIM1_CH3N TIM15_CH1N(2) (1) I2C1_SCL PB10 - PB11 EVENTOUT I2C2_SCL(2) I2C1_SDA(1) I2C2_SDA(2) SPI1_NSS(1) PB12 SPI2_NSS(2) SPI1_SCK(1) PB13 SPI2_SCK(2) SPI1_MISO(1) PB14 SPI2_MISO(2) SPI1_MOSI(1) PB15 SPI2_MOSI(2) 1. This feature is available on STM32F030x6 and STM32F030x4 devices only. 2. This feature is available on STM32F030x8 devices only. STM32F030x4 STM32F030x6 STM32F030x8 DocID024849 Rev 1 Pin name Pinouts and pin descriptions 32/88 Table 13. Alternate functions selected through GPIOB_AFR registers for port B STM32F030x4 STM32F030x6 STM32F030x8 5 Memory mapping Memory mapping Figure 7. STM32F030x memory map 0xFFFF FFFF 0x4800 17FF AHB2 7 0x4800 0000 0xE010 0000 0xE000 0000 Cortex- M Internal Peripherals reserved 6 0xC000 0000 0x4002 43FF ")# 5 0x4002 0000 reserved 0xA000 0000 0x4001 8000 4 "1# 0x1FFF FFFF reserved 0x1FFF FC00 0x4001 0000 Option Bytes 0x1FFF F800 0x8000 0000 reserved System memory 0x4000 8000 3 0x1FFF EC00 "1# 0x6000 0000 0x4000 0000 reserved 2 0x4000 0000 Peripherals 0x0801 0000 1 Flash memory 0x2000 0000 SRAM Y
 reserved 0 CODE 0x0001 0000 'MBTI
TZTUFN
NFNPSZ PS
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EFQFOEJOH
PO #005
DPOGJHVSBUJPO 0x0000 0000 0x0000 0000 Reserved MS19840V1 DocID024849 Rev 1 33/88 35 Memory mapping STM32F030x4 STM32F030x6 STM32F030x8 Table 14. STM32F030x peripheral register boundary addresses Bus Boundary address Size Peripheral 0x4800 1800 - 0x5FFF FFFF ~384 MB Reserved 0x4800 1400 - 0x4800 17FF 1 KB GPIOF 0x4800 1000 - 0x4800 13FF 1 KB Reserved 0x4800 0C00 - 0x4800 0FFF 1 KB GPIOD 0x4800 0800 - 0x4800 0BFF 1 KB GPIOC 0x4800 0400 - 0x4800 07FF 1 KB GPIOB 0x4800 0000 - 0x4800 03FF 1 KB GPIOA 0x4002 4400 - 0x47FF FFFF ~128 MB Reserved 0x4002 3400 - 0x4002 43FF 4 KB Reserved 0x4002 3000 - 0x4002 33FF 1 KB CRC 0x4002 2400 - 0x4002 2FFF 3 KB Reserved 0x4002 2000 - 0x4002 23FF 1 KB FLASH Interface 0x4002 1400 - 0x4002 1FFF 3 KB Reserved 0x4002 1000 - 0x4002 13FF 1 KB RCC 0x4002 0400 - 0x4002 0FFF 3 KB Reserved 0x4002 0000 - 0x4002 03FF 1 KB DMA 0x4001 8000 - 0x4001 FFFF 32 KB Reserved 0x4001 5C00 - 0x4001 7FFF 9 KB Reserved 0x4001 5800 - 0x4001 5BFF 1 KB DBGMCU 0x4001 4C00 - 0x4001 57FF 3 KB Reserved 0x4001 4800 - 0x4001 4BFF 1 KB TIM17 0x4001 4400 - 0x4001 47FF 1 KB TIM16 0x4001 4000 - 0x4001 43FF 1 KB TIM15(1) 0x4001 3C00 - 0x4001 3FFF 1 KB Reserved 0x4001 3800 - 0x4001 3BFF 1 KB USART1 0x4001 3400 - 0x4001 37FF 1 KB Reserved 0x4001 3000 - 0x4001 33FF 1 KB SPI1 0x4001 2C00 - 0x4001 2FFF 1 KB TIM1 0x4001 2800 - 0x4001 2BFF 1 KB Reserved 0x4001 2400 - 0x4001 27FF 1 KB ADC 0x4001 0800 - 0x4001 23FF 7 KB Reserved 0x4001 0400 - 0x4001 07FF 1 KB EXTI 0x4001 0000 - 0x4001 03FF 1 KB SYSCFG 0x4000 8000 - 0x4000 FFFF 32 KB Reserved AHB2 AHB1 APB 34/88 DocID024849 Rev 1 STM32F030x4 STM32F030x6 STM32F030x8 Memory mapping Table 14. STM32F030x peripheral register boundary addresses (continued) Bus Boundary address Size Peripheral 0x4000 7400 - 0x4000 7FFF 3 KB Reserved 0x4000 7000 - 0x4000 73FF 1 KB PWR 0x4000 5C00 - 0x4000 6FFF 5 KB Reserved 0x4000 5800 - 0x4000 5BFF 1 KB I2C2(1) 0x4000 5400 - 0x4000 57FF 1 KB I2C1 0x4000 4800 - 0x4000 53FF 3 KB Reserved 0x4000 4400 - 0x4000 47FF 1 KB USART2(1) 0x4000 3C00 - 0x4000 43FF 2 KB Reserved 0x4000 3800 - 0x4000 3BFF 1 KB SPI2(1) 0x4000 3400 - 0x4000 37FF 1 KB Reserved 0x4000 3000 - 0x4000 33FF 1 KB IWDG 0x4000 2C00 - 0x4000 2FFF 1 KB WWDG 0x4000 2800 - 0x4000 2BFF 1 KB RTC 0x4000 2400 - 0x4000 27FF 1 KB Reserved 0x4000 2000 - 0x4000 23FF 1 KB TIM14 0x4000 1400 - 0x4000 1FFF 3 KB Reserved 0x4000 1000 - 0x4000 13FF 1 KB TIM6(1) 0x4000 0800 - 0x4000 0FFF 2 KB Reserved 0x4000 0400 - 0x4000 07FF 1 KB TIM3 0x4000 0000 - 0x4000 03FF 1 KB Reserved APB 1. This feature is available on STM32F030x8 devices only. For STM32F030x6 and STM32F060x4, the area is Reserved. DocID024849 Rev 1 35/88 35 Electrical characteristics STM32F030x4 STM32F030x6 STM32F030x8 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3). 6.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3.3 V. They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2). 6.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 8. 6.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 9. Figure 8. Pin loading conditions Figure 9. Pin input voltage MCU pin MCU pin C = 50 pF VIN MS19210V1 36/88 DocID024849 Rev 1 MS19211V1 STM32F030x4 STM32F030x6 STM32F030x8 6.1.6 Electrical characteristics Power supply scheme Figure 10. Power supply scheme OUT GP I/Os IN Level shifter LSE, RTC, Wake-up logic IO Logic Kernel logic (CPU, Digital & Memories) VDD 2 × VDD 2 × 100 nF + 1 × 4.7 μF VDDA Regulator 2 × VSS VDDA VREF+ VREF- 10 nF + 1 μF ADC Analog: RCs, PLL, ... VSSA MS32141V1 Caution: Each power supply pair (VDD/VSS, VDDA/VSSA etc.) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device. DocID024849 Rev 1 37/88 73 Electrical characteristics 6.1.7 STM32F030x4 STM32F030x6 STM32F030x8 Current consumption measurement Figure 11. Current consumption measurement scheme IDD VDD IDDA VDDA MS32142V1 6.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 15: Voltage characteristics, Table 16: Current characteristics, and Table 17: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 15. Voltage characteristics(1) Symbol VDD–VSS VDD–VDDA VIN(2) |VDDx| |VSSX VSS| VESD(HBM) Ratings Min Max Unit –0.3 4.0 V - 0.4 V Input voltage on FT and FTf pins VSS  0.3 VDD + 4.0 V Input voltage on TTa pins VSS  0.3 4.0 V Input voltage on any other pin VSS 0.3 4.0 V Variations between different VDD power pins - 50 mV Variations between all the different ground pins - 50 mV External main supply voltage (including VDDA and VDD) Allowed voltage difference for VDD > VDDA Electrostatic discharge voltage (human body model) see Section 6.3.12: Electrical sensitivity characteristics 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. VIN maximum must always be respected. Refer to Table 16: Current characteristics for the maximum allowed injected current values. 38/88 DocID024849 Rev 1 STM32F030x4 STM32F030x6 STM32F030x8 Electrical characteristics Table 16. Current characteristics Symbol Ratings Max. IVDD Total current into sum of all VDD_x and VDDSDx power lines (source)(1) 120 IVSS Total current out of sum of all VSS_x and VSSSD ground lines (sink)(1) -120 IVDD(PIN) IVSS(PIN) IIO(PIN) IIO(PIN) Maximum current into each VDD_x or VDDSDx power pin (source)(1) Maximum current out of each VSS_x or VSSSD ground pin (sink) -100 25 Output current source by any I/O and control pin -25 Total output current sunk by sum of all IOs and control pins(2) Total output current sourced by sum of all IOs and control pins mA 80 (2) Injected current on FT, FTf and B pins -80 -5/+0 (4) ±5 Injected current on TC and RST pin Injected current on TTa pins(5) IINJ(PIN) 100 Output current sunk by any I/O and control pin (3) IINJ(PIN) (1) Unit ±5 Total injected current (sum of all I/O and control pins)(6) ± 25 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages. 3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. 4. A positive injection is induced by VIN>VDD while a negative injection is induced by VINVDDA while a negative injection is induced by VIN