STM32F070CB STM32F070RB
STM32F070C6 STM32F070F6
ARM®-based 32-bit MCU, up to 128 KB Flash, USB FS 2.0,
11 timers, ADC, communication interfaces, 2.4 - 3.6 V
Datasheet - production data
Features
• Core: ARM® 32-bit Cortex®-M0 CPU,
frequency up to 48 MHz
• Memories
– 32 to 128 Kbytes of Flash memory
– 6 to 16 Kbytes of SRAM with HW parity
• CRC calculation unit
LQFP64 10x10 mm
LQFP48 7x7 mm
• Communication interfaces
– Up to two I2C interfaces
–
• Reset and power management
– Digital & I/Os supply: VDD = 2.4 V to 3.6 V
– Analog supply: VDDA = VDD to 3.6 V
– Power-on/Power down reset (POR/PDR)
– Low power modes: Sleep, Stop, Standby
• Clock management
– 4 to 32 MHz crystal oscillator
– 32 kHz oscillator for RTC with calibration
– Internal 8 MHz RC with x6 PLL option
– Internal 40 kHz RC oscillator
• Up to 51 fast I/Os
– All mappable on external interrupt vectors
– Up to 51 I/Os with 5V tolerant capability
TSSOP20
Fast Mode Plus (1 Mbit/s) support, with
20 mA current sink
–
SMBus/PMBus support (on single I/F)
– Up to four USARTs supporting master
synchronous SPI and modem control; one
with auto baud rate detection
– Up to two SPIs (18 Mbit/s) with 4 to 16
programmable bit frames
– USB 2.0 full-speed interface with BCD and
LPM support
• Serial wire debug (SWD)
• All packages ECOPACK®2
• 5-channel DMA controller
• One 12-bit, 1.0 µs ADC (up to 16 channels)
– Conversion range: 0 to 3.6 V
– Separate analog supply: 2.4 V to 3.6 V
• Calendar RTC with alarm and periodic wakeup
from Stop/Standby
• 11 timers
– One 16-bit advanced-control timer for
six-channel PWM output
– Up to seven 16-bit timers, with up to four
IC/OC, OCN, usable for IR control
decoding
– Independent and system watchdog timers
– SysTick timer
February 2017
This is information on a product in full production.
DocID027114 Rev 3
1/83
www.st.com
Contents
STM32F070CB/RB/C6/F6
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1
ARM®-Cortex®-M0 core with embedded Flash and SRAM . . . . . . . . . . . 12
3.2
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4
Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 13
3.5
Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.2
Power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.3
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.4
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.6
Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.7
General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.8
Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.9
Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.10
3.11
2/83
3.5.1
3.9.1
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 16
3.9.2
Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 16
Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.10.1
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.10.2
Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.11.1
Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.11.2
General-purpose timers (TIM3, TIM14..17) . . . . . . . . . . . . . . . . . . . . . . 19
3.11.3
Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.11.4
Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.11.5
System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.11.6
SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.12
Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.13
Inter-integrated circuit interfaces (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.14
Universal synchronous/asynchronous receiver/transmitter (USART) . . . 21
DocID027114 Rev 3
STM32F070CB/RB/C6/F6
Contents
3.15
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.16
Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.17
Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4
Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1.6
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.1.7
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.3.2
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 40
6.3.3
Embedded reset and power control block characteristics . . . . . . . . . . . 40
6.3.4
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.3.5
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.3.6
Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.3.7
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.3.8
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.3.9
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.3.10
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.3.11
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.3.12
Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.3.13
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.3.14
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.3.15
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.3.16
12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.3.17
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.3.18
Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
DocID027114 Rev 3
3/83
4
Contents
STM32F070CB/RB/C6/F6
6.3.19
7
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
7.1
LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
7.2
LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
7.3
TSSOP20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
7.4
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
7.4.1
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
8
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4/83
DocID027114 Rev 3
STM32F070CB/RB/C6/F6
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
STM32F070CB/RB/C6/F6 family device features and peripheral counts . . . . . . . . . . . . . . 10
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
STM32F070CB/RB/C6/F6 I2C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
STM32F70x0 USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
STM32F070CB/RB/C6/F6 SPI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
STM32F070xB/6 pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Alternate functions selected through GPIOA_AFR registers for port A . . . . . . . . . . . . . . . 30
Alternate functions selected through GPIOB_AFR registers for port B . . . . . . . . . . . . . . . 31
Alternate functions selected through GPIOC_AFR registers for port C . . . . . . . . . . . . . . . 32
Alternate functions selected through GPIOD_AFR registers for port D . . . . . . . . . . . . . . . 32
Alternate functions selected through GPIOF_AFR registers for port F. . . . . . . . . . . . . . . . 32
STM32F070CB/RB/C6/F6 peripheral register boundary addresses. . . . . . . . . . . . . . . . . . 34
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 40
Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Typical and maximum current consumption from VDD supply at VDD = 3.6 V . . . . . . . . . . 42
Typical and maximum current consumption from the VDDA supply . . . . . . . . . . . . . . . . . . 42
Typical and maximum consumption in Stop and Standby modes . . . . . . . . . . . . . . . . . . . 43
Typical current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
HSI14 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
DocID027114 Rev 3
5/83
6
List of tables
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
6/83
STM32F070CB/RB/C6/F6
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
IWDG min/max timeout period at 40 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
WWDG min/max timeout value at 48 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
USB electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
LQFP64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
LQFP48 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
TSSOP20 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
DocID027114 Rev 3
STM32F070CB/RB/C6/F6
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
LQFP64 64-pin package pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
LQFP48 48-pin package pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
TSSOP20 20-pin package pinout (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
STM32F070CB/RB/C6/F6 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
TC and TTa I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Five volt tolerant (FT and FTf) I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
LQFP64 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
LQFP64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
LQFP48 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
LQFP48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
LQFP48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
TSSOP20 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
TSSOP20 footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
TSSOP20 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
DocID027114 Rev 3
7/83
7
Introduction
1
STM32F070CB/RB/C6/F6
Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F070CB/RB/C6/F6 microcontrollers.
This document should be read in conjunction with the STM32F0x0xx reference manual
(RM0360). The reference manual is available from the STMicroelectronics website
www.st.com.
For information on the ARM® Cortex®-M0 core, please refer to the Cortex®-M0 Technical
Reference Manual, available from the www.arm.com website.
8/83
DocID027114 Rev 3
STM32F070CB/RB/C6/F6
2
Description
Description
The STM32F070CB/RB/C6/F6 microcontrollers incorporate the high-performance ARM®
Cortex®-M0 32-bit RISC core operating at a 48 MHz frequency, high-speed embedded
memories (up to 128 Kbytes of Flash memory and up to 16 Kbytes of SRAM), and an
extensive range of enhanced peripherals and I/Os. All devices offer standard
communication interfaces (up to two I2Cs, up to two SPIs and up to four USARTs), one USB
Full speed device, one 12-bit ADC, seven general-purpose 16-bit timers and an advancedcontrol PWM timer.
The STM32F070CB/RB/C6/F6 microcontrollers operate in the -40 to +85 °C temperature
range from a 2.4 to 3.6V power supply. A comprehensive set of power-saving modes allows
the design of low-power applications.
The STM32F070CB/RB/C6/F6 microcontrollers include devices in three different packages
ranging from 20 pins to 64 pins. Depending on the device chosen, different sets of
peripherals are included. The description below provides an overview of the complete range
of STM32F070CB/RB/C6/F6 peripherals proposed.
These features make the STM32F070CB/RB/C6/F6 microcontrollers suitable for a wide
range of applications such as application control and user interfaces, handheld equipment,
A/V receivers and digital TV, PC peripherals, gaming and GPS platforms, industrial
applications, PLCs, inverters, printers, scanners, alarm systems, video intercoms, and
HVACs.
DocID027114 Rev 3
9/83
23
Description
STM32F070CB/RB/C6/F6
Table 1. STM32F070CB/RB/C6/F6 family device features and peripheral counts
Peripheral
STM32F070F6
STM32F070C6
STM32F070RB
Flash (Kbytes)
32
128
SRAM (Kbytes)
6
16
Advanced
control
Timers
Comm.
interfaces
1 (16-bit)
General
purpose
4 (16-bit)
5 (16-bit)
Basic
-
2 (16-bit)
SPI
1
2
2C
1
2
2
4
I
USART
USB
12-bit ADC
(number of channels)
GPIOs
1
1
(9 ext. + 2 int.)
1
(10 ext. + 2 int.)
1
(10 ext. + 2 int.)
1
(16 ext. + 2 int.)
15
37
37
51
Max. CPU frequency
48 MHz
Operating voltage
Operating temperature
Packages
10/83
STM32F070CB
2.4 to 3.6 V
Ambient operating temperature: -40°C to 85°C
Junction temperature: -40°C to 105°C
TSSOP20
LQFP48
DocID027114 Rev 3
LQFP48
LQFP64
STM32F070CB/RB/C6/F6
Description
Figure 1. Block diagram
32:(5
6HULDO:LUH
'HEXJ
2EO
)ODVK
PHPRU\
LQWHUIDFH
6:&/.
6:',2
DV$)
19,&
65$0
FRQWUROOHU
%XVPDWUL[
&257(;0&38
I0$; 0+]
9''
)ODVK*3/
.%.%
ELW
#9''$
+6,
3//&/.
/6,
*3'0$
FKDQQHOV
9'' WR9
966
#9''
65$0
.%.%
+6,
92/75(*
9WR9
325
5HVHW
,QW
6833/ @
*3,2SRUW%
3&> @
*3,2SRUW&
3'
*3,2SRUW'
3)> @
*3,2SRUW)
5(6(7 &/2&.
&21752/
$+%GHFRGHU
3$> @
6\VWHPDQGSHULSKHUDO
FORFNV
3RZHU
&RQWUROOHU
;7$/N+]
57&
26&B,1
26&B287
7$03(557&
$/$50287
57&LQWHUIDFH
&5&
3:07,0(5
FKDQQHOV
FRPSOFKDQQHOV
%5.(75LQSXWDV$)
$+%
$3%
$)
''
7,0(5
FK(75DV$)
7,0(5
FKDQQHODV$)
7,0(5
FKDQQHOV
FRPSO%5.DV$)
7,0(5
FKDQQHO
FRPSO%5.DV$)
7,0(5
FKDQQHO
FRPSO%5.DV$)
(;7,7:.83
86%
3+<
86%
#9''
:LQGRZ:'*
65$0
%
,5B287DV$)
'%*0&8
026,0,62
6&.166
DV$)
026,0,62
6&.166
DV$)
86$57
5;7;&76576
&.DV$)
86$57
5;7;&76576
&.DV$)
86$57
5;7;&76576
&.DV$)
86$57
5;7;&76576
&.DV$)
7,0(5
,&
6&/6'$60%$
P$)0 DV$)
7,0(5
,&
6&/6'$DV$)
63,
63,
63$@
9''
966
3%
3$
3$
3$
%227
3)26&B,1
3)26&B287
1567
9''$
3$
3$
3$
3$
3$
069
Table 9. Legend/abbreviations used in the pinout table
Name
Pin name
Pin type
I/O structure
Abbreviation
Unless otherwise specified in brackets below the pin name, the pin function during and
after reset is the same as the actual pin name
S
Supply pin
I
Input only pin
I/O
Input / output pin
FT
5 V tolerant I/O
FTf
5 V tolerant I/O, FM+ capable
TTa
3.3 V tolerant I/O directly connected to ADC
TC
Standard 3.3 V I/O
B
RST
Notes
Pin
functions
Definition
Dedicated BOOT0 pin
Bidirectional reset pin with embedded weak pull-up resistor
Unless otherwise specified by a note, all I/Os are set as floating inputs during and after
reset.
Alternate
functions
Functions selected through GPIOx_AFR registers
Additional
functions
Functions directly selected/enabled through peripheral registers
DocID027114 Rev 3
25/83
29
Pinouts and pin descriptions
STM32F070CB/RB/C6/F6
Table 10. STM32F070xB/6 pin definitions
TSSOP20
1
-
Pin name
(function after
reset)
Pin
type
Notes
LQFP48
1
Pin functions
I/O structure
LQFP64
Pin numbers
VDD
S
-
-
Alternate functions
Additional functions
Digital power supply
-
WKUP2,
RTC_TAMP1,
RTC_TS,
RTC_OUT
-
OSC32_IN
(2)
-
OSC32_OUT
FT
-
I2C1_SDA(3)
OSC_IN
I/O
FT
-
I2C1_SCL(3)
OSC_OUT
NRST
I/O
RST
-
-
PC0
I/O
TTa
-
EVENTOUT
ADC_IN10
-
-
PC1
I/O
TTa
-
EVENTOUT
ADC_IN11
10
-
-
PC2
I/O
TTa
-
SPI2_MISO, EVENTOUT
ADC_IN12
11
-
-
PC3
I/O
TTa
-
SPI2_MOSI, EVENTOUT
ADC_IN13
12
8
-
VSSA
S
-
-
Analog ground
13
9
5
VDDA
S
-
-
Analog power supply
14
10
6
PA0
I/O
TTa
(4)
USART2_CTS,
USART4_TX
RTC_ TAMP2,
WKUP1, ADC_IN0,
15
11
7
PA1
I/O
TTa
(4)
USART2_RTS,
TIM15_CH1N,
USART4_RX, EVENTOUT
ADC_IN1
16
12
8
PA2
I/O
TTa
(4)
USART2_TX, TIM15_CH1
ADC_IN2, WKUP4
USART2_RX, TIM15_CH2
ADC_IN3
2
2
-
PC13
I/O
TC
3
3
-
PC14-OSC32_IN
(PC14)
I/O
TC
4
4
-
PC15OSC32_OUT
(PC15)
I/O
TC
5
5
2
PF0-OSC_IN
(PF0)
I/O
6
6
3
PF1-OSC_OUT
(PF1)
7
7
4
8
-
9
(1)
(2)
(1)
(2)
(1)
Device reset input / internal reset output (active low)
17
13
9
PA3
I/O
TTa
(4)
18
-
-
VSS
S
-
-
Ground
19
-
-
VDD
S
-
-
Digital power supply
20
14
10
PA4
I/O
TTa
-
SPI1_NSS, TIM14_CH1,
USART2_CK,
USB_NOE(3)
ADC_IN4
21
15
11
PA5
I/O
TTa
-
SPI1_SCK
ADC_IN5
26/83
DocID027114 Rev 3
STM32F070CB/RB/C6/F6
Pinouts and pin descriptions
Table 10. STM32F070xB/6 pin definitions (continued)
TSSOP20
12
PA6
Pin
type
I/O
Notes
16
Pin name
(function after
reset)
Pin functions
I/O structure
22
LQFP48
LQFP64
Pin numbers
Alternate functions
Additional functions
TTa
(4)
SPI1_MISO, TIM3_CH1,
TIM1_BKIN,
TIM16_CH1, EVENTOUT,
USART3_CTS
ADC_IN6
ADC_IN7
23
17
13
PA7
I/O
TTa
-
SPI1_MOSI, TIM3_CH2,
TIM14_CH1,
TIM1_CH1N, TIM17_CH1,
EVENTOUT
24
-
-
PC4
I/O
TTa
(4)
EVENTOUT, USART3_TX
ADC_IN14
USART3_RX
ADC_IN15, WKUP5
25
-
-
PC5
I/O
TTa
(4)
26
18
-
PB0
I/O
TTa
(4)
TIM3_CH3, TIM1_CH2N,
EVENTOUT,
USART3_CK
ADC_IN8
27
19
14
PB1
I/O
TTa
(4)
TIM3_CH4,
USART3_RTS,
TIM14_CH1, TIM1_CH3N
ADC_IN9
28
20
-
PB2
I/O
FT
-
-
-
SPI2_SCK, USART3_TX
-
USART3_RX,
EVENTOUT, I2C2_SDA
-
29
21
-
PB10
I/O
FT
(4)
30
22
-
PB11
I/O
FT
(4)
31
23
15
VSS
S
-
-
Ground
32
24
16
VDD
S
-
-
Digital power supply
33
25
-
PB12
I/O
FT
(4)
TIM1_BKIN, TIM15_BKIN,
SPI2_NSS, EVENTOUT,
USART3_CK
-
34
26
-
PB13
I/O
FTf
(4)
SPI2_SCK, I2C2_SCL,
TIM1_CH1N,
USART3_CTS
-
35
27
-
PB14
I/O
FTf
(4)
SPI2_MISO, I2C2_SDA,
TIM1_CH2N, TIM15_CH1,
USART3_RTS
-
36
28
-
PB15
I/O
FT
(4)
SPI2_MOSI, TIM1_CH3N,
TIM15_CH1N,
TIM15_CH2
WKUP7,
RTC_REFIN
37
-
-
PC6
I/O
FT
-
TIM3_CH1
-
38
-
-
PC7
I/O
FT
-
TIM3_CH2
-
39
-
-
PC8
I/O
FT
-
TIM3_CH3
-
40
-
-
PC9
I/O
FT
-
TIM3_CH4
-
DocID027114 Rev 3
27/83
29
Pinouts and pin descriptions
STM32F070CB/RB/C6/F6
Table 10. STM32F070xB/6 pin definitions (continued)
LQFP48
TSSOP20
I/O structure
Notes
Pin functions
LQFP64
Pin numbers
41
29
-
PA8
I/O
FT
-
USART1_CK, TIM1_CH1,
EVENTOUT, MCO
-
42
30
17
PA9
I/O
FT
(4)
USART1_TX, TIM1_CH2,
TIM15_BKIN,
I2C1_SCL(3)
-
43
31
18
PA10
I/O
FT
-
USART1_RX, TIM1_CH3,
TIM17_BKIN,
I2C1_SDA(3)
-
44
32
17(5)
PA11
I/O
FT
-
USART1_CTS,
TIM1_CH4, EVENTOUT
USB_DM
45
33
18(5)
PA12
I/O
FT
-
USART1_RTS,
TIM1_ETR, EVENTOUT
USB_DP
46
34
19
PA13
I/O
FT
(6)
IR_OUT, SWDIO,
USB_NOE
-
47
35
-
VSS
S
-
-
Ground
48
36
-
VDD
S
-
-
Digital power supply
49
37
20
PA14
I/O
FT
-
USART2_TX, SWCLK
-
50
38
-
PA15
I/O
FT
(4)
SPI1_NSS, USART2_RX,
USART4_RTS,
EVENTOUT
-
51
-
-
PC10
I/O
FT
(4)
USART3_TX,
USART4_TX
-
52
-
-
PC11
I/O
FT
(4)
USART3_RX,
USART4_RX
-
53
-
-
PC12
I/O
FT
(4)
USART3_CK,
USART4_CK
-
54
-
-
PD2
I/O
FT
(4)
TIM3_ETR,
USART3_RTS
-
55
39
-
PB3
I/O
FT
-
SPI1_SCK, EVENTOUT
-
56
40
-
PB4
I/O
FT
-
SPI1_MISO, TIM17_BKIN,
TIM3_CH1, EVENTOUT
-
57
41
-
PB5
I/O
FT
(4)
SPI1_MOSI, I2C1_SMBA,
TIM16_BKIN,
TIM3_CH2
WKUP6
58
42
-
PB6
I/O
FTf
-
I2C1_SCL, USART1_TX,
TIM16_CH1N
-
28/83
Pin name
(function after
reset)
Pin
type
Alternate functions
Additional functions
DocID027114 Rev 3
STM32F070CB/RB/C6/F6
Pinouts and pin descriptions
Table 10. STM32F070xB/6 pin definitions (continued)
LQFP48
TSSOP20
I/O structure
Notes
Pin functions
LQFP64
Pin numbers
59
43
-
PB7
I/O
FTf
(4)
60
44
1
BOOT0
I
B
-
61
45
-
PB8
I/O
FTf
-
I2C1_SCL, TIM16_CH1
-
62
46
-
PB9
I/O
FTf
(4)
SPI2_NSS, I2C1_SDA,
IR_OUT,
TIM17_CH1, EVENTOUT
-
63
47
-
VSS
S
-
-
Ground
64
48
-
VDD
S
-
-
Digital power supply
Pin name
(function after
reset)
Pin
type
Alternate functions
Additional functions
I2C1_SDA, USART1_RX,
USART4_CTS,
TIM17_CH1N
-
Boot memory selection
1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF.
- These GPIOs must not be used as current sources (e.g. to drive an LED).
2. After the first RTC domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the
content of the RTC registers which are not reset by the system reset. For details on how to manage these GPIOs, refer to
the RTC domain and RTC register descriptions in the reference manual.
3. Available on STM32F070C6/F6 devices only.
4. TIM15, I2C2, WKUP4, WKUP5, WKUP6, WKUP7, SPI2, USART3 and USART4 are available on STM32F070CB/RB
devices only.
5. On STM32F070C6/F6 devices, pin pair PA11/12 can be remapped instead of pin pair PA9/10 using SYSCFG_CFGR1
register.
6. After reset, these pins are configured as SWDIO and SWCLK alternate functions, and the internal pull-up on the SWDIO
pin and the internal pull-down on the SWCLK pin are activated.
DocID027114 Rev 3
29/83
29
30/83
Table 11. Alternate functions selected through GPIOA_AFR registers for port A
Pin
name
AF0
AF1
AF2
AF3
AF4
AF5
PA0
-
USART2_CTS
-
-
USART4_TX(1)
-
-
-
-
-
USART2_RTS
-
-
PA2
(1)
TIM15_CH1
USART2_TX
-
-
-
-
-
-
PA3
TIM15_CH2(1)
USART2_RX
-
-
-
-
-
-
-
TIM14_CH1
-
-
-
-
-
-
-
-
EVENTOUT
PA4
SPI1_NSS
USART2_CK
USB_NOE(2)
PA5
SPI1_SCK
-
-
(1)
TIM15_CH1N
DocID027114 Rev 3
PA6
SPI1_MISO
TIM3_CH1
TIM1_BKIN
-
USART3_CTS
TIM16_CH1
EVENTOUT
-
PA7
SPI1_MOSI
TIM3_CH2
TIM1_CH1N
-
TIM14_CH1
TIM17_CH1
EVENTOUT
-
PA8
MCO
USART1_CK
TIM1_CH1
EVENTOUT
-
PA9
(1)
TIM15_BKIN
USART1_TX
TIM1_CH2
-
-
-
-
I2C1_SCL
(2)
-
-
-
I2C1_SDA
(2)
-
-
-
PA10
TIM17_BKIN
USART1_RX
TIM1_CH3
-
PA11
EVENTOUT
USART1_CTS
TIM1_CH4
-
-
-
-
-
PA12
EVENTOUT
USART1_RTS
TIM1_ETR
-
-
-
-
-
PA13
SWDIO
IR_OUT
USB_NOE
-
-
-
-
-
PA14
SWCLK
USART2_TX
-
-
-
-
-
-
PA15
SPI1_NSS
USART2_RX
-
EVENTOUT
USART4_RTS(1)
-
-
-
Available on STM32F070C6/F6 devices only.
STM32F070CB/RB/C6/F6
1. Available on STM32F070CB/RB devices only.
2.
AF7
USART4_RX(1)
PA1
(1)
AF6
Pin name
AF0
AF1
AF2
AF3
AF4
AF5
PB0
EVENTOUT
TIM3_CH3
TIM1_CH2N
-
USART3_CK(1)
-
PB1
TIM14_CH1
TIM3_CH4
TIM1_CH3N
-
USART3_RTS(1)
PB2
-
-
-
-
-
-
PB3
SPI1_SCK
EVENTOUT
-
-
-
-
PB4
SPI1_MISO
TIM3_CH1
EVENTOUT
-
-
TIM17_BKIN
PB5
SPI1_MOSI
TIM3_CH2
TIM16_BKIN
I2C1_SMBA
-
-
PB6
USART1_TX
I2C1_SCL
TIM16_CH1N
-
-
(1)
DocID027114 Rev 3
USART1_RX
I2C1_SDA
TIM17_CH1N
-
PB8
-
I2C1_SCL
TIM16_CH1
-
-
-
PB9
IR_OUT
I2C1_SDA
TIM17_CH1
EVENTOUT
-
SPI2_NSS(1)
PB10
-
I2C2_SCL(1)
-
-
USART3_TX(1)
SPI2_SCK(1)
PB11
EVENTOUT
I2C2_SDA(1)
-
-
USART3_RX(1)
-
PB12
SPI2_NSS(1)
EVENTOUT
TIM1_BKIN
-
USART3_CK(1)
TIM15_BKIN(1)
PB13
SPI2_SCK(1)
-
TIM1_CH1N
-
USART3_CTS(1)
I2C2_SCL(1)
PB14
SPI2_MISO(1)
TIM15_CH1
TIM1_CH2N
-
USART3_RTS(1)
I2C2_SDA(1)
PB15
SPI2_MOSI(1)
TIM15_CH2
TIM1_CH3N
TIM15_CH1N(1)
-
-
1. Available on STM32F070xB devices only.
USART4_CTS
-
PB7
STM32F070CB/RB/C6/F6
Table 12. Alternate functions selected through GPIOB_AFR registers for port B
31/83
STM32F070CB/RB/C6/F6
Table 13. Alternate functions selected through GPIOC_AFR registers for port C
Pin name
AF0(1)
AF1(1)
PC0
EVENTOUT(1)
-
PC1
EVENTOUT(1)
-
PC2
(1)
EVENTOUT
SPI2_MISO(1)
PC3
EVENTOUT(1)
SPI2_MOSI(1)
PC4
EVENTOUT(1)
USART3_TX(1)
PC5
-
USART3_RX(1)
PC6
TIM3_CH1(1)
-
PC7
TIM3_CH2(1)
-
PC8
(1)
TIM3_CH3
-
PC9
TIM3_CH4(1)
-
PC10
USART4_TX
(1)
USART3_TX(1)
PC11
USART4_RX(1)
USART3_RX(1)
PC12
USART4_CK(1)
USART3_CK(1)
PC13
-
-
PC14
-
-
PC15
-
-
1. Available on STM32F070xB devices only.
Table 14. Alternate functions selected through GPIOD_AFR registers for port D
Pin name
AF0(1)
AF1(1)
PD2
TIM3_ETR(1)
-
1. Available on STM32F070xB devices only.
Table 15. Alternate functions selected through GPIOF_AFR registers for port F
Pin name
AF0
AF1
PF0
-
I2C1_SDA(1)
PF1
-
I2C1_SCL(1)
1. Available on STM32F070x6 devices only.
32/83
DocID027114 Rev 3
STM32F070CB/RB/C6/F6
5
Memory mapping
Memory mapping
Figure 6. STM32F070CB/RB/C6/F6 memory map
[))))))))
[))
2ESERVED
!("
[(
[(
[
&RUWH[0LQWHUQDO
SHULSKHUDOV
2ESERVED
2ESERVED
[&
[))
!("
2ESERVED
[
2ESERVED
[$
[
2ESERVED
[)))))))
[))))&
[))))
[
!0"
2ESERVED
2SWLRQ%\WHV
[
2ESERVED
6\VWHPPHPRU\
2ESERVED
[
[)))&[
!0"
[
[
[
2ESERVED
2ESERVED
3HULSKHUDOV
[
2ESERVED
)ODVKPHPRU\
[
65$0
[
2ESERVED
&2'(
[
&LASH SYSTEM
MEMORYOR32!-
DEPENDINGON"//4
CONFIGURATION
[
[
06Y 9
1. The start address of the system memory is 0x1FFF C800 on STM32F070xB devices and 0x1FFF C400 on STM32F070x6
devices.
DocID027114 Rev 3
33/83
35
Memory mapping
STM32F070CB/RB/C6/F6
Table 16. STM32F070CB/RB/C6/F6 peripheral register boundary addresses
Bus
Boundary address
Size
Peripheral
-
0x4800 1800 - 0x5FFF FFFF
~384 MB
Reserved
0x4800 1400 - 0x4800 17FF
1 KB
GPIOF
0x4800 1000 - 0x4800 13FF
1 KB
Reserved
0x4800 0C00 - 0x4800 0FFF
1 KB
GPIOD
0x4800 0800 - 0x4800 0BFF
1 KB
GPIOC
0x4800 0400 - 0x4800 07FF
1 KB
GPIOB
0x4800 0000 - 0x4800 03FF
1 KB
GPIOA
0x4002 4400 - 0x47FF FFFF
~128 MB
Reserved
0x4002 3400 - 0x4002 43FF
4 KB
Reserved
0x4002 3000 - 0x4002 33FF
1 KB
CRC
0x4002 2400 - 0x4002 2FFF
3 KB
Reserved
0x4002 2000 - 0x4002 23FF
1 KB
FLASH Interface
0x4002 1400 - 0x4002 1FFF
3 KB
Reserved
0x4002 1000 - 0x4002 13FF
1 KB
RCC
0x4002 0400 - 0x4002 0FFF
3 KB
Reserved
0x4002 0000 - 0x4002 03FF
1 KB
DMA
0x4001 8000 - 0x4001 FFFF
32 KB
Reserved
0x4001 5C00 - 0x4001 7FFF
9 KB
Reserved
0x4001 5800 - 0x4001 5BFF
1 KB
DBGMCU
0x4001 4C00 - 0x4001 57FF
3 KB
Reserved
0x4001 4800 - 0x4001 4BFF
1 KB
TIM17
0x4001 4400 - 0x4001 47FF
1 KB
TIM16
0x4001 4000 - 0x4001 43FF
1 KB
TIM15
0x4001 3C00 - 0x4001 3FFF
1 KB
Reserved
0x4001 3800 - 0x4001 3BFF
1 KB
USART1
0x4001 3400 - 0x4001 37FF
1 KB
Reserved
0x4001 3000 - 0x4001 33FF
1 KB
SPI1
0x4001 2C00 - 0x4001 2FFF
1 KB
TIM1
0x4001 2800 - 0x4001 2BFF
1 KB
Reserved
0x4001 2400 - 0x4001 27FF
1 KB
ADC
0x4001 0800 - 0x4001 23FF
7 KB
Reserved
0x4001 0400 - 0x4001 07FF
1 KB
EXTI
0x4001 0000 - 0x4001 03FF
1 KB
SYSCFG
0x4000 8000 - 0x4000 FFFF
32 KB
Reserved
AHB2
-
AHB1
-
APB
-
34/83
DocID027114 Rev 3
STM32F070CB/RB/C6/F6
Memory mapping
Table 16. STM32F070CB/RB/C6/F6 peripheral register boundary addresses (continued)
Bus
APB
Boundary address
Size
Peripheral
0x4000 7400 - 0x4000 7FFF
3 KB
Reserved
0x4000 7000 - 0x4000 73FF
1 KB
PWR
0x4000 6C00 - 0x4000 6FFF
1 KB
Reserved
0x4000 6400 - 0x4000 67FF
2 KB
Reserved
0x4000 6000 - 0x4000 63FF
1 KB
USB RAM
0x4000 5800 - 0x4000 5BFF
1 KB
I2C2(1)
0x4000 5400 - 0x4000 57FF
1 KB
I2C1
0x4000 5000 - 0x4000 53FF
3 KB
Reserved
0x4000 4C00 - 0x4000 4FFF
1 KB
USART4(1)
0x4000 4800 - 0x4000 4BFF
1 KB
USART3(1)
0x4000 4400 - 0x4000 47FF
1 KB
USART2
0x4000 3C00 - 0x4000 43FF
2 KB
Reserved
0x4000 3800 - 0x4000 3BFF
1 KB
SPI2(1)
0x4000 3400 - 0x4000 37FF
1 KB
Reserved
0x4000 3000 - 0x4000 33FF
1 KB
IWDG
0x4000 2C00 - 0x4000 2FFF
1 KB
WWDG
0x4000 2800 - 0x4000 2BFF
1 KB
RTC
0x4000 2400 - 0x4000 27FF
1 KB
Reserved
0x4000 2000 - 0x4000 23FF
1 KB
TIM14
0x4000 1800 - 0x4000 1FFF
2 KB
Reserved
0x4000 1400 - 0x4000 17FF
1 KB
TIM7
0x4000 1000 - 0x4000 13FF
1 KB
TIM6
0x4000 0800 - 0x4000 0FFF
2 KB
Reserved
0x4000 0400 - 0x4000 07FF
1 KB
TIM3
0x4000 0000 - 0x4000 03FF
1 KB
Reserved
1. Available on STM32F070CB/RB devices only.
DocID027114 Rev 3
35/83
35
Electrical characteristics
STM32F070CB/RB/C6/F6
6
Electrical characteristics
6.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
6.1.1
Minimum and maximum values
Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3σ).
6.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3.3 V. They
are given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ±2σ).
6.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 7.
6.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 8.
Figure 7. Pin loading conditions
Figure 8. Pin input voltage
0&8SLQ
0&8SLQ
& S)
9,1
06 9
36/83
DocID027114 Rev 3
06 9
STM32F070CB/RB/C6/F6
6.1.6
Electrical characteristics
Power supply scheme
Figure 9. Power supply scheme
/6(57&
:DNHXSORJLF
3RZHUVZLWFK
9''
9&25(
[9''
5HJXODWRU
287
[Q)
*3,2V
,1
[)
/HYHOVKLIWHU
9'',2
,2
ORJLF
.HUQHOORJLF
&38'LJLWDO
0HPRULHV
[966
9''$
9''$
Q)
)
95()
95()
$'&
$QDORJ
5&V3//«
966$
06Y 9
Caution:
Each power supply pair (VDD/VSS, VDDA/VSSA etc.) must be decoupled with filtering ceramic
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure the good functionality of
the device.
DocID027114 Rev 3
37/83
69
Electrical characteristics
6.1.7
STM32F070CB/RB/C6/F6
Current consumption measurement
Figure 10. Current consumption measurement scheme
,''
9''
,''$
9''$
069
6.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 17: Voltage characteristics,
Table 18: Current characteristics and Table 19: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Table 17. Voltage characteristics(1)
Symbol
Ratings
Min
Max
Unit
VDD–VSS
External main supply voltage
-0.3
4.0
V
VDDA–VSS
External analog supply voltage
-0.3
4.0
V
VDD–VDDA
Allowed voltage difference for VDD > VDDA
-
0.4
VIN(2)
Input voltage on FT and FTf pins
VSS −0.3
Input voltage on TTa pins
VSS −0.3
BOOT0
0
VDDIOx + 4.0
V
(3)
V
4.0
VDDIOx + 4.0
V
(3)
V
VSS − 0.3
4.0
V
Variations between different VDD power pins
-
50
mV
|VSSx − VSS|
Variations between all the different ground
pins
-
50
mV
VESD(HBM)
Electrostatic discharge voltage
(human body model)
Input voltage on any other pin
|ΔVDDx|
see Section 6.3.12: Electrical
sensitivity characteristics
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 18: Current characteristics for the maximum
allowed injected current values.
3. VDDIOx is internally connected with VDD pin.
38/83
DocID027114 Rev 3
-
STM32F070CB/RB/C6/F6
Electrical characteristics
Table 18. Current characteristics
Symbol
Ratings
Max.
ΣIVDD
Total current into sum of all VDD power lines (source)(1)
120
ΣIVSS
(1)
-120
Total current out of sum of all VSS ground lines (sink)
IVDD(PIN)
Maximum current into each VDD power pin (source)
(1)
100
IVSS(PIN)
Maximum current out of each VSS ground pin (sink)(1)
-100
Output current sunk by any I/O and control pin
IIO(PIN)
25
Output current source by any I/O and control pin
ΣIIO(PIN)
IINJ(PIN)(3)
Total output current sunk by sum of all I/Os and control pins
ΣIINJ(PIN)
-25
(2)
mA
80
Total output current sourced by sum of all I/Os and control pins(2)
-80
Injected current on FT and FTf pins
-5/+0(4)
Injected current on TC and RST pin
±5
Injected current on TTa pins
Unit
(5)
±5
Total injected current (sum of all I/O and control pins)(6)
± 25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.
3. A positive injection is induced by VIN > VDDIOx while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be
exceeded. Refer to Table 17: Voltage characteristics for the maximum allowed input voltage values.
4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum
value.
5. On these I/Os, a positive injection is induced by VIN > VDDA. Negative injection disturbs the analog performance of the
device. See note (2) below Table 51: ADC accuracy.
6. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and
negative injected currents (instantaneous values).
Table 19. Thermal characteristics
Symbol
TSTG
TJ
Ratings
Storage temperature range
Value
Unit
–65 to +150
°C
150
°C
Maximum junction temperature
6.3
Operating conditions
6.3.1
General operating conditions
Table 20. General operating conditions
Symbol
Parameter
Conditions
Min
Max
fHCLK
Internal AHB clock frequency
-
0
48
fPCLK
Internal APB clock frequency
-
0
48
VDD
Standard operating voltage
-
2.4
3.6
DocID027114 Rev 3
Unit
MHz
V
39/83
69
Electrical characteristics
STM32F070CB/RB/C6/F6
Table 20. General operating conditions (continued)
Symbol
VDDA
VIN
Parameter
Analog operating voltage
I/O input voltage
Conditions
Min
Max
Unit
Must have a potential equal
to or higher than VDD
2.4
3.6
V
TC and RST I/O
-0.3
VDDIOx+0.3
TTa I/O
-0.3
VDDA+0.3(2)
FT and FTf I/O
-0.3
5.5(2)
BOOT0
0
5.5
LQFP64
-
455
PD
Power dissipation at TA = 85 °C
for suffix 6 (1)
LQFP48
-
364
TSSOP20
-
263
TA
Ambient temperature for the
suffix 6 version
Maximum power dissipation
-40
85
-40
105
TJ
Junction temperature range
Suffix 6 version
-40
105
Low power dissipation
(2)
V
mW
°C
°C
1. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax.
2. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 7.4:
Thermal characteristics).
6.3.2
Operating conditions at power-up / power-down
The parameters given in Table 21 are derived from tests performed under the ambient
temperature condition summarized in Table 20.
Table 21. Operating conditions at power-up / power-down
Symbol
Parameter
VDD rise time rate
tVDD
-
VDD fall time rate
VDDA rise time rate
tVDDA
6.3.3
Conditions
-
VDDA fall time rate
Min
Max
0
∞
20
∞
0
∞
20
∞
Unit
µs/V
Embedded reset and power control block characteristics
The parameters given in Table 22 are derived from tests performed under the ambient
temperature and supply voltage conditions summarized in Table 20: General operating
conditions.
Table 22. Embedded reset and power control block characteristics
Symbol
VPOR/PDR(1)
40/83
Parameter
Power on/power down
reset threshold
Conditions
Min
Typ
Max
Unit
Falling edge(2)
1.80
1.88
1.96(3)
V
1.84(3)
1.92
2.00
V
Rising edge
DocID027114 Rev 3
STM32F070CB/RB/C6/F6
Electrical characteristics
Table 22. Embedded reset and power control block characteristics (continued)
Symbol
VPDRhyst
tRSTTEMPO(4)
Parameter
Conditions
Min
Typ
Max
Unit
PDR hysteresis
-
-
40
-
mV
Reset temporization
-
1.50
2.50
4.50
ms
1. The PDR detector monitors VDD and also VDDA (if kept enabled in the option bytes). The POR detector
monitors only VDD.
2. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
3. Data based on characterization results, not tested in production.
4. Guaranteed by design, not tested in production.
6.3.4
Embedded reference voltage
The parameters given in Table 23 are derived from tests performed under the ambient
temperature and supply voltage conditions summarized in Table 20: General operating
conditions.
Table 23. Embedded internal reference voltage
Symbol
Parameter
VREFINT
Internal reference
voltage
Conditions
Min
Typ
Max
Unit
-40°C < TA < +85°C
1.2
1.23
1.25
V
tSTART
ADC_IN17 buffer startup
time
-
-
-
10(1)
µs
tS_vrefint
ADC sampling time when
reading the internal
reference voltage
-
4 (1)
-
-
µs
ΔVREFINT
Internal reference
voltage spread over the
temperature range
VDDA = 3 V
-
-
10(1)
mV
TCoeff
Temperature coefficient
-
-100(1)
-
100(1) ppm/°C
1. Guaranteed by design, not tested in production.
6.3.5
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 10: Current consumption
measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to CoreMark code.
DocID027114 Rev 3
41/83
69
Electrical characteristics
STM32F070CB/RB/C6/F6
Typical and maximum current consumption
The MCU is placed under the following conditions:
•
All I/O pins are in analog input mode
•
All peripherals are disabled except when explicitly mentioned
•
•
The Flash memory access time is adjusted to the fHCLK frequency:
–
0 wait state and Prefetch OFF from 0 to 24 MHz
–
1 wait state and Prefetch ON above 24 MHz
When the peripherals are enabled fPCLK = fHCLK
The parameters given in Table 24 to Table 26 are derived from tests performed under
ambient temperature and supply voltage conditions summarized in Table 20: General
operating conditions.
Table 24. Typical and maximum current consumption from VDD supply at VDD = 3.6 V
Symbol
All peripherals enabled
IDD
IDD
IDD
Parameter
Conditions
fHCLK
Max @ TA(1)
Unit
Typ
85 °C
Supply current in
HSI or HSE clock, PLL on
Run mode, code
executing from Flash
HSI or HSE clock, PLL off
Supply current in
Run mode, code
executing from RAM
Supply current in
Sleep mode, code
executing from Flash
or RAM
HSI or HSE clock, PLL on
HSI or HSE clock, PLL off
HSI or HSE clock, PLL on
HSI or HSE clock, PLL off
48 MHz
24.1
27.6
24 MHz
12.4
14.4
8 MHz
4.52
5.28
48 MHz
23.1
25.0
24 MHz
11.5
13.6
8 MHz
4.34
5.03
48 MHz
15.0
17.3
24 MHz
7.53
8.87
8 MHz
2.95
3.41
mA
mA
mA
1. Data based on characterization results, not tested in production unless otherwise specified.
Table 25. Typical and maximum current consumption from the VDDA supply
VDDA = 3.6 V
Symbol
Parameter
Conditions(1)
fHCLK
Typ
Max @ TA
Unit
85 °C
HSE bypass, PLL on
IDDA
42/83
Supply current in
Run or Sleep mode,
code executing from
Flash or RAM
48 MHz
165
196
8 MHz
3.6
5.2
1 MHz
3.6
5.2
HSI clock, PLL on
48 MHz
245
279
HSI clock, PLL off
8 MHz
83.4
95.3
HSE bypass, PLL off
DocID027114 Rev 3
µA
STM32F070CB/RB/C6/F6
Electrical characteristics
1. Current consumption from the VDDA supply is independent of whether the digital peripherals are enabled or disabled, being
in Run or Sleep mode or executing from Flash or RAM. Furthermore, when the PLL is off, IDDA is independent from the
frequency.
Table 26. Typical and maximum consumption in Stop and Standby modes
Symbol
IDD
Typ @VDD
(VDD = VDDA)
Max(1)
3.6 V
TA = 85 °C
Regulator in run mode, all oscillators OFF
15.9
49
Regulator in low-power mode, all oscillators OFF
3.7
33
1.5
-
Regulator in run or lowpower mode, all
oscillators OFF
2.8
3.6
LSI ON and IWDG ON
3.5
-
LSI OFF and IWDG OFF
2.6
3.6
Regulator in run or lowpower mode, all
oscillators OFF
1.5
-
LSI ON and IWDG ON
2.2
-
LSI OFF and IWDG OFF
1.4
-
Parameter
Conditions
Supply current in
Stop mode
Supply current in
LSI ON and IWDG ON
Standby mode
Supply current in
Stop mode
VDDA monitoring ON
Supply current in
Standby mode
IDDA
Supply current in
Stop mode
VDDA monitoring OFF
Supply current in
Standby mode
Unit
µA
1. Data based on characterization results, not tested in production unless otherwise specified.
Typical current consumption
The MCU is placed under the following conditions:
•
VDD = VDDA = 3.3 V
•
All I/O pins are in analog input configuration
•
The Flash access time is adjusted to fHCLK frequency:
–
0 wait state and Prefetch OFF from 0 to 24 MHz
–
1 wait state and Prefetch ON above 24 MHz
•
When the peripherals are enabled, fPCLK = fHCLK
•
PLL is used for frequencies greater than 8 MHz
•
AHB prescaler of 2, 4, 8 and 16 is used for the frequencies 4 MHz, 2 MHz, 1 MHz and
500 kHz respectively
DocID027114 Rev 3
43/83
69
Electrical characteristics
STM32F070CB/RB/C6/F6
Table 27. Typical current consumption in Run mode, code with data processing
running from Flash
Typ
Symbol
IDD
IDDA
Parameter
Conditions
Supply current in Run
Running from
mode from VDD
HSE crystal
supply
clock 8 MHz,
Supply current in Run code executing
mode from VDDA
from Flash
supply
fHCLK
Peripherals Peripherals
enabled
disabled
48 MHz
23.5
13.5
8 MHz
4.8
3.1
48 MHz
163.3
163.3
8 MHz
2.5
2.5
Unit
mA
µA
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 45: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution:
Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption measured previously, the I/Os
used by an application also contribute to the current consumption. When an I/O pin
switches, it uses the current from the I/O supply voltage to supply the I/O pin circuitry and to
charge/discharge the capacitive load (internal or external) connected to the pin:
I SW = V DDIOx × f SW × C
44/83
DocID027114 Rev 3
STM32F070CB/RB/C6/F6
Electrical characteristics
where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDDIOx is the I/O supply voltage
fSW is the I/O switching frequency
C is the total capacitance seen by the I/O pin: C = CINT + CEXT + CS
CS is the PCB board capacitance including the pad pin.
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
Table 28. Switching output I/O current consumption
Symbol
Parameter
Conditions(1)
VDDIOx = 3.3 V
CEXT = 0 pF
C = CINT + CEXT+ CS
ISW
I/O current
consumption
VDDIOx = 3.3 V
CEXT = 22 pF
C = CINT + CEXT+ CS
VDDIOx = 3.3 V
CEXT = 47 pF
C = CINT + CEXT+ CS
C = Cint
I/O toggling
frequency (fSW)
Typ
4 MHz
0.18
8 MHz
0.37
16 MHz
0.76
24 MHz
1.39
48 MHz
2.188
4 MHz
0.49
8 MHz
0.94
16 MHz
2.38
24 MHz
3.99
4 MHz
0.81
8 MHz
1.7
16 MHz
3.67
Unit
mA
1. CS = 7 pF (estimated value).
6.3.6
Wakeup time from low-power mode
The wakeup times given in Table 29 are the latency between the event and the execution of
the first user instruction. The device goes in low-power mode after the WFE (Wait For
Event) instruction, in the case of a WFI (Wait For Interruption) instruction, 16 CPU cycles
must be added to the following timings due to the interrupt latency in the Cortex M0
architecture.
The SYSCLK clock source setting is kept unchanged after wakeup from Sleep mode.
During wakeup from Stop or Standby mode, SYSCLK takes the default setting: HSI 8 MHz.
The wakeup source from Sleep and Stop mode is an EXTI line configured in event mode.
The wakeup source from Standby mode is the WKUP1 pin (PA0).
All timings are derived from tests performed under the ambient temperature and supply
voltage conditions summarized in Table 20: General operating conditions.
DocID027114 Rev 3
45/83
69
Electrical characteristics
STM32F070CB/RB/C6/F6
Table 29. Low-power mode wakeup timings
Symbol
Parameter
Typ @VDD =
VDDA
Conditions
Max Unit
= 3.3 V
tWUSTOP
Wakeup from Stop mode
Regulator in run mode
2.8
5
-
51
-
-
4 SYSCLK
cycles
-
tWUSTANDBY Wakeup from Standby mode
tWUSLEEP
6.3.7
Wakeup from Sleep mode
µs
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.14. However,
the recommended clock input waveform is shown in Figure 11: High-speed external clock
source AC timing diagram.
Table 30. High-speed external user clock characteristics
Parameter(1)
Symbol
Min
Typ
Max
Unit
-
8
32
MHz
fHSE_ext
User external clock source frequency
VHSEH
OSC_IN input pin high level voltage
0.7 VDDIOx
-
VDDIOx
VHSEL
OSC_IN input pin low level voltage
VSS
-
0.3 VDDIOx
15
-
-
tw(HSEH)
tw(HSEL)
OSC_IN high or low time
tr(HSE)
tf(HSE)
OSC_IN rise or fall time
V
ns
-
-
20
1. Guaranteed by design, not tested in production.
Figure 11. High-speed external clock source AC timing diagram
WZ +6(+
9+6(+
9+6(/
WU +6(
WI +6(
WZ +6(/
W
7+6(
06 9
46/83
DocID027114 Rev 3
STM32F070CB/RB/C6/F6
Electrical characteristics
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.14. However,
the recommended clock input waveform is shown in Figure 12.
Table 31. Low-speed external user clock characteristics
Parameter(1)
Symbol
Min
Typ
Max
Unit
-
32.768
1000
kHz
fLSE_ext User external clock source frequency
VLSEH
OSC32_IN input pin high level voltage
0.7 VDDIOx
-
VDDIOx
VLSEL
OSC32_IN input pin low level voltage
VSS
-
0.3 VDDIOx
450
-
-
tw(LSEH)
OSC32_IN high or low time
tw(LSEL)
tr(LSE)
tf(LSE)
V
ns
OSC32_IN rise or fall time
-
-
50
1. Guaranteed by design, not tested in production.
Figure 12. Low-speed external clock source AC timing diagram
WZ /6(+
9/6(+
9/6(/
WU /6(
WI /6(
W
WZ /6(/
7/6(
06 9
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 32. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and startup stabilization time. Refer
to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).
Table 32. HSE oscillator characteristics
Symbol
fOSC_IN
RF
Conditions(1)
Min(2)
Typ
Max(2)
Unit
Oscillator frequency
-
4
8
32
MHz
Feedback resistor
-
-
200
-
kΩ
Parameter
DocID027114 Rev 3
47/83
69
Electrical characteristics
STM32F070CB/RB/C6/F6
Table 32. HSE oscillator characteristics
Symbol
Conditions(1)
Min(2)
Typ
Max(2)
-
-
8.5
VDD = 3.3 V,
Rm = 45 Ω,
CL = 10 pF@8 MHz
-
0.5
-
VDD = 3.3 V,
Rm = 30 Ω,
CL = 20 pF@32 MHz
-
1.5
-
Startup
10
-
-
mA/V
VDD is stabilized
-
2
-
ms
Parameter
(3)
During startup
IDD
gm
tSU(HSE)(4)
HSE current consumption
Oscillator transconductance
Startup time
Unit
mA
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Guaranteed by design, not tested in production.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 20 pF range (Typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 13). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 13. Typical application with an 8 MHz crystal
5HVRQDWRUZLWKLQWHJUDWHG
FDSDFLWRUV
&/
26&B,1
0+]
UHVRQDWRU
&/
5(;7
I+6(
5)
%LDV
FRQWUROOHG
JDLQ
26&B287
06 9
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. All the information given in this paragraph are based on design simulation results
48/83
DocID027114 Rev 3
STM32F070CB/RB/C6/F6
Electrical characteristics
obtained with typical external components specified in Table 33. In the application, the
resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
Table 33. LSE oscillator characteristics (fLSE = 32.768 kHz)
Symbol
LSE current
consumption
IDD
Oscillator
transconductance
gm
tSU(LSE)
(3)
Conditions(1)
Min(2)
Typ
Max(2)
low drive capability
-
0.5
0.9
medium-low drive capability
-
-
1
medium-high drive capability
-
-
1.3
high drive capability
-
-
1.6
low drive capability
5
-
-
medium-low drive capability
8
-
-
medium-high drive capability
15
-
-
high drive capability
25
-
-
VDDIOx is stabilized
-
2
-
Parameter
Startup time
Unit
µA
µA/V
s
1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator
design guide for ST microcontrollers”.
2. Guaranteed by design, not tested in production.
3.
Note:
tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized
32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly
with the crystal manufacturer
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 14. Typical application with a 32.768 kHz crystal
5HVRQDWRUZLWKLQWHJUDWHG
FDSDFLWRUV
&/
26&B,1
I/6(
'ULYH
SURJUDPPDEOH
DPSOLILHU
N+]
UHVRQDWRU
26&B287
&/
069
Note:
An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.
DocID027114 Rev 3
49/83
69
Electrical characteristics
6.3.8
STM32F070CB/RB/C6/F6
Internal clock source characteristics
The parameters given in Table 34 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 20: General operating
conditions. The provided curves are characterization results, not tested in production.
High-speed internal (HSI) RC oscillator
Table 34. HSI oscillator characteristics(1)
Symbol
fHSI
TRIM
Parameter
Conditions
Min
Typ
Max
Unit
Frequency
-
-
8
-
MHz
HSI user trimming step
-
-
-
1(2)
%
-
45(2)
-
55(2)
%
-
±5
-
%
-
±1(3)
-
%
DuCyHSI
Duty cycle
ACCHSI
Accuracy of the HSI oscillator
(factory calibrated)
tSU(HSI)
HSI oscillator startup time
-
1(2)
-
2(2)
µs
IDDA(HSI)
HSI oscillator power
consumption
-
-
80
-
µA
TA = -40 to 85°C
TA = 25°C
1. VDDA = 3.3 V, TA = -40 to 85°C unless otherwise specified.
2. Guaranteed by design, not tested in production.
3. With user calibration.
High-speed internal 14 MHz (HSI14) RC oscillator (dedicated to ADC)
Table 35. HSI14 oscillator characteristics(1)
Symbol
fHSI14
TRIM
Parameter
Conditions
Min
Typ
-
-
14
Frequency
HSI14 user-trimming step
DuCy(HSI14) Duty cycle
Max
Unit
-
MHz
(2)
-
-
-
1
%
-
45(2)
-
55(2)
%
ACCHSI14
Accuracy of the HSI14
oscillator (factory calibrated)
TA = –40 to 85 °C
-
±5
-
%
tsu(HSI14)
HSI14 oscillator startup time
-
1(2)
-
2(2)
µs
HSI14 oscillator power
consumption
-
-
100
-
µA
IDDA(HSI14)
1. VDDA = 3.3 V, TA = -40 to 85 °C unless otherwise specified.
2. Guaranteed by design, not tested in production.
Low-speed internal (LSI) RC oscillator
Table 36. LSI oscillator characteristics(1)
Symbol
fLSI
50/83
Parameter
Frequency
DocID027114 Rev 3
Min
Typ
Max
Unit
30
40
50
kHz
STM32F070CB/RB/C6/F6
Electrical characteristics
Table 36. LSI oscillator characteristics(1)
Symbol
Parameter
(2)
tsu(LSI)
IDDA(LSI)(2)
Min
Typ
Max
Unit
LSI oscillator startup time
-
-
85
µs
LSI oscillator power consumption
-
0.75
-
µA
1. VDDA = 3.3 V, TA = -40 to 85 °C unless otherwise specified.
2. Guaranteed by design, not tested in production.
6.3.9
PLL characteristics
The parameters given in Table 37 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 20: General operating
conditions.
Table 37. PLL characteristics
Value
Symbol
fPLL_IN
fPLL_OUT
tLOCK
Parameter
Unit
Min
Typ
Max
PLL input clock(1)
1(2)
8.0
24(2)
MHz
PLL input clock duty cycle
40(2)
-
60(2)
%
PLL multiplier output clock
16(2)
-
48
MHz
-
200(2)
µs
-
300(2)
ps
PLL lock time
JitterPLL
-
Cycle-to-cycle jitter
-
1. Take care to use the appropriate multiplier factors to obtain PLL input clock values compatible with the
range defined by fPLL_OUT.
2. Guaranteed by design, not tested in production.
6.3.10
Memory characteristics
Flash memory
The characteristics are given at TA = -40 to 85 °C unless otherwise specified.
Table 38. Flash memory characteristics
Min
Typ
Max(1)
Unit
16-bit programming time TA = -40 to +85 °C
-
53.5
-
µs
Page erase time (2)
TA = -40 to +85 °C
-
30
-
ms
tME
Mass erase time
TA = -40 to +85 °C
-
30
-
ms
IDD
Supply current
Write mode
-
-
10
mA
Erase mode
-
-
12
mA
2.4
-
3.6
V
Symbol
tprog
tERASE
Vprog
Parameter
Programming voltage
Conditions
-
1. Guaranteed by design, not tested in production.
2. Page size is 1KB for STM32F070x6 devices and 2KB for STM32F070xB devices.
DocID027114 Rev 3
51/83
69
Electrical characteristics
STM32F070CB/RB/C6/F6
Table 39. Flash memory endurance and data retention
Symbol
NEND
tRET
Min(1)
Unit
TA = -40 to +85 °C
1
kcycle
(2)
20
Years
Parameter
Endurance
Data retention
Conditions
1 kcycle
at TA = 85 °C
1. Data based on characterization results, not tested in production.
2. Cycling performed over the whole temperature range.
6.3.11
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
•
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 40. They are based on the EMS levels and classes
defined in application note AN1709.
Table 40. EMS characteristics
Symbol
Parameter
Conditions
Level/
Class
VFESD
VDD = 3.3V, LQFP48, TA = +25 °C,
Voltage limits to be applied on any I/O pin
fHCLK = 48 MHz,
to induce a functional disturbance
conforming to IEC 61000-4-2
3B
VEFTB
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD = 3.3V, LQFP48, TA = +25°C,
fHCLK = 48 MHz,
conforming to IEC 61000-4-4
4B
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
52/83
DocID027114 Rev 3
STM32F070CB/RB/C6/F6
Electrical characteristics
The software flowchart must include the management of runaway conditions such as:
•
Corrupted program counter
•
Unexpected reset
•
Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 41. EMI characteristics
Symbol Parameter
SEMI
6.3.12
Conditions
Monitored
frequency band
0.1 to 30 MHz
VDD = 3.6 V, TA = 25 °C,
30 to 130 MHz
LQFP100 package
Peak level
compliant with
130 MHz to 1 GHz
IEC 61967-2
EMI Level
Max vs. [fHSE/fHCLK]
Unit
8/48 MHz
-3
23
dBµV
17
4
-
Electrical sensitivity characteristics
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
DocID027114 Rev 3
53/83
69
Electrical characteristics
STM32F070CB/RB/C6/F6
Table 42. ESD absolute maximum ratings
Symbol
Ratings
Conditions
Packages
Class
Maximum
value(1)
Unit
VESD(HBM)
Electrostatic discharge voltage TA = +25 °C, conforming
(human body model)
to JESD22-A114
All
2
2000
V
VESD(CDM)
Electrostatic discharge voltage TA = +25 °C, conforming
(charge device model)
to ANSI/ESD STM5.3.1
All
C4
500
V
1. Data based on characterization results, not tested in production.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
•
A supply overvoltage is applied to each power supply pin.
•
A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 43. Electrical sensitivities
Symbol
LU
6.3.13
Parameter
Static latch-up class
Conditions
TA = +105 °C conforming to JESD78A
Class
II level A
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDDIOx (for standard, 3.3 V-capable I/O pins) should be avoided during normal
product operation. However, in order to give an indication of the robustness of the
microcontroller in cases when abnormal injection accidentally happens, susceptibility tests
are performed on a sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of the -5 µA/+0 µA range) or other functional failure (for example reset occurrence or
oscillator frequency deviation).
The characterization results are given in Table 44.
Negative induced leakage current is caused by negative injection and positive induced
leakage current is caused by positive injection.
54/83
DocID027114 Rev 3
STM32F070CB/RB/C6/F6
Electrical characteristics
Table 44. I/O current injection susceptibility
Functional
susceptibility
Symbol
Description
Unit
Negative Positive
injection injection
IINJ
6.3.14
Injected current on BOOT0 and PF1 pins
-0
NA
Injected current on PA9, PB3, PB13, PF11 pins with induced
leakage current on adjacent pins less than 50 µA
-5
NA
Injected current on PA11 and PA12 pins with induced
leakage current on adjacent pins less than -1 mA
-5
NA
Injected current on all other FT and FTf pins
-5
NA
Injected current on PB0 and PB1 pins
-5
NA
Injected current on PC0 pin
-0
+5
Injected current on all other TTa, TC and RST pins
-5
+5
mA
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 45 are derived from tests
performed under the conditions summarized in Table 20: General operating conditions. All
I/Os are designed as CMOS- and TTL-compliant (except BOOT0).
Table 45. I/O static characteristics
Symbol
VIL
VIH
Vhys
Parameter
Low level input
voltage
High level input
voltage
Schmitt trigger
hysteresis
Conditions
Min
Typ
Max
TC and TTa I/O
-
-
0.3 VDDIOx+0.07(1)
FT and FTf I/O
-
-
0.475 VDDIOx–0.2(1)
BOOT0
-
-
0.3 VDDIOx–0.3(1)
All I/Os except
BOOT0 pin
-
-
0.3 VDDIOx
TC and TTa I/O
0.445 VDDIOx+0.398(1)
-
-
-
-
-
-
FT and FTf I/O
0.5 VDDIOx
+0.2(1)
(1)
BOOT0
0.2 VDDIOx+0.95
All I/Os except
BOOT0 pin
0.7 VDDIOx
-
TC and TTa I/O
-
200(1)
-
-
(1)
-
(1)
-
FT and FTf I/O
BOOT0
-
DocID027114 Rev 3
100
300
Unit
V
V
mV
55/83
69
Electrical characteristics
STM32F070CB/RB/C6/F6
Table 45. I/O static characteristics (continued)
Symbol
Ilkg
RPU
Parameter
Input leakage
current(2)
Weak pull-up
equivalent resistor
(4)
RPD
Weak pull-down
equivalent
resistor(4)
CIO
I/O pin capacitance
Conditions
Min
Typ
Max
TC, FT and FTf I/O
TTa in digital mode
VSS ≤ VIN ≤ VDDIOx
-
-
± 0.1
TTa in digital mode
VDDIOx ≤ VIN ≤ VDDA
-
-
1
TTa in analog mode
VSS ≤ VIN ≤ VDDA
-
-
± 0.2
FT and FTf I/O (3)
VDDIOx ≤ VIN ≤ 5 V
-
-
10
VIN = VSS
25
40
55
kΩ
VIN = VDDIOx
25
40
55
kΩ
-
5
-
pF
-
Unit
µA
1. Data based on design simulation only. Not tested in production.
2. The leakage could be higher than the maximum value, if negative current is injected on adjacent pins. Refer to Table 44:
I/O current injection susceptibility.
3. To sustain a voltage higher than VDDIOx + 0.3 V, the internal pull-up/pull-down resistors must be disabled.
4. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10% order).
All I/Os are CMOS- and TTL-compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 15 for standard I/Os, and in Figure 16 for
5 V tolerant I/Os. The following curves are design simulation results, not tested in
production.
56/83
DocID027114 Rev 3
STM32F070CB/RB/C6/F6
Electrical characteristics
Figure 15. TC and TTa I/O input characteristics
7(67('5$1*(
77/VWDQGDUGUHTXLUHPHQW
HQW
LUHP
UHTX
DUG
WDQG
9,1 9
6V
&02
,2[
9 ''
PLQ
9 ,+
81'(),1(',13875$1*(
',2[
9'
9,+PLQ
9'',2[
HQW
9,/PD[
GUHTXLUHP
26VWDQGDU
0
&
9'',2[
9,/PD[
77/VWDQGDUGUHTXLUHPHQW
7(67('5$1*(
9'',2[ 9
06Y9
Figure 16. Five volt tolerant (FT and FTf) I/O input characteristics
7(67('5$1*(
77/VWDQGDUGUHTXLUHPHQW
HQW
DUG
WDQG
9,1 9
6V
&02
LUHP
UHTX
,2[
9 ''
PLQ
81'(),1(',13875$1*(
9 ,+
9,+PLQ
9,/PD[
,2[
9''
9
'',2[
77/VWDQGDUGUHTXLUHPHQW
HQW
GUHTXLUHP
6VWDQGDU
&02
9'',2[
9,/PD[
7(67('5$1*(
9'',2[ 9
06Y9
DocID027114 Rev 3
57/83
69
Electrical characteristics
STM32F070CB/RB/C6/F6
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or
source up to +/- 20 mA (with a relaxed VOL/VOH).
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
•
The sum of the currents sourced by all the I/Os on VDDIOx, plus the maximum
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
ΣIVDD (see Table 17: Voltage characteristics).
•
The sum of the currents sunk by all the I/Os on VSS, plus the maximum consumption of
the MCU sunk on VSS, cannot exceed the absolute maximum rating ΣIVSS (see
Table 17: Voltage characteristics).
Output voltage levels
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 20: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT, TTa or
TC unless otherwise specified).
Table 46. Output voltage characteristics(1)
Symbol
Parameter
VOL
Output low level voltage for an I/O pin
VOH
Output high level voltage for an I/O pin
VOL(2)
Output low level voltage for an I/O pin
VOH(2)
Output high level voltage for an I/O pin
VOL(2)
Output low level voltage for an I/O pin
VOH(2)
Output high level voltage for an I/O pin
VOLFm+(2)
Output low level voltage for an FTf I/O pin in
Fm+ mode
Conditions
Min
Max
|IIO| = 8 mA
VDDIOx ≥ 2.7 V
-
0.4
VDDIOx–0.4
-
-
1.3
VDDIOx–1.3
-
-
0.4
VDDIOx–0.4
-
|IIO| = 20 mA
VDDIOx ≥ 2.7 V
-
0.4
V
|IIO| = 10 mA
-
0.4
V
|IIO| = 20 mA
VDDIOx ≥ 2.7 V
|IIO| = 6 mA
Unit
V
V
V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 17:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ΣIIO.
2. Data based on characterization results. Not tested in production.
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 17 and
Table 47, respectively.
Unless otherwise specified, the parameters given are derived from tests performed under
the ambient temperature and supply voltage conditions summarized in Table 20: General
operating conditions.
58/83
DocID027114 Rev 3
STM32F070CB/RB/C6/F6
Electrical characteristics
Table 47. I/O AC characteristics(1)(2)
OSPEEDRy
[1:0] value(1)
Symbol
Parameter
Conditions
Min
Max
Unit
-
2
MHz
-
125
-
125
-
10
-
25
-
25
CL = 30 pF, VDDIOx ≥ 2.7 V
-
50
CL = 50 pF, VDDIOx ≥ 2.7 V
-
30
CL = 50 pF, 2.4 V ≤VDDIOx < 2.7 V
-
20
CL = 30 pF, VDDIOx ≥ 2.7 V
-
5
CL = 50 pF, VDDIOx ≥ 2.7 V
-
8
CL = 50 pF, 2.4 V ≤VDDIOx < 2.7 V
-
12
CL = 30 pF, VDDIOx ≥ 2.7 V
-
5
CL = 50 pF, VDDIOx ≥ 2.7 V
-
8
CL = 50 pF, 2.4 V ≤VDDIOx < 2.7 V
-
12
-
2
-
12
-
34
10
-
fmax(IO)out Maximum frequency(3)
x0
tf(IO)out
Output fall time
tr(IO)out
Output rise time
CL = 50 pF, VDDIOx ≥ 2.4 V
fmax(IO)out Maximum frequency(3)
01
tf(IO)out
Output fall time
tr(IO)out
Output rise time
fmax(IO)out Maximum
11
tf(IO)out
tr(IO)out
Fm+
configuration
(4)
-
CL = 50 pF, VDDIOx ≥ 2.4 V
frequency(3)
Output fall time
Output rise time
fmax(IO)out Maximum
frequency(3)
CL = 50 pF, VDDIOx ≥ 2.4 V
tf(IO)out
Output fall time
tr(IO)out
Output rise time
tEXTIpw
Pulse width of external
signals detected by the
EXTI controller
-
ns
MHz
ns
MHz
ns
MHz
ns
ns
1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the STM32F0xxxx RM0360 reference manual for a
description of GPIO Port configuration register.
2. Guaranteed by design, not tested in production.
3. The maximum frequency is defined in Figure 17.
4. When Fm+ configuration is set, the I/O speed control is bypassed. Refer to the STM32F0xxxx reference manual RM0360
for a detailed description of Fm+ I/O configuration.
DocID027114 Rev 3
59/83
69
Electrical characteristics
STM32F070CB/RB/C6/F6
Figure 17. I/O AC characteristics definition
W I ,2 RXW
W U ,2 RXW
7
7DQGLIWKHGXW\F\FOHLV
0D[LPXPIUHTXHQF\LVDFKLHYHGLI WW
U I
ZKHQORDGHGE\& VHHWKHWDEOH,2$&FKDUDFWHULVWLFVGHILQLWLRQ
069
6.3.15
NRST pin characteristics
The NRST pin input driver uses the CMOS technology. It is connected to a permanent pullup resistor, RPU.
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 20: General operating conditions.
Table 48. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL(NRST)
NRST input low level voltage
-
-
-
0.3 VDD+0.07(1)
VIH(NRST)
NRST input high level voltage
-
0.445 VDD+0.398(1)
-
-
Vhys(NRST)
NRST Schmitt trigger voltage
hysteresis
-
-
200
-
mV
V
RPU
Weak pull-up equivalent
resistor(2)
VIN = VSS
25
40
55
kΩ
VF(NRST)
NRST input filtered pulse
-
-
-
100(1)
ns
2.7 < VDD < 3.6
300(3)
-
-
2.4 < VDD < 3.6
500(3)
-
-
VNF(NRST) NRST input not filtered pulse
1. Data based on design simulation only. Not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance is minimal (~10% order).
3. Data based on design simulation only. Not tested in production.
60/83
DocID027114 Rev 3
ns
STM32F070CB/RB/C6/F6
Electrical characteristics
Figure 18. Recommended NRST pin protection
([WHUQDO
UHVHWFLUFXLW
9''
538
1567
,QWHUQDOUHVHW
)LOWHU
)
06 9
1. The external capacitor protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 48: NRST pin characteristics. Otherwise the reset will not be taken into account by the device.
6.3.16
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 49 are preliminary values derived
from tests performed under ambient temperature, fPCLK frequency and VDDA supply voltage
conditions summarized in Table 20: General operating conditions.
Note:
It is recommended to perform a calibration after each power-up.
Table 49. ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA
Analog supply voltage for
ADC ON
-
2.4
-
3.6
V
VDD = VDDA = 3.3 V
-
0.9
-
mA
IDDA (ADC)
Current consumption of
the ADC(1)
fADC
ADC clock frequency
-
0.6
-
14
MHz
fS(2)
Sampling rate
-
0.05
-
1
MHz
fADC = 14 MHz
-
-
823
kHz
-
-
-
17
1/fADC
fTRIG(2)
External trigger
frequency
VAIN
Conversion voltage range
-
0
-
VDDA
V
RAIN(2)
External input impedance
See Equation 1 and
Table 50 for details
-
-
50
kΩ
RADC(2)
Sampling switch
resistance
-
-
-
1
kΩ
CADC(2)
Internal sample and hold
capacitor
-
-
-
8
pF
DocID027114 Rev 3
61/83
69
Electrical characteristics
STM32F070CB/RB/C6/F6
Table 49. ADC characteristics (continued)
Symbol
Parameter
tCAL(2)(3)
Conditions
Calibration time
tlatr(2)
JitterADC
tS(2)
ADC_DR register write
latency
5.9
µs
-
83
1/fADC
1.5 ADC
cycles + 3
fPCLK cycles
-
ADC clock = PCLK/2
-
4.5
-
fPCLK
cycle
ADC clock = PCLK/4
-
8.5
-
fPCLK
cycle
tCONV(2)
fADC = fPCLK/2 =
14 MHz
0.196
µs
fADC = fPCLK/2
5.5
1/fPCLK
fADC = fPCLK/4 =
12 MHz
0.219
µs
fADC = fPCLK/4
10.5
1/fPCLK
fADC = fHSI14 = 14 MHz
0.188
-
0.259
µs
fADC = fHSI14
-
1
-
1/fHSI14
fADC = 14 MHz
0.107
-
17.1
µs
-
1.5
-
239.5
1/fADC
Sampling time
Total conversion time
(including sampling time)
Unit
-
ADC jitter on trigger
conversion
Stabilization time
Max
1.5 ADC
cycles + 2
fPCLK cycles
Trigger conversion
latency
tSTAB(2)
Typ
fADC = 14 MHz
ADC clock = HSI14
WLATENCY(2)(4)
Min
fADC = 14 MHz,
12-bit resolution
12-bit resolution
14
1
-
1/fADC
18
14 to 252 (tS for sampling +12.5 for
successive approximation)
µs
1/fADC
1. During conversion of the sampled value (12.5 x ADC clock period), an additional consumption of 100 µA on IDDA and 60 µA
on IDD should be taken into account.
2. Guaranteed by design, not tested in production.
3. Specified value includes only ADC timing. It does not include the latency of the register access.
4. This parameter specify latency for transfer of the conversion result to the ADC_DR register. EOC flag is set at this time.
Equation 1: RAIN max formula
TS
- – R ADC
R AIN < --------------------------------------------------------------N+2
f ADC × C ADC × ln ( 2
)
The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
62/83
DocID027114 Rev 3
STM32F070CB/RB/C6/F6
Electrical characteristics
Table 50. RAIN max for fADC = 14 MHz
Ts (cycles)
tS (µs)
RAIN max (kΩ)(1)
1.5
0.11
0.4
7.5
0.54
5.9
13.5
0.96
11.4
28.5
2.04
25.2
41.5
2.96
37.2
55.5
3.96
50
71.5
5.11
NA
239.5
17.1
NA
1. Guaranteed by design, not tested in production.
Table 51. ADC accuracy(1)(2)(3)
Symbol
Parameter
ET
Total unadjusted error
EO
Offset error
EG
Gain error
ED
Differential linearity error
EL
Integral linearity error
Test conditions
fPCLK = 48 MHz,
fADC = 14 MHz, RAIN < 10 kΩ
VDDA = 2.7 V to 3.6 V
TA = −40 to 85 °C
Typ
Max(4)
±3.3
±4
±1.9
±2.8
±2.8
±3
±0.7
±1.3
±1.2
±1.7
Unit
LSB
1. ADC DC accuracy values are measured after internal calibration.
2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-robust) analog input
pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog
input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject
negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.14 does not affect the ADC
accuracy.
3. Better performance may be achieved in restricted VDDA, frequency and temperature ranges.
4. Data based on characterization results, not tested in production.
DocID027114 Rev 3
63/83
69
Electrical characteristics
STM32F070CB/RB/C6/F6
Figure 19. ADC accuracy characteristics
966$
(*
([DPSOHRIDQDFWXDOWUDQVIHUFXUYH
7KHLGHDOWUDQVIHUFXUYH
(QGSRLQWFRUUHODWLRQOLQH
(7 7RWDO8QDMXVWHG(UURU PD[LPXPGHYLDWLRQ
EHWZHHQWKHDFWXDODQGLGHDOWUDQVIHUFXUYHV
(2 2IIVHW(UURU PD[LPXPGHYLDWLRQ
EHWZHHQWKHILUVWDFWXDOWUDQVLWLRQDQGWKHILUVW
LGHDORQH
(* *DLQ(UURU GHYLDWLRQEHWZHHQWKHODVW
LGHDOWUDQVLWLRQDQGWKHODVWDFWXDORQH
(' 'LIIHUHQWLDO/LQHDULW\(UURU PD[LPXP
GHYLDWLRQEHWZHHQDFWXDOVWHSVDQGWKHLGHDORQHV
(/ ,QWHJUDO/LQHDULW\(UURU PD[LPXPGHYLDWLRQ
EHWZHHQDQ\DFWXDOWUDQVLWLRQDQGWKHHQGSRLQW
FRUUHODWLRQOLQH
(7
(2
(/
('
/6%,'($/
9''$
06 9
Figure 20. Typical connection diagram using the ADC
9 ''$
6DPSOHDQGKROG$'&
FRQ YHU WHU
97
5 $,1
9$,1
5 $'&
$,1[
& SDU DVLWLF
97
,/ $
ELW
FRQ YHU WHU
&$'&
06 9
1. Refer to Table 49: ADC characteristics for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 9: Power supply scheme.
The 10 nF capacitor should be ceramic (good quality) and it should be placed as close as
possible to the chip.
64/83
DocID027114 Rev 3
STM32F070CB/RB/C6/F6
6.3.17
Electrical characteristics
Temperature sensor characteristics
Table 52. TS characteristics
Symbol
Parameter
TL(1)
Avg_Slope
Min
Typ
Max
Unit
-
±1
±2
°C
4.0
4.3
4.6
mV/°C
1.34
1.43
1.52
V
VSENSE linearity with temperature
(1)
V30
Average slope
Voltage at 30 °C (± 5 °C)
(2)
tSTART(1)
ADC_IN16 buffer startup time
-
-
10
µs
tS_temp(1)
ADC sampling time when reading the
temperature
4
-
-
µs
1. Guaranteed by design, not tested in production.
2. Measured at VDDA = 3.3 V ± 10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte. Refer to Table 2:
Temperature sensor calibration values.
6.3.18
Timer characteristics
The parameters given in the following tables are guaranteed by design.
Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 53. TIMx characteristics
Symbol
tres(TIM)
fEXT
Parameter
Timer resolution
Timer external clock
frequency on CH1 to
CH4
16-bit timer maximum
period
tMAX_COUNT
32-bit timer maximum
period
Conditions
Min
Typ
Max
Unit
-
-
1
-
tTIMxCLK
fTIMxCLK = 48 MHz
-
20.8
-
ns
-
-
fTIMxCLK/2
-
MHz
fTIMxCLK = 48 MHz
-
24
-
MHz
-
-
216
-
tTIMxCLK
fTIMxCLK = 48 MHz
-
1365
-
µs
-
-
232
-
tTIMxCLK
fTIMxCLK = 48 MHz
-
89.48
-
s
DocID027114 Rev 3
65/83
69
Electrical characteristics
STM32F070CB/RB/C6/F6
Table 54. IWDG min/max timeout period at 40 kHz (LSI)(1)
Prescaler divider
PR[2:0] bits
Min timeout RL[11:0]=
0x000
Max timeout RL[11:0]=
0xFFF
/4
0
0.1
409.6
/8
1
0.2
819.2
/16
2
0.4
1638.4
/32
3
0.8
3276.8
/64
4
1.6
6553.6
/128
5
3.2
13107.2
/256
6 or 7
6.4
26214.4
Unit
ms
1. These timings are given for a 40 kHz clock but the microcontroller internal RC frequency can vary from 30
to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing
of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.
Table 55. WWDG min/max timeout value at 48 MHz (PCLK)
6.3.19
Prescaler
WDGTB
Min timeout value
Max timeout value
1
0
0.0853
5.4613
2
1
0.1706
10.9226
4
2
0.3413
21.8453
8
3
0.6826
43.6906
Unit
ms
Communication interfaces
I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual rev. 03 for:
•
Standard-mode (Sm): with a bit rate up to 100 kbit/s
•
Fast-mode (Fm): with a bit rate up to 400 kbit/s
•
Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
The I2C timings requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to Reference manual).
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and VDDIOx is disabled, but is still present. Only FTf I/O pins
support Fm+ low level output current maximum requirement. Refer to Section 6.3.14: I/O
port characteristics for the I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog
filter characteristics:
66/83
DocID027114 Rev 3
STM32F070CB/RB/C6/F6
Electrical characteristics
Table 56. I2C analog filter characteristics(1)
Symbol
Parameter
Min
Max
Unit
tAF
Maximum pulse width of spikes that
are suppressed by the analog filter
50(2)
260(3)
ns
1. Guaranteed by design, not tested in production.
2. Spikes with widths below tAF(min) are filtered.
3. Spikes with widths above tAF(max) are not filtered
SPI characteristics
Unless otherwise specified, the parameters given in Table 57 for SPI are derived from tests
performed under the ambient temperature, fPCLKx frequency and supply voltage conditions
summarized in Table 20: General operating conditions.
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics.
Table 57. SPI characteristics(1)
Symbol
fSCK
1/tc(SCK)
Parameter
SPI clock frequency
Conditions
Min
Max
Master mode
-
18
Slave mode
-
18
-
6
tr(SCK)
tf(SCK)
SPI clock rise and fall
time
Capacitive load: C = 15 pF
tsu(NSS)
NSS setup time
Slave mode
4Tpclk
-
th(NSS)
NSS hold time
Slave mode
2Tpclk + 10
-
SCK high and low time
Master mode, fPCLK = 36 MHz,
presc = 4
Tpclk/2 -2
Tpclk/2 + 1
Master mode
4
-
Slave mode
5
-
Master mode
4
-
Slave mode
5
-
Data output access time
Slave mode, fPCLK = 20 MHz
0
3Tpclk
Data output disable time
Slave mode
0
18
tv(SO)
Data output valid time
Slave mode (after enable edge)
-
22.5
tv(MO)
Data output valid time
Master mode (after enable edge)
-
6
Slave mode (after enable edge)
11.5
-
Master mode (after enable edge)
2
-
Slave mode
25
75
tw(SCKH)
tw(SCKL)
tsu(MI)
tsu(SI)
th(MI)
th(SI)
ta(SO)(2)
tdis(SO)
(3)
th(SO)
th(MO)
DuCy(SCK)
Data input setup time
Data input hold time
Data output hold time
SPI slave input clock
duty cycle
Unit
MHz
ns
ns
%
1. Data based on characterization results, not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z
DocID027114 Rev 3
67/83
69
Electrical characteristics
STM32F070CB/RB/C6/F6
Figure 21. SPI timing diagram - slave mode and CPHA = 0
166LQSXW
6&.,QSXW
W68 166
&3+$
&32/
WK 166
WF 6&.
WZ 6&.+
WZ 6&./
&3+$
&32/
W9 62
WD 62
0,62
287387
WU 6&.
WI 6&.
WK 62
06%287
%,7287
06%,1
%,7,1
WGLV 62
/6%287
WVX 6,
026,
,1387
/6%,1
WK 6,
DLF
Figure 22. SPI timing diagram - slave mode and CPHA = 1
166LQSXW
6&.LQSXW
W68 166
&3+$
&32/
&3+$
&32/
WZ 6&.+
WZ 6&./
WK 62
WY 62
WD 62
0,62
287387
06%287
%,7287
WU 6&.
WI 6&.
WGLV 62
/6%287
WK 6,
WVX 6,
026,
,1387
WK 166
WF 6&.
06%,1
%,7,1
/6%,1
DLE
1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
68/83
DocID027114 Rev 3
STM32F070CB/RB/C6/F6
Electrical characteristics
Figure 23. SPI timing diagram - master mode
+LJK
166LQSXW
6&.2XWSXW
&3+$
&32/
6&.2XWSXW
WF 6&.
&3+$
&32/
&3+$
&32/
&3+$
&32/
WVX 0,
0,62
,13 87
WZ 6&.+
WZ 6&./
WU 6&.
WI 6&.
%,7,1
06%,1
/6%,1
WK 0,
026,
287387
% , 7287
06%287
WY 02
/6%287
WK 02
DLF
1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
USB characteristics
The STM32F070CB/RB/C6/F6 USB interface is fully compliant with the USB specification
version 2.0 and is USB-IF certified (for Full-speed device operation).
Table 58. USB electrical characteristics
Symbol
Conditions
Min.
Typ
Max.
Unit
USB transceiver operating
voltage
-
3.0(1)
-
3.6
V
tSTARTUP(2)
USB transceiver startup time
-
-
-
1.0
µs
RPUI
Embedded USB_DP pull-up
value during idle
-
1.1
1.26
1.5
RPUR
Embedded USB_DP pull-up
value during reception
-
ZDRV(2)
Output driver impedance(3)
VDD
Parameter
kΩ
Driving high
and low
2.0
2.26
2.6
28
40
44
Ω
1. The STM32F070CB/RB/C6/F6 USB functionality is ensured down to 2.7 V, but the USB electrical
characteristics are degraded in the 2.7-to-3.0 V voltage range.
2. Guaranteed by design, not tested in production.
3. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-); the matching
impedance is already included in the embedded driver.
DocID027114 Rev 3
69/83
69
Package information
7
STM32F070CB/RB/C6/F6
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
7.1
LQFP64 package information
LQFP64 is 64-pin, 10 x 10 mm low-profile quad flat package.
Figure 24. LQFP64 outline
PP
*$8*(3/$1(
F
$
$
$
6($7,1*3/$1(
&
$
FFF &
'
'
'
.
/
/
3,1
,'(17,),&$7,21
(
(
(
E
H
:B0(B9
1. Drawing is not to scale.
Table 59. LQFP64 mechanical data
inches(1)
millimeters
Symbol
70/83
Min
Typ
Max
Min
Typ
Max
A
-
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
DocID027114 Rev 3
STM32F070CB/RB/C6/F6
Package information
Table 59. LQFP64 mechanical data (continued)
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
c
0.090
-
0.200
0.0035
-
0.0079
D
-
12.000
-
-
0.4724
-
D1
-
10.000
-
-
0.3937
-
D3
-
7.500
-
-
0.2953
-
E
-
12.000
-
-
0.4724
-
E1
-
10.000
-
-
0.3937
-
E3
-
7.500
-
-
0.2953
-
e
-
0.500
-
-
0.0197
-
K
0°
3.5°
7°
0°
3.5°
7°
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 25. LQFP64 recommended footprint
AIC
1. Dimensions are expressed in millimeters.
DocID027114 Rev 3
71/83
80
Package information
STM32F070CB/RB/C6/F6
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 26. LQFP64 marking example (package top view)
5HYLVLRQFRGH
3
3URGXFWLGHQWLILFDWLRQ
45.'
3#5
'DWHFRGH
: 88
3LQLGHQWLILFDWLRQ
06 9
1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
72/83
DocID027114 Rev 3
STM32F070CB/RB/C6/F6
LQFP48 package information
LQFP48 is a 48-pin, 7 x 7 mm low-profile quad flat package
Figure 27. LQFP48 outline
3%!4).'
0,!.%
#
C
!
!
!
MM
'!5'%0,!.%
CCC #
$
+
!
$
,
,
$
%
%
B
%
7.2
Package information
0).
)$%.4)&)#!4)/.
E
"?-%?6
1. Drawing is not to scale.
Table 60. LQFP48 mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
-
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
c
0.090
-
0.200
0.0035
-
0.0079
D
8.800
9.000
9.200
0.3465
0.3543
0.3622
D1
6.800
7.000
7.200
0.2677
0.2756
0.2835
D3
-
5.500
-
-
0.2165
-
E
8.800
9.000
9.200
0.3465
0.3543
0.3622
DocID027114 Rev 3
73/83
80
Package information
STM32F070CB/RB/C6/F6
Table 60. LQFP48 mechanical data (continued)
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
E1
6.800
7.000
7.200
0.2677
0.2756
0.2835
E3
-
5.500
-
-
0.2165
-
e
-
0.500
-
-
0.0197
-
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
k
0°
3.5°
7°
0°
3.5°
7°
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 28. LQFP48 recommended footprint
AID
1. Dimensions are expressed in millimeters.
74/83
DocID027114 Rev 3
STM32F070CB/RB/C6/F6
Package information
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 29. LQFP48 marking example (package top view)
'HYLFHLGHQWLILFDWLRQ
45.
'$#5
'DWHFRGH
:
88
3LQLGHQWLILFDWLRQ
3
5HYLVLRQFRGH
06 9
1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
DocID027114 Rev 3
75/83
80
Package information
7.3
STM32F070CB/RB/C6/F6
TSSOP20 package information
TSSOP20 is a 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch package.
Figure 30.TSSOP20 outline
ϮϬ
ϭϭ
Đ
ϭ
ϭ
^ d/E'
W>E
Ϭ͘Ϯϱŵŵ
'h' W>E
ϭϬ
W/Eϭ
/ Ed/&/d/KE
Ŭ
ĂĂĂ
ϭ
Ϯ
ď
>
>ϭ
Ğ
zͺD ͺsϯ
1. Drawing is not to scale.
Table 61. TSSOP20 mechanical data
inches(1)
millimeters
Symbol
76/83
Min.
Typ.
Max.
Min.
Typ.
Max.
A
-
-
1.200
-
-
0.0472
A1
0.050
-
0.150
0.0020
-
0.0059
A2
0.800
1.000
1.050
0.0315
0.0394
0.0413
b
0.190
-
0.300
0.0075
-
0.0118
c
0.090
-
0.200
0.0035
-
0.0079
D
6.400
6.500
6.600
0.2520
0.2559
0.2598
E
6.200
6.400
6.600
0.2441
0.2520
0.2598
E1
4.300
4.400
4.500
0.1693
0.1732
0.1772
e
-
0.650
-
-
0.0256
-
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
DocID027114 Rev 3
STM32F070CB/RB/C6/F6
Package information
Table 61. TSSOP20 mechanical data (continued)
inches(1)
millimeters
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
k
0°
-
8°
0°
-
8°
aaa
-
-
0.100
-
-
0.0039
1. Values in inches are converted from mm and rounded to four decimal digits.
Figure 31. TSSOP20 footprint
9!?&0?6
1. Dimensions are expressed in millimeters.
DocID027114 Rev 3
77/83
80
Package information
STM32F070CB/RB/C6/F6
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 32. TSSOP20 marking example (package top view)
'HYLFHLGHQWLILFDWLRQ
''1
'DWHFRGH
3LQLGHQWLILFDWLRQ
5HYLVLRQFRGH
:
88
3
06 9
1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
78/83
DocID027114 Rev 3
STM32F070CB/RB/C6/F6
7.4
Package information
Thermal characteristics
The maximum chip junction temperature (TJmax) must never exceed the values given in
Table 20: General operating conditions.
The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max x ΘJA)
Where:
•
TA max is the maximum ambient temperature in °C,
•
ΘJA is the package junction-to-ambient thermal resistance, in ° C/W,
•
PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
•
PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = Σ (VOL × IOL) + Σ ((VDD - VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
Table 62. Package thermal characteristics
Symbol
ΘJ
7.4.1
Parameter
Value
Thermal resistance junction-ambient
LQFP64 - 10 mm x 10 mm
44
Thermal resistance junction-ambient
LQFP48 - 7 mm x 7 mm
55
Thermal resistance junction-ambient
TSSOP20 - 6.5 mm x 6.4 mm
76
Unit
°C/W
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org
DocID027114 Rev 3
79/83
80
Ordering information
8
STM32F070CB/RB/C6/F6
Ordering information
For a list of available options (memory, package, and so on) or for further information on any
aspect of this device, please contact your nearest ST sales office.
+
Table 63. Ordering information scheme
Example:
STM32
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
F = General-purpose
Sub-family
070 = STM32F070xx
Pin count
F = 20 pins
C = 48 pins
R = 64 pins
Code size
6 = 32 Kbyte of Flash memory
B = 128 Kbyte of Flash memory
Package
P = TSSOP
T = LQFP
Temperature range
6 = –40 to 85 °C
Options
xxx = programmed parts
TR = tape and reel
80/83
DocID027114 Rev 3
F
070
C
6
T
6
x
STM32F070CB/RB/C6/F6
9
Revision history
Revision history
Table 64. Document revision history
Date
Revision
27-Nov-2014
1
Initial release.
2
Updated the number of SPI in Features and Section:
Description.
Updated Section: Serial peripheral interface (SPI).
Updated the fourth footnote of Table: STM32F070xB/i
pin definitions, and added the reference to PB9 pin.
Moved the AF3 data to AF4 for PA9 and PA10 pins in
Table: Alternate functions selected through GPIOA_AFR
registers for port A.
Added the reference to footnote 1 to AF0 data for PB12,
PB13, PB14 and PB15, and to AF5 data for PB9 and
PB10 in Table: Alternate functions selected through
GPIOB_AFR registers for port B.
Added the reference to footnote 1 to SPI2 in Table:
STM32F070xB/6 peripheral register boundary
addressesF070.
3
Updated:
– Removal of Table 1 from cover page (all part numbers
put in the header)
– Table 1: STM32F070CB/RB/C6/F6 family device
features and peripheral counts; number of int. ADC
channels corrected
– Figure 1: Block diagram
– Figure 2: Clock tree
– Table 7: STM32F70x0 USART implementation
– Figure 6: STM32F070CB/RB/C6/F6 memory map and
added the note related to the start address of the
system memory
– Figure 9: Power supply scheme
– Section 3.5.1: Power supply schemes
– Section 3.11: Timers and watchdogs - number of
complementary outputs in the table
– Table 10: STM32F070xB/6 pin definitions - TSSOP20
pinout correction, pins 10, 15 and 16
– Table 23: Embedded internal reference voltage:
added tSTART, changed VREFINT and tS_vrefint values
and notes
– Table 33: LSE oscillator characteristics (fLSE = 32.768
kHz) LSEDRV[1:0] values removed (see ref. manual)
– Table 49: ADC characteristics - tSTAB defined relative
to clock frequency; notes 3. and 4. added
– Table 52: TS characteristics: removed the min. value
for tSTART
15-Jan-2015
07-Feb-2016
Changes
DocID027114 Rev 3
81/83
82
Revision history
STM32F070CB/RB/C6/F6
Table 64. Document revision history (continued)
Date
07-Feb-2016
82/83
Revision
3
Changes
– Figure 15 and Figure 16 improved
– Section 7: Package information name and structure
change
– Section 8: Ordering information renamed from Part
numbering; removed undue code sizes
DocID027114 Rev 3
STM32F070CB/RB/C6/F6
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2017 STMicroelectronics – All rights reserved
DocID027114 Rev 3
83/83
83
工商网监
湘ICP备2023018690号
