STM32F101ZGT6

STM32F101xF STM32F101xG XL-density access line, ARM®-based 32-bit MCU with 768 KB to 1 MB Flash, 15 timers, 1 ADC and 10 communication interfaces Datasheet - production data Features • Core: ARM® 32-bit Cortex®-M3 CPU with MPU – 36 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance – Single-cycle multiplication and hardware division • Memories – 768 Kbytes to 1 Mbyte of Flash memory (dual bank with read-while-write capability) – 80 Kbytes of SRAM – Flexible static memory controller with 4 Chip Select. Supports Compact Flash, SRAM, PSRAM, NOR and NAND memories – LCD parallel interface, 8080/6800 modes • Clock, reset and supply management – 2.0 to 3.6 V application supply and I/Os – POR, PDR, and programmable voltage detector (PVD) – 4-to-16 MHz crystal oscillator – Internal 8 MHz factory-trimmed RC – Internal 40 kHz RC with calibration capability – 32 kHz oscillator for RTC with calibration • Low power – Sleep, Stop and Standby modes – VBAT supply for RTC and backup registers LQFP144 20 × 20 mm LQFP100 14 × 14 mm LQFP64 10 × 10 mm – 51/80/112 I/Os, all mappable on 16 external interrupt vectors and almost all 5 V-tolerant • Debug mode – Serial wire debug (SWD) & JTAG interfaces – Cortex-M3 Embedded Trace Macrocell™ • Up to 15 timers – Up to ten 16-bit timers, with up to 4 IC/OC/PWM or pulse counters – 2 × watchdog timers (Independent and Window) – SysTick timer: a 24-bit downcounter – 2 × 16-bit basic timers to drive the DAC • Up to 10 communication interfaces – Up to 2 x I2C interfaces (SM7816 interface, LIN, IrDA capability, modem control) – Up to 3 SPIs (18 Mbit/s) • CRC calculation unit, 96-bit unique ID • ECOPACK® packages Table 1. Device summary • 1 x 12-bit, 1 µs A/D converters (up to 16 channels) – Conversion range: 0 to 3.6 V – Temperature sensor Reference STM32F101xF STM32F101RF STM32F101VF STM32F101ZF STM32F101xG STM32F101RG STM32F101VG STM32F101ZG • 2 × 12-bit D/A converters • DMA – 12-channel DMA controller – Peripherals supported: timers, ADC, DAC, SPIs, I2Cs and USARTs Part number • Up to 112 fast I/O ports December 2016 This is information on a product in full production. DocID16553 Rev 5 1/117 www.st.com Contents STM32F101xF, STM32F101xG Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2/117 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.2 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.1 ARM® Cortex®-M3 core with embedded Flash and SRAM . . . . . . . . . . 15 2.3.2 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.3 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.4 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 15 2.3.5 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.6 FSMC (flexible static memory controller) . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.7 LCD parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.8 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 16 2.3.9 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.10 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.11 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.12 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.13 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.14 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.15 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.16 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.17 RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 19 2.3.18 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.19 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.20 Universal synchronous/asynchronous receiver transmitters (USARTs) . 21 2.3.21 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.22 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.23 ADC (analog to digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.24 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.25 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.26 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.27 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DocID16553 Rev 5 STM32F101xF, STM32F101xG Contents 3 Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.1 6 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 39 5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 40 5.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.3.10 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.3.12 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 78 5.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.3.16 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5.3.17 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 5.3.18 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 5.3.19 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 5.3.20 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 DocID16553 Rev 5 3/117 4 Contents STM32F101xF, STM32F101xG 6.1 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6.2 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.3 LQFP64 information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 6.4.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 6.4.2 Evaluating the maximum junction temperature for an application . . . . 112 7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 4/117 DocID16553 Rev 5 STM32F101xF, STM32F101xG List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM32F101xF and STM32F101xG features and peripheral counts . . . . . . . . . . . . . . . . . 11 STM32F101xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 STM32F101xF and STM32F101xG timer feature comparison . . . . . . . . . . . . . . . . . . . . . . 19 STM32F101xF/STM32F101xG pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 40 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Maximum current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Maximum current consumption in Run mode, code with data processing running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 44 Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 44 Typical current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Typical current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . 47 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Low-speed user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . 58 Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . 59 Asynchronous multiplexed NOR/PSRAM read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Asynchronous multiplexed NOR/PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 67 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Switching characteristics for PC Card/CF read and write cycles in attribute/common space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Switching characteristics for PC Card/CF read and write cycles in I/O space . . . . . . . . . . 74 Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 DocID16553 Rev 5 5/117 6 List of tables Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. 6/117 STM32F101xF, STM32F101xG Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 SCL frequency (fPCLK1= 36 MHz, VDD = VDD_I2C = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . 88 STM32F10xxx SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 LQPF100 – 14 x 14 mm, 100-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package mechanical data . . . . . . . . 108 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 STM32F101xF and STM32F101xG ordering information scheme . . . . . . . . . . . . . . . . . . 113 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 DocID16553 Rev 5 STM32F101xF, STM32F101xG List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. STM32F101xF and STM32F101xG access line block diagram . . . . . . . . . . . . . . . . . . . . . 12 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 43 Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 43 Typical current consumption on VBAT with RTC on vs. temperature at different VBAT values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Typical current consumption in Standby mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . . 58 Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . . 59 Asynchronous multiplexed NOR/PSRAM read waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 60 Asynchronous multiplexed NOR/PSRAM write waveforms . . . . . . . . . . . . . . . . . . . . . . . . 62 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 67 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 PC Card/CompactFlash controller waveforms for common memory read access . . . . . . . 70 PC Card/CompactFlash controller waveforms for common memory write access . . . . . . . 70 PC Card/CompactFlash controller waveforms for attribute memory read access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 PC Card/CompactFlash controller waveforms for attribute memory write access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . . 72 PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . . 73 NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . . 75 NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . . 76 Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 DocID16553 Rev 5 7/117 8 List of figures Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. 8/117 STM32F101xF, STM32F101xG I2C bus AC waveforms and measurement circuit(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 SPI timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 SPI timing diagram - slave mode and CPHA=1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . . 96 Power supply and reference decoupling (VREF+ connected to VDDA) . . . . . . . . . . . . . . . 97 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline . . . . . . . . . . . . . . 101 LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 LQFP144 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 LQFP100 – 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . 105 LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 LQFP100 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 108 LQFP64 - 10 x 10 mm low-profile quad flat recommended footprint . . . . . . . . . . . . . . . . 109 LQFP64 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 LQFP64 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 DocID16553 Rev 5 STM32F101xF, STM32F101xG 1 Introduction Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F101xF and STM32F101xG XL-density access line microcontrollers. For more details on the whole STMicroelectronics STM32F101xx family, please refer to Section 2.2: Full compatibility throughout the family. The XL-density STM32F101xx datasheet should be read in conjunction with the STM32F10xxx reference manual. For information on programming, erasing and protection of the internal Flash memory please refer to the STM32F10xxx Flash programming manual. The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com. For information on the Cortex®-M3 core please refer to the Cortex®-M3 Technical Reference Manual, available from the www.arm.com website. DocID16553 Rev 5 9/117 Description 2 STM32F101xF, STM32F101xG Description The STM32F101xF and STM32F101xG access line family incorporates the highperformance ARM® Cortex®-M3 32-bit RISC core operating at a 36 MHz frequency, highspeed embedded memories (Flash memory up to 1 Mbyte and SRAM of 80 Kbytes), and an extensive range of enhanced I/Os and peripherals connected to two APB buses. All devices offer one 12-bit ADC, ten general-purpose 16-bit timers, as well as standard and advanced communication interfaces: up to two I2Cs, three SPIs and five USARTs. The STM32F101xx XL-density access line family operates in the –40 to +85 °C temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving mode allows the design of low-power applications. These features make the STM32F101xx XL-density access line microcontroller family suitable for a wide range of applications such as medical and handheld equipment, PC peripherals and gaming, GPS platforms, industrial applications, PLC, printers, scanners alarm systems , power meters, and video intercom. 10/117 DocID16553 Rev 5 STM32F101xF, STM32F101xG 2.1 Description Device overview The STM32F101xx XL-density access line family offers devices in 3 different package types: from 64 pins to 144 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. Figure 1 shows the general block diagram of the device family. Table 2. STM32F101xF and STM32F101xG features and peripheral counts Peripherals STM32F101Rx Flash memory 768 KB 1 MB STM32F101Vx 768 KB 1 MB STM32F101Zx 768 KB 1 MB SRAM in Kbytes 80 80 80 FSMC No Yes Yes Timers General-purpose 10 Basic 2 SPI Communication 2 I C interfaces USART GPIOs 3 2 5 51 80 12-bit ADC Number of channels 1 16 12-bit DAC Number of channels YES 2 CPU frequency 36 MHz Operating voltage Operating temperatures Package 112 2.0 to 3.6 V Ambient temperature: –40 to +85 °C (see Table 10) Junction temperature: –40 to +105 °C (see Table 10) LQFP64 LQFP100(1) LQFP144 1. For the LQFP100 package, only FSMC Bank1 and Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16- or 8-bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available in this package. DocID16553 Rev 5 11/117 Description STM32F101xF, STM32F101xG 37*4!' %4- 4RACETRIG 4RACE CONTROLLER 0BUS )BUS -05 #ORTEX -#05 &MAX-(Z $BUS 3YSTEM .6)# &LASH OBL INTERFACE .*4234 *4$) *4#+37#,+ *4-337$)/ *4$/ AS!& 40)5 "US MATRIX 42!#%#,+ 42!#%$;= AS!3 &LASH+BYTE BIT &LASH OBL INTERFACE Figure 1. STM32F101xF and STM32F101xG access line block diagram &LASH+BYTE BIT 6$$ 0/2 2ESET 2#-(Z '0$-! 2#K(Z CHANNELS 0,, '0$-! !;= $;= #,+ ./% .7% .%;= .",;= .7!)4 ., AS!& CHANNELS 2ESET CLOCK CONTROL )NT 0/20$2 6$$ 84!,/3#  -(Z 3TANDBY INTERFACE 84!, K(Z !(" !0" 4)- 0#;= '0)/PORT# 0$;= '0)/PORT$ 0%;= '0)/PORT% 0&;= '0)/PORT& 0';= '0)/PORT' CHANNELSAS!& 4)- CHANNELAS!& 4)- CHANNELAS!& 4)- -/3)-)3/3#+ .33AS!& 30) 2848#43243 AS!& 53!24 !0"&MAX-(Z '0)/PORT" !0"&MAX-(Z 0";= /3#?). /3#?/54 6 "!4 6TO 6 6"!4 %84)4 7+50 '0)/PORT! .234 6$$! 633! 06$ 24# "ACKUP REG !75 "ACK UPINTERFAC E 0!;= 633 )7$' 0#,+ 0#,+ (#,+ &#,+ &3-# !(" !0" !& 6OLTREG 6TO6 6$$! 3UPPLY SUPERVISION 6 $$! 32!+BYTE 6$$ 0OWER /3#?). /3#?/54 4!-0%2 24# !,!2-3%#/.$/54 CHANNELSAS!& 4)- CHANNELSAS!& 4)- CHANNELSAS!& 4)- CHANNELSAS!& 4)- CHANNELSAS!& 4)- CHANNELAS!& 4)- 53!24  53!24  CHANNELAS!& 2848#43243  #+AS!& 2848#43243  #+AS!& 5!24  2848AS!& 5!24  28 48AS!& 30) -/3)-)3/ 3#+.33AS!& 30) -/3)-)3/ 3#+.33AS!& )# 3#,3$!3-"!AS!& 77$' )# 3#,3$!3-"!AS!& 4)- )& BIT$!# )& BIT$!# 4EMPSENSOR !$#?).;= 6 2%&n 6 2%&  BIT!$# )& 4)- 6 $$! 6$$! $!#?/54AS!& $!#?/54AS!& 6 2%& AI 1. TA = –40 °C to +85 °C (junction temperature up to 105 °C). 2. AF = alternate function on I/O port pin. 12/117 DocID16553 Rev 5 STM32F101xF, STM32F101xG Description Figure 2. Clock tree &,)4&#,+ -(Z (3)2# (3) &3-##,+ 0ERIPHERALCLOCK ENABLE -(ZMAX  0,,32#  37 0,,-5, (3) X XXX 0,, 393#,+ !(" 0RESCALER -(Z  MAX 0,,#,+ !0" 0RESCALER  -(ZMAX 0#,+ TO!0" PERIPHERALS 0ERIPHERAL#LOCK %NABLE !0" 0RESCALER  0,,8402%  -(Z (3%/3# TO#ORTEX3YSTEMTIMER &#,+#ORTEX FREERUNNINGCLOCK 4)- )F!0"PRESCALER X ELSEX #33 /3#?).  /3#?/54 ,3%/3# K(Z TO4)- AND 4)-X#,+ 0ERIPHERAL#LOCK %NABLE -(ZMAX 0ERIPHERAL#LOCK %NABLE 4)- )F!0"PRESCALER X ELSEX  /3#?). TO&3-# (#,+ TO!("BUSCORE MEMORYAND$-! #LOCK %NABLE (3% /3#?/54 TO&LASHPROGRAMMING INTERFACE TO24# ,3% 24##,+ !$# 0RESCALER  0#,+ TO!0"PERIPHERALS TO4)-4)- AND4)- 4)-X#,+ 0ERIPHERAL#LOCK %NABLE TO!$# !$##,+ 24#3%,;= ,3)2# K(Z TOINDEPENDENTWATCHDOG)7$' ,3) )7$'#,+ -AIN #LOCK/UTPUT  -#/ 0,,#,+ ,EGEND (3%(IGHSPEEDEXTERNALCLOCKSIGNAL IG (3) (3) (IGHSPEEDINTERNALCLOCKSIGNAL (3% ,3) ,OWSPEEDINTERNALCLOCKSIGNAL 393#,+ ,3% ,OWSPEEDEXTERNALCLOCKSIGNAL -#/ AI 1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is 36 MHz. 2. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz or 28 MHz. DocID16553 Rev 5 13/117 Description 2.2 STM32F101xF, STM32F101xG Full compatibility throughout the family The STM32F101xx is a complete family whose members are fully pin-to-pin, software and feature compatible.In the reference manual, the STM32F101x4 and STM32F101x6 are identified as low-density devices, the STM32F101x8 and STM32F101xB are referred to as medium-density devices, the STM32F101xC, STM32F101xD and STM32F101xE are referred to as high-density devices, and the STM32F101xF and STM32F101xG are referred to as XL-density devices. Low-, high-density and XL-density devices are an extension of the STM32F101x8/B medium-density devices, they are specified in the STM32F101x4/6, STM32F101xC/D/E and STM32F101xF/G datasheets, respectively. Low-density devices feature lower Flash memory and RAM capacities, less timers and peripherals. High-density devices have higher Flash memory and RAM densities, and additional peripherals like FSMC and DAC. XL-density devices bring greater Flash and RAM capacities, and more features, namely an MPU, a higher number of timers and a dual bank Flash memory, while remaining fully compatible with the other members of the family. The STM32F101x4, STM32F101x6, STM32F101xC, STM32F101xD, STM32F101xE, STM32F101xF and STM32F101xG are a drop-in replacement for the STM32F101x8/B devices, allowing the user to try different memory densities and providing a greater degree of freedom during the development cycle. Moreover, the STM32F101xx access line family is fully compatible with all existing STM32F103xx performance line and STM32F102xx USB access line devices. Table 3. STM32F101xx family Memory size Low-density devices Pinout 16 KB Flash 32 KB Flash(1) Medium-density devices 64 KB Flash 128 KB Flash 4 KB RAM 6 KB RAM 10 KB RAM 16 KB RAM 144 100 64 2 × USARTs 2 × 16-bit timers 1 × SPI, 1 × I2C 1 × ADC 3 × USARTs 3 × 16-bit timers 2 × SPIs, 2 × I2Cs, 1 × ADC High-density devices XL-density devices 256 KB 384 KB 512 KB Flash Flash Flash 768 KB Flash 1 MB Flash 32 KB RAM 80 KB RAM 80 KB RAM 48 KB RAM 48 KB RAM 5 × USARTs 10 × 16-bit timers, 5 × USARTs 2 × basic timers 4 × 16-bit timers, 3 × SPIs, 2 × I2Cs, 2 × basic timers 1 × ADC, 1 × DAC 3 × SPIs, 2 × I2Cs, FSMC (100 and 144 1 × ADC, 1 × DAC pins), Cortex-M3 with FSMC (100 and 144 pins) MPU, Dual bank Flash memory 48 36 1. For orderable part numbers that do not show the A internal code after the temperature range code (6), the reference datasheet for electrical characteristics is that of the STM32F101x8/B medium-density devices. 14/117 DocID16553 Rev 5 STM32F101xF, STM32F101xG Description 2.3 Overview 2.3.1 ARM® Cortex®-M3 core with embedded Flash and SRAM The ARM® Cortex®-M3 processor is the latest generation of ARM® processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. The ARM® Cortex®-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM® core in the memory size usually associated with 8- and 16-bit devices. The STM32F101xF and STM32F101xG access line family having an embedded ARM® core, is therefore compatible with all ARM® tools and software. Figure 1 shows the general block diagram of the device family. 2.3.2 Memory protection unit The memory protection unit (MPU) is used to separate the processing of tasks from the data protection. The MPU can manage up to 8 protection areas that can all be further divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. The memory protection unit is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-time operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it. 2.3.3 Embedded Flash memory 768 Kbytes to 1 Mbyte of embedded Flash are available for storing programs and data. The Flash memory is organized as two banks. The first bank has a size of 512 Kbytes. The second bank is either 256 or 512 Kbytes depending on the device. This gives the device the capability of writing to one bank while executing code from the other bank (read-while-write capability). 2.3.4 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. DocID16553 Rev 5 15/117 Description 2.3.5 STM32F101xF, STM32F101xG Embedded SRAM 80 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states. 2.3.6 FSMC (flexible static memory controller) The FSMC is embedded in the STM32F101xF and STM32F101xG access line family. It has four Chip Select outputs supporting the following modes: PC Card/Compact Flash, SRAM, PSRAM, NOR and NAND. Functionality overview: 2.3.7 • The three FSMC interrupt lines are ORed in order to be connected to the NVIC • Write FIFO • Code execution from external memory except for NAND Flash and PC Card • The targeted frequency is HCLK/2, so external access is at 18 MHz when HCLK is at 36 MHz LCD parallel interface The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or highperformance solutions using external controllers with dedicated acceleration. 2.3.8 Nested vectored interrupt controller (NVIC) The STM32F101xF and STM32F101xG access line embeds a nested vectored interrupt controller able to handle up to 60 maskable interrupt channels (not including the 16 interrupt lines of Cortex®-M3) and 16 priority levels. • Closely coupled NVIC gives low-latency interrupt processing • Interrupt entry vector table address passed directly to the core • Closely coupled NVIC core interface • Allows early processing of interrupts • Processing of late arriving higher priority interrupts • Support for tail-chaining • Processor state automatically saved • Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimal interrupt latency. 2.3.9 External interrupt/event controller (EXTI) The external interrupt/event controller consists of 19 edge detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 112 GPIOs can be connected to the 16 external interrupt lines. 16/117 DocID16553 Rev 5 STM32F101xF, STM32F101xG 2.3.10 Description Clocks and startup System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock is available when necessary (for example with failure of an indirectly used external oscillator). Several prescalers are used to configure the AHB frequency, the high-speed APB (APB2) domain and the low-speed APB (APB1) domain. The maximum frequency of the AHB and APB domains is 36 MHz. See Figure 2 for details on the clock tree. 2.3.11 Boot modes At startup, boot pins are used to select one of three boot options: • Boot from user Flash: you have an option to boot from any of two memory banks. By default, boot from Flash memory bank 1 is selected. You can choose to boot from Flash memory bank 2 by setting a bit in the option bytes. • Boot from system memory • Boot from embedded SRAM The bootloader is located in system memory. It is used to reprogram the Flash memory by using USART1. 2.3.12 Power supply schemes • VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. Provided externally through VDD pins. • VSSA, VDDA = 2.0 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC or DAC is used). VDDA and VSSA must be connected to VDD and VSS, respectively. • VBAT = 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. For more details on how to connect power pins, refer to Figure 9: Power supply scheme. 2.3.13 Power supply supervisor The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an external reset circuit. The device features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to Table 12: Embedded reset and power control block characteristics for the values of VPOR/PDR and VPVD. DocID16553 Rev 5 17/117 Description 2.3.14 STM32F101xF, STM32F101xG Voltage regulator The regulator has three operation modes: main (MR), low power (LPR) and power down. • MR is used in the nominal regulation mode (Run) • LPR is used in the Stop modes. • Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost) This regulator is always enabled after reset. It is disabled in Standby mode. 2.3.15 Low-power modes The STM32F101xF and STM32F101xG access line supports three low-power modes to achieve the best compromise between low-power consumption, short startup time and available wakeup sources: • Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. • Stop mode Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode. The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output or the RTC alarm. • Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry. The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs. Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode. 2.3.16 DMA The flexible 12-channel general-purpose DMAs (7 channels for DMA1 and 5 channels for DMA2) are able to manage memory-to-memory, peripheral-to-memory and memory-toperipheral transfers. The two DMA controllers support circular buffer management, removing the need for user code intervention when the controller reaches the end of the buffer. Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent. DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose and basic timers TIMx, DAC and ADC. 18/117 DocID16553 Rev 5 STM32F101xF, STM32F101xG 2.3.17 Description RTC (real-time clock) and backup registers The RTC and the backup registers are supplied through a switch that takes power either on VDD supply when present or through the VBAT pin. The backup registers are forty-two 16-bit registers used to store 84 bytes of user application data when VDD power is not present. They are not reset by a system or power reset, and they are not reset when the device wakes up from the Standby mode. The real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power RC oscillator or the high speed external clock divided by 128. The internal low-speed RC has a typical frequency of 40 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation. The RTC features a 32-bit programmable counter for long term measurement using the Compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz. 2.3.18 Timers and watchdogs The XL-density STM32F101xx access line devices include up to ten general-purpose timers, two basic timers, two watchdog timers and a SysTick timer. Table 4: STM32F101xF and STM32F101xG timer feature comparison compares the features of the general-purpose and basic timers. Table 4. STM32F101xF and STM32F101xG timer feature comparison DMA Capture/compare Complementary request channels outputs generation Counter resolution Counter type Prescaler factor TIM2, TIM3, TIM4, TIM5 16-bit Up, down, up/down Any integer between 1 and 65536 Yes 4 No TIM9, TIM12 16-bit Up Any integer between 1 and 65536 No 2 No TIM10, TIM11, TIM13, TIM14 16-bit Up Any integer between 1 and 65536 No 1 No TIM6, TIM7 16-bit Up Any integer between 1 and 65536 Yes 0 No Timer General-purpose timers (TIMx) There are 10 synchronizable general-purpose timers embedded in the STM32F101xF and STM32F101xG XL-density access line devices (see Table 4 for differences). • TIM2, TIM3, TIM4, TIM5 There are up to 4 synchronizable general-purpose timers (TIM2, TIM3, TIM4 and TIM5) embedded in the STM32F101xF and STM32F101xG access line devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input capture/output compare, PWM or DocID16553 Rev 5 19/117 Description STM32F101xF, STM32F101xG one-pulse mode output. This gives up to 16 input captures / output compares / PWMs on the largest packages. Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs. They all have independent DMA request generation. These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. • TIM10, TIM11 and TIM9 These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM10 and TIM11 feature one independent channel, whereas TIM9 has two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be used as simple time bases. • TIM13, TIM14 and TIM12 These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM13 and TIM14 feature one independent channel, whereas TIM12 has two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be used as simple time bases. Basic timers TIM6 and TIM7 These timers are mainly used for DAC trigger generation. They can also be used as a generic 16-bit time base. Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode. Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features: 20/117 • A 24-bit down counter • Autoreload capability • Maskable system interrupt generation when the counter reaches 0. • Programmable clock source DocID16553 Rev 5 STM32F101xF, STM32F101xG 2.3.19 Description I²C bus Up to two I²C bus interfaces can operate in multi-master and slave modes. They support standard and fast modes. They support 7/10-bit addressing mode and 7-bit dual addressing mode (as slave). A hardware CRC generation/verification is embedded. They can be served by DMA and they support SMBus 2.0/PMBus. 2.3.20 Universal synchronous/asynchronous receiver transmitters (USARTs) The STM32F101xF and STM32F101xG access line embeds three universal synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3) and two universal asynchronous receiver transmitters (UART4 and UART5). These five interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. The five interfaces are able to communicate at speeds of up to 2.25 Mbit/s. USART1, USART2 and USART3 also provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller except for UART5. 2.3.21 Serial peripheral interface (SPI) Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the DMA controller. 2.3.22 GPIOs (general-purpose inputs/outputs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high currentcapable. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. 2.3.23 ADC (analog to digital converter) A 12-bit analog-to-digital converter is embedded into STM32F101xF and STM32F101xG access line devices. It has up to 16 external channels, performing conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs. The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. DocID16553 Rev 5 21/117 Description STM32F101xF, STM32F101xG The events generated by the general-purpose timers (TIMx) can be internally connected to the ADC start trigger and injection trigger, respectively, to allow the application to synchronize A/D conversion and timers. 2.3.24 DAC (digital-to-analog converter) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration. This dual digital Interface supports the following features: • two DAC converters: one for each output channel • 8-bit or 12-bit monotonic output • left or right data alignment in 12-bit mode • synchronized update capability • noise-wave generation • triangular-wave generation • dual DAC channel independent or simultaneous conversions • DMA capability for each channel • external triggers for conversion • input voltage reference VREF+ Seven DAC trigger inputs are used in the STM32F101xF and STM32F101xG access line family. The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels. 2.3.25 Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value. 2.3.26 Serial wire JTAG debug port (SWJ-DP) The ARM® SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 2.3.27 Embedded Trace Macrocell™ The ARM® Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F10xxx through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. TPA hardware is commercially available from common development tool vendors. It operates with third party debugger software tools. 22/117 DocID16553 Rev 5 STM32F101xF, STM32F101xG 3 Pinouts and pin descriptions Pinouts and pin descriptions                                     6$$? 633? 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0' 6$$? 633? 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$? 633? 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0!  0!  Figure 3. LQFP144 pinout                                     ,1&0                                     6$$? 633? .# 0!  0!  0!  0!  0!  0!  0# 0# 0# 0# 6$$? 633? 0' 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$? 633? 0$ 0$ 0$ 0$ 0$ 0$ 0" 0" 0" 0" 633? 6$$? 0& 0& 0& 0' 0' 0% 0% 0% 633? 6$$? 0% 0% 0% 0% 0% 0% 0" 0" 633? 6$$? 0!  633? 6$$? 0!  0!  0!  0!  0# 0# 0" 0" 0" 0& 0&                                     0% 0% 0% 0% 0% 6"!4 0# 4!-0%2 24# 0# /3#?). 0# /3#?/54 0& 0& 0& 0& 0& 0& 633? 6$$? 0& 0& 0& 0& 0& /3#?). /3#?/54 .234 0# 0# 0# 0# 633! 62%& 62%& 6$$! 0!  7+50 0!  0!  AI 1. The above figure shows the package top view. DocID16553 Rev 5 23/117 Pinouts and pin descriptions STM32F101xF, STM32F101xG                          6$$? 633? 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! Figure 4. LQFP100 pinout                          ,1&0                          6$$? 633? .# 0! 0! 0! 0! 0! 0! 0# 0# 0# 0# 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0" 0" 0" 0" 0! 633? 6$$? 0! 0! 0! 0! 0# 0# 0" 0" 0" 0% 0% 0% 0% 0% 0% 0% 0% 0% 0" 0" 633? 6$$?                          0% 0% 0% 0% 0% 6"!4 0# 4!-0%2 24# 0# /3#?). 0# /3#?/54 633? 6$$? /3#?). /3#?/54 .234 0# 0# 0# 0# 633! 62%& 62%& 6$$! 0! 7+50 0! 0! AI 1. The above figure shows the package top view. 24/117 DocID16553 Rev 5 STM32F101xF, STM32F101xG Pinouts and pin descriptions sͺϯ s^^ͺϯ W ϵ W ϴ KK d Ϭ W ϳ W ϲ W ϱ W ϰ W ϯ WϮ WϭϮ Wϭϭ WϭϬ W ϭϱ W ϭϰ Figure 5. LQFP64 pinout ϲϰ ϲϯ ϲϮ ϲϭ ϲϬ ϱϵ ϱϴ ϱϳ ϱϲ ϱϱ ϱϰ ϱϯ ϱϮ ϱϭ ϱϬ ϰϵ ϰϴ ϭ ϰϳ Ϯ ϰϲ ϯ ϰϱ ϰ ϰϰ ϱ ϰϯ ϲ ϰϮ ϳ ϰϭ ϴ >Y&Wϲϰ ϰϬ ϵ ϯϵ ϭϬ ϯϴ ϭϭ ϯϳ ϭϮ ϯϲ ϭϯ ϯϱ ϭϰ ϯϰ ϭϱ ϯϯ ϭϲ ϭϳ ϭϴ ϭϵ ϮϬ Ϯϭ ϮϮ Ϯϯ Ϯϰ Ϯϱ Ϯϲ Ϯϳ Ϯϴ Ϯϵ ϯϬ ϯϭ ϯϮ sͺϮ s ^^ͺϮ W ϭϯ W ϭϮ W ϭϭ W ϭϬ W ϵ W ϴ Wϵ Wϴ Wϳ Wϲ W ϭϱ W ϭϰ W ϭϯ W ϭϮ W ϯ s ^^ͺϰ sͺϰ W ϰ W ϱ W ϲ W ϳ Wϰ Wϱ W Ϭ W ϭ W Ϯ Wϭ Ϭ Wϭ ϭ s ^^ͺϭ sͺϭ sd WϭϯͲdDWZͲZd W ϭϰͲK ^ ϯϮͺ/E W ϭϱͲK ^ ϯϮͺKh d W  ϬͲK^ ͺ/E W  ϭͲK^ ͺKhd EZ^d WϬ Wϭ WϮ Wϯ s^^ s W ϬͲt< hW W ϭ W Ϯ DL 1. The above figure shows the package top view. Table 5. STM32F101xF/STM32F101xG pin definitions Alternate functions(4) I / O level(2) Remap LQFP100 Default LQFP64 Main function(3) (after reset) LQFP144 Type(1) Pins Pin name 1 - 1 PE2 I/O FT PE2 TRACECLK / FSMC_A23 - 2 - 2 PE3 I/O FT PE3 TRACED0 / FSMC_A19 - 3 - 3 PE4 I/O FT PE4 TRACED1 / FSMC_A20 - 4 - 4 PE5 I/O FT PE5 TRACED2 / FSMC_A21 TIM9_CH1 5 - 5 PE6 I/O FT PE6 TRACED3 / FSMC_A22 TIM9_CH2 6 1 6 VBAT - VBAT - - 7 2 7 - PC13(6) TAMPER-RTC - - PC14(6) OSC32_IN - - PC15(6) OSC32_OUT - 8 3 S PC13-TAMPER-RTC(5) I/O 8 PC14-OSC32_IN(5) I/O 9 4 9 PC15-OSC32_OUT(5) 10 - - PF0 I/O FT PF0 FSMC_A0 - 11 - - PF1 I/O FT PF1 FSMC_A1 - I/O DocID16553 Rev 5 25/117 Pinouts and pin descriptions STM32F101xF, STM32F101xG Table 5. STM32F101xF/STM32F101xG pin definitions (continued) Alternate functions(4) I / O level(2) Remap LQFP100 Default LQFP64 Main function(3) (after reset) LQFP144 Type(1) Pins Pin name 12 - - PF2 I/O FT PF2 FSMC_A2 - 13 - - PF3 I/O FT PF3 FSMC_A3 - 14 - - PF4 I/O FT PF4 FSMC_A4 - 15 - - PF5 I/O FT PF5 FSMC_A5 - 16 - 10 VSS_5 S - VSS_5 - - 17 - 11 VDD_5 S - VDD_5 - - 18 - - PF6 I/O - PF6 FSMC_NIORD TIM10_CH1 19 - - PF7 I/O - PF7 FSMC_NREG TIM11_CH1 20 - - PF8 I/O - PF8 FSMC_NIOWR TIM13_CH1 21 - - PF9 I/O - PF9 FSMC_CD TIM14_CH1 22 - - PF10 I/O - PF10 FSMC_INTR - 23 5 12 OSC_IN I - OSC_IN - PD0(7) 24 6 13 OSC_OUT O - OSC_OUT - PD1(7) 25 7 14 NRST I/O - NRST - - 26 8 15 PC0 I/O - PC0 ADC_IN10 - 27 9 16 PC1 I/O - PC1 ADC_IN11 - 28 10 17 PC2 I/O - PC2 ADC_IN12 - 29 11 18 PC3 I/O - PC3 ADC_IN13 - 30 12 19 VSSA S - VSSA - - 31 - 20 VREF- S - VREF- - - 32 - 21 VREF+ S - VREF+ - - 33 13 22 VDDA S - VDDA - - USART2_CTS(8)/ 34 14 23 PA0-WKUP I/O - PA0 WKUP/ ADC_IN0 / TIM5_CH1/ TIM2_CH1_ETR(8) - 35 15 24 PA1 I/O - PA1 USART2_RTS(8)/ ADC_IN1 / TIM5_CH2 TIM2_CH2(8) - 36 16 25 PA2 I/O - PA2 USART2_TX(8)/ TIM5_CH3 / ADC_IN2/ TIM2_CH3(8) / TIM9_CH1 - 26/117 DocID16553 Rev 5 STM32F101xF, STM32F101xG Pinouts and pin descriptions Table 5. STM32F101xF/STM32F101xG pin definitions (continued) Alternate functions(4) I / O level(2) Pin name Type(1) LQFP100 LQFP64 LQFP144 Pins Main function(3) (after reset) Default Remap - 37 17 26 PA3 I/O - PA3 USART2_RX(8) / TIM5_CH4/ ADC_IN3 / TIM2_CH4(8)/ TIM9_CH2 38 18 27 VSS_4 S - VSS_4 - - 39 19 28 VDD_4 S - VDD_4 - - 40 20 29 PA4 I/O - PA4 SPI1_NSS/ DAC_OUT1 / ADC_IN4 / USART2_CK(8) - 41 21 30 PA5 I/O - PA5 SPI1_SCK / DAC_OUT2 / ADC_IN5 - 42 22 31 PA6 I/O - PA6 SPI1_MISO / ADC_IN6 / TIM3_CH1(8) / TIM13_CH1 - 43 23 32 PA7 I/O - PA7 SPI1_MOSI / ADC_IN7 / TIM3_CH2(8)/ TIM14_CH1 - 44 24 33 PC4 I/O - PC4 ADC_IN14 - 45 25 34 PC5 I/O - PC5 ADC_IN15 - 46 26 35 PB0 I/O - PB0 ADC_IN8 / TIM3_CH3(8) - PB1 TIM3_CH4(8) - 47 27 36 PB1 I/O 48 28 37 PB2 I/O FT PB2/BOOT1 - - 49 - - PF11 I/O FT PF11 FSMC_NIOS16 - 50 - - PF12 I/O FT PF12 FSMC_A6 - 51 - - VSS_6 S - VSS_6 - - 52 - - VDD_6 S - VDD_6 - - 53 - - PF13 I/O FT PF13 FSMC_A7 - 54 - - PF14 I/O FT PF14 FSMC_A8 - 55 - - PF15 I/O FT PF15 FSMC_A9 - 56 - - PG0 I/O FT PG0 FSMC_A10 - 57 - - PG1 I/O FT PG1 FSMC_A11 - 58 - 38 PE7 I/O FT PE7 FSMC_D4 - 59 - 39 PE8 I/O FT PE8 FSMC_D5 - 60 - 40 PE9 I/O FT PE9 FSMC_D6 - 61 - - VSS_7 VSS_7 - - S - - ADC_IN9 / DocID16553 Rev 5 27/117 Pinouts and pin descriptions STM32F101xF, STM32F101xG Table 5. STM32F101xF/STM32F101xG pin definitions (continued) Alternate functions(4) I / O level(2) - VDD_7 LQFP100 S LQFP64 Main function(3) (after reset) LQFP144 Type(1) Pins Pin name 62 - - VDD_7 63 - 41 PE10 I/O FT PE10 FSMC_D7 - 64 - 42 PE11 I/O FT PE11 FSMC_D8 - 65 - 43 PE12 I/O FT PE12 FSMC_D9 - 66 - 44 PE13 I/O FT PE13 FSMC_D10 - 67 - 45 PE14 I/O FT PE14 FSMC_D11 - 68 - 46 PE15 I/O FT PE15 FSMC_D12 - 69 29 47 PB10 I/O FT PB10 I2C2_SCL / USART3_TX(8) TIM2_CH3 PB11 USART3_RX(8) TIM2_CH4 Remap - - 70 30 48 PB11 71 31 49 VSS_1 S - VSS_1 - - 72 32 50 VDD_1 S - VDD_1 - - 73 33 51 PB12 I/O FT PB12 SPI2_NSS(8) / I2C2_SMBA / USART3_CK(8) - 74 34 52 PB13 I/O FT PB13 SPI2_SCK(8) / USART3_CTS(8) - 75 35 53 PB14 I/O FT PB14 SPI2_MISO(8) / USART3_RTS(8) / TIM12_CH1 - 76 36 54 PB15 I/O FT PB15 SPI2_MOSI(8) / TIM12_CH2 - 77 - 55 PD8 I/O FT PD8 FSMC_D13 USART3_TX 78 - 56 PD9 I/O FT PD9 FSMC_D14 USART3_RX 79 - 57 PD10 I/O FT PD10 FSMC_D15 USART3_CK 80 - 58 PD11 I/O FT PD11 FSMC_A16 USART3_CTS 81 - 59 PD12 I/O FT PD12 FSMC_A17 TIM4_CH1 / USART3_RTS 82 - 60 PD13 I/O FT PD13 FSMC_A18 TIM4_CH2 83 - - VSS_8 S - VSS_8 - - 84 - - VDD_8 S - VDD_8 - - 85 - 61 PD14 I/O FT PD14 FSMC_D0 TIM4_CH3 86 - 62 PD15 I/O FT PD15 FSMC_D1 TIM4_CH4 87 - - PG2 I/O FT PG2 FSMC_A12 - 28/117 I/O FT Default I2C2_SDA / DocID16553 Rev 5 STM32F101xF, STM32F101xG Pinouts and pin descriptions Table 5. STM32F101xF/STM32F101xG pin definitions (continued) Alternate functions(4) I / O level(2) Remap LQFP100 Default LQFP64 Main function(3) (after reset) LQFP144 Type(1) Pins Pin name 88 - - PG3 I/O FT PG3 FSMC_A13 - 89 - - PG4 I/O FT PG4 FSMC_A14 - 90 - - PG5 I/O FT PG5 FSMC_A15 - 91 - - PG6 I/O FT PG6 FSMC_INT2 - 92 - - PG7 I/O FT PG7 FSMC_INT3 - 93 - - PG8 I/O FT PG8 - - 94 - - VSS_9 S - VSS_9 - - 95 - - VDD_9 S - VDD_9 - - 96 37 63 PC6 I/O FT PC6 - TIM3_CH1 97 38 64 PC7 I/O FT PC7 - TIM3_CH2 98 39 65 PC8 I/O FT PC8 - TIM3_CH3 99 40 66 PC9 I/O FT PC9 - TIM3_CH4 100 41 67 PA8 I/O FT PA8 USART1_CK / MCO - PA9 USART1_TX(8) - 101 42 68 PA9 I/O FT 102 43 69 PA10 I/O FT PA10 USART1_RX(8) 103 44 70 PA11 I/O FT PA11 USART1_CTS - 104 45 71 PA12 I/O FT PA12 USART1_RTS - 105 46 72 PA13 I/O FT JTMS-SWDIO - PA13 106 - 73 Not connected 107 47 74 VSS_2 S - VSS_2 - - 108 48 75 VDD_2 S - VDD_2 - - 109 49 76 PA14 I/O FT JTCKSWCLK - PA14 110 50 77 PA15 I/O FT JTDI SPI3_NSS TIM2_CH1_ETR/ PA15 /SPI1_NSS 111 51 78 PC10 I/O FT PC10 UART4_TX USART3_TX 112 52 79 PC11 I/O FT PC11 UART4_RX USART3_RX 113 53 80 PC12 I/O FT PC12 UART5_TX USART3_CK 114 - 81 PD0 I/O FT - FSMC_D2(9) - 115 - 82 PD1 I/O FT - FSMC_D3(9) - DocID16553 Rev 5 29/117 Pinouts and pin descriptions STM32F101xF, STM32F101xG Table 5. STM32F101xF/STM32F101xG pin definitions (continued) Alternate functions(4) I / O level(2) Pin name Type(1) LQFP100 LQFP64 LQFP144 Pins Main function(3) (after reset) Default Remap 116 54 83 PD2 I/O FT PD2 TIM3_ETR / UART5_RX - 117 - 84 PD3 I/O FT PD3 FSMC_CLK USART2_CTS 118 - 85 PD4 I/O FT PD4 FSMC_NOE USART2_RTS 119 - 86 PD5 I/O FT PD5 FSMC_NWE USART2_TX 120 - - VSS_10 S - VSS_10 - - 121 - - VDD_10 S - VDD_10 - - 122 - 87 PD6 I/O FT PD6 FSMC_NWAIT USART2_RX 123 - 88 PD7 I/O FT PD7 FSMC_NE1 / FSMC_NCE2 USART2_CK 124 - - PG9 I/O FT PG9 FSMC_NE2 / FSMC_NCE3 - 125 - - PG10 I/O FT PG10 FSMC_NE3 / FSMC_NCE4_1 - 126 - - PG11 I/O FT PG11 FSMC_NCE4_2 - 127 - - PG12 I/O FT PG12 FSMC_NE4 - 128 - - PG13 I/O FT PG13 FSMC_A24 - 129 - - PG14 I/O FT PG14 FSMC_A25 - 130 - - VSS_11 S - VSS_11 - - 131 - - VDD_11 S - VDD_11 - - 132 - - PG15 I/O FT PG15 - - 133 55 89 PB3 I/O FT JTDO SPI3_SCK TIM2_CH2 /PB3 TRACESWO SPI1_SCK 134 56 90 PB4 I/O FT NJTRST SPI3_MISO PB4 / TIM3_CH1 SPI1_MISO 135 57 91 PB5 I/O PB5 I2C1_SMBA/ SPI3_MOSI TIM3_CH2 / SPI1_MOSI 136 58 92 PB6 I/O FT PB6 I2C1_SCL / TIM4_CH1(8) USART1_TX 137 59 93 PB7 I/O FT PB7 I2C1_SDA / FSMC_NADV / TIM4_CH2(8) USART1_RX 138 60 94 BOOT0 - - 139 61 95 140 62 96 30/117 PB8 PB9 I - - I/O FT I/O FT BOOT0 PB8 PB9 TIM4_CH3 (8) / TIM10_CH1 I2C1_SCL TIM4_CH4 (8) / TIM11_CH1 I2C1_SDA DocID16553 Rev 5 STM32F101xF, STM32F101xG Pinouts and pin descriptions Table 5. STM32F101xF/STM32F101xG pin definitions (continued) Alternate functions(4) I / O level(2) Remap LQFP100 Default LQFP64 Main function(3) (after reset) LQFP144 Type(1) Pins Pin name 141 - 97 PE0 I/O FT PE0 TIM4_ETR(8) / FSMC_NBL0 - 142 - 98 PE1 I/O FT PE1 FSMC_NBL1 - 143 63 99 VSS_3 S - VSS_3 - - 144 64 100 VDD_3 S - VDD_3 - - 1. I = input, O = output, S = supply. 2. FT = 5 V tolerant. 3. Function availability depends on the chosen device. 4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register). 5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED). 6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 7. For the LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100 and LQFP144 packages, PD0 and PD1 are available by default, so there is no need for remapping. For more details, refer to Alternate function I/O and debug configuration section in the STM32F10xxx reference manual 8. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 9. For devices delivered in LQFP64 packages, the FSMC function is not available. DocID16553 Rev 5 31/117 Pinouts and pin descriptions STM32F101xF, STM32F101xG Table 6. FSMC pin definition FSMC Pins 32/117 LQFP100(1) CF CF/IDE NOR/PSRAM/ SRAM PE2 - - A23 A23 - Yes PE3 - - A19 A19 - Yes PE4 - - A20 A20 - Yes PE5 - - A21 A21 - Yes PE6 - - A22 A22 - Yes PF0 A0 A0 A0 - - - PF1 A1 A1 A1 - - - PF2 A2 A2 A2 - - - PF3 A3 - A3 - - - PF4 A4 - A4 - - - PF5 A5 - A5 - - - PF6 NIORD NIORD - - - - PF7 NREG NREG - - - - PF8 NIOWR NIOWR - - - - PF9 CD CD - - - - PF10 INTR INTR - - - - PF11 NIOS16 NIOS16 - - - - PF12 A6 - A6 - - - PF13 A7 - A7 - - - PF14 A8 - A8 - - - PF15 A9 - A9 - - - PG0 A10 - A10 - - - PG1 - - A11 - - - PE7 D4 D4 D4 DA4 D4 Yes PE8 D5 D5 D5 DA5 D5 Yes PE9 D6 D6 D6 DA6 D6 Yes PE10 D7 D7 D7 DA7 D7 Yes PE11 D8 D8 D8 DA8 D8 Yes PE12 D9 D9 D9 DA9 D9 Yes PE13 D10 D10 D10 DA10 D10 Yes PE14 D11 D11 D11 DA11 D11 Yes PE15 D12 D12 D12 DA12 D12 Yes PD8 D13 D13 D13 DA13 D13 Yes DocID16553 Rev 5 NOR/PSRAM Mux NAND 16 bit STM32F101xF, STM32F101xG Pinouts and pin descriptions Table 6. FSMC pin definition (continued) FSMC Pins LQFP100(1) CF CF/IDE NOR/PSRAM/ SRAM NOR/PSRAM Mux NAND 16 bit PD9 D14 D14 D14 DA14 D14 Yes PD10 D15 D15 D15 DA15 D15 Yes PD11 - - A16 A16 CLE Yes PD12 - - A17 A17 ALE Yes PD13 - - A18 A18 PD14 D0 D0 D0 DA0 D0 Yes PD15 D1 D1 D1 DA1 D1 Yes PG2 - - A12 - - - PG3 - - A13 - - - PG4 - - A14 - - - PG5 - - A15 - - - PG6 - - - - INT2 - PG7 - - - - INT3 - PD0 D2 D2 D2 DA2 D2 Yes PD1 D3 D3 D3 DA3 D3 Yes PD3 - - CLK CLK - Yes PD4 NOE NOE NOE NOE NOE Yes PD5 NWE NWE NWE NWE NWE Yes PD6 NWAIT NWAIT NWAIT NWAIT NWAIT Yes PD7 - - NE1 NE1 NCE2 Yes PG9 - - NE2 NE2 NCE3 - PG10 NCE4_1 NCE4_1 NE3 NE3 - - PG11 NCE4_2 NCE4_2 - - - - PG12 - - NE4 NE4 - - PG13 - - A24 A24 - - PG14 - - A25 A25 - - PB7 - - NADV NADV - Yes PE0 - - NBL0 NBL0 - Yes PE1 - - NBL1 NBL1 - Yes Yes 1. Ports F and G are not available in devices delivered in 100-pin packages. DocID16553 Rev 5 33/117 Memory mapping 4 STM32F101xF, STM32F101xG Memory mapping The memory map is shown in Figure 6. Figure 6. Memory map [)))))))) [( ['))))))) 0E\WH EORFN &RUWH[0 V LQWHUQDO SHULSKHUDOV 0E\WH EORFN 1RWXVHG [& [%))))))) 0E\WH EORFN )60&UHJLVWHU [$ [))))))) [ [))))))) [ [))))))) 0E\WH EORFN )60&EDQN EDQN 0E\WH EORFN )60&EDQN EDQN 0E\WH EORFN 3HULSKHUDOV [ [))))))) 0E\WH EORFN 65$0 [ [))))))) 0E\WH EORFN &RGH [ [))))))) [ 5HVHUYHG 65$0.%DOLDVHG E\ELWEDQGLQJ [[))) 2SWLRQ%\WHV 6\VWHPPHPRU\ 5HVHUYHG [))))[))))) [)))([)))))) [[)))'))) )ODVKPHPRU\EDQN .%RU.% [[))))) )ODVKPHPRU\EDQN [[)))) .% [[)))))) 5HVHUYHG $OLDVHGWR)ODVKRUV\VWHP [))))) PHPRU\GHSHQGLQJRQ [ %227SLQV 5HVHUYHG [$[%))))))) )60&UHJLVWHU [$[$))) )60&EDQN3&&$5' [[))))))) )60&EDQN1$1'1$1' [[))))))) )60&EDQN1$1'1$1' [[))))))) )60&EDQN125365$0 [&[))))))) )60&EDQN125365$0 [[%)))))) )60&EDQN125365$0 [[)))))) )60&EDQN125365$0 [[)))))) 5HVHUYHG [[))))))) &5& [[)) 5HVHUYHG [[))) )ODVKLQWHUIDFHV  [[)) 5HVHUYHG [[))) 5&& [[)) 5HVHUYHG [[))) '0$ [[)) '0$ [[)) 5HVHUYHG [[)))) 7,0 [[)) 7,0 [[)) 7,0 [&[))) 5HVHUYHG [&[%)) 86$57 [[%)) 5HVHUYHG [[)) 63, [[)) 5HVHUYHG [[))) $'& [[)) 3RUW* [[)) 3RUW) [&[))) 3RUW( [[%)) 3RUW' [[)) 3RUW& [[)) 3RUW% [&[))) 3RUW$ [[%)) (;7, [[)) $),2 [[)) 5HVHUYHG [[)))) '$& [[)) 3:5 [[)) %.3 [&[))) 5HVHUYHG [&[%)) ,& [[%)) ,& [[)) 8$57 [[)) 8$57 [&[))) 86$57 [[%)) 86$57 [[)) 5HVHUYHG [[)) 63, [&[))) 63, [[%)) 5HVHUYHG [[)) ,:'* [[)) ::'* [&[))) 57& [[%)) 5HVHUYHG [[)) 7,0 [[)) 7,0 [&[))) 7,0 7,0 [[)) 7,0 [[)) 7,0 [&[))) [[%)) 7,0 [[%)) 7,0 [[)) 7,0 [[)) DL 34/117 DocID16553 Rev 5 STM32F101xF, STM32F101xG Electrical characteristics 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3Σ). 5.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the 2 V ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2Σ). 5.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 7. DocID16553 Rev 5 35/117 Electrical characteristics 5.1.5 STM32F101xF, STM32F101xG Pin input voltage The input voltage measurement on a pin of the device is described in Figure 8. Figure 7. Pin loading conditions Figure 8. Pin input voltage 670)3,1 670)3,1 9,1 & S) DL DL 5.1.6 Power supply scheme Figure 9. Power supply scheme s d ĂĐŬƵƉĐŝƌĐƵŝƚƌLJ ;K^ϯϮ@ $GGUHVV WY%/B1( )60&B1%/>@ WK%/B1:( 1%/ WY'DWDB1( WK'DWDB1:( 'DWD )60&B'>@ W Y1$'9B1( WZ1$'9 )60&B1$'9 DL 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 32. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2) Symbol tw(NE) tv(NWE_NE) tw(NWE) th(NE_NWE) tv(A_NE) Parameter Min Max Unit FSMC_NE low time 3tHCLK + 0.5 3tHCLK + 1.5 ns FSMC_NEx low to FSMC_NWE low tHCLK + 0.5 tHCLK + 1.5 ns FSMC_NWE low time tHCLK – 0.5 tHCLK + 1 ns FSMC_NWE high to FSMC_NE high hold time tHCLK – 0.5 - ns - 0 ns tHCLK - ns - 1.5 ns tHCLK – 1.5 - ns - tHCLK ns FSMC_NEx low to FSMC_A valid th(A_NWE) Address hold time after FSMC_NWE high tv(BL_NE) FSMC_NEx low to FSMC_BL valid th(BL_NWE) FSMC_BL hold time after FSMC_NWE high tv(Data_NE) FSMC_NEx low to Data valid DocID16553 Rev 5 59/117 Electrical characteristics STM32F101xF, STM32F101xG Table 32. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2) Symbol Parameter Min Max Unit tHCLK - ns FSMC_NEx low to FSMC_NADV low - 0 ns FSMC_NADV low time - tHCLK + 1.5 ns th(Data_NWE) Data hold time after FSMC_NWE high tv(NADV_NE) tw(NADV) 1. CL = 15 pF. 2. Guaranteed by characterization results. Figure 21. Asynchronous multiplexed NOR/PSRAM read waveforms TW.% &3-#?.% TV./%?.% T H.%?./% &3-#?./% T W./% &3-#?.7% TV!?.% &3-#?!;= T H!?./% !DDRESS TV",?.% TH",?./% &3-#?.",;= .", TH$ATA?.% TSU$ATA?.% T V!?.% &3-#? !$;= TSU$ATA?./% !DDRESS T V.!$6?.% TH$ATA?./% $ATA TH!$?.!$6 TW.!$6 &3-#?.!$6 AIB Table 33. Asynchronous multiplexed NOR/PSRAM read timings(1)(2) Symbol Min Max Unit FSMC_NE low time 7tHCLK + 0.5 7tHCLK + 2 ns FSMC_NEx low to FSMC_NOE low 3tHCLK + 0.5 3tHCLK + 1.5 ns 4tHCLK – 1 4tHCLK + 1 ns 0.5 - ns - 0 ns tv(NADV_NE) FSMC_NEx low to FSMC_NADV low 0 1 ns FSMC_NADV low time tHCLK + 0.5 tHCLK + 2 ns tHCLK - ns tw(NE) tv(NOE_NE) tw(NOE) th(NE_NOE) tv(A_NE) tw(NADV) th(AD_NADV) 60/117 Parameter FSMC_NOE low time FSMC_NOE high to FSMC_NE high hold time FSMC_NEx low to FSMC_A valid FSMC_AD (address) valid hold time after FSMC_NADV high DocID16553 Rev 5 STM32F101xF, STM32F101xG Electrical characteristics Table 33. Asynchronous multiplexed NOR/PSRAM read timings(1)(2) (continued) Symbol Parameter th(A_NOE) Address hold time after FSMC_NOE high th(BL_NOE) FSMC_BL hold time after FSMC_NOE high Min Max Unit tHCLK -2 - ns 0.5 - ns tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 0 ns tsu(Data_NE) Data to FSMC_NEx high setup time 4tHCLK - 0.5 - ns 4tHCLK - 1 - ns Data hold time after FSMC_NEx high 0 - ns th(Data_NOE) Data hold time after FSMC_NOE high 0 - ns tsu(Data_NOE) Data to FSMC_NOE high setup time th(Data_NE) 1. CL = 15 pF. 2. Guaranteed by characterization results. DocID16553 Rev 5 61/117 Electrical characteristics STM32F101xF, STM32F101xG Figure 22. Asynchronous multiplexed NOR/PSRAM write waveforms WZ1( )60&B1([ )60&B12( WY1:(B1( WZ1:( W K1(B1:( )60&B1:( WK$B1:( WY$B1( )60&B$>@ $GGUHVV WY%/B1( WK%/B1:( )60&B1%/>@ 1%/ W Y$B1( )60&B$'>@ W Y'DWDB1$'9 $GGUHVV W Y1$'9B1( WK'DWDB1:( 'DWD WK$'B1$'9 WZ1$'9 )60&B1$'9 DL% Table 34. Asynchronous multiplexed NOR/PSRAM write timings(1)(2) Symbol Min Max Unit 5tHCLK + 0.5 5tHCLK + 2 ns tHCLK + 1 tHCLK + 1.5 ns 3tHCLK + 2 ns tHCLK - 0.5 - ns - 3.5 ns tv(NADV_NE) FSMC_NEx low to FSMC_NADV low 0 1 ns FSMC_NADV low time tHCLK + 0.5 tHCLK + 1.5 ns th(AD_NADV) FSMC_AD (address) valid hold time after FSMC_NADV high tHCLK – 0.5 - ns th(A_NWE) Address hold time after FSMC_NWE high 4tHCLK – 2 - ns tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 0.5 ns tHCLK – 1.5 - ns - tHCLK + 6 ns tHCLK – 0.5 - ns tw(NE) tv(NWE_NE) tw(NWE) th(NE_NWE) tv(A_NE) tw(NADV) th(BL_NWE) Parameter FSMC_NE low time FSMC_NEx low to FSMC_NWE low FSMC_NWE low time FSMC_NWE high to FSMC_NE high hold time FSMC_NEx low to FSMC_A valid FSMC_BL hold time after FSMC_NWE high tv(Data_NADV) FSMC_NADV high to Data valid th(Data_NWE) Data hold time after FSMC_NWE high 1. CL = 15 pF. 2. Guaranteed by characterization results. 62/117 DocID16553 Rev 5 3tHCLK – 1 STM32F101xF, STM32F101xG Electrical characteristics Synchronous waveforms and timings Figure 23 through Figure 26 represent synchronous waveforms and Table 36 through Table 38 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: • BurstAccessMode = FSMC_BurstAccessMode_Enable; • MemoryType = FSMC_MemoryType_CRAM; • WriteBurst = FSMC_WriteBurst_Enable; • CLKDivision = 1; (0 is not supported, see the STM32F10xxx reference manual) • DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM Figure 23. Synchronous multiplexed NOR/PSRAM read timings %867851  WZ&/. WZ&/. )60&B&/. 'DWDODWHQF\  WG&/./1([/ W G&/./1([+ )60&B1([ WG&/./1$'9/ WG&/./1$'9+ )60&B1$'9 WG&/./$,9 WG&/./$9 )60&B$>@ WG&/.+12(/ WG&/./12(+ )60&B12( WG&/./$'9 WG&/./$',9 WVX$'9&/.+ )60&B$'>@ $'>@ WK&/.+$'9 WVX$'9&/.+ ' WVX1:$,79&/.+ WK&/.+$'9 ' WK&/.+1:$,79 )60&B1:$,7 :$,7&)* E:$,732/E WVX1:$,79&/.+ WK&/.+1:$,79 )60&B1:$,7 :$,7&)* E:$,732/E WVX1:$,79&/.+ WK&/.+1:$,79 DLK DocID16553 Rev 5 63/117 Electrical characteristics STM32F101xF, STM32F101xG Table 35. Synchronous multiplexed NOR/PSRAM read timings(1)(2) Symbol tw(CLK) Parameter FSMC_CLK period Max Unit 55.5 - ns td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x = 0...2) - 0.5 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x = 0...2) 1 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 1 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 0.5 - ns - 0 ns 1.5 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x = 16...25) td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x = 16...25) td(CLKL-NOEL) FSMC_CLK low to FSMC_NOE low - 14 ns td(CLKL-NOEH) FSMC_CLK low to FSMC_NOE high 1 - ns td(CLKL-ADV) FSMC_CLK low to FSMC_AD[15:0] valid - 11 ns td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid 0.5 - ns tsu(ADV-CLKH) FSMC_A/D[15:0] valid data before FSMC_CLK high 2 - ns th(CLKH-ADV) FSMC_A/D[15:0] valid data after FSMC_CLK high 0 - ns tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high 8 - ns th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high 2 - ns 1. CL = 15 pF. 2. Guaranteed by characterization results. 64/117 Min DocID16553 Rev 5 STM32F101xF, STM32F101xG Electrical characteristics Figure 24. Synchronous multiplexed PSRAM write timings "53452. TW#,+ TW#,+ &3-#?#,+ $ATALATENCY TD#,+, .%X, TD#,+, .%X( &3-#?.%X TD#,+, .!$6, TD#,+, .!$6( &3-#?.!$6 TD#,+, !6 TD#,+, !)6 &3-#?!;= TD#,+, .7%, TD#,+, .7%( &3-#?.7% TD#,+, !$)6 TD#,+, !$6 &3-#?!$;= TD#,+, $ATA TD#,+, $ATA !$;= $ $ &3-#?.7!)4 7!)4#&'B7!)40/,B TSU.7!)46 #,+( TH#,+( .7!)46 TD#,+, .",( &3-#?.", AIG DocID16553 Rev 5 65/117 Electrical characteristics STM32F101xF, STM32F101xG Table 36. Synchronous multiplexed PSRAM write timings(1)(2) Symbol tw(CLK) Parameter FSMC_CLK period Max Unit 27.5 - ns td(CLKL-NExL) FSMC_CLK low to FSMC_Nex low (x = 0...2) - 0 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x = 0...2) 1 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 1 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 1 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x = 16...25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x = 16...25) 1 - ns td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low - 1 ns td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high 1.5 - ns td(CLKL-ADV) FSMC_CLK low to FSMC_AD[15:0] valid - 10 ns td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid 1 - ns td(CLKL-Data) FSMC_A/D[15:0] valid after FSMC_CLK low - 6 ns td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high 1 - ns tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high 7 - ns th(CLKH-NWAITV) 2 - ns FSMC_NWAIT valid after FSMC_CLK high 1. CL = 15 pF. 2. Guaranteed by characterization results. 66/117 Min DocID16553 Rev 5 STM32F101xF, STM32F101xG Electrical characteristics Figure 25. Synchronous non-multiplexed NOR/PSRAM read timings "53452. TW#,+ TW#,+ &3-#?#,+ TD#,+, .%X, TD#,+, .%X( $ATALATENCY &3-#?.%X TD#,+, .!$6, TD#,+, .!$6( &3-#?.!$6 TD#,+, !)6 TD#,+, !6 &3-#?!;= TD#,+( ./%, TD#,+, ./%( &3-#?./% TSU$6 #,+( TH#,+( $6 TSU$6 #,+( &3-#?$;= $ TSU.7!)46 #,+( TH#,+( $6 $ $ TH#,+( .7!)46 &3-#?.7!)4 7!)4#&'B7!)40/,B TSU.7!)46 #,+( T H#,+( .7!)46 &3-#?.7!)4 7!)4#&'B7!)40/,B TSU.7!)46 #,+( TH#,+( .7!)46 AIG Table 37. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2) Symbol tw(CLK) Parameter FSMC_CLK period Min Max Unit 27.6 - ns td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x = 0...2) - 1.5 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x = 0...2) 2 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 0.5 ns 1 - ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x = 0...25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x = 0...25) 2 - ns td(CLKL-NOEL) FSMC_CLK low to FSMC_NOE low - tHCLK + 1 ns td(CLKL-NOEH) FSMC_CLK low to FSMC_NOE high 1.5 - ns tsu(DV-CLKH) FSMC_D[15:0] valid data before FSMC_CLK high 3.5 - ns th(CLKH-DV) FSMC_D[15:0] valid data after FSMC_CLK high 0 - ns tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_SMCLK high 7 - ns th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high 2 - ns 1. CL = 15 pF. DocID16553 Rev 5 67/117 Electrical characteristics STM32F101xF, STM32F101xG 2. Guaranteed by characterization results. Figure 26. Synchronous non-multiplexed PSRAM write timings %867851  WZ&/. WZ&/. )60&B&/. 'DWDODWHQF\  WG&/./1([/ W G&/./1([+ )60&B1([ WG&/./1$'9/ WG&/./1$'9+ )60&B1$'9 WG&/./$,9 WG&/./$9 )60&B$>@ WG&/.+12(/ WG&/./12(+ )60&B12( WG&/./$'9 WG&/./$',9 WVX$'9&/.+ )60&B$'>@ $'>@ WK&/.+$'9 WVX$'9&/.+ ' WVX1:$,79&/.+ WK&/.+$'9 ' WK&/.+1:$,79 )60&B1:$,7 :$,7&)* E:$,732/E WVX1:$,79&/.+ WK&/.+1:$,79 )60&B1:$,7 :$,7&)* E:$,732/E WVX1:$,79&/.+ WK&/.+1:$,79 DLK Table 38. Synchronous non-multiplexed PSRAM write timings(1)(2) Symbol tw(CLK) 68/117 Parameter FSMC_CLK period Min Max Unit 27.6 - ns td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x = 0...2) - 0.5 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x = 0...2) 1.5 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 1 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 0.5 - ns - 0 ns 1.5 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x = 16...25) td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x = 16...25) td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low - 1 ns td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high 1.5 - ns - 2.5 ns 0.5 - ns td(CLKL-Data) FSMC_D[15:0] valid data after FSMC_CLK low td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high DocID16553 Rev 5 STM32F101xF, STM32F101xG Electrical characteristics Table 38. Synchronous non-multiplexed PSRAM write timings(1)(2) (continued) Symbol Parameter Min Max Unit tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high 7 - ns th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high 2 - ns 1. CL = 15 pF. 2. Guaranteed by characterization results. PC Card/CompactFlash controller waveforms and timings Figure 27 through Figure 32 represent synchronous waveforms and Table 40 and Table 41 provide the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: • COM.FSMC_SetupTime = 0x04; • COM.FSMC_WaitSetupTime = 0x07; • COM.FSMC_HoldSetupTime = 0x04; • COM.FSMC_HiZSetupTime = 0x00; • ATT.FSMC_SetupTime = 0x04; • ATT.FSMC_WaitSetupTime = 0x07; • ATT.FSMC_HoldSetupTime = 0x04; • ATT.FSMC_HiZSetupTime = 0x00; • IO.FSMC_SetupTime = 0x04; • IO.FSMC_WaitSetupTime = 0x07; • IO.FSMC_HoldSetupTime = 0x04; • IO.FSMC_HiZSetupTime = 0x00; • TCLRSetupTime = 0; • TARSetupTime = 0; DocID16553 Rev 5 69/117 Electrical characteristics STM32F101xF, STM32F101xG Figure 27. PC Card/CompactFlash controller waveforms for common memory read access )60&B1&(B )60&B1&(B WK1&([$, WY1&([$ )60&B$>@ WK1&([15(* WK1&([1,25' WK1&([1,2:5 WG15(*1&([ WG1,25'1&([ )60&B15(* )60&B1,2:5 )60&B1,25' )60&B1:( WG1&(B12( )60&B12( WZ12( WVX'12( WK12(' )60&B'>@ DLE 1. FSMC_NCE4_2 remains high (inactive during 8-bit access. Figure 28. PC Card/CompactFlash controller waveforms for common memory write access )60&B1&(B )60&B1&(B +LJK WY1&(B$ WK1&(B$, )60&B$>@ WK1&(B15(* WK1&(B1,25' WK1&(B1,2:5 WG15(*1&(B WG1,25'1&(B )60&B15(* )60&B1,2:5 )60&B1,25' WG1&(B1:( WZ1:( WG1:(1&(B )60&B1:( )60&B12( 0(0[+,=  WG'1:( WY1:(' WK1:(' )60&B'>@ DLE 70/117 DocID16553 Rev 5 STM32F101xF, STM32F101xG Electrical characteristics Figure 29. PC Card/CompactFlash controller waveforms for attribute memory read access )60&B1&(B WY1&(B$ WK1&(B$, )60&B1&(B +LJK )60&B$>@ )60&B1,2:5 )60&B1,25' WG15(*1&(B WK1&(B15(* )60&B15(* )60&B1:( WG1&(B12( WZ12( WG12(1&(B )60&B12( WVX'12( WK12(' )60&B'>@ DLE 1. Only data bits 0...7 are read (bits 8...15 are disregarded). DocID16553 Rev 5 71/117 Electrical characteristics STM32F101xF, STM32F101xG Figure 30. PC Card/CompactFlash controller waveforms for attribute memory write access )60&B1&(B )60&B1&(B +LJK WY1&(B$ WK1&(B$, )60&B$>@ )60&B1,2:5 )60&B1,25' WG15(*1&(B WK1&(B15(* )60&B15(* WG1&(B1:( WZ1:( )60&B1:( WG1:(1&(B )60&B12( WY1:(' )60&B'>@ DLE 1. Only data bits 0...7 are driven (bits 8...15 remains HiZ). Figure 31. PC Card/CompactFlash controller waveforms for I/O space read access )60&B1&(B )60&B1&(B WK1&(B$, WY1&([$ )60&B$>@ )60&B15(* )60&B1:( )60&B12( )60&B1,2:5 WZ1,25' WG1,25'1&(B )60&B1,25' WVX'1,25' WG1,25'' )60&B'>@ DL% 72/117 DocID16553 Rev 5 STM32F101xF, STM32F101xG Electrical characteristics Figure 32. PC Card/CompactFlash controller waveforms for I/O space write access )60&B1,2:5 WY1&([$ WK1&(B$, )60&B$>@ )60&B15(* )60&B1:( )60&B12( )60&B1,25' WG1&(B1,2:5 WZ1,2:5 )60&B1,2:5 $77[+,=  WY1,2:5' WK1,2:5' )60&B'>@ DLE Table 39. Switching characteristics for PC Card/CF read and write cycles in attribute/common space Symbol Parameter Min Max tv(NCEx-A) FSMC_NCEx low to FSMC_Ay valid - 0 th(NCEx-AI) FSMC_NCEx high to FSMC_Ax invalid 0 - td(NREG-NCEx) FSMC_NCEx low to FSMC_NREG valid - 2 th(NCEx-NREG) FSMC_NCEx high to FSMC_NREG invalid tHCLK + 4 - td(NCEx_NWE) FSMC_NCEx low to FSMC_NWE low - 5tHCLK + 1 td(NCEx_NOE) FSMC_NCEx low to FSMC_NOE low - 5tHCLK + 1 FSMC_NOE low width 8tHCLK - 0.5 8tHCLK + 1 FSMC_NOE high to FSMC_NCEx high 5tHCLK - 0.5 - 32 - tHCLK - 8tHCLK – 1 8tHCLK + 4 5tHCLK + 1.5 - tw(NOE) td(NOE-NCEx tsu(D-NOE) FSMC_D[15:0] valid data before FSMC_NOE high th(NOE-D) FSMC_NOE high to FSMC_D[15:0] invalid tw(NWE) FSMC_NWE low width td(NWE_NCEx) FSMC_NWE high to FSMC_NCEx high td(NCEx-NWE) FSMC_NCEx low to FSMC_NWE low - 5tHCLK + 1 tv(NWE-D) FSMC_NWE low to FSMC_D[15:0] valid - 0 th(NWE-D) FSMC_NWE high to FSMC_D[15:0] invalid 11tHCLK - td(D-NWE) FSMC_D[15:0] valid before FSMC_NWE high 13tHCLK + 2.5 - DocID16553 Rev 5 Unit ns 73/117 Electrical characteristics STM32F101xF, STM32F101xG Table 40. Switching characteristics for PC Card/CF read and write cycles in I/O space Symbol Parameter tw(NIOWR) FSMC_NIOWR low width tv(NIOWR-D) FSMC_NIOWR low to FSMC_D[15:0] valid th(NIOWR-D) FSMC_NIOWR high to FSMC_D[15:0] invalid Min Max Unit 8 THCLK - ns - 5 THCLK 4 ns 11THCLK 7 - ns td(NCE4_1-NIOWR) FSMC_NCE4_1 low to FSMC_NIOWR valid - 5THCLK + 1 ns th(NCEx-NIOWR) FSMC_NCEx high to FSMC_NIOWR invalid 5THCLK 2.5 - ns td(NIORD-NCEx) FSMC_NCEx low to FSMC_NIORD valid - 5THCLK 0.5 ns th(NCEx-NIORD) FSMC_NCEx high to FSMC_NIORD) valid 5 THCLK 0.5 - ns 8THCLK - ns tw(NIORD) FSMC_NIORD low width tsu(D-NIORD) FSMC_D[15:0] valid before FSMC_NIORD high 28 - ns td(NIORD-D) FSMC_D[15:0] valid after FSMC_NIORD high 3 - ns NAND controller waveforms and timings Figure 33 through Figure 36 represent synchronous waveforms and Table 40 and Table 41 provide the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: 74/117 • COM.FSMC_SetupTime = 0x00; • COM.FSMC_WaitSetupTime = 0x02; • COM.FSMC_HoldSetupTime = 0x02; • COM.FSMC_HiZSetupTime = 0x00; • ATT.FSMC_SetupTime = 0x01; • ATT.FSMC_WaitSetupTime = 0x02; • ATT.FSMC_HoldSetupTime = 0x01; • ATT.FSMC_HiZSetupTime = 0x00; • Bank = FSMC_Bank_NAND; • MemoryDataWidth = FSMC_MemoryDataWidth_16b; • ECC = FSMC_ECC_Enable; • ECCPageSize = FSMC_ECCPageSize_512Bytes; • TCLRSetupTime = 0; • TARSetupTime = 0; DocID16553 Rev 5 STM32F101xF, STM32F101xG Electrical characteristics Figure 33. NAND controller waveforms for read access )60&B1&([ /RZ $/()60&B$ &/()60&B$ )60&B1:( WK12($/( WG$/(12( )60&B12(15( WVX'12( WK12(' )60&B'>@ DLE Figure 34. NAND controller waveforms for write access )60&B1&([ /RZ $/()60&B$ &/()60&B$ WG$/(1:( WK1:($/( )60&B1:( )60&B12(15( WY1:(' WK1:(' )60&B'>@ DLE Figure 35. NAND controller waveforms for common memory read access )60&B1&([ /RZ $/()60&B$ &/()60&B$ WG$/(12( WK12($/( )60&B1:( WZ12( )60&B12( WVX'12( WK12(' )60&B'>@ DLE DocID16553 Rev 5 75/117 Electrical characteristics STM32F101xF, STM32F101xG Figure 36. NAND controller waveforms for common memory write access )60&B1&([ /RZ $/()60&B$ &/()60&B$ WG$/(1:( WZ1:( WK1:($/( )60&B1:( )60&B12( WG'1:( WY1:(' WK1:(' )60&B'>@ DLE Table 41. Switching characteristics for NAND Flash write cycles(1) Symbol tw(NWE) Parameter FSMC_NWE low width Min Max Unit 3tHCLK 3tHCLK ns - 0 ns tv(NWE-D) FSMC_NWE low to FSMC_D[15:0] valid th(NWE-D) FSMC_NWE high to FSMC_D[15:0] invalid 2tHCLK + 2 - ns td(ALE-NWE) FSMC_ALE valid before FSMC_NWE low - 3tHCLK + 1.5 ns th(NWE-ALE) FSMC_NWE high to FSMC_ALE invalid 3tHCLK + 8 - ns td(ALE-NOE) FSMC_ALE valid before FSMC_NOE low - 2tHCLK ns th(NOE-ALE) FSMC_NWE high to FSMC_ALE invalid 2tHCLK - ns 1. CL = 15 pF. 5.3.11 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (Electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports), the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: • Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. • FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. 76/117 DocID16553 Rev 5 STM32F101xF, STM32F101xG Electrical characteristics The test results are given in Table 42. They are based on the EMS levels and classes defined in application note AN1709. Table 42. EMS characteristics Symbol Parameter Conditions Level/Class VFESD VDD = 3.3 V, LQFP144, Voltage limits to be applied on any I/O pin to TA = +25 °C, fHCLK= 36 MHz induce a functional disturbance conforms to IEC 61000-4-2 2B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 3.3 V, LQFP144, TA = +25 °C, fHCLK = 36 MHz conforms to IEC 61000-4-4 4A Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and pre qualification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: • Corrupted program counter • Unexpected reset • Critical Data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device is monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading. Table 43. EMI characteristics Symbol Parameter SEMI Peak level Conditions Monitored frequency band 0.1 MHz to 30 MHz VDD = 3.3 V, TA = 25 °C, 30 MHz to 130 MHz LQFP144 package compliant with 130 MHz to 1 GHz IEC 61967-2 SAE EMI Level DocID16553 Rev 5 Max vs. [fHSE/fHCLK] Unit 8/36 MHz 8 27 dBµV 26 4 - 77/117 Electrical characteristics 5.3.12 STM32F101xF, STM32F101xG Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/JESD22-C101 standard. Table 44. ESD absolute maximum ratings Symbol Ratings Conditions Class Maximum value(1) VESD(HBM) Electrostatic discharge voltage (human body model) TA = +25 °C, conforming to JESD22-A114 2 2000 VESD(CDM) Electrostatic discharge TA = +25 °C, conforming to voltage (charge device model) JESD22-C101 III 500 Unit V 1. Guaranteed by characterization results. Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: • A supply overvoltage is applied to each power supply pin • A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78 IC latch-up standard. Table 45. Electrical sensitivities Symbol LU 5.3.13 Parameter Static latch-up class Conditions TA = +85 °C conforming to JESD78A Class II level A I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibilty to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (>5 LSB TUE), out of spec current injection on adjacent pins or other functional failure (for example reset, oscillator frequency deviation). 78/117 DocID16553 Rev 5 STM32F101xF, STM32F101xG Electrical characteristics The test results are given in Table 46 Table 46. I/O current injection susceptibility Functional susceptibility Symbol IINJ Description Negative injection Positive injection Injected current on OSC_IN32, OSC_OUT32, PA4, PA5, PC13 -0 +0 Injected current on all FT pins -5 +0 Injected current on any other pin -5 +5 DocID16553 Rev 5 Unit mA 79/117 Electrical characteristics 5.3.14 STM32F101xF, STM32F101xG I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 47 are derived from tests performed under the conditions summarized in Table 10. All I/Os are CMOS and TTL compliant. Table 47. I/O static characteristics Symbol VIL Parameter Standard IO input low level voltage IO FT(1) input low level voltage Conditions Min Typ Max Unit –0.3 - 0.28*(VDD-2 V)+0.8 V V –0.3 - 0.32*(VDD-2V)+0.75 V V 0.41*(VDD-2 V)+1.3 V - VDD+0.3 V 0.42*(VDD-2 V)+1 V - 200 - - mV 5% VDD(3) - - mV VSS ≤VIN ≤VDD Standard I/Os - - ±1 VIN = 5 V I/O FT - - 3 - Standard IO input high level voltage VIH Vhys IO FT(1) input high level voltage Standard IO Schmitt trigger voltage hysteresis(2) VDD > 2 V VDD ≤2 V Input leakage current (4) 5.2 V - IO FT Schmitt trigger voltage hysteresis(2) Ilkg 5.5 µA RPU Weak pull-up equivalent resistor(5) VIN = VSS 30 40 50 kΩ RPD Weak pull-down equivalent resistor(5) VIN = VDD 30 40 50 kΩ CIO I/O pin capacitance - - 5 - pF 1. FT = Five-volt tolerant. In order to sustain a voltage higher than VDD+0.3 the internal pull-up/pull-down resistors must be disabled. 2. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization results. 3. With a minimum of 100 mV. 4. Leakage could be higher than maximum value if negative current is injected on adjacent pins. 5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimum (~10% order). All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in Figure 37 and Figure 38 for standard I/Os, and in Figure 39 and Figure 40 for 5 V tolerant I/Os. 80/117 DocID16553 Rev 5 STM32F101xF, STM32F101xG Electrical characteristics Figure 37. Standard I/O input characteristics - CMOS port 6)(6),6  6   6 )( $$ 6 $$ ENT6 )( QUIREM NDARDRE -/3STA # 7)(MIN    7),MAX    6   6), $$ 6 MENT6 ), $$ RDREQUIRE #-/3STANDA  )NPUTRANGE NOTGUARANTEED           6$$6  AIB Figure 38. Standard I/O input characteristics - TTL port 6)(6),6 7)(MIN 44,REQUIREMENTS 6)( 6   6   6 )( $$ )NPUTRANGE NOTGUARANTEED   7),MAX    6 ),6 $$  44,REQUIREMENTS 6),6    6$$6 AI DocID16553 Rev 5 81/117 Electrical characteristics STM32F101xF, STM32F101xG Figure 39. 5 V tolerant I/O input characteristics - CMOS port 6)(6),6 6 $$ TS6 )( UIREMEN REQ TANDARD #-/3S             )NPUTRANGE NOTGUARANTEED    6 ),6 $$ T6 ),6 $$ REQUIRMEN /3STANDARD #-    6 )(6 $$   6$$6  6$$ AIB Figure 40. 5 V tolerant I/O input characteristics - TTL port 6)(6),6 44,REQUIREMENT6 )(6    6   6 )( $$ 7)(MIN 7),MAX  )NPUTRANGE NOTGUARANTEED   6 ), 6 $$   44,REQUIREMENTS6 ),6    6$$6 AI Output driving current The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source up to ± 20 mA (with a relaxedVOL/VOH) except PC13, PC14 and PC15 which can sink or source up to ±3 mA. When using the GPIOs PC13 to PC15 in output mode, the speed should not exceed 2 MHz with a maximum load of 30 pF. In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.2: 82/117 • The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 8). • The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 8). DocID16553 Rev 5 STM32F101xF, STM32F101xG Electrical characteristics Output voltage levels Unless otherwise specified, the parameters given in Table 48 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. All I/Os are CMOS and TTL compliant. Table 48. Output voltage characteristics Symbol VOL(1) VOH (3) VOL(1) VOH (3) VOL(1) VOH (3) VOL(1) VOH (3) Parameter Output Low level voltage for an I/O pin when 8 pins are sunk at the same time Output High level voltage for an I/O pin when 8 pins are sourced at the same time Output low level voltage for an I/O pin when 8 pins are sunk at the same time Output high level voltage for an I/O pin when 8 pins are sourced at the same time Output low level voltage for an I/O pin when 8 pins are sunk at the same time Output high level voltage for an I/O pin when 8 pins are sourced at the same time Output low level voltage for an I/O pin when 8 pins are sunk at the same time Output high level voltage for an I/O pin when 8 pins are sourced at the same time Conditions Min Max CMOS port(2), IIO = +8 mA, 2.7 V < VDD < 3.6 V - 0.4 TTL port(2) IIO = +8 mA 2.7 V < VDD < 3.6 V IIO = +20 mA(4) 2.7 V < VDD < 3.6 V IIO = +6 mA(4) 2 V < VDD < 2.7 V Unit V VDD–0.4 - - 0.4 V 2.4 - - 1.3 V VDD–1.3 - - 0.4 V VDD–0.4 - 1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 8 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52. 3. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 8 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. 4. Guaranteed by characterization results. DocID16553 Rev 5 83/117 Electrical characteristics STM32F101xF, STM32F101xG Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 41 and Table 49, respectively. Unless otherwise specified, the parameters given in Table 49 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. Table 49. I/O AC characteristics(1) MODEx [1:0] bit value(1) Symbol Parameter fmax(IO)out Maximum frequency(2) 10 tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time fmax(IO)out Maximum frequency(2) 01 tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time Fmax(IO)out Maximum 11 tf(IO)out tr(IO)out Frequency(2) Output high to low level fall time Conditions CL = 50 pF, VDD = 2 V to 3.6 V tEXTIpw 2 MHz CL = 50 pF, VDD = 2 V to 3.6 V ns (3) 125 CL= 50 pF, VDD = 2 V to 3.6 V 10 MHz 25(3) CL= 50 pF, VDD = 2 V to 3.6 V ns 25(3) CL= 30 pF, VDD = 2.7 V to 3.6 V 50 MHz CL = 50 pF, VDD = 2.7 V to 3.6 V 30 MHz CL = 50 pF, VDD = 2 V to 2.7 V 20 MHz CL = 30 pF, VDD = 2.7 V to 3.6 V 5(3) CL = 50 pF, VDD = 2.7 V to 3.6 V 8(3) CL = 50 pF, VDD = 2 V to 2.7 V 12(3) CL = 30 pF, VDD = 2.7 V to 3.6 V 5(3) Output low to high level rise CL = 50 pF, VDD = 2.7 V to 3.6 V time Pulse width of external signals detected by the EXTI controller Unit 125(3) CL = 50 pF, VDD = 2 V to 2.7 V - Max - ns 8(3) 12(3) 10 ns 1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a description of GPIO Port configuration register. 2. The maximum frequency is defined in Figure 41. 3. Guaranteed by design. 84/117 DocID16553 Rev 5 STM32F101xF, STM32F101xG Electrical characteristics Figure 41. I/O AC characteristics definition       (;7(51$/ 287387 21&/ WU,2RXW WI,2RXW 7 0D[LPXPIUHTXHQF\LVDFKLHYHGLIWUWI”7DQGLIWKHGXW\F\FOHLV ZKHQORDGHGE\&/VSHFLILHGLQWKHWDEOH³,2$&FKDUDFWHULVWLFV´  5.3.15 DLG NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 47). Unless otherwise specified, the parameters given in Table 50 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. Table 50. NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit VIL(NRST)(1) NRST Input low level voltage - –0.5 - 0.8 VIH(NRST)(1) NRST Input high level voltage - 2 - VDD+0.5 Vhys(NRST) NRST Schmitt trigger voltage hysteresis - - 200 - mV VIN = VSS 30 40 50 kΩ - - - 100 ns - 300 - - ns RPU VF(NRST)(1) Weak pull-up equivalent resistor(2) NRST Input filtered pulse VNF(NRST)(1) NRST Input not filtered pulse V 1. Guaranteed by design. 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order). DocID16553 Rev 5 85/117 Electrical characteristics STM32F101xF, STM32F101xG Figure 42. Recommended NRST pin protection ([WHUQDO UHVHWFLUFXLW 9'' 538 1567 ,QWHUQDOUHVHW )LOWHU —) 069 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 50. Otherwise the reset will not be taken into account by the device. 3. The external capacitor on NRST must be placed as close as possible to the device. 5.3.16 TIM timer characteristics The parameters given in Table 51 are guaranteed by design. Refer to Section 5.3.13: I/O current injection characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 51. TIMx(1) characteristics Symbol tres(TIM) fEXT ResTIM tCOUNTER Parameter Conditions Min Max Unit 1 - tTIMxCLK 27.8 - ns - 0 fTIMxCLK/2 MHz fTIMxCLK = 36 MHz 0 18 MHz Timer resolution - - 16 bit 16-bit counter clock period when internal clock is selected - 1 65536 tTIMxCLK 1820 µs Timer resolution time Timer external clock frequency on CH1 to CH4 tMAX_COUNT Maximum possible count fTIMxCLK = 36 MHz fTIMxCLK = 36 MHz 0.0278 - - 65536 × 65536 tTIMxCLK fTIMxCLK = 36 MHz - 119.2 s 1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3 and TIM4 timers. 86/117 DocID16553 Rev 5 STM32F101xF, STM32F101xG 5.3.17 Electrical characteristics Communications interfaces I2C interface characteristics The STM32F101xF and STM32F101xG access line I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 52. Refer also to Section 5.3.13: I/O current injection characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Table 52. I2C characteristics Symbol Parameter Standard mode I2C(1)(2) Fast mode I2C(1)(2) Unit Min Max Min Max tw(SCLL) SCL clock low time 4.7 - 1.3 - tw(SCLH) SCL clock high time 4.0 - 0.6 - tsu(SDA) SDA setup time 250 - 100 - th(SDA) SDA data hold time - 3450(3) - 900(3) tr(SDA) tr(SCL) SDA and SCL rise time - 1000 - 300 tf(SDA) tf(SCL) SDA and SCL fall time - 300 - 300 th(STA) Start condition hold time 4.0 - 0.6 - tsu(STA) Repeated Start condition setup time 4.7 - 0.6 - tsu(STO) Stop condition setup time 4.0 - 0.6 - µs tw(STO:STA) Stop to Start condition time (bus free) 4.7 - 1.3 - µs Cb Capacitive load for each bus line - 400 - 400 pF tSP Pulse width of the spikes that are suppressed by the analog filter for standard and fast mode 0 50(4) 0 50(4) μs µs ns µs 1. Guaranteed by design. 2. fPCLK1 must be at least 2 MHz to achieve standard mode I2C frequencies. It must be at least 4 MHz to achieve the fast mode I2C frequencies and it must be a multiple of 10 MHz in order to reach the I2C fast mode maximum clock speed of 400 kHz. 3. The maximum data hold time has only to be met if the interface does not stretch the low period of SCL signal. 4. The minimum width of the spikes filtered by the analog filter is above tSP(max). DocID16553 Rev 5 87/117 Electrical characteristics STM32F101xF, STM32F101xG Figure 43. I2C bus AC waveforms and measurement circuit(1) 9''B,& 9''B,& 53 53 670 56 6'$ ,ð&EXV 56 6&/ 67$575(3($7(' 67$57 67$57 WVX67$ 6'$ WI6'$ WU6'$ WK67$ WVX6'$ WK6'$ WZ6&// 6&/ WZ6&/+ WU6&/ WI6&/ WZ67267$ 6 723 WVX672 DLG 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. 1. RS = series protection resistor. 2. RP = external pull-up resistor. 3. VDD_I2C is the I2C bus power supply. Table 53. SCL frequency (fPCLK1= 36 MHz, VDD = VDD_I2C = 3.3 V)(1)(2) fSCL I2C_CCR value (kHz) RP = 4.7 kΩ 400 0x801E 300 0x8028 200 0x803C 100 0x00B4 50 0x0168 20 0x0384 1. RP = External pull-up resistance, fSCL = I2C speed. 2. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the tolerance on the achieved speed ±2%. These variations depend on the accuracy of the external components used to design the application. 88/117 DocID16553 Rev 5 STM32F101xF, STM32F101xG Electrical characteristics SPI interface characteristics Unless otherwise specified, the parameters given in Table 54Table 55 are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 10. Refer to Section 5.3.13: I/O current injection characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 54. STM32F10xxx SPI characteristics Symbol Parameter fSCK 1/tc(SCK) SPI clock frequency Min Max Master mode - 10 Slave mode - 10 SPI clock rise and fall time Capacitive load: C = 30 pF - 8 tsu(NSS)(1) NSS setup time Slave mode 4tPCLK - th(NSS)(1) NSS hold time Slave mode 73 - Master mode, fPCLK = 36 MHz, presc = 4 50 60 Master mode - SPI1 3 - Master mode - SPI2 5 - Slave mode 4 - Master mode - SPI1 4 - Data input hold time Master mode - SPI2 6 - Slave mode 5 - Slave mode, fPCLK = 36 MHz, presc = 4 0 55 Slave mode, fPCLK = 20 MHz - 4tPCLK Data output disable time Slave mode 10 - tv(SO) (1) Data output valid time Slave mode (after enable edge) - 25 tv(MO)(1) Data output valid time Master mode (after enable edge) - 6 Slave mode (after enable edge) 25 - Master mode (after enable edge) 6 - tr(SCK) tf(SCK) (1) tw(SCKH) SCK high and low tw(SCKL)(1) time tsu(MI) (1) tsu(SI)(1) th(MI) (1) th(SI) ta(SO) Data input setup time (1) (1)(2) tdis(SO)(1)(3) th(SO)(1) th(MO) (1) Data output access time Data output hold time Conditions Unit MHz ns 1. Guaranteed by characterization results. 2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z DocID16553 Rev 5 89/117 Electrical characteristics STM32F101xF, STM32F101xG Table 55. SPI characteristics Symbol fSCK 1/tc(SCK) Parameter Conditions SPI clock frequency Min Max Master mode - 18 Slave mode - 18 - 8 ns % tr(SCK) tf(SCK) SPI clock rise and fall time Capacitive load: C = 30 pF DuCy(SCK) SPI slave input clock duty cycle Slave mode 30 70 NSS setup time Slave mode 4tPCLK - NSS hold time Slave mode 2tPCLK - SCK high and low time Master mode, fPCLK = 36 MHz, presc = 4 50 60 Master mode 5 - Slave mode 5 - Master mode 5 - Slave mode 4 - tsu(NSS)(1) th(NSS) (1) tw(SCKH)(1) tw(SCKL)(1) tsu(MI) (1) tsu(SI)(1) th(MI) Data input setup time (1) th(SI)(1) Data input hold time ta(SO)(1)(2) Data output access time Slave mode, fPCLK = 20 MHz 0 3tPCLK tdis(SO)(1)(3) Data output disable time Slave mode 2 10 (1)(1) Data output valid time Slave mode (after enable edge) - 25 tv(MO)(1)(1) Data output valid time Master mode (after enable edge) - 5 Slave mode (after enable edge) 15 - Master mode (after enable edge) 2 - tv(SO) th(SO)(1) th(MO)(1) Data output hold time Unit MHz 1. Guaranteed by characterization results. 2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z 90/117 DocID16553 Rev 5 ns STM32F101xF, STM32F101xG Electrical characteristics Figure 44. SPI timing diagram - slave mode and CPHA=0 166LQSXW 6&.,QSXW W68166 &3+$  &32/  WK166 WF6&. WZ6&.+ WZ6&./ &3+$  &32/  W962 WD62 0,62 287387 WU6&. WI6&. WK62 06%287 %,7287 06%,1 %,7,1 WGLV62 /6%287 WVX6, 026, ,1387 /6%,1 WK6, DLF Figure 45. SPI timing diagram - slave mode and CPHA=1(1) 166LQSXW 6&.LQSXW W68166 &3+$  &32/  &3+$  &32/  WZ6&.+ WZ6&./ WK62 WY62 WD62 0,62 287387 06%287 %,7287 WU6&. WI6&. WGLV62 /6%287 WK6, WVX6, 026, ,1387 WK166 WF6&. 06%,1 %,7,1 /6%,1 DLE 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. DocID16553 Rev 5 91/117 Electrical characteristics STM32F101xF, STM32F101xG Figure 46. SPI timing diagram - master mode(1) +LJK 166LQSXW 6&.2XWSXW &3+$  &32/  6&.2XWSXW WF6&. &3+$  &32/  &3+$  &32/  &3+$  &32/  WVX0, 0,62 ,13 87 WZ6&.+ WZ6&./ WU6&. WI6&. %,7,1 06%,1 /6%,1 WK0, 026, 287387 06%287 % , 7287 WY02 /6%287 WK02 DLF 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. 5.3.18 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 56 are preliminary values derived from tests performed under ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 10. Note: 92/117 It is recommended to perform a calibration after each power-up. DocID16553 Rev 5 STM32F101xF, STM32F101xG Electrical characteristics Table 56. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA Power supply - 2.4 - 3.6 V VREF+ Positive reference voltage - 2.4 - VDDA V VREF- Negative reference voltage - - 0 - V IVREF Current on the VREF input pin - - 160 220(1) µA fADC ADC clock frequency - 0.6 - 14 MHz fS(2) Sampling rate - 0.05 - 1 MHz fADC = 14 MHz - - 823 kHz - - - 17 1/fADC - 0 (VSSA or VREFtied to ground) - VREF+ V See Equation 1 and Table 57 for details - - 50 kΩ - - - 1 kΩ - - - 8 pF fTRIG(2) VAIN RAIN(2) External trigger frequency Conversion voltage range(3) External input impedance RADC(2) Sampling switch resistance CADC(2) Internal sample and hold capacitor tCAL(2) Calibration time fADC = 14 MHz 5.9 µs - 83 1/fADC tlat(2) Injection trigger conversion latency fADC = 14 MHz - tlatr(2) Regular trigger conversion latency fADC = 14 MHz tS(2) Sampling time tSTAB(2) Power-up time tCONV(2) Total conversion time (including sampling time) - - 0.214 µs - - 3(4) 1/fADC - - 0.143 µs (4) 1/fADC - - - 2 fADC = 14 MHz 0.107 - 17.1 µs - 1.5 - 239.5 1/fADC - 0 0 1 µs fADC = 14 MHz 1 - 18 µs - 14 to 252 (tS for sampling +12.5 for 1/fADC successive approximation) 1. Guaranteed by characterization results. 2. Guaranteed by design. 3. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package. Refer to Section 3: Pinouts and pin descriptions for further details. 4. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 56. Equation 1: RAIN max formula: TS - – R ADC R AIN < --------------------------------------------------------------N+2 f ADC × C ADC × ln ( 2 ) DocID16553 Rev 5 93/117 Electrical characteristics STM32F101xF, STM32F101xG The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). Table 57. RAIN max for fADC = 14 MHz(1) Ts (cycles) tS (µs) RAIN max (kΩ) 1.5 0.11 0.4 7.5 0.54 5.9 13.5 0.96 11.4 28.5 2.04 25.2 41.5 2.96 37.2 55.5 3.96 50 71.5 5.11 NA 239.5 17.1 NA 1. Guaranteed by design. Table 58. ADC accuracy - limited test conditions(1)(2) Symbol Parameter ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error Test conditions Typ Max(3) fPCLK2 = 28 MHz, fADC = 14 MHz, RAIN < 10 kΩ, VDDA = 3 V to 3.6 V, TA = 25 °C Measurements made after ADC calibration VREF+ = VDDA ±1.3 ±2 ±1 ±1.5 ±0.5 ±1.5 ±0.7 ±1 ±0.8 ±1.5 Unit LSB 1. ADC DC accuracy values are measured after internal calibration. 2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 5.3.13 does not affect the ADC accuracy. 3. Guaranteed by characterization results. 94/117 DocID16553 Rev 5 STM32F101xF, STM32F101xG Electrical characteristics Table 59. ADC accuracy(1) (2)(3) Symbol Parameter Test conditions ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fPCLK2 = 28 MHz, fADC = 14 MHz, RAIN < 10 kΩ, VDDA = 2.4 V to 3.6 V Measurements made after ADC calibration Typ Max(4) ±2 ±5 ±1.5 ±2.5 ±1.5 ±3 ±1 ±2 ±1.5 ±3 Unit LSB 1. ADC DC accuracy values are measured after internal calibration. 2. Better performance could be achieved in restricted VDD, frequency, VREF and temperature ranges. 3. ADC accuracy vs. negative injection current: Injecting negative current on any of the standard (non-robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 5.3.13 does not affect the ADC accuracy. 4. Preliminary values. Figure 47. ADC accuracy characteristics 9''$ 95() RUGHSHQGLQJRQSDFNDJH >/6%,'($/    (*   ([DPSOHRIDQDFWX DOWUDQVIH UFXUYH 7KHLGHDOWUDQVIHUFX UYH (QGSRLQWFRUUHODWLRQOLQH  (7 7RWDOXQDGMXVWHG(UURUPD[LPXPGHYLDWLRQ EHWZHHQWKHDFWXDODQGWKHLGHDOWUDQVIHUFXUYHV (2 2IIVHW(UURUGHYLDWLRQEHWZHHQWKHILUVWDFWXDO WUDQVLWLRQDQGWKHODVWDFWXDORQH (* *DLQ(UURUGHYLDWLRQEHWZHHQWKHODVWLGHDO WUDQVLWLRQDQGWKHODVWDFWXDORQH (' 'LIIHUHQWLDO/LQHDULW\(UURUPD[LPXPGHYLDWLRQ EHWZHHQDFWXDOVWHSVDQGWKHLGHDORQH (/ ,QWHJUDO/LQHDULW\(UURUPD[LPXPGHYLDWLRQ EHWZHHQDQ\DFWXDOWUDQVLWLRQDQGWKHHQGSRLQW FRUUHODWLRQOLQH  (7      (2  (/  ('  /6%,'($/   966$            9''$ DLH DocID16553 Rev 5 95/117 Electrical characteristics STM32F101xF, STM32F101xG Figure 48. Typical connection diagram using the ADC 670)[[[ 9'' 5$,1 9$,1 6DPSOHDQGKROG$'& FRQYHUWHU 97 9 5$'& $,1[ 97 9 &SDUDVLWLF ,/“—$ ELW FRQYHUWHU &$'& DLG 1. Refer to Table 56 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. General PCB design guidelines Power supply decoupling should be performed as shown in Figure 49 or Figure 50, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 49. Power supply and reference decoupling (VREF+ not connected to VDDA) 670)[[[ 9 5() 6HHQRWH —)Q) 9 ''$ —)Q) 9 66$9 5() 6HHQRWH DLF 1. VREF+ and VREF- inputs are available only on 100-pin packages. 96/117 DocID16553 Rev 5 STM32F101xF, STM32F101xG Electrical characteristics Figure 50. Power supply and reference decoupling (VREF+ connected to VDDA) 34-&XXX 62%&6$$! 3EENOTE —&N& 62%&n633! 3EENOTE AIC 1. VREF+ and VREF- inputs are available only on 100-pin packages. 5.3.19 DAC electrical specifications Table 60. DAC characteristics Symbol Parameter Conditions Min Typ Max(1) Unit Comments VDDA Analog supply voltage 2.4 - 3.6 V - VREF+ Reference supply voltage 2.4 - 3.6 V VREF+ must always be below VDDA VSSA Ground 0 - 0 V - RLOAD connected to VSSA 5 - - RLOAD connected to VDDA 25 RLOAD(2) Resistive load with buffer ON DAC output buffer ON kΩ - - - RO(2) Impedance output with buffer OFF - - 15 When the buffer is OFF, the minimum resistive load kΩ between DAC_OUT and VSS to have a 1% accuracy is 1.5 MΩ CLOAD(2) Capacitive load - - 50 Maximum capacitive load at pF DAC_OUT pin (when the buffer is ON). DocID16553 Rev 5 97/117 Electrical characteristics STM32F101xF, STM32F101xG Table 60. DAC characteristics (continued) Symbol Typ Lower DAC_OUT DAC_OUT voltage with buffer (2) min ON 0.2 - - V Higher DAC_OUT DAC_OUT voltage with buffer max(2) ON - - VDDA – 0.2 V Lower DAC_OUT DAC_OUT voltage with buffer (2) min OFF - 0.5 - mV Higher DAC_OUT DAC_OUT voltage with buffer (2) max OFF - IDDA DNL(1) INL(1) Offset(1) Gain error(1) 98/117 DAC DC current consumption in quiescent mode (Standby mode) DAC DC current consumption in quiescent mode(3) Differential non linearity Difference between two consecutive code1LSB) Integral non linearity (difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023) Offset error (difference between measured value at Code (0x800) and the ideal value = VREF+/2) Gain error Conditions Max(1) Unit Min IDDVREF+ Parameter - VREF+ – 1LSB Comments It gives the maximum output excursion of the DAC. It corresponds to 12-bit input code (0x0E0) to (0xF1C) at VREF+ = 3.6 V and (0x155) and (0xEAB) at VREF+ = 2.4 V. It gives the maximum output excursion of the DAC. V - - 220 With no load, worst code (0xF1C) at VREF+ = 3.6 V in µA terms of DC consumption on the inputs. - - 380 µA With no load, worst code (0xF1C) at VREF+ = 3.6 V in µA terms of DC consumption on the inputs. With no load, middle code (0x800) on the inputs. - - 480 - - ±0.5 LSB Given for the DAC in 10-bit configuration. - - ±2 LSB Given for the DAC in 12-bit configuration. - - ±1 LSB Given for the DAC in 10-bit configuration. - - ±4 LSB Given for the DAC in 12-bit configuration. - - ±10 mV - - - ±3 LSB Given for the DAC in 10-bit at VREF+ = 3.6 V. - - ±12 LSB Given for the DAC in 12-bit at VREF+ = 3.6 V. - - ±0.5 % DocID16553 Rev 5 Given for the DAC in 12bit configuration. STM32F101xF, STM32F101xG Electrical characteristics Table 60. DAC characteristics (continued) Symbol Parameter Conditions Max(1) Unit Min Typ Settling time (full scale: for a 10-bit input code transition between the lowest tSETTLING and the highest input codes when DAC_OUT reaches final value ±1LSB - 3 4 µs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ Update rate(1) Max frequency for a correct DAC_OUT change when small variation in the input code (from code i to i+1LSB) - - 1 MS/s CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ tWAKEUP(1) Wakeup time from off state (Setting the ENx bit in the DAC Control register) - 6.5 10 CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ µs input code between lowest and highest possible ones. - –67 –40 dB No RLOAD, CLOAD = 50 pF Power supply rejection ratio (to PSRR+ (2) VDDA) (static DC measurement Comments 1. Preliminary values. 2. Guaranteed by design. 3. Quiescent mode refers to the state of the DAC when a steady value is kept on the output so that no dynamic consumption is involved. Figure 51. 12-bit buffered /non-buffered DAC %XIIHU 5/ '$&B287[ ELW GLJLWDOWR DQDORJ FRQYHUWHU &/ AI6 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. DocID16553 Rev 5 99/117 Electrical characteristics 5.3.20 STM32F101xF, STM32F101xG Temperature sensor characteristics Table 61. TS characteristics Symbol TL(1) Parameter VSENSE linearity with temperature (1) Min Typ Max Unit - ±1 ±2 °C Avg_Slope Average slope 4.0 4.3 4.6 mV/°C V25(1) Voltage at 25°C 1.34 1.43 1.52 V Startup time 4 - 10 µs ADC sampling time when reading the temperature - - 17.1 µs tSTART (2) TS_temp(3)(2) 1. Preliminary values. 2. Guaranteed by design. 3. Shortest sampling time can be determined in the application by multiple iterations. 100/117 DocID16553 Rev 5 STM32F101xF, STM32F101xG 6 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. LQFP144 package information Figure 52. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline C ! ! 3%!4).' 0,!.% # ! MM CCC # $ , $ + ! '!5'%0,!.% , $     % % % B 6.1    0). )$%.4)&)#!4)/.  E !?-%?6 1. Drawing is not to scale. DocID16553 Rev 5 101/117 Package information STM32F101xF, STM32F101xG Table 62. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data Symbol inches(1) millimeters Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 21.800 22.000 22.200 0.8583 0.8661 0.874 D1 19.800 20.000 20.200 0.7795 0.7874 0.7953 D3 - 17.500 - - 0.689 - E 21.800 22.000 22.200 0.8583 0.8661 0.874 E1 19.800 20.000 20.200 0.7795 0.7874 0.7953 E3 - 17.500 - 0.689 e - 0.500 - 0.0197 L 0.450 0.600 0.750 L1 - 1.000 - k 0° 3.5° 7° 0° 3.5° 7° ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 102/117 DocID16553 Rev 5 0.0177 0.0236 0.0295 0.0394 STM32F101xF, STM32F101xG Package information Figure 53. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package footprint                 DLH 1. Dimensions are expressed in millimeters. DocID16553 Rev 5 103/117 Package information STM32F101xF, STM32F101xG Device marking for LQFP144 The following figure gives an example of topside marking versus pin 1 position identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 54. LQFP144 marking (package top view) 5HYLVLRQFRGH 3URGXFWLGHQWLILFDWLRQ 5 670)=)7 'DWHFRGH < :: 3LQ LGHQWLILHU 06Y9 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. 104/117 DocID16553 Rev 5 STM32F101xF, STM32F101xG 6.2 Package information LQFP100 package information Figure 55. LQFP100 – 14 x 14 mm, 100-pin low-profile quad flat package outline C ! MM ! ! 3%!4).'0,!.% # '!5'%0,!.% $ , $ ! + CCC # , $     % % % B   0).  )$%.4)&)#!4)/.  E ,?-%?6 1. Drawing is not to scale. Table 63. LQPF100 – 14 x 14 mm, 100-pin low-profile quad flat package mechanical data Symbol inches(1) millimeters Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 15.800 16.000 16.200 0.622 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.5591 D3 - 12.000 - - 0.4724 - E 15.800 16.000 16.200 0.622 0.6299 0.6378 E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 DocID16553 Rev 5 105/117 Package information STM32F101xF, STM32F101xG Table 63. LQPF100 – 14 x 14 mm, 100-pin low-profile quad flat package mechanical data (continued) Symbol inches(1) millimeters Min Typ Max Min Typ Max E3 - 12.000 - - 0.4724 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0° 3.5° 7° 0° 3.5° 7° ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 56. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint                AIC 1. Dimensions are in millimeters. 106/117 DocID16553 Rev 5 STM32F101xF, STM32F101xG Package information Device marking for LQFP100 The following figure gives an example of topside marking versus pin 1 position identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 57. LQFP100 marking (package top view) 3URGXFWLGHQWLILFDWLRQ 670) 9*75 5HYLVLRQFRGH 'DWHFRGH < :: 3LQ LQGHQWLILHU 06Y9 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. DocID16553 Rev 5 107/117 Package information 6.3 STM32F101xF, STM32F101xG LQFP64 information Figure 58. LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package outline PP *$8*(3/$1( F $ $ $ 6($7,1*3/$1( & $ FFF & ' ' ' . / /      ( ( ( E  3,1 ,'(17,),&$7,21   H :B0(B9 1. Drawing is not to scale. Table 64. LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D - 12.000 - - 0.4724 - D1 - 10.000 - - 0.3937 - D3 - 7.500 - - 0.2953 - E - 12.000 - - 0.4724 - E1 - 10.000 - - 0.3937 - E3 - 7.500 - - 0.2953 - 108/117 DocID16553 Rev 5 STM32F101xF, STM32F101xG Package information Table 64. LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max e - 0.500 - - 0.0197 - θ 0° 3.5° 7° 0° 3.5° 7° L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 59. LQFP64 - 10 x 10 mm low-profile quad flat recommended footprint                 AIC 1. Dimensions are in millimeters. DocID16553 Rev 5 109/117 Package information STM32F101xF, STM32F101xG Device marking for LQFP64 The following figure gives an example of topside marking versus pin 1 position identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 60. LQFP64 marking (package top view) 5HYLVLRQFRGH 5 3URGXFWLGHQWLILFDWLRQ 670) 5)7 'DWHFRGH < :: 3LQ LQGHQWLILHU 06Y9 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. 110/117 DocID16553 Rev 5 STM32F101xF, STM32F101xG 6.4 Package information Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 10: General operating conditions on page 39. The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max × ΘJA) Where: • TA max is the maximum ambient temperature in °C, • ΘJA is the package junction-to-ambient thermal resistance, in °C/W, • PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), • PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 65. Package thermal characteristics Symbol ΘJA 6.4.1 Parameter Value Thermal resistance junction-ambient LQFP144 - 20 x 20 mm / 0.5 mm pitch 30 Thermal resistance junction-ambient LQFP100 - 14 x 14 mm / 0.5 mm pitch 46 Thermal resistance junction-ambient LQFP64 - 10 x 10 mm / 0.5 mm pitch 45 Unit °C/W Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air), available from www.jedec.org. DocID16553 Rev 5 111/117 Package information 6.4.2 STM32F101xF, STM32F101xG Evaluating the maximum junction temperature for an application When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Table 66: STM32F101xF and STM32F101xG ordering information scheme. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. Here, only temperature range 6 is available (–40 to 85 °C). The following example shows how to calculate the temperature range needed for a given application, making it possible to check whether the required temperature range is compatible with the STM32F10xxx junction temperature range. Example: High-performance application Assuming the following application conditions: Maximum ambient temperature TAmax = 82 °C (measured according to JESD51-2), IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output mode at low level with IOL = 20 mA, VOL= 1.3 V PINTmax = 50 mA × 3.5 V= 175 mW PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW This gives: PINTmax = 175 mW and PIOmax = 272 mW PDmax = 175 + 272 = 447 mW Thus: PDmax = 447 mW Using the values obtained in Table 66 TJmax is calculated as follows: – For LQFP64, 45 °C/W TJmax = 82 °C + (45 °C/W × 447 mW) = 82 °C + 20.1 °C = 102.1 °C This is within the junction temperature range of the STM32F10xxx (–40 < TJ < 105 °C). Figure 61. LQFP64 PD max vs. TA 700 PD (mW) 600 500 400 Suffix 6 300 200 100 0 65 75 85 95 TA (°C) 112/117 DocID16553 Rev 5 105 115 STM32F101xF, STM32F101xG 7 Part numbering Part numbering Table 66. STM32F101xF and STM32F101xG ordering information scheme Example: STM32 F 101 R F T 6 xxx Device family STM32 = ARM®-based 32-bit microcontroller Product type F = general-purpose Device subfamily 101 = access line Pin count R = 64 pins V = 100 pins Z = 144 pins Flash memory size F = 768 Kbytes of Flash memory G = 1 Mbyte of Flash memory Package T = LQFP Temperature range 6 = Industrial temperature range, –40 to 85 °C. Options xxx = programmed parts TR = tape and real For a list of available options (speed, package, etc..) or for further information on any aspect of this device, please contact your nearest ST sales office. DocID16553 Rev 5 113/117 Revision history 8 STM32F101xF, STM32F101xG Revision history Table 67. Document revision history Date Revision 27-Oct-2009 1 Initial release. 2 LQFP64 package mechanical data updated: see Figure 58: LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package outline and Table 64: LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package mechanical data. Internal code removed from Table 66: STM32F101xF and STM32F101xG ordering information scheme. Updated note 2 below Table 52: I2C characteristics Updated Figure 43: I2C bus AC waveforms and measurement circuit(1) Updated Figure 42: Recommended NRST pin protection Updated note 1 below Table 47: I/O static characteristics Updated Table 20: Peripheral current consumption Updated Table 14: Maximum current consumption in Run mode, code with data processing running from Flash Updated Table 15: Maximum current consumption in Run mode, code with data processing running from RAM Updated Table 16: Maximum current consumption in Sleep mode, code running from Flash or RAM Updated Table 17: Typical and maximum current consumptions in Stop and Standby modes Updated Table 18: Typical current consumption in Run mode, code with data processing running from Flash Updated Table 19: Typical current consumption in Sleep mode, code running from Flash or RAM Updated Table 24: LSE oscillator characteristics (fLSE = 32.768 kHz) Updated Figure 19: Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms on page 58 Added Section 5.3.13: I/O current injection characteristics on page 99. 15-Nov-2010 114/117 Changes DocID16553 Rev 5 STM32F101xF, STM32F101xG Revision history Table 67. Document revision history (continued) Date 25-Nov-2014 Revision Changes 3 Updated number of ADCs in Table 2: STM32F101xF and STM32F101xG features and peripheral counts. Modified Section 2.3.22: GPIOs (general-purpose inputs/outputs) on page 21. Added note below Figure 3: LQFP144 pinout, Figure 4: LQFP100 pinout, and Figure 5: LQFP64 pinout. Modified OSC_IN, OSC_OUT, PD0, PD1, PB8, PB9 and PF8 in Table 5: STM32F101xF/STM32F101xG pin definitions on page 25/ Updated notes related to parameters not tested in production in the whole document. Modified notes in Table 7: Voltage characteristics on page 37 and Table 8: Current characteristics on page 38. Removed ADC2/3 and CAN from Table 20: Peripheral current consumption on page 48. Modified tw(HSE) value in Table 21: High-speed external user clock characteristics on page 50. Updated Table 24: LSE oscillator characteristics (fLSE = 32.768 kHz) on page 53. Changed JESD22-C101 to ANSI/ESD STM5.3.1 in Section : Electrostatic discharge (ESD). Updated Section 5.3.10: FSMC characteristics on page 57. Updated Figure 41: I/O AC characteristics definition. Updated conditions related to Section : I2C interface characteristics on page 87. Modified Table 52: I2C characteristics on page 87, updated Figure 43: I2C bus AC waveforms and measurement circuit(1) and VDD/VDD_I2C conditions in Table 53: SCL frequency (fPCLK1= 36 MHz, VDD = VDD_I2C = 3.3 V) on page 88. Modified Section : Output driving current on page 82. Modified Table 52: I2C characteristics on page 87 and updated Figure 43: I2C bus AC waveforms and measurement circuit(1). Modified Figure 46: SPI timing diagram - master mode(1) on page 92. Modified notes in Table 56: ADC characteristics on page 93 and Table 59: ADC accuracy on page 95. Updated IDDA definition in Table 60: DAC characteristics on page 97 and removed comment related to the offset parameter for ±10 mV. Added Device marking information for all packages. DocID16553 Rev 5 115/117 Revision history STM32F101xF, STM32F101xG Table 67. Document revision history (continued) Date 18-May-2015 13-Dec-2016 116/117 Revision Changes 4 Modified Cortex-M3 technical reference manual url in Section 1: Introduction. Updated Table 20: Peripheral current consumption. Restored CDM standard and class in Table 44: ESD absolute maximum ratings Updated ccc dimension in Table 62: LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data and Section : Device marking for LQFP144. Updated Section : Device marking for LQFP100. Updated Table 64: LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package mechanical data and Section : Device marking for LQFP64. 5 Updated: – Table 5: STM32F101xF/STM32F101xG pin definitions – |VSSX - VSS| in Table 7: Voltage characteristics to add VREF– RLOAD in Table 60: DAC characteristics – Figure 42: Recommended NRST pin protection – Section 6: Package information Added: – VREF- in Table 56: ADC characteristics DocID16553 Rev 5 STM32F101xF, STM32F101xG IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved DocID16553 Rev 5 117/117 117