STM32F439IIT6

STM32F437xx STM32F439xx 32b Arm® Cortex®-M4 MCU+FPU, 225DMIPS, up to 2MB Flash/256+4KB RAM, crypto, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 20 com. interfaces, camera&LCD-TFT Datasheet - production data Features • Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 180 MHz, MPU, 225 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions • Memories – Up to 2 MB of Flash memory organized into two banks allowing read-while-write – Up to 256+4 KB of SRAM including 64-KB of CCM (core coupled memory) data RAM – Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, Compact Flash/NOR/NAND memories • LCD parallel interface, 8080/6800 modes • LCD-TFT controller with fully programmable resolution (total width up to 4096 pixels, total height up to 2048 lines and pixel clock up to 83 MHz) • Chrom-ART Accelerator™ for enhanced graphic content creation (DMA2D) • Clock, reset and supply management – 1.7 V to 3.6 V application supply and I/Os – POR, PDR, PVD and BOR – 4-to-26 MHz crystal oscillator – Internal 16 MHz factory-trimmed RC (1% accuracy) – 32 kHz oscillator for RTC with calibration – Internal 32 kHz RC with calibration • Low power – Sleep, Stop and Standby modes – VBAT supply for RTC, 20×32 bit backup registers + optional 4 KB backup SRAM • 3×12-bit, 2.4 MSPS ADC: up to 24 channels and 7.2 MSPS in triple interleaved mode • 2×12-bit D/A converters • General-purpose DMA: 16-stream DMA controller with FIFOs and burst support • Up to 17 timers: up to twelve 16-bit and two 32bit timers up to 180 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input January 2018 This is information on a product in full production. &"'! LQFP100 (14 × 14 mm) UFBGA176 (10 x 10 mm) LQFP144 (20 × 20 mm) UFBGA169 (7 × 7 mm) LQFP176 (24 × 24 mm) TFBGA216 (13 x 13 mm) LQFP208 (28 x 28 mm) WLCSP143 • Debug mode – SWD & JTAG interfaces – Cortex-M4 Trace Macrocell™ • Up to 168 I/O ports with interrupt capability – Up to 164 fast I/Os up to 90 MHz – Up to 166 5 V-tolerant I/Os • Up to 21 communication interfaces – Up to 3 × I2C interfaces (SMBus/PMBus) – Up to 4 USARTs/4 UARTs (11.25 Mbit/s, ISO7816 interface, LIN, IrDA, modem control) – Up to 6 SPIs (45 Mbits/s), 2 with muxed full-duplex I2S for audio class accuracy via internal audio PLL or external clock – 1 x SAI (serial audio interface) – 2 × CAN (2.0B Active) and SDIO interface • Advanced connectivity – USB 2.0 full-speed device/host/OTG controller with on-chip PHY – USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI – 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII • 8- to 14-bit parallel camera interface up to 54 Mbytes/s • Cryptographic acceleration: hardware acceleration for AES 128, 192, 256, Triple DES, HASH (MD5, SHA-1, SHA-2), and HMAC • True random number generator • CRC calculation unit • RTC: subsecond accuracy, hardware calendar • 96-bit unique ID DocID024244 Rev 11 1/241 www.st.com STM32F437xx and STM32F439xx Table 1. Device summary Reference Part number STM32F437xx STM32F437VG, STM32F437ZG, STM32F437IG, STM32F437VI, STM32F437ZI, STM32F437II, STM32F437AI STM32F439xx STM32F439VI, STM32F439VG, STM32F439ZG, STM32F439ZI, STM32F439IG, STM32F439II, STM32F439BG, STM32F439BI, STM32F439NI, STM32F439AI, STM32F439NG 2/241 DocID024244 Rev 11 STM32F437xx and STM32F439xx Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1 3 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1 Arm® Cortex®-M4 with FPU and embedded Flash and SRAM . . . . . . . . 21 3.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 21 3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.5 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 22 3.6 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.7 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.8 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.9 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.10 LCD-TFT controller (available only on STM32F439xx) . . . . . . . . . . . . . . 24 3.11 Chrom-ART Accelerator™ (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.12 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 25 3.13 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.14 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.15 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.16 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.17 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.18 3.17.1 Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.17.2 Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.18.1 Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.18.2 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.18.3 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 32 3.19 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 32 3.20 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.21 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 DocID024244 Rev 11 3/241 6 Contents STM32F437xx and STM32F439xx 3.22 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.22.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.22.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.22.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.22.4 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.22.5 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.22.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.23 Inter-integrated circuit interface ( I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.24 Universal synchronous/asynchronous receiver transmitters (USART) . . 37 3.25 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.26 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.27 Serial Audio interface (SAI1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.28 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.29 Audio and LCD PLL(PLLSAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.30 Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . . . . 40 3.31 Ethernet MAC interface with dedicated DMA and IEEE 1588 support . . . 40 3.32 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.33 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 41 3.34 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 41 3.35 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.36 Cryptographic acceleration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.37 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.38 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.39 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.40 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.41 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.42 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.43 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.1 4/241 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 DocID024244 Rev 11 STM32F437xx and STM32F439xx Contents 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 6.3.2 VCAP1/VCAP2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 6.3.3 Operating conditions at power-up / power-down (regulator ON) . . . . . . 98 6.3.4 Operating conditions at power-up / power-down (regulator OFF) . . . . . 98 6.3.5 Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . 99 6.3.6 Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6.3.7 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6.3.8 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 118 6.3.9 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 119 6.3.10 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 123 6.3.11 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 6.3.12 PLL spread spectrum clock generation (SSCG) characteristics . . . . . 128 6.3.13 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 6.3.14 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 6.3.15 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 134 6.3.16 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 6.3.17 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 6.3.18 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 6.3.19 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 6.3.20 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 6.3.21 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 6.3.22 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 6.3.23 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 6.3.24 Reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 6.3.25 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 6.3.26 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 6.3.27 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 195 6.3.28 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 196 DocID024244 Rev 11 5/241 6 Contents 7 8 STM32F437xx and STM32F439xx 6.3.29 SD/SDIO MMC card host interface (SDIO) characteristics . . . . . . . . . 198 6.3.30 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 7.1 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 7.2 WLCSP143 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 7.3 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 7.4 LQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211 7.5 LQFP208 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 7.6 UFBGA169 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 7.7 UFBGA176+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 7.8 TFBGA216 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 7.9 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 Appendix A Recommendations when using internal reset OFF . . . . . . . . . . . 229 A.1 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 Appendix B Application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 9 6/241 B.1 USB OTG full speed (FS) interface solutions . . . . . . . . . . . . . . . . . . . . . 230 B.2 USB OTG high speed (HS) interface solutions . . . . . . . . . . . . . . . . . . . . 232 B.3 Ethernet interface solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 DocID024244 Rev 11 STM32F437xx and STM32F439xx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 STM32F437xx and STM32F439xx features and peripheral counts . . . . . . . . . . . . . . . . . . 16 Voltage regulator configuration mode versus device operating mode . . . . . . . . . . . . . . . . 29 Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 32 Voltage regulator modes in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 STM32F437xx and STM32F439xx pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . 53 FMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 STM32F437xx and STM32F439xx alternate function mapping . . . . . . . . . . . . . . . . . . . . . 75 STM32F437xx and STM32F439xx register boundary addresses. . . . . . . . . . . . . . . . . . . . 87 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 97 VCAP1/VCAP2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 98 Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 98 reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled except prefetch) or RAM . . . . . . 102 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled) . . . . . . . . . . . . . . . . . . . . . . . . . 103 Typical and maximum current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . 104 Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . 105 Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . 106 Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . 106 Typical current consumption in Run mode, code with data processing running from Flash memory or RAM, regulator ON (ART accelerator enabled except prefetch), VDD=1.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Typical current consumption in Run mode, code with data processing running from Flash memory, regulator OFF (ART accelerator enabled except prefetch). . . . . . . 109 Typical current consumption in Sleep mode, regulator ON, VDD=1.7 V . . . . . . . . . . . . . 110 Tyical current consumption in Sleep mode, regulator OFF. . . . . . . . . . . . . . . . . . . . . . . . 111 Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 HSE 4-26 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 DocID024244 Rev 11 7/241 9 List of tables Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. 8/241 STM32F437xx and STM32F439xx PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 PLLISAI (audio and LCD-TFT PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Flash memory programming with VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 USB OTG full speed startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 USB OTG full speed DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 USB OTG full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 USB HS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Dynamic characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Dynamics characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . 156 Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 157 Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 158 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 ADC static accuracy at fADC = 18 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 ADC static accuracy at fADC = 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 ADC static accuracy at fADC = 36 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 ADC dynamic accuracy at fADC = 18 MHz - limited test conditions . . . . . . . . . . . . . . . . . 161 ADC dynamic accuracy at fADC = 36 MHz - limited test conditions . . . . . . . . . . . . . . . . . 161 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Asynchronous non-multiplexed SRAM/PSRAM/NOR read NWAIT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 173 Asynchronous non-multiplexed SRAM/PSRAM/NOR write NWAIT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 175 Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 176 DocID024244 Rev 11 STM32F437xx and STM32F439xx Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. List of tables Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 177 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 181 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Switching characteristics for PC Card/CF read and write cycles in attribute/common space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Switching characteristics for PC Card/CF read and write cycles in I/O space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 191 SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 LPSDR SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Dynamic characteristics: SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 LQPF100 100-pin, 14 x 14 mm low-profile quad flat package mechanical data. . . . . . . . 201 WLCSP143 - 143-ball, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 WLCSP143 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . 206 LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 LQFP176 - 176-pin, 24 x 24 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 UFBGA169 - 169-ball 7 x 7 mm 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 UFBGA169 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 220 UFBGA176+25 - ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . 222 UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . . 223 TFBGA216 - 216 ball 13 × 13 mm 0.8 mm pitch thin fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 229 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 DocID024244 Rev 11 9/241 9 List of figures STM32F437xx and STM32F439xx List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. 10/241 Compatible board design STM32F10xx/STM32F2xx/STM32F4xx for LQFP100 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx for LQFP144 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Compatible board design between STM32F2xx and STM32F4xx for LQFP176 and UFBGA176 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 STM32F437xx and STM32F439xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 STM32F437xx and STM32F439xx Multi-AHB matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 27 PDR_ON control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Startup in regulator OFF: slow VDD slope - power-down reset risen after VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . 31 Startup in regulator OFF mode: fast VDD slope - power-down reset risen before VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 31 STM32F43x LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 STM32F43x WLCSP143 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 STM32F43x LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 STM32F43x LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 STM32F43x LQFP208 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 STM32F43x UFBGA169 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 STM32F43x UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 STM32F43x TFBGA216 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Typical VBAT current consumption (LSE and RTC ON/backup RAM OFF) . . . . . . . . . . . 107 Typical VBAT current consumption (LSE and RTC ON/backup RAM ON) . . . . . . . . . . . . 107 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 ACCHSI accuracy versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 ACCLSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 FT I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 DocID024244 Rev 11 STM32F437xx and STM32F439xx Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. Figure 86. Figure 87. Figure 88. Figure 89. List of figures SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 USB OTG full speed timings: definition of data signal rise and fall time . . . . . . . . . . . . . . 153 ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 164 Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 165 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 171 Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 173 Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 174 Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 176 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 181 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 PC Card/CompactFlash controller waveforms for common memory read access . . . . . . 184 PC Card/CompactFlash controller waveforms for common memory write access . . . . . . 184 PC Card/CompactFlash controller waveforms for attribute memory read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 PC Card/CompactFlash controller waveforms for attribute memory write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . 186 PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . 187 NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 190 NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 190 SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 LQFP100 -100-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . . 200 LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 WLCSP143 - 143-ball, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 WLCSP143 - 143-ball, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 WLCSP143 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 LQFP144-144-pin, 20 x 20 mm low-profile quad flat package outline . . . . . . . . . . . . . . . 207 LQPF144- 144-pin,20 x 20 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 LQFP176 - 176-pin, 24 x 24 mm low-profile quad flat package outline . . . . . . . . . . . . . . 211 DocID024244 Rev 11 11/241 12 List of figures Figure 90. Figure 91. Figure 92. Figure 93. Figure 94. Figure 95. Figure 96. Figure 97. Figure 98. Figure 99. Figure 100. Figure 101. Figure 102. Figure 103. Figure 104. Figure 105. Figure 106. Figure 107. Figure 108. Figure 109. 12/241 STM32F437xx and STM32F439xx LQFP176 - 176-pin, 24 x 24 mm low profile quad flat recommended footprint. . . . . . . . . 213 LQFP176 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package outline . . . . . . . . . . . . . . 215 LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 LQFP208 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 UFBGA169 - 169-ball 7 x 7 mm 0.50 mm pitch, ultra fine pitch ball grid array package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 UFBGA169 - 169-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 UFBGA169 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 UFBGA176+25 - ball 10 x 10 mm, 0.65 mm pitch ultra thin fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 UFBGA176+25-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 UFBGA176+25 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 TFBGA216 - 216 ball 13 × 13 mm 0.8 mm pitch thin fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 TFBGA176 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 USB controller configured as peripheral-only and used in Full speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 USB controller configured as host-only and used in full speed mode. . . . . . . . . . . . . . . . 230 USB controller configured in dual mode and used in full speed mode . . . . . . . . . . . . . . . 231 USB controller configured as peripheral, host, or dual-mode and used in high speed mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 MII mode using a 25 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 RMII with a 50 MHz oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 RMII with a 25 MHz crystal and PHY with PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 DocID024244 Rev 11 STM32F437xx and STM32F439xx 1 Introduction Introduction This datasheet provides the description of the STM32F437xx and STM32F439xx line of microcontrollers. For more details on the whole STMicroelectronics STM32 family, please refer to Section 2.1: Full compatibility throughout the family. The STM32F437xx and STM32F439xx datasheet should be read in conjunction with the STM32F4xx reference manual. For information on the Cortex®-M4 core, please refer to the Cortex®-M4 programming manual (PM0214), available from www.st.com. DocID024244 Rev 11 13/241 44 Description 2 STM32F437xx and STM32F439xx Description The STM32F437xx and STM32F439xx devices are based on the high-performance Arm® Cortex®-M4 32-bit RISC core operating at a frequency of up to 180 MHz. The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all Arm® singleprecision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security. The STM32F437xx and STM32F439xx devices incorporate high-speed embedded memories (Flash memory up to 2 Mbyte, up to 256 Kbytes of SRAM), up to 4 Kbytes of backup SRAM, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix. All devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose 16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers, a true random number generator (RNG) and a cryptographic acceleration cell. They also feature standard and advanced communication interfaces. • Up to three I2Cs • Six SPIs, two I2Ss full duplex. To achieve audio class accuracy, the I2S peripherals can be clocked via a dedicated internal audio PLL or via an external clock to allow synchronization. • Four USARTs plus four UARTs • An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the ULPI), • Two CANs • One SAI serial audio interface • An SDIO/MMC interface • Ethernet and camera interface • LCD-TFT display controller • Chrom-ART Accelerator™. Advanced peripherals include an SDIO, a flexible memory control (FMC) interface, a camera interface for CMOS sensors and a cryptographic acceleration cell. Refer to Table 2: STM32F437xx and STM32F439xx features and peripheral counts for the list of peripherals available on each part number. The STM32F437xx and STM32F439xx devices operates in the –40 to +105 °C temperature range from a 1.7 to 3.6 V power supply. The supply voltage can drop to 1.7 V with the use of an external power supply supervisor (refer to Section 3.17.2: Internal reset OFF). A comprehensive set of power-saving mode allows the design of low-power applications. The STM32F437xx and STM32F439xx devices offer devices in 8 packages ranging from 100 pins to 216 pins. The set of included peripherals changes with the device chosen. 14/241 DocID024244 Rev 11 STM32F437xx and STM32F439xx Description These features make the STM32F437xx and STM32F439xx microcontrollers suitable for a wide range of applications: • Motor drive and application control • Medical equipment • Industrial applications: PLC, inverters, circuit breakers • Printers, and scanners • Alarm systems, video intercom, and HVAC • Home audio appliances Figure 4 shows the general block diagram of the device family. DocID024244 Rev 11 15/241 44 Peripherals Flash memory in Kbytes SRAM in Kbytes STM32F437 Vx STM32F439 Vx STM32F437Zx 1024 2048 1024 1024 2048 STM32F437AI STM32F439AI 2048 2048 2048 STM32F439Ix STM32F439Bx STM32F439Nx 1024 1024 1024 1024 1024 2048 256(112+16+64+64) Backup 4 2048 2048 2048 2048 Yes(1) Ethernet Yes Generalpurpose 10 Advance d-control 2 Basic 2 DocID024244 Rev 11 Random number generator Yes SPI / I2S 4/2 (full duplex)(2) 6/2 (full duplex)(2) I 2C 3 USART/ UART 4/4 USB Communication OTG FS interfaces USB OTG HS Yes Yes 2 SAI 1 SDIO Yes LCD-TFT Yes No Yes No Yes Chrom-ART Accelerator™ (DMA2D) Yes No Yes Yes Cryptography Yes 82 114 140 168 168 STM32F437xx and STM32F439xx CAN Camera interface GPIOs STM32F437Ix System FMC memory controller Timers STM32F439Zx Description 16/241 Table 2. STM32F437xx and STM32F439xx features and peripheral counts Peripherals 12-bit ADC Number of channels STM32F437 Vx STM32F439 Vx STM32F437Zx STM32F437AI STM32F439AI STM32F437Ix STM32F439Ix STM32F439Bx STM32F439Nx LQFP208 TFBGA216 3 16 24 12-bit DAC Number of channels Yes 2 Maximum CPU frequency 180 MHz 1.7 to 3.6 V(3) Operating voltage Ambient temperatures: –40 to +85 °C /–40 to +105 °C Operating temperatures Package STM32F439Zx Junction temperature: –40 to + 125 °C LQFP100 WLCSP143 LQFP144 UFBGA169 WLCSP143 LQFP144 UFBGA176 LQFP176 DocID024244 Rev 11 1. For the LQFP100 package, only FMC Bank1 or Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16- or 8-bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available in this package. 2. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode. 3. VDD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.17.2: Internal reset OFF). STM32F437xx and STM32F439xx Table 2. STM32F437xx and STM32F439xx features and peripheral counts (continued) Description 17/241 Description 2.1 STM32F437xx and STM32F439xx Full compatibility throughout the family The STM32F437xx and STM32F439xx devices are part of the STM32F4 family. They are fully pin-to-pin, software and feature compatible with the STM32F2xx devices, allowing the user to try different memory densities, peripherals, and performances (FPU, higher frequency) for a greater degree of freedom during the development cycle. The STM32F437xx and STM32F439xx devices maintain a close compatibility with the whole STM32F10xx family. All functional pins are pin-to-pin compatible. The STM32F437xx and STM32F439xx, however, are not drop-in replacements for the STM32F10xx devices: the two families do not have the same power scheme, and so their power pins are different. Nonetheless, transition from the STM32F10xx to the STM32F43x family remains simple as only a few pins are impacted. Figure 1, Figure 2, and Figure 3, give compatible board designs between the STM32F4xx, STM32F2xx, and STM32F10xx families. Figure 1. Compatible board design STM32F10xx/STM32F2xx/STM32F4xx for LQFP100 package    966    966 966 966      ŸUHVLVWRURUVROGHULQJEULGJH SUHVHQWIRUWKH670)[[[ FRQILJXUDWLRQQRWSUHVHQWLQWKH 670)[[FRQILJXUDWLRQ  966 966 966IRU670)[[ 7ZRŸUHVLVWRUVFRQQHFWHGWR 9''IRU670)[[ 9'' 966 966IRUWKH670)[[ 966IRUWKH670)[[ 966RU1&IRUWKH670)[[ DLG 18/241 DocID024244 Rev 11 STM32F437xx and STM32F439xx Description Figure 2. Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx for LQFP144 package 966  ŸUHVLVWRURUVROGHULQJEULGJH SUHVHQWIRUWKH670)[[ FRQILJXUDWLRQQRWSUHVHQWLQWKH 670)[[FRQILJXUDWLRQ      966 966 6LJQDOIURP H[WHUQDOSRZHU VXSSO\ VXSHUYLVRU 1RWSRSXODWHGZKHQŸ UHVLVWRURUVROGHULQJ EULGJHSUHVHQW 3'5B21       966 9'' 966 1RWSRSXODWHGIRU670)[[ 7ZRŸUHVLVWRUVFRQQHFWHGWR 966IRU670)[[ 966IRUWKH670)[[ 9'' 966 9''IRU670)[[ 9669''RU1&IRUWKH670)[[ 9''RUVLJQDOIURPH[WHUQDOSRZHUVXSSO\VXSHUYLVRUIRUWKH670)[[ DLG Figure 3. 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The timers connected to APB2 are clocked from TIMxCLK up to 180 MHz, while the timers connected to APB1 are clocked from TIMxCLK either up to 90 MHz or 180 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register. 2. The LCD-TFT is available only on STM32F439xx devices. 20/241 DocID024244 Rev 11 STM32F437xx and STM32F439xx Functional overview 3 Functional overview 3.1 Arm® Cortex®-M4 with FPU and embedded Flash and SRAM The Arm® Cortex®-M4 with FPU processor is the latest generation of Arm processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. The Arm® Cortex®-M4 with FPU core is a 32-bit RISC processor that features exceptional code-efficiency, delivering the high-performance expected from an Arm core in the memory size usually associated with 8- and 16-bit devices. The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution. Its single precision FPU (floating point unit) speeds up software development by using metalanguage development tools, while avoiding saturation. The STM32F43x family is compatible with all Arm tools and software. Figure 4 shows the general block diagram of the STM32F43x family. Note: Cortex-M4 with FPU core is binary compatible with the Cortex-M3 core. 3.2 Adaptive real-time memory accelerator (ART Accelerator™) The ART Accelerator™ is a memory accelerator which is optimized for STM32 industrystandard Arm® Cortex®-M4 with FPU processors. It balances the inherent performance advantage of the Arm® Cortex®-M4 with FPU over Flash memory technologies, which normally requires the processor to wait for the Flash memory at higher frequencies. To release the processor full 225 DMIPS performance at this frequency, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 128-bit Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART Accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 180 MHz. 3.3 Memory protection unit The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it. DocID024244 Rev 11 21/241 44 Functional overview 3.4 STM32F437xx and STM32F439xx Embedded Flash memory The devices embed a Flash memory of up to 2 Mbytes available for storing programs and data. 3.5 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a software signature during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location. 3.6 Embedded SRAM All devices embed: • Up to 256Kbytes of system SRAM including 64 Kbytes of CCM (core coupled memory) data RAM RAM memory is accessed (read/write) at CPU clock speed with 0 wait states. • 4 Kbytes of backup SRAM This area is accessible only from the CPU. Its content is protected against possible unwanted write accesses, and is retained in Standby or VBAT mode. 3.7 Multi-AHB bus matrix The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, Ethernet, USB HS, LCD-TFT, and DMA2D) and the slaves (Flash memory, RAM, FMC, AHB and APB peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously. 22/241 DocID024244 Rev 11 STM32F437xx and STM32F439xx Functional overview Figure 5. STM32F437xx and STM32F439xx Multi-AHB matrix &KURP$57$FFHOHUDWRU '0$' ,&2'( '&2'( $&&(/ '0$' /&'7)7B0 86%B+6B0 0$& 86%27* /&'7)7 (WKHUQHW +6 (7+(51(7B0 '0$B3 *3 '0$ '0$B0(0 '0$B0(0 *3 '0$ '0$B3, 6EXV 'EXV $50 &RUWH[0 ,EXV .E\WH &&0GDWD5$0 )ODVK PHPRU\ 65$0 .E\WH 65$0 .E\WH 65$0 .E\WH $+% SHULSKHUDOV $3% $+% SHULSKHUDOV )0&H[WHUQDO 0HP&WO $3% %XVPDWUL[6 -36 3.8 DMA controller (DMA) The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (AHB/APB). The two DMA controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. The two DMA controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code. Each stream is connected to dedicated hardware DMA requests, with support for software trigger on each stream. Configuration is made by software and transfer sizes between source and destination are independent. DocID024244 Rev 11 23/241 44 Functional overview STM32F437xx and STM32F439xx The DMA can be used with the main peripherals: 3.9 • SPI and I2S • I2C • USART • General-purpose, basic and advanced-control timers TIMx • DAC • SDIO • Cryptographic acceleration • Camera interface (DCMI) • ADC • SAI1. Flexible memory controller (FMC) All devices embed an FMC. It has four Chip Select outputs supporting the following modes: PCCard/Compact Flash, SDRAM/LPSDR SDRAM, SRAM, PSRAM, NOR Flash and NAND Flash. Functionality overview: • 8-,16-, 32-bit data bus width • Read FIFO for SDRAM controller • Write FIFO • Maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is 90 MHz. LCD parallel interface The FMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration. 3.10 LCD-TFT controller (available only on STM32F439xx) The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue) and delivers all signals to interface directly to a broad range of LCD and TFT panels up to XGA (1024x768) resolution with the following features: 24/241 • 2 displays layers with dedicated FIFO (64x32-bit) • Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer • Up to 8 Input color formats selectable per layer • Flexible blending between two layers using alpha value (per pixel or constant) • Flexible programmable parameters for each layer • Color keying (transparency color) • Up to 4 programmable interrupt events. DocID024244 Rev 11 STM32F437xx and STM32F439xx 3.11 Functional overview Chrom-ART Accelerator™ (DMA2D) The Chrom-Art Accelerator™ (DMA2D) is a graphic accelerator which offers advanced bit blitting, row data copy and pixel format conversion. It supports the following functions: • Rectangle filling with a fixed color • Rectangle copy • Rectangle copy with pixel format conversion • Rectangle composition with blending and pixel format conversion. Various image format coding are supported, from indirect 4bpp color mode up to 32bpp direct color. It embeds dedicated memory to store color lookup tables. An interrupt can be generated when an operation is complete or at a programmed watermark. All the operations are fully automatized and are running independently from the CPU or the DMAs. 3.12 Nested vectored interrupt controller (NVIC) The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 91 maskable interrupt channels plus the 16 interrupt lines of the Cortex®M4 with FPU core. • Closely coupled NVIC gives low-latency interrupt processing • Interrupt entry vector table address passed directly to the core • Allows early processing of interrupts • Processing of late arriving, higher-priority interrupts • Support tail chaining • Processor state automatically saved • Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimum interrupt latency. 3.13 External interrupt/event controller (EXTI) The external interrupt/event controller consists of 23 edge-detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 168 GPIOs can be connected to the 16 external interrupt lines. 3.14 Clocks and startup On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The 16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy over the full temperature range. The application can then select as system clock either the RC oscillator or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is DocID024244 Rev 11 25/241 44 Functional overview STM32F437xx and STM32F439xx detected, the system automatically switches back to the internal RC oscillator and a software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing to increase the frequency up to 180 MHz. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example if an indirectly used external oscillator fails). Several prescalers allow the configuration of the two AHB buses, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB buses is 180 MHz while the maximum frequency of the high-speed APB domains is 90 MHz. The maximum allowed frequency of the low-speed APB domain is 45 MHz. The devices embed a dedicated PLL (PLLI2S) and PLLSAI which allows to achieve audio class performance. In this case, the I2S master clock can generate all standard sampling frequencies from 8 kHz to 192 kHz. 3.15 Boot modes At startup, boot pins are used to select one out of three boot options: • Boot from user Flash • Boot from system memory • Boot from embedded SRAM The boot loader is located in system memory. It is used to reprogram the Flash memory through a serial interface. Refer to application note AN2606 for details. 3.16 Power supply schemes • VDD = 1.7 to 3.6 V: external power supply for I/Os and the internal regulator (when enabled), provided externally through VDD pins. • VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively. • VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. Note: VDD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.17.2: Internal reset OFF). Refer to Table 3: Voltage regulator configuration mode versus device operating mode to identify the packages supporting this option. 3.17 Power supply supervisor 3.17.1 Internal reset ON On packages embedding the PDR_ON pin, the power supply supervisor is enabled by holding PDR_ON high. On the other package, the power supply supervisor is always enabled. The device has an integrated power-on reset (POR)/ power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is 26/241 DocID024244 Rev 11 STM32F437xx and STM32F439xx Functional overview reached, the option byte loading process starts, either to confirm or modify default BOR thresholds, or to disable BOR permanently. Three BOR thresholds are available through option bytes. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for an external reset circuit. The device also features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. 3.17.2 Internal reset OFF This feature is available only on packages featuring the PDR_ON pin. The internal power-on reset (POR) / power-down reset (PDR) circuitry is disabled through the PDR_ON pin. An external power supply supervisor should monitor VDD and should maintain the device in reset mode as long as VDD is below a specified threshold. PDR_ON should be connected to this external power supply supervisor. Refer to Figure 6: Power supply supervisor interconnection with internal reset OFF. Figure 6. Power supply supervisor interconnection with internal reset OFF 9'' ([WHUQDO9''SRZHUVXSSO\VXSHUYLVRU ([WUHVHWFRQWUROOHUDFWLYHZKHQ 9''9 3'5B21 1567 $SSOLFDWLRQUHVHW VLJQDORSWLRQDO 9'' 069 The VDD specified threshold, below which the device must be maintained under reset, is 1.7 V (see Figure 7). A comprehensive set of power-saving mode allows to design low-power applications. When the internal reset is OFF, the following integrated features are no more supported: • The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled • The brownout reset (BOR) circuitry must be disabled • The embedded programmable voltage detector (PVD) is disabled • VBAT functionality is no more available and VBAT pin should be connected to VDD. All packages, except for the LQFP100, allow to disable the internal reset through the PDR_ON signal. DocID024244 Rev 11 27/241 44 Functional overview STM32F437xx and STM32F439xx Figure 7. PDR_ON control with internal reset OFF 9 '' 3'5 9 WLPH 5HVHWE\RWKHUVRXUFHWKDQ SRZHUVXSSO\VXSHUYLVRU 1567 3'5B21 3'5B21 WLPH 069 3.18 Voltage regulator The regulator has four operating modes: • • 3.18.1 Regulator ON – Main regulator mode (MR) – Low power regulator (LPR) – Power-down Regulator OFF Regulator ON On packages embedding the BYPASS_REG pin, the regulator is enabled by holding BYPASS_REG low. On all other packages, the regulator is always enabled. There are three power modes configured by software when the regulator is ON: • MR mode used in Run/sleep modes or in Stop modes – In Run/Sleep mode The MR mode is used either in the normal mode (default mode) or the over-drive mode (enabled by software). Different voltages scaling are provided to reach the best compromise between maximum frequency and dynamic power consumption. 28/241 DocID024244 Rev 11 STM32F437xx and STM32F439xx Functional overview The over-drive mode allows operating at a higher frequency than the normal mode for a given voltage scaling. – In Stop modes The MR can be configured in two ways during stop mode: MR operates in normal mode (default mode of MR in stop mode) MR operates in under-drive mode (reduced leakage mode). • LPR is used in the Stop modes: The LP regulator mode is configured by software when entering Stop mode. Like the MR mode, the LPR can be configured in two ways during stop mode: • – LPR operates in normal mode (default mode when LPR is ON) – LPR operates in under-drive mode (reduced leakage mode). Power-down is used in Standby mode. The Power-down mode is activated only when entering in Standby mode. The regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption. The contents of the registers and SRAM are lost. Refer to Table 3 for a summary of voltage regulator modes versus device operating modes. Two external ceramic capacitors should be connected on VCAP_1 and VCAP_2 pin. Refer to Figure 22: Power supply scheme and Table 19: VCAP1/VCAP2 operating conditions. All packages have the regulator ON feature. Table 3. Voltage regulator configuration mode versus device operating mode(1) Voltage regulator configuration Run mode Sleep mode Stop mode Standby mode Normal mode MR MR MR or LPR - Over-drive mode(2) MR MR - - Under-drive mode - - MR or LPR - Power-down mode - - - Yes 1. ‘-’ means that the corresponding configuration is not available. 2. The over-drive mode is not available when VDD = 1.7 to 2.1 V. 3.18.2 Regulator OFF This feature is available only on packages featuring the BYPASS_REG pin. The regulator is disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply externally a V12 voltage source through VCAP_1 and VCAP_2 pins. Since the internal voltage scaling is not managed internally, the external voltage value must be aligned with the targeted maximum frequency. Refer to Table 17: General operating conditions.The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors. Refer to Figure 22: Power supply scheme. When the regulator is OFF, there is no more internal monitoring on V12. An external power supply supervisor should be used to monitor the V12 of the logic power domain. PA0 pin should be used for this purpose, and act as power-on reset on V12 power domain. DocID024244 Rev 11 29/241 44 Functional overview STM32F437xx and STM32F439xx In regulator OFF mode, the following features are no more supported: • PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic power domain which is not reset by the NRST pin. • As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As a consequence, PA0 and NRST pins must be managed separately if the debug connection under reset or pre-reset is required. • The over-drive and under-drive modes are not available. • The Standby mode is not available. Figure 8. Regulator OFF 9 ([WHUQDO9&$3BSRZHU $SSOLFDWLRQUHVHW VXSSO\VXSHUYLVRU ([WUHVHWFRQWUROOHUDFWLYH VLJQDORSWLRQDO ZKHQ9&$3B0LQ9 9'' 3$ 9'' 1567 %@ 50,,B&56B'9 DLE Table 72. Dynamics characteristics: Ethernet MAC signals for RMII(1) Symbol Parameter tsu(RXD) Receive data setup time tih(RXD) Receive data hold time tsu(CRS) Carrier sense setup time tih(CRS) Carrier sense hold time td(TXEN) Transmit enable valid delay time td(TXD) Transmit data valid delay time Condition Min Typ Max 1.5 - - 0 - - 1 - - 1 - - 2.7 V < VDD < 3.6 V 8 10.5 12 1.71 V < VDD < 3.6 V 8 10.5 14 2.7 V < VDD < 3.6 V 8 11 12.5 1.71 V < VDD < 3.6 V 8 11 14.5 1.71 V < VDD < 3.6 V Unit ns 1. Guaranteed by characterization results. Table 73 gives the list of Ethernet MAC signals for MII and Figure 48 shows the corresponding timing diagram. DocID024244 Rev 11 157/241 199 Electrical characteristics STM32F437xx and STM32F439xx Figure 49. Ethernet MII timing diagram 0,,B5;B&/. WVX5;' WVX(5 WVX'9 WLK5;' WLK(5 WLK'9 0,,B5;'>@ 0,,B5;B'9 0,,B5;B(5 0,,B7;B&/. WG7;(1 WG7;' 0,,B7;B(1 0,,B7;'>@ AIB Table 73. Dynamics characteristics: Ethernet MAC signals for MII(1) Symbol Parameter Condition Min Typ Max tsu(RXD) Receive data setup time 9 - - tih(RXD) Receive data hold time 10 - - tsu(DV) Data valid setup time 9 - - tih(DV) Data valid hold time 8 - - tsu(ER) Error setup time 6 - - tih(ER) Error hold time 8 - - 2.7 V < VDD < 3.6 V 8 10 14 1.71 V < VDD < 3.6 V 8 10 16 2.7 V < VDD < 3.6 V 7.5 10 15 1.71 V < VDD < 3.6 V 7.5 10 17 td(TXEN) Transmit enable valid delay time td(TXD) Transmit data valid delay time 1.71 V < VDD < 3.6 V Unit ns 1. Guaranteed by characterization results. CAN (controller area network) interface Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate function characteristics (CANx_TX and CANx_RX). 158/241 DocID024244 Rev 11 STM32F437xx and STM32F439xx 6.3.21 Electrical characteristics 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 74 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 17. Table 74. ADC characteristics Symbol Parameter VDDA Power supply VREF+ Positive reference voltage VREF- Negative reference voltage Conditions Typ Max (1) 1.7 - 3.6 1.7(1) - VDDA - 0 - 0.6 15 18 MHz VDDA = 2.4 to 3.6 V 0.6 30 36 MHz fADC = 30 MHz, 12-bit resolution - - 1764 kHz - - 17 1/fADC 0 (VSSA or VREFtied to ground) - VREF+ V - - 50 kΩ 1.5 - 6 kΩ - 4 7 pF - - 0.100 µs - - 3(5) 1/fADC - - 0.067 µs - - 2(5) 1/fADC 0.100 - 16 µs 3 - 480 1/fADC - 2 3 µs fADC = 30 MHz 12-bit resolution 0.50 - 16.40 µs fADC = 30 MHz 10-bit resolution 0.43 - 16.34 µs fADC = 30 MHz 8-bit resolution 0.37 - 16.27 µs fADC = 30 MHz 6-bit resolution 0.30 - 16.20 µs VDDA − VREF+ < 1.2 V (1) fADC fTRIG(2) VAIN RAIN(2) ADC clock frequency External trigger frequency VDDA = 1.7 to 2.4 V Conversion voltage range(3) External input impedance See Equation 1 for details RADC(2)(4) Sampling switch resistance CADC(2) Internal sample and hold capacitor tlat(2) Injection trigger conversion latency fADC = 30 MHz tlatr(2) Regular trigger conversion latency fADC = 30 MHz tS(2) Sampling time tSTAB(2) Power-up time tCONV(2) Total conversion time (including sampling time) fADC = 30 MHz Min 9 to 492 (tS for sampling +n-bit resolution for successive approximation) DocID024244 Rev 11 Unit V 1/fADC 159/241 199 Electrical characteristics STM32F437xx and STM32F439xx Table 74. ADC characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit 12-bit resolution Single ADC - - 2 Msps 12-bit resolution Interleave Dual ADC mode - - 3.75 Msps 12-bit resolution Interleave Triple ADC mode - - 6 Msps Sampling rate fS(2) (fADC = 30 MHz, and tS = 3 ADC cycles) IVREF+(2) ADC VREF DC current consumption in conversion mode - 300 500 µA IVDDA(2) ADC VDDA DC current consumption in conversion mode - 1.6 1.8 mA 1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.17.2: Internal reset OFF). 2. Guaranteed by characterization results. 3. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA. 4. RADC maximum value is given for VDD=1.7 V, and minimum value for VDD=3.3 V. 5. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 74. Equation 1: RAIN max formula R AIN ( k – 0.5 ) - – R ADC = --------------------------------------------------------------N+2 f ADC × C ADC × ln ( 2 ) The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the ADC_SMPR1 register. Table 75. ADC static accuracy at fADC = 18 MHz Symbol ET Parameter Test conditions Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fADC =18 MHz VDDA = 1.7 to 3.6 V VREF = 1.7 to 3.6 V VDDA − VREF < 1.2 V 1. Guaranteed by characterization results. 160/241 DocID024244 Rev 11 Typ Max(1) ±3 ±4 ±2 ±3 ±1 ±3 ±1 ±2 ±2 ±3 Unit LSB STM32F437xx and STM32F439xx a Table 76. ADC static accuracy at fADC = 30 MHz Symbol ET Electrical characteristics Parameter Test conditions Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fADC = 30 MHz, RAIN < 10 kΩ, VDDA = 2.4 to 3.6 V, VREF = 1.7 to 3.6 V, VDDA − VREF < 1.2 V Typ Max(1) ±2 ±5 ±1.5 ±2.5 ±1.5 ±3 ±1 ±2 ±1.5 ±3 Unit LSB 1. Guaranteed by characterization results. Table 77. ADC static accuracy at fADC = 36 MHz Symbol ET Parameter Test conditions Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fADC =36 MHz, VDDA = 2.4 to 3.6 V, VREF = 1.7 to 3.6 V VDDA − VREF < 1.2 V Typ Max(1) ±4 ±7 ±2 ±3 ±3 ±6 ±2 ±3 ±3 ±6 Unit LSB 1. Guaranteed by characterization results. Table 78. ADC dynamic accuracy at fADC = 18 MHz - limited test conditions(1) Symbol Parameter Test conditions ENOB Effective number of bits SINAD Signal-to-noise and distortion ratio SNR Signal-to-noise ratio THD Total harmonic distortion fADC =18 MHz VDDA = VREF+= 1.7 V Input Frequency = 20 KHz Temperature = 25 °C Min Typ Max Unit 10.3 10.4 - bits 64 64.2 - 64 65 - − 67 − 72 - dB 1. Guaranteed by characterization results. Table 79. ADC dynamic accuracy at fADC = 36 MHz - limited test conditions(1) Symbol Parameter Test conditions ENOB Effective number of bits SINAD Signal-to noise and distortion ratio SNR Signal-to noise ratio THD Total harmonic distortion fADC =36 MHz VDDA = VREF+ = 3.3 V Input Frequency = 20 KHz Temperature = 25 °C Min Typ Max Unit 10.6 10.8 - bits 66 67 - 64 68 - − 70 − 72 - dB 1. Guaranteed by characterization results. DocID024244 Rev 11 161/241 199 Electrical characteristics Note: STM32F437xx and STM32F439xx ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.17 does not affect the ADC accuracy. Figure 50. ADC accuracy characteristics 6 2%& 6 $$! ;,3" )$%!, ORDEPENDINGONPACKAGE =   %'     %4      %/  %,  %$  , 3")$%!,   6 33!          6$$! 1. See also Table 76. 2. Example of an actual transfer curve. 3. Ideal transfer curve. 4. End point correlation line. 5. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO = Offset Error: deviation between the first actual transition and the first ideal one. EG = Gain Error: deviation between the last ideal transition and the last actual one. ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL = Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. 162/241 DocID024244 Rev 11 AIC STM32F437xx and STM32F439xx Electrical characteristics Figure 51. Typical connection diagram using the ADC 670) 9'' 5$,1 $,1[ 9$,1 &SDUDVLWLF 6DPSOHDQGKROG$'& FRQYHUWHU 97 9 5$'& 97 9 ,/“—$ ELW FRQYHUWHU & $'& DL 1. Refer to Table 74 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this, fADC should be reduced. DocID024244 Rev 11 163/241 199 Electrical characteristics STM32F437xx and STM32F439xx General PCB design guidelines Power supply decoupling should be performed as shown in Figure 52 or Figure 53, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 52. Power supply and reference decoupling (VREF+ not connected to VDDA) 670) 95() —)Q) 9''$ —)Q)  966$95() DLE 1. VREF+ and VREF– inputs are both available on UFBGA176. VREF+ is also available on LQFP100, LQFP144, and LQFP176. When VREF+ and VREF– are not available, they are internally connected to VDDA and VSSA. 164/241 DocID024244 Rev 11 STM32F437xx and STM32F439xx Electrical characteristics Figure 53. Power supply and reference decoupling (VREF+ connected to VDDA) 670) 95()9''$  —)Q)  95()966$ DLF 1. VREF+ and VREF– inputs are both available on UFBGA176. VREF+ is also available on LQFP100, LQFP144, and LQFP176. When VREF+ and VREF– are not available, they are internally connected to VDDA and VSSA. 6.3.22 Temperature sensor characteristics Table 80. Temperature sensor characteristics Symbol TL(1) Parameter Min Typ Max Unit - ±1 ±2 °C - 2.5 mV/°C Voltage at 25 °C - 0.76 V Startup time - 6 10 µs 10 - - µs VSENSE linearity with temperature Avg_Slope(1) Average slope V25(1) tSTART (2) TS_temp(2) ADC sampling time when reading the temperature (1 °C accuracy) 1. Guaranteed by characterization results. 2. Guaranteed by design. Table 81. Temperature sensor calibration values Symbol Parameter Memory address TS_CAL1 TS ADC raw data acquired at temperature of 30 °C, VDDA= 3.3 V 0x1FFF 7A2C - 0x1FFF 7A2D TS_CAL2 TS ADC raw data acquired at temperature of 110 °C, VDDA= 3.3 V 0x1FFF 7A2E - 0x1FFF 7A2F DocID024244 Rev 11 165/241 199 Electrical characteristics 6.3.23 STM32F437xx and STM32F439xx VBAT monitoring characteristics Table 82. VBAT monitoring characteristics Symbol Parameter Min Typ Max Unit KΩ R Resistor bridge for VBAT - 50 - Q Ratio on VBAT measurement - 4 - Error on Q –1 - +1 % ADC sampling time when reading the VBAT 1 mV accuracy 5 - - µs Er (1) TS_vbat(2)(2) 1. Guaranteed by design. 2. Shortest sampling time can be determined in the application by multiple iterations. 6.3.24 Reference voltage The parameters given in Table 83 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 17. Table 83. internal reference voltage Symbol VREFINT TS_vrefint(1) VRERINT_s(2) Parameter Internal reference voltage Conditions Min Typ Max Unit –40 °C < TA < +105 °C 1.18 1.21 1.24 V 10 - - µs - 3 5 mV ADC sampling time when reading the internal reference voltage Internal reference voltage spread over the temperature range VDD = 3V ± 10mV TCoeff(2) Temperature coefficient - 30 50 ppm/°C tSTART(2) Startup time - 6 10 µs 1. Shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design, not tested in production Table 84. Internal reference voltage calibration values Symbol VREFIN_CAL 166/241 Parameter Raw data acquired at temperature of 30 °C VDDA = 3.3 V DocID024244 Rev 11 Memory address 0x1FFF 7A2A - 0x1FFF 7A2B STM32F437xx and STM32F439xx 6.3.25 Electrical characteristics DAC electrical characteristics Table 85. DAC characteristics Symbol Parameter Conditions Min Typ VDDA Analog supply voltage - 1.7(1) - 3.6 V - VREF+ Reference supply voltage - 1.7(1) - 3.6 V VREF+ ≤VDDA VSSA Ground - 0 - 0 V - 5 - - RLOAD(2) Resistive load RLOAD connected DAC output to VSSA buffer ON R LOAD connected to VDDA Max Unit Comments kΩ 25 - - - - 15 When the buffer is OFF, the Minimum resistive load kΩ between DAC_OUT and VSS to have a 1% accuracy is 1.5 MΩ CLOAD(2) Capacitive load - - - 50 Maximum capacitive load at pF DAC_OUT pin (when the buffer is ON). DAC_O Lower DAC_OUT UT (2) voltage with buffer ON min - 0.2 - - V DAC_O Higher DAC_OUT UT voltage with buffer ON (2) max - - - VDDA − 0.2 V DAC_O Lower DAC_OUT UT voltage with buffer min(2) OFF - - 0.5 - mV - VREF+ − 1LSB RO(2) Impedance output with buffer OFF DAC_O Higher DAC_OUT UT voltage with buffer max(2) OFF DAC DC VREF current consumption in IVREF+(4) quiescent mode (Standby mode) - - - - 170 It gives the maximum output excursion of the DAC. V 240 µA - - 50 DocID024244 Rev 11 75 It gives the maximum output excursion of the DAC. It corresponds to 12-bit input code (0x0E0) to (0xF1C) at VREF+ = 3.6 V and (0x1C7) to (0xE38) at VREF+ = 1.7 V With no load, worst code (0x800) at VREF+ = 3.6 V in terms of DC consumption on the inputs With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs 167/241 199 Electrical characteristics STM32F437xx and STM32F439xx Table 85. DAC characteristics (continued) Symbol Parameter DAC DC VDDA IDDA(4) current consumption in quiescent mode(3) Conditions Min Typ Max Unit Comments - - 280 380 µA 625 With no load, worst code (0xF1C) at VREF+ = 3.6 V in µA terms of DC consumption on the inputs With no load, middle code (0x800) on the inputs - - 475 - - - - - - ±2 LSB Given for the DAC in 12-bit configuration. - - - ±1 LSB Given for the DAC in 10-bit configuration. - - - ±4 LSB Given for the DAC in 12-bit configuration. - - - ±10 mV Given for the DAC in 12-bit configuration - - - ±3 LSB Given for the DAC in 10-bit at VREF+ = 3.6 V - - - ±12 LSB Given for the DAC in 12-bit at VREF+ = 3.6 V Gain Gain error error(4) - - - ±0.5 % Given for the DAC in 12-bit configuration Settling time (full scale: for a 10-bit input code transition tSETTLIN between the lowest (4) and the highest input G codes when DAC_OUT reaches final value ±4LSB - - 3 6 µs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ Total Harmonic THD(4) Distortion Buffer ON - - - - dB CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ Max frequency for a correct DAC_OUT Update change when small rate(2) variation in the input code (from code i to i+1LSB) - - - 1 MS/ CLOAD ≤ 50 pF, s RLOAD ≥ 5 kΩ Differential non linearity Difference DNL(4) between two consecutive code1LSB) INL(4) Integral non linearity (difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023) Offset error (difference between Offset(4) measured value at Code (0x800) and the ideal value = VREF+/2) 168/241 DocID024244 Rev 11 ±0.5 LSB Given for the DAC in 10-bit configuration. STM32F437xx and STM32F439xx Electrical characteristics Table 85. DAC characteristics (continued) Symbol Conditions Min Typ Wakeup time from off tWAKEUP( state (Setting the ENx 4) bit in the DAC Control register) - - 6.5 10 CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ µs input code between lowest and highest possible ones. Power supply rejection ratio (to VDDA) (static DC measurement) - - –67 –40 dB No RLOAD, CLOAD = 50 pF PSRR+ (2) Parameter Max Unit Comments 1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.17.2: Internal reset OFF). 2. Guaranteed by design. 3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic consumption occurs. 4. Guaranteed by characterization. Figure 54. 12-bit buffered /non-buffered DAC %XIIHUHGQRQEXIIHUHG'$& %XIIHU  5/2$' ELW GLJLWDOWR DQDORJ FRQYHUWHU '$&[B287 &/2$' DLD 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. DocID024244 Rev 11 169/241 199 Electrical characteristics 6.3.26 STM32F437xx and STM32F439xx FMC characteristics Unless otherwise specified, the parameters given in Table 86 to Table 101 for the FMC interface are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage conditions summarized in Table 17, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 except at VDD range 1.7 to 2.1V where OSPEEDRy[1:0] = 11 • Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.17: I/O port characteristics for more details on the input/output characteristics. Asynchronous waveforms and timings Figure 55 through Figure 58 represent asynchronous waveforms and Table 86 through Table 93 provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration: 170/241 • AddressSetupTime = 0x1 • AddressHoldTime = 0x1 • DataSetupTime = 0x1 (except for asynchronous NWAIT mode , DataSetupTime = 0x5) • BusTurnAroundDuration = 0x0 • For SDRAM memories, VDD ranges from 2.7 to 3.6 V and maximum frequency FMC_SDCLK = 90 MHz • For Mobile LPSDR SDRAM memories, VDD ranges from 1.7 to 1.95 V and maximum frequency FMC_SDCLK = 84 MHz DocID024244 Rev 11 STM32F437xx and STM32F439xx Electrical characteristics Figure 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms TW.% &-#?.% TV./%?.% T W./% T H.%?./% &-#?./% &-#?.7% TV!?.% &-#?!;= T H!?./% !DDRESS TV",?.% T H",?./% &-#?.",;= T H$ATA?.% T SU$ATA?./% TH$ATA?./% T SU$ATA?.% $ATA &-#?$;= T V.!$6?.% TW.!$6 &-#?.!$6  &-#?.7!)4 TH.%?.7!)4 TSU.7!)4?.% -36 1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used. Table 86. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)(2) Symbol Min Max Unit 2THCLK − 0.5 2 THCLK+0.5 ns 0 1 ns 2THCLK 2THCLK+ 0.5 ns FMC_NOE high to FMC_NE high hold time 0 - ns FMC_NEx low to FMC_A valid - 2 ns th(A_NOE) Address hold time after FMC_NOE high 0 - ns tv(BL_NE) FMC_NEx low to FMC_BL valid - 2 ns th(BL_NOE) FMC_BL hold time after FMC_NOE high 0 - ns tsu(Data_NE) Data to FMC_NEx high setup time THCLK + 2.5 - ns THCLK +2 - ns tw(NE) tv(NOE_NE) tw(NOE) th(NE_NOE) tv(A_NE) tsu(Data_NOE) Parameter FMC_NE low time FMC_NEx low to FMC_NOE low FMC_NOE low time Data to FMC_NOEx high setup time DocID024244 Rev 11 171/241 199 Electrical characteristics STM32F437xx and STM32F439xx Table 86. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)(2) (continued) Symbol Parameter Min Max Unit th(Data_NOE) Data hold time after FMC_NOE high 0 - ns th(Data_NE) Data hold time after FMC_NEx high 0 - ns tv(NADV_NE) FMC_NEx low to FMC_NADV low - 0 ns FMC_NADV low time - THCLK +1 ns tw(NADV) 1. CL = 30 pF. 2. Guaranteed by characterization results. Table 87. Asynchronous non-multiplexed SRAM/PSRAM/NOR read NWAIT timings(1)(2) Symbol Min Max FMC_NE low time 7THCLK+0.5 7THCLK+1 FMC_NWE low time 5THCLK − 1.5 5THCLK +2 tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5THCLK+1.5 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4THCLK+1 - tw(NE) tw(NOE) Parameter 1. CL = 30 pF. 2. Guaranteed by characterization results. 172/241 DocID024244 Rev 11 Unit ns STM32F437xx and STM32F439xx Electrical characteristics Figure 56. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms TW.% &-#?.%X &-#?./% TV.7%?.% TW.7% T H.%?.7% &-#?.7% TV!?.% &-#?!;= TH!?.7% !DDRESS TV",?.% &-#?.",;= TH",?.7% .", TV$ATA?.% TH$ATA?.7% $ATA &-#?$;= T V.!$6?.% &-#?.!$6  TW.!$6 &-#?.7!)4 TH.%?.7!)4 TSU.7!)4?.% -36 1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used. Table 88. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2) Symbol tw(NE) tv(NWE_NE) tw(NWE) th(NE_NWE) tv(A_NE) Parameter FMC_NE low time FMC_NEx low to FMC_NWE low FMC_NWE low time FMC_NWE high to FMC_NE high hold time FMC_NEx low to FMC_A valid th(A_NWE) Address hold time after FMC_NWE high tv(BL_NE) FMC_NEx low to FMC_BL valid Min Max Unit 3THCLK 3THCLK+1 ns THCLK − 0.5 THCLK+ 0.5 ns THCLK THCLK+ 0.5 ns THCLK +1.5 - ns - 0 ns THCLK+0.5 - ns - 1.5 ns THCLK+0.5 - ns th(BL_NWE) FMC_BL hold time after FMC_NWE high tv(Data_NE) Data to FMC_NEx low to Data valid - THCLK+ 2 ns th(Data_NWE) Data hold time after FMC_NWE high THCLK+0.5 - ns tv(NADV_NE) FMC_NEx low to FMC_NADV low - 0.5 ns FMC_NADV low time - THCLK+ 0.5 ns tw(NADV) 1. CL = 30 pF. 2. Guaranteed by characterization results. DocID024244 Rev 11 173/241 199 Electrical characteristics STM32F437xx and STM32F439xx Table 89. Asynchronous non-multiplexed SRAM/PSRAM/NOR write NWAIT timings(1)(2) Symbol Parameter Min Max Unit FMC_NE low time 8THCLK+1 8THCLK+2 ns FMC_NWE low time 6THCLK − 1 6THCLK+2 ns tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 6THCLK+1.5 - ns th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid tw(NE) tw(NWE) 4THCLK+1 ns 1. CL = 30 pF. 2. Guaranteed by characterization results. Figure 57. Asynchronous multiplexed PSRAM/NOR read waveforms TW.% &-#? .% TV./%?.% T H.%?./% &-#?./% T W./% &-#?.7% TH!?./% TV!?.% &-#? !;= !DDRESS TV",?.% TH",?./% &-#? .",;= .", TH$ATA?.% TSU$ATA?.% T V!?.% &-#? !$;= T V.!$6?.% TSU$ATA?./% TH$ATA?./% $ATA !DDRESS TH!$?.!$6 TW.!$6 &-#?.!$6 &-#?.7!)4 TH.%?.7!)4 TSU.7!)4?.% -36 174/241 DocID024244 Rev 11 STM32F437xx and STM32F439xx Electrical characteristics Table 90. Asynchronous multiplexed PSRAM/NOR read timings(1)(2) Symbol tw(NE) tv(NOE_NE) ttw(NOE) th(NE_NOE) tv(A_NE) tv(NADV_NE) tw(NADV) Parameter Min Max Unit 3THCLK − 1 3THCLK+0.5 ns 2THCLK − 0.5 2THCLK ns THCLK − 1 THCLK+1 ns FMC_NOE high to FMC_NE high hold time 1 - ns FMC_NEx low to FMC_A valid - 2 ns FMC_NEx low to FMC_NADV low 0 2 ns THCLK − 0.5 THCLK+0.5 ns FMC_NE low time FMC_NEx low to FMC_NOE low FMC_NOE low time FMC_NADV low time th(AD_NADV) FMC_AD(address) valid hold time after FMC_NADV high) 0 - ns th(A_NOE) Address hold time after FMC_NOE high THCLK − 0.5 - ns th(BL_NOE) FMC_BL time after FMC_NOE high 0 - ns FMC_NEx low to FMC_BL valid - 2 ns tv(BL_NE) tsu(Data_NE) Data to FMC_NEx high setup time THCLK+1.5 - ns tsu(Data_NOE) Data to FMC_NOE high setup time THCLK+1 - ns th(Data_NE) Data hold time after FMC_NEx high 0 - ns th(Data_NOE) Data hold time after FMC_NOE high 0 - ns 1. CL = 30 pF. 2. Guaranteed by characterization results. Table 91. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1)(2) Symbol tw(NE) tw(NOE) Parameter Min Max Unit FMC_NE low time 8THCLK+0.5 8THCLK+2 ns FMC_NWE low time 5THCLK − 1 5THCLK +1.5 ns 5THCLK +1.5 - ns tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4THCLK+1 ns 1. CL = 30 pF. 2. Guaranteed by characterization results. DocID024244 Rev 11 175/241 199 Electrical characteristics STM32F437xx and STM32F439xx Figure 58. Asynchronous multiplexed PSRAM/NOR write waveforms TW.% &-#? .%X &-#?./% TW.7% TV.7%?.% T H.%?.7% &-#?.7% TH!?.7% TV!?.% &-#? !;= !DDRESS TV",?.% &-#? .",;= TH",?.7% .", T V!?.% T V$ATA?.!$6 !DDRESS &-#? !$;= TH$ATA?.7% $ATA TH!$?.!$6 T V.!$6?.% TW.!$6 &-#?.!$6 &-#?.7!)4 TH.%?.7!)4 TSU.7!)4?.% -36 Table 92. Asynchronous multiplexed PSRAM/NOR write timings(1)(2) Symbol tw(NE) tv(NWE_NE) tw(NWE) th(NE_NWE) tv(A_NE) tv(NADV_NE) tw(NADV) th(AD_NADV) Parameter Min Max Unit 4THCLK 4THCLK+0.5 ns THCLK − 1 THCLK+0.5 ns FMC_NWE low time 2THCLK 2THCLK+0.5 ns FMC_NWE high to FMC_NE high hold time THCLK - ns - 0 ns 0.5 1 ns THCLK − 0.5 THCLK+ 0.5 ns THCLK − 2 - ns FMC_NE low time FMC_NEx low to FMC_NWE low FMC_NEx low to FMC_A valid FMC_NEx low to FMC_NADV low FMC_NADV low time FMC_AD(adress) valid hold time after FMC_NADV high) th(A_NWE) Address hold time after FMC_NWE high THCLK - ns th(BL_NWE) FMC_BL hold time after FMC_NWE high THCLK − 2 - ns tv(BL_NE) FMC_NEx low to FMC_BL valid - 2 ns tv(Data_NADV) FMC_NADV high to Data valid - THCLK +1.5 ns th(Data_NWE) Data hold time after FMC_NWE high THCLK +0.5 - ns 1. CL = 30 pF. 2. Guaranteed by characterization results. 176/241 DocID024244 Rev 11 STM32F437xx and STM32F439xx Electrical characteristics Table 93. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)(2) Symbol tw(NE) tw(NWE) Parameter Min Max Unit FMC_NE low time 9THCLK 9THCLK+0.5 ns FMC_NWE low time 7THCLK 7THCLK+2 ns 6THCLK+1.5 - ns 4THCLK–1 - ns tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 1. CL = 30 pF. 2. Guaranteed by characterization results. Synchronous waveforms and timings Figure 59 through Figure 62 represent synchronous waveforms and Table 94 through Table 97 provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration: • BurstAccessMode = FMC_BurstAccessMode_Enable; • MemoryType = FMC_MemoryType_CRAM; • WriteBurst = FMC_WriteBurst_Enable; • CLKDivision = 1; (0 is not supported, see the STM32F4xx reference manual : RM0090) • DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM In all timing tables, the THCLK is the HCLK clock period (with maximum FMC_CLK = 90 MHz). DocID024244 Rev 11 177/241 199 Electrical characteristics STM32F437xx and STM32F439xx Figure 59. Synchronous multiplexed NOR/PSRAM read timings "53452. TW#,+ TW#,+ &-#?#,+ $ATALATENCY TD#,+, .%X, &-#?.%X T D#,+, .!$6, TD#,+( .%X( TD#,+, .!$6( &-#?.!$6 TD#,+, !6 TD#,+( !)6 &-#?!;= TD#,+, ./%, TD#,+( ./%( &-#?./% T D#,+, !$6 &-#?!$;= TD#,+, !$)6 TSU!$6 #,+( !$;= TH#,+( !$6 TSU!$6 #,+( $ TSU.7!)46 #,+( &-#?.7!)4 7!)4#&'B 7!)40/,B TSU.7!)46 #,+( &-#?.7!)4 7!)4#&'B 7!)40/,B TSU.7!)46 #,+( TH#,+( !$6 $ TH#,+( .7!)46 TH#,+( .7!)46 TH#,+( .7!)46 -36 Table 94. Synchronous multiplexed NOR/PSRAM read timings(1)(2) Symbol tw(CLK) 178/241 Parameter FMC_CLK period Min Max Unit 2THCLK − 1 - ns - 0 ns THCLK - ns td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) td(CLKH_NExH) FMC_CLK high to FMC_NEx high (x= 0…2) td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 0 ns td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - ns td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 0 ns td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) 0 - ns td(CLKL-NOEL) FMC_CLK low to FMC_NOE low - THCLK+0.5 ns td(CLKH-NOEH) FMC_CLK high to FMC_NOE high THCLK − 0.5 - ns td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 0.5 ns td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 - ns DocID024244 Rev 11 STM32F437xx and STM32F439xx Electrical characteristics Table 94. Synchronous multiplexed NOR/PSRAM read timings(1)(2) (continued) Symbol Parameter Min Max Unit tsu(ADV-CLKH) FMC_A/D[15:0] valid data before FMC_CLK high 5 - ns th(CLKH-ADV) FMC_A/D[15:0] valid data after FMC_CLK high 0 - ns tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 4 - ns th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 0 - ns 1. CL = 30 pF. 2. Guaranteed by characterization results. Figure 60. Synchronous multiplexed PSRAM write timings "53452. TW#,+ TW#,+ &-#?#,+ $ATALATENCY TD#,+, .%X, TD#,+( .%X( &-#?.%X TD#,+, .!$6, TD#,+, .!$6( &-#?.!$6 TD#,+( !)6 TD#,+, !6 &-#?!;= TD#,+( .7%( TD#,+, .7%, &-#?.7% TD#,+, !$)6 TD#,+, !$6 &-#?!$;= TD#,+, $ATA TD#,+, $ATA !$;= $ $ &-#?.7!)4 7!)4#&'B 7!)40/,B TSU.7!)46 #,+( TH#,+( .7!)46 TD#,+( .",( &-#?.", -36 DocID024244 Rev 11 179/241 199 Electrical characteristics STM32F437xx and STM32F439xx Table 95. Synchronous multiplexed PSRAM write timings(1)(2) Symbol Min Max Unit 2THCLK − 1 - ns - 1.5 ns THCLK - ns td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 0 ns td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - ns - 0 ns THCLK - ns - 0 ns THCLK −0.5 - ns tw(CLK) Parameter FMC_CLK period, VDD range= 2.7 to 3.6 V td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) td(CLKL-NWEL) FMC_CLK low to FMC_NWE low t(CLKH-NWEH) FMC_CLK high to FMC_NWE high td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 3 ns td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 - ns td(CLKL-DATA) FMC_A/D[15:0] valid data after FMC_CLK low - 3 ns td(CLKL-NBLL) FMC_CLK low to FMC_NBL low 0 - ns td(CLKH-NBLH) FMC_CLK high to FMC_NBL high THCLK −0.5 - ns tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 4 - ns th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 0 - ns 1. CL = 30 pF. 2. Guaranteed by characterization results. 180/241 DocID024244 Rev 11 STM32F437xx and STM32F439xx Electrical characteristics Figure 61. Synchronous non-multiplexed NOR/PSRAM read timings TW#,+ TW#,+ &-#?#,+ TD#,+, .%X, TD#,+( .%X( $ATALATENCY &-#?.%X TD#,+, .!$6, TD#,+, .!$6( &-#?.!$6 TD#,+( !)6 TD#,+, !6 &-#?!;= TD#,+, ./%, TD#,+( ./%( &-#?./% TSU$6 #,+( TH#,+( $6 TSU$6 #,+( &-#?$;= TH#,+( $6 $ &-#?.7!)4 7!)4#&'B 7!)40/,B TSU.7!)46 #,+( TH#,+( .7!)46 TSU.7!)46 #,+( &-#?.7!)4 7!)4#&'B 7!)40/,B $ TSU.7!)46 #,+( T H#,+( .7!)46 TH#,+( .7!)46 -36 Table 96. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2) Symbol Min Max Unit 2THCLK − 1 - ns - 0.5 ns THCLK - ns FMC_CLK low to FMC_NADV low - 0 ns FMC_CLK low to FMC_NADV high 0 - ns td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 0 ns td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) THCLK − 0.5 - ns - THCLK+2 ns THCLK − 0.5 - ns 5 - ns tw(CLK) t(CLKL-NExL) td(CLKHNExH) td(CLKLNADVL) td(CLKLNADVH) Parameter FMC_CLK period FMC_CLK low to FMC_NEx low (x=0..2) FMC_CLK high to FMC_NEx high (x= 0…2) td(CLKL-NOEL) FMC_CLK low to FMC_NOE low td(CLKHNOEH) FMC_CLK high to FMC_NOE high tsu(DV-CLKH) FMC_D[15:0] valid data before FMC_CLK high DocID024244 Rev 11 181/241 199 Electrical characteristics STM32F437xx and STM32F439xx Table 96. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2) (continued) Symbol Parameter th(CLKH-DV) FMC_D[15:0] valid data after FMC_CLK high t(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high th(CLKH- Max Unit 0 - ns 4 FMC_NWAIT valid after FMC_CLK high NWAIT) Min 0 1. CL = 30 pF. 2. Guaranteed by characterization results. Figure 62. Synchronous non-multiplexed PSRAM write timings TW#,+ TW#,+ &-#?#,+ TD#,+, .%X, TD#,+( .%X( $ATALATENCY &-#?.%X TD#,+, .!$6, TD#,+, .!$6( &-#?.!$6 TD#,+( !)6 TD#,+, !6 &-#?!;= TD#,+, .7%, TD#,+( .7%( &-#?.7% TD#,+, $ATA TD#,+, $ATA $ &-#?$;= $ &-#?.7!)4 7!)4#&'B7!)40/,B TSU.7!)46 #,+( TD#,+( .",( TH#,+( .7!)46 &-#?.", -36 Table 97. Synchronous non-multiplexed PSRAM write timings(1)(2) Symbol Min Max Unit 2THCLK − 1 - ns - 0.5 ns THCLK - ns td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 0 ns td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - ns - 0 ns t(CLK) FMC_CLK period td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) t(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) td(CLKL-AV) 182/241 Parameter FMC_CLK low to FMC_Ax valid (x=16…25) DocID024244 Rev 11 STM32F437xx and STM32F439xx Electrical characteristics Table 97. Synchronous non-multiplexed PSRAM write timings(1)(2) (continued) Symbol td(CLKH-AIV) td(CLKL-NWEL) Parameter Min Max Unit FMC_CLK high to FMC_Ax invalid (x=16…25) 0 - ns FMC_CLK low to FMC_NWE low - 0 ns THCLK −0.5 - ns td(CLKH-NWEH) FMC_CLK high to FMC_NWE high td(CLKL-Data) FMC_D[15:0] valid data after FMC_CLK low - 2.5 ns td(CLKL-NBLL) FMC_CLK low to FMC_NBL low 0 - ns td(CLKH-NBLH) FMC_CLK high to FMC_NBL high THCLK −0.5 - ns tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 4 th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 0 1. CL = 30 pF. 2. Guaranteed by characterization results. PC Card/CompactFlash controller waveforms and timings Figure 63 through Figure 68 represent synchronous waveforms, and Table 98 and Table 99 provide the corresponding timings. The results shown in this table are obtained with the following FMC configuration: • COM.FMC_SetupTime = 0x04; • COM.FMC_WaitSetupTime = 0x07; • COM.FMC_HoldSetupTime = 0x04; • COM.FMC_HiZSetupTime = 0x00; • ATT.FMC_SetupTime = 0x04; • ATT.FMC_WaitSetupTime = 0x07; • ATT.FMC_HoldSetupTime = 0x04; • ATT.FMC_HiZSetupTime = 0x00; • IO.FMC_SetupTime = 0x04; • IO.FMC_WaitSetupTime = 0x07; • IO.FMC_HoldSetupTime = 0x04; • IO.FMC_HiZSetupTime = 0x00; • TCLRSetupTime = 0; • TARSetupTime = 0. In all timing tables, the THCLK is the HCLK clock period. DocID024244 Rev 11 183/241 199 Electrical characteristics STM32F437xx and STM32F439xx Figure 63. PC Card/CompactFlash controller waveforms for common memory read access &-#?.#%? &-#?.#%? TH.#%X !) TV.#%X ! &-#?!;= TH.#%X .2%' TH.#%X .)/2$ TH.#%X .)/72 TD.2%' .#%X TD.)/2$ .#%X &-#?.2%' &-#?.)/72 &-#?.)/2$ &-#?.7% TD.#%? ./% &-#?./% TW./% TSU$ ./% TH./% $ &-#?$;= -36 1. FMC_NCE4_2 remains high (inactive during 8-bit access. Figure 64. PC Card/CompactFlash controller waveforms for common memory write access &-#?.#%? &-#?.#%? (IGH TV.#%? ! TH.#%? !) &-#?!;= TH.#%? .2%' TH.#%? .)/2$ TH.#%? .)/72 TD.2%' .#%? TD.)/2$ .#%? &-#?.2%' &-#?.)/72 &-#?.)/2$ TD.#%? .7% TW.7% TD.7% .#%? &-#?.7% &-#?./% -%-X(): TD$ .7% TV.7% $ TH.7% $ &-#?$;= -36 184/241 DocID024244 Rev 11 STM32F437xx and STM32F439xx Electrical characteristics Figure 65. PC Card/CompactFlash controller waveforms for attribute memory read access &-#?.#%? TV.#%? ! &-#?.#%? TH.#%? !) (IGH &-#?!;= &-#?.)/72 &-#?.)/2$ TD.2%' .#%? TH.#%? .2%' &-#?.2%' &-#?.7% TD.#%? ./% TW./% TD./% .#%? &-#?./% TSU$ ./% TH./% $ &-#?$;= -36 1. Only data bits 0...7 are read (bits 8...15 are disregarded). DocID024244 Rev 11 185/241 199 Electrical characteristics STM32F437xx and STM32F439xx Figure 66. PC Card/CompactFlash controller waveforms for attribute memory write access &-#?.#%? &-#?.#%? (IGH TV.#%? ! TH.#%? !) &-#?!;= &-#?.)/72 &-#?.)/2$ TD.2%' .#%? TH.#%? .2%' &-#?.2%' TD.#%? .7% TW.7% &-#?.7% TD.7% .#%? &-#?./% TV.7% $ &-#?$;= -36 1. Only data bits 0...7 are driven (bits 8...15 remains Hi-Z). Figure 67. PC Card/CompactFlash controller waveforms for I/O space read access &-#?.#%? &-#?.#%? TH.#%? !) TV.#%X ! &-#?!;= &-#?.2%' &-#?.7% &-#?./% &-#?.)/72 TW.)/2$ TD.)/2$ .#%? &-#?.)/2$ TSU$ .)/2$ TD.)/2$ $ &-#?$;= -36 186/241 DocID024244 Rev 11 STM32F437xx and STM32F439xx Electrical characteristics Figure 68. PC Card/CompactFlash controller waveforms for I/O space write access &-#?.#%? &-#?.#%? TV.#%X ! TH.#%? !) &-#?!;= &-#?.2%' &-#?.7% &-#?./% &-#?.)/2$ T D.#%? .)/72 TW.)/72 &-#?.)/72 !44X(): TV.)/72 $ TH.)/72 $ &-#?$;= -36 Table 98. Switching characteristics for PC Card/CF read and write cycles in attribute/common space(1)(2) Symbol Parameter Min Max Unit tv(NCEx-A) FMC_Ncex low to FMC_Ay valid - 0 ns th(NCEx_AI) FMC_NCEx high to FMC_Ax invalid 0 - ns td(NREG-NCEx) FMC_NCEx low to FMC_NREG valid - 1 ns th(NCEx-NREG) FMC_NCEx high to FMC_NREG invalid THCLK − 2 - ns td(NCEx-NWE) FMC_NCEx low to FMC_NWE low - 5THCLK ns 8THCLK − 0.5 8THCLK+0.5 ns tw(NWE) FMC_NWE low width td(NWE_NCEx) FMC_NWE high to FMC_NCEx high 5THCLK+1 - ns tV(NWE-D) FMC_NWE low to FMC_D[15:0] valid - 0 ns th(NWE-D) FMC_NWE high to FMC_D[15:0] invalid 9THCLK − 0.5 - ns td(D-NWE) FMC_D[15:0] valid before FMC_NWE high 13THCLK − 3 td(NCEx-NOE) tw(NOE) td(NOE_NCEx) tsu (D-NOE) th(NOE-D) FMC_NCEx low to FMC_NOE low FMC_NOE low width FMC_NOE high to FMC_NCEx high FMC_D[15:0] valid data before FMC_NOE high FMC_NOE high to FMC_D[15:0] invalid ns - 5THCLK ns 8 THCLK − 0.5 8 THCLK+0.5 ns 5THCLK − 1 - ns THCLK - ns 0 - ns 1. CL = 30 pF. 2. Guaranteed by characterization results. DocID024244 Rev 11 187/241 199 Electrical characteristics STM32F437xx and STM32F439xx Table 99. Switching characteristics for PC Card/CF read and write cycles in I/O space(1)(2) Symbol Parameter tw(NIOWR) FMC_NIOWR low width tv(NIOWR-D) FMC_NIOWR low to FMC_D[15:0] valid th(NIOWR-D) FMC_NIOWR high to FMC_D[15:0] invalid Min Max Unit 8THCLK − 0.5 - ns - 0 ns 9THCLK − 2 - ns - 5THCLK ns 5THCLK - ns - 5THCLK ns 6THCLK+2 - ns 8THCLK − 0.5 8THCLK+0.5 ns THCLK - ns 0 - ns td(NCE4_1-NIOWR) FMC_NCE4_1 low to FMC_NIOWR valid th(NCEx-NIOWR) FMC_NCEx high to FMC_NIOWR invalid td(NIORD-NCEx) FMC_NCEx low to FMC_NIORD valid th(NCEx-NIORD) FMC_NCEx high to FMC_NIORD) valid tw(NIORD) FMC_NIORD low width tsu(D-NIORD) FMC_D[15:0] valid before FMC_NIORD high td(NIORD-D) FMC_D[15:0] valid after FMC_NIORD high 1. CL = 30 pF. 2. Guaranteed by characterization results. NAND controller waveforms and timings Figure 69 through Figure 72 represent synchronous waveforms, and Table 100 and Table 101 provide the corresponding timings. The results shown in this table are obtained with the following FMC configuration: • COM.FMC_SetupTime = 0x01; • COM.FMC_WaitSetupTime = 0x03; • COM.FMC_HoldSetupTime = 0x02; • COM.FMC_HiZSetupTime = 0x01; • ATT.FMC_SetupTime = 0x01; • ATT.FMC_WaitSetupTime = 0x03; • ATT.FMC_HoldSetupTime = 0x02; • ATT.FMC_HiZSetupTime = 0x01; • Bank = FMC_Bank_NAND; • MemoryDataWidth = FMC_MemoryDataWidth_16b; • ECC = FMC_ECC_Enable; • ECCPageSize = FMC_ECCPageSize_512Bytes; • TCLRSetupTime = 0; • TARSetupTime = 0. In all timing tables, the THCLK is the HCLK clock period. 188/241 DocID024244 Rev 11 STM32F437xx and STM32F439xx Electrical characteristics Figure 69. NAND controller waveforms for read access &-#?.#%X !,%&-#?! #,%&-#?! &-#?.7% TD!,% ./% TH./% !,% &-#?./%.2% TSU$ ./% TH./% $ &-#?$;= -36 Figure 70. NAND controller waveforms for write access &-#?.#%X !,%&-#?! #,%&-#?! TH.7% !,% TD!,% .7% &-#?.7% &-#?./%.2% TV.7% $ TH.7% $ &-#?$;= -36 DocID024244 Rev 11 189/241 199 Electrical characteristics STM32F437xx and STM32F439xx Figure 71. NAND controller waveforms for common memory read access &-#?.#%X !,%&-#?! #,%&-#?! TH./% !,% TD!,% ./% &-#?.7% TW./% &-#?./% TSU$ ./% TH./% $ &-#?$;= -36 Figure 72. NAND controller waveforms for common memory write access &-#?.#%X !,%&-#?! #,%&-#?! TD!,% ./% TW.7% TH./% !,% &-#?.7% &-#?. /% TD$ .7% TV.7% $ TH.7% $ &-#?$;= -36 Table 100. Switching characteristics for NAND Flash read cycles(1) Symbol tw(N0E) Parameter FMC_NOE low width Max 4THCLK − 0.5 4THCLK+0.5 Unit ns tsu(D-NOE) FMC_D[15-0] valid data before FMC_NOE high 9 - ns th(NOE-D) FMC_D[15-0] valid data after FMC_NOE high 0 - ns td(ALE-NOE) FMC_ALE valid before FMC_NOE low - 3THCLK − 0.5 ns th(NOE-ALE) FMC_NWE high to FMC_ALE invalid 3THCLK − 2 - ns 1. CL = 30 pF. 190/241 Min DocID024244 Rev 11 STM32F437xx and STM32F439xx Electrical characteristics Table 101. Switching characteristics for NAND Flash write cycles(1) Symbol tw(NWE) Parameter FMC_NWE low width Min Max Unit 4THCLK 4THCLK+1 ns 0 - ns tv(NWE-D) FMC_NWE low to FMC_D[15-0] valid th(NWE-D) FMC_NWE high to FMC_D[15-0] invalid 3THCLK − 1 - ns td(D-NWE) FMC_D[15-0] valid before FMC_NWE high 5THCLK − 3 - ns - 3THCLK −0.5 ns 3THCLK − 1 - ns td(ALE-NWE) FMC_ALE valid before FMC_NWE low th(NWE-ALE) FMC_NWE high to FMC_ALE invalid 1. CL = 30 pF. SDRAM waveforms and timings Figure 73. SDRAM read access waveforms (CL = 1) &-#?3$#,+ TD3$#,+,?!DD# TH3$#,+,?!DD2 TD3$#,+,?!DD2 &-#?!>@ 2OWN #OL #OL #OLI #OLN TH3$#,+,?!DD# TH3$#,+,?3.$% TD3$#,+,?3.$% &-#?3$.%;= TD3$#,+,?.2!3 TH3$#,+,?.2!3 &-#?3$.2!3 TH3$#,+,?.#!3 TD3$#,+,?.#!3 &-#?3$.#!3 &-#?3$.7% TSU3$#,+(?$ATA &-#?$;= TH3$#,+(?$ATA $ATA $ATA $ATAI $ATAN -36 DocID024244 Rev 11 191/241 199 Electrical characteristics STM32F437xx and STM32F439xx Table 102. SDRAM read timings(1)(2) Symbol Parameter Min Max tw(SDCLK) FMC_SDCLK period 2THCLK − 0.5 2THCLK+0.5 tsu(SDCLKH _Data) Data input setup time 2 - th(SDCLKH_Data) Data input hold time 0 - td(SDCLKL_Add) Address valid time - 1.5 td(SDCLKL- SDNE) Chip select valid time - 0.5 th(SDCLKL_SDNE) Chip select hold time 0 - td(SDCLKL_SDNRAS) SDNRAS valid time - 0.5 th(SDCLKL_SDNRAS) SDNRAS hold time 0 - td(SDCLKL_SDNCAS) SDNCAS valid time - 0.5 th(SDCLKL_SDNCAS) SDNCAS hold time 0 - Unit ns 1. CL = 30 pF on data and address lines. CL=15pF on FMC_SDCLK. 2. Guaranteed by characterization results. Table 103. LPSDR SDRAM read timings(1)(2) Symbol Parameter Min Max tW(SDCLK) FMC_SDCLK period 2THCLK − 0.5 2THCLK+0.5 tsu(SDCLKH_Data) Data input setup time 2.5 - th(SDCLKH_Data) Data input hold time 0 - td(SDCLKL_Add) Address valid time - 1 td(SDCLKL_SDNE) Chip select valid time - 1 th(SDCLKL_SDNE) Chip select hold time 1 - td(SDCLKL_SDNRAS SDNRAS valid time - 1 th(SDCLKL_SDNRAS) SDNRAS hold time 1 - td(SDCLKL_SDNCAS) SDNCAS valid time - 1 th(SDCLKL_SDNCAS) SDNCAS hold time 1 - 1. CL = 10 pF. 2. Guaranteed by characterization results. 192/241 DocID024244 Rev 11 Unit ns STM32F437xx and STM32F439xx Electrical characteristics Figure 74. SDRAM write access waveforms &-#?3$#,+ TD3$#,+,?!DD# TH3$#,+,?!DD2 TD3$#,+,?!DD2 &-#?!>@ 2OWN #OL #OL #OLI #OLN TH3$#,+,?!DD# TH3$#,+,?3.$% TD3$#,+,?3.$% &-#?3$.%;= TH3$#,+,?.2!3 TD3$#,+,?.2!3 &-#?3$.2!3 TD3$#,+,?.#!3 TH3$#,+,?.#!3 TD3$#,+,?.7% TH3$#,+,?.7% &-#?3$.#!3 &-#?3$.7% TD3$#,+,?$ATA &-#?$;= TD3$#,+,?.", $ATA $ATA $ATAI $ATAN TH3$#,+,?$ATA &-#?.",;= -36 DocID024244 Rev 11 193/241 199 Electrical characteristics STM32F437xx and STM32F439xx Table 104. SDRAM write timings(1)(2) Symbol Parameter Min Max tw(SDCLK) FMC_SDCLK period 2THCLK − 0.5 2THCLK+0.5 td(SDCLKL _Data) Data output valid time - 3.5 th(SDCLKL _Data) Data output hold time 0 - td(SDCLKL_Add) Address valid time - 1.5 td(SDCLKL_SDNWE) SDNWE valid time - 1 th(SDCLKL_SDNWE) SDNWE hold time 0 - td(SDCLKL_ SDNE) Chip select valid time - 0.5 th(SDCLKL-_SDNE) Chip select hold time 0 - td(SDCLKL_SDNRAS) SDNRAS valid time - 2 th(SDCLKL_SDNRAS) SDNRAS hold time 0 - td(SDCLKL_SDNCAS) SDNCAS valid time - 0.5 td(SDCLKL_SDNCAS) SDNCAS hold time 0 - td(SDCLKL_NBL) NBL valid time - 0.5 th(SDCLKL_NBL) NBLoutput time 0 - Unit ns 1. CL = 30 pF on data and address lines. CL=15pF on FMC_SDCLK. 2. Guaranteed by characterization results. Table 105. LPSDR SDRAM write timings(1)(2) Symbol Parameter Min Max tw(SDCLK) FMC_SDCLK period 2THCLK − 0.5 2THCLK+0.5 td(SDCLKL _Data) Data output valid time - 5 th(SDCLKL _Data) Data output hold time 2 - td(SDCLKL_Add) Address valid time - 2.8 td(SDCLKL-SDNWE) SDNWE valid time - 2 th(SDCLKL-SDNWE) SDNWE hold time 1 - td(SDCLKL- SDNE) Chip select valid time - 1.5 th(SDCLKL- SDNE) Chip select hold time 1 - td(SDCLKL-SDNRAS) SDNRAS valid time - 1.5 th(SDCLKL-SDNRAS) SDNRAS hold time 1.5 - td(SDCLKL-SDNCAS) SDNCAS valid time - 1.5 td(SDCLKL-SDNCAS) SDNCAS hold time 1.5 - td(SDCLKL_NBL) NBL valid time - 1.5 th(SDCLKL-NBL) NBL output time 1.5 - 1. CL = 10 pF. 2. Guaranteed by characterization results. 194/241 DocID024244 Rev 11 Unit ns STM32F437xx and STM32F439xx 6.3.27 Electrical characteristics Camera interface (DCMI) timing specifications Unless otherwise specified, the parameters given in Table 106 for DCMI are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage summarized in Table 17, with the following configuration: • DCMI_PIXCLK polarity: falling • DCMI_VSYNC and DCMI_HSYNC polarity: high • Data formats: 14 bits Table 106. DCMI characteristics Symbol Parameter Min Max - 0.4 - 54 MHz Pixel clock input duty cycle 30 70 % tsu(DATA) Data input setup time 2 - th(DATA) Data input hold time 2.5 - tsu(HSYNC) tsu(VSYNC) DCMI_HSYNC/DCMI_VSYNC input setup time 0.5 - th(HSYNC) th(VSYNC) DCMI_HSYNC/DCMI_VSYNC input hold time 1 - Frequency ratio DCMI_PIXCLK/fHCLK DCMI_PIXCLK Pixel clock input DPixel Unit ns Figure 75. DCMI timing diagram '&0,B3,;&/. '&0,B3,;&/. WVX+6@ 1JYFM 1JYFM   1JYFM / WK'$7$ +6@ /&'B%>@ -LINESDATA 96