STM32L162VET6

STM32L162xE Ultra-low-power 32-bit MCU ARM®-based Cortex®-M3 with 512KB Flash, 80KB SRAM, 16KB EEPROM, LCD, USB, ADC, DAC, AES Datasheet - production data Features • Ultra-low-power platform – 1.65 V to 3.6 V power supply – -40 °C to 105 °C temperature range – 290 nA Standby mode (3 wakeup pins) – 1.11 µA Standby mode + RTC – 560 nA Stop mode (16 wakeup lines) – 1.4 µA Stop mode + RTC – 11 µA Low-power run mode down to 4.6 µA in Low-power sleep mode – 195 µA/MHz Run mode – 10 nA ultra-low I/O leakage – 8 µs wakeup time • AES 128-bit encryption hardware accelerator • Up to 34 capacitive sensing channels • CRC calculation unit, 96-bit unique ID • Reset and supply management – Low-power, ultrasafe BOR (brownout reset) with 5 selectable thresholds – Ultra-low-power POR/PDR – Programmable voltage detector (PVD) • Clock sources – 1 to 24 MHz crystal oscillator – 32 kHz oscillator for RTC with calibration – Internal 16 MHz oscillator factory trimmed RC(+/-1%) with PLL option – Internal low-power 37 kHz oscillator – Internal multispeed low-power 65 kHz to 4.2 MHz oscillator – PLL for CPU clock and USB (48 MHz) August 2017 This is information on a product in full production. WLCSP104 (0.4 mm pitch) • Up to 116 fast I/Os (102 I/Os 5V tolerant), all mappable on 16 external interrupt vectors • Memories – 512 Kbytes of Flash memory with ECC (with 2 banks of 256 Kbytes enabling RWW capability) – 80 Kbytes of RAM – 16 Kbytes of true EEPROM with ECC – 128-byte backup register • LCD driver up to 8x40 segments, contrast adjustment, blinking mode, step-up converter • Core: ARM® Cortex®-M3 32-bit CPU – From 32 kHz up to 32 MHz max – 1.25 DMIPS/MHz (Dhrystone 2.1) – Memory protection unit • Pre-programmed bootloader – USB and USART supported LQFP144 (20 × 20 mm) LQFP100 (14 × 14 mm) LQFP64 (10 × 10 mm) • Rich analog peripherals (down to 1.8 V) – 2x operational amplifiers – 12-bit ADC 1 Msps up to 40 channels – 12-bit DAC 2 ch with output buffers – 2x ultra-low-power comparators (window mode and wake up capability) • DMA controller 12x channels • 11x peripheral communication interfaces – 1x USB 2.0 (internal 48 MHz PLL) – 5x USARTs – Up to 8x SPIs (2x I2S, 3x 16 Mbit/s) – 2x I2Cs (SMBus/PMBus) • 11x timers: 1x 32-bit, 6x 16-bit with up to 4 IC/OC/PWM channels, 2x 16-bit basic timers, 2x watchdog timers (independent and window) • Development support: serial wire debug, JTAG and trace Table 1. Device summary Reference STM32L162xE DocID025882 Rev 7 Part number STM32L162RE, STM32L162VE, STM32L162ZE 1/130 www.st.com Contents STM32L162xE Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 2/130 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 Ultra-low-power device continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.2.1 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.2 Shared peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.3 Common system strategy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 ARM® Cortex®-M3 core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3 Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3.4 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.5 Low-power real-time clock and backup registers . . . . . . . . . . . . . . . . . . . 22 3.6 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.7 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.8 DMA (direct memory access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.9 LCD (liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.10 ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.10.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.10.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.11 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.12 Operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.13 Ultra-low-power comparators and reference voltage . . . . . . . . . . . . . . . . 26 3.14 System configuration controller and routing interface . . . . . . . . . . . . . . . 26 3.15 Touch sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 DocID025882 Rev 7 STM32L162xE Contents 3.16 AES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.17 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.18 3.17.1 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM9, TIM10 and TIM11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.17.2 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.17.3 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.17.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.17.5 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.18.1 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.18.2 Universal synchronous/asynchronous receiver transmitter (USART) . . 29 3.18.3 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.18.4 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.18.5 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.19 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 29 3.20 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.20.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.20.2 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.1.7 Optional LCD power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.1.8 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.3.2 Embedded reset and power control block characteristics . . . . . . . . . . . 59 DocID025882 Rev 7 3/130 4 Contents 7 STM32L162xE 6.3.3 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.3.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.3.5 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.3.11 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.3.15 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.3.16 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.3.17 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6.3.18 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 6.3.19 Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.3.20 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 6.3.21 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 6.3.22 LCD controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 7.1 LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 7.2 LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 7.3 LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 7.4 WLCSP104, 0.4 mm pitch wafer level chip scale package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 7.5 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 7.5.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 9 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 4/130 DocID025882 Rev 7 STM32L162xE List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ultra-low-power STM32L162xE device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Functionalities depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . 14 CPU frequency range depending on dynamic voltage scaling . . . . . . . . . . . . . . . . . . . . . . 15 Functionalities depending on the working mode (from Run/active down to standby) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 STM32L162xE pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 59 Embedded internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Current consumption in Run mode, code with data processing running from Flash. . . . . . 63 Current consumption in Run mode, code with data processing running from RAM . . . . . . 64 Current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Current consumption in Low-power run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Current consumption in Low-power sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 68 Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 70 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Flash memory and data EEPROM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Flash memory and data EEPROM endurance and retention . . . . . . . . . . . . . . . . . . . . . . . 84 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 DocID025882 Rev 7 5/130 6 List of tables Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. 6/130 STM32L162xE I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 SCL frequency (fPCLK1= 32 MHz, VDD = VDD_I2C = 3.3 V). . . . . . . . . . . . . . . . . . . . . . . . 94 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 USB: full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 ADC clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Maximum source impedance RAIN max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 LCD controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . 114 LQPF100, 14 x 14 mm, 100-pin low-profile quad flat package mechanical data . . . . . . . 116 LQFP64, 10 x 10 mm 64-pin low-profile quad flat package mechanical data. . . . . . . . . . 119 WLCSP104, 0.4 mm pitch wafer level chip scale package mechanical data . . . . . . . . . . 123 WLCSP104, 0.4 mm pitch recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . 124 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 DocID025882 Rev 7 STM32L162xE List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Ultra-low-power STM32L162xE block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 STM32L162ZE LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 STM32L162VE LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 STM32L162RE LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 STM32L162VEY WLCSP104 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Optional LCD power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Maximum dynamic current consumption on VREF+ supply pin during ADC conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 113 LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package top view example . . . . . . 115 LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 116 LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package top view example . . . . . . 118 LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 119 LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 LQFP64 10 x 10 mm, 64-pin low-profile quad flat package top view example . . . . . . . . . 121 WLCSP104, 0.4 mm pitch wafer level chip scale package outline . . . . . . . . . . . . . . . . . . 122 WLCSP104, 0.4 mm pitch wafer level chip scale package recommended footprint. . . . . 123 WLCSP104, 0.4 mm pitch wafer level chip scale package top view example . . . . . . . . . 124 Thermal resistance suffix 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Thermal resistance suffix 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 DocID025882 Rev 7 7/130 7 Introduction 1 STM32L162xE Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32L162xE ultra-low-power ARM® Cortex®-M3 based microcontroller product line. STM32L162xE devices are microcontrollers with a Flash memory density of 512 Kbytes. The ultra-low-power STM32L162xE family includes devices in 4 different package types: from 64 pins to 144 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. These features make the ultra-low-power STM32L162xE microcontroller family suitable for a wide range of applications: • Medical and handheld equipment • Application control and user interface • PC peripherals, gaming, GPS and sport equipment • Alarm systems, wired and wireless sensors, video intercom • Utility metering This STM32L162xE datasheet should be read in conjunction with the STM32L1xxxx reference manual (RM0038). The application note “Getting started with STM32L1xxxx hardware development” (AN3216) gives a hardware implementation overview. Both documents are available from the STMicroelectronics website www.st.com. For information on the ARM® Cortex®-M3 core please refer to the ARM® Cortex®-M3 technical reference manual, available from the www.arm.com website. Figure 1 shows the general block diagram of the device family. 8/130 DocID025882 Rev 7 STM32L162xE 2 Description Description The ultra-low-power STM32L162xE devices incorporate the connectivity power of the universal serial bus (USB) with the high-performance ARM® Cortex®-M3 32-bit RISC core operating at a frequency of 32 MHz (33.3 DMIPS), a memory protection unit (MPU), highspeed embedded memories (Flash memory up to 512 Kbytes and RAM up to 80 Kbytes) and an extensive range of enhanced I/Os and peripherals connected to two APB buses. The STM32L162xE devices offer two operational amplifiers, one 12-bit ADC, two DACs, two ultra-low-power comparators, AES, one general-purpose 32-bit timer, six general-purpose 16-bit timers and two basic timers, which can be used as time bases. Moreover, the STM32L162xE devices contain standard and advanced communication interfaces: up to two I2Cs, three SPIs, two I2S, two UARTs, three USARTs and an USB. The STM32L162xE devices offer up to 34 capacitive sensing channels to simply add a touch sensing functionality to any application. They also include a real-time clock and a set of backup registers that remain powered in Standby mode. Finally, the integrated LCD controller has a built-in LCD voltage generator that allows to drive up to 8 multiplexed LCDs with the contrast independent of the supply voltage. The ultra-low-power STM32L162xE devices operate from a 1.8 to 3.6 V power supply (down to 1.65 V at power down) with BOR and from a 1.65 to 3.6 V power supply without BOR option. They are available in the -40 to +85 °C and -40 to +105 °C temperature ranges. A comprehensive set of power-saving modes allows the design of low-power applications. DocID025882 Rev 7 9/130 53 Description 2.1 STM32L162xE Device overview Table 2. Ultra-low-power STM32L162xE device features and peripheral counts Peripheral STM32L162RE STM32L162VE Flash (Kbytes) 512 Data EEPROM (Kbytes) 16 RAM (Kbytes) 80 AES 1 Timers 32 bit 1 Generalpurpose 6 Basic 2 SPI 8(3)(1) I2S 2 Communication 2 I C interfaces 2 USART 5 USB 1 GPIOs 51 83 Operational amplifiers 12-bit synchronized ADC Number of channels 1 21 1 25 1 1 4x32 or 8x28 4x44 or 8x40 2 Capacitive sensing channels 23 Max. CPU frequency Operating temperatures Packages 34 32 MHz 1.8 V to 3.6 V (down to 1.65 V at power-down) with BOR option 1.65 V to 3.6 V without BOR option Ambient operating temperature: -40 °C to 85 °C / -40 °C to 105 °C Junction temperature: –40 to + 110 °C LQFP64 LQFP100, WLCSP104 1. 5 SPIs are USART configured in synchronous mode emulating SPI master. 10/130 1 40 2 2 Comparators Operating voltage 115 2 12-bit DAC Number of channels LCD COM x SEG STM32L162ZE DocID025882 Rev 7 LQFP144 STM32L162xE 2.2 Description Ultra-low-power device continuum The ultra-low-power family offers a large choice of cores and features. From proprietary 8bit to up to Cortex-M3, including the Cortex-M0+, the STM32Lx series are the best choice to answer the user needs, in terms of ultra-low-power features. The STM32 ultra-low-power series are the best fit, for instance, for gas/water meter, keyboard/mouse or fitness and healthcare, wearable applications. Several built-in features like LCD drivers, dual-bank memory, Low-power run mode, op-amp, AES 128-bit, DAC, USB crystal-less and many others will clearly allow to build very cost-optimized applications by reducing BOM. Note: STMicroelectronics as a reliable and long-term manufacturer ensures as much as possible the pin-to-pin compatibility between any STM8Lxxxxx and STM32Lxxxxx devices and between any of the STM32Lx and STM32Fx series. Thanks to this unprecedented scalability, the old applications can be upgraded to respond to the latest market features and efficiency demand. 2.2.1 Performance All the families incorporate highly energy-efficient cores with both Harvard architecture and pipelined execution: advanced STM8 core for STM8L families and ARM Cortex-M3 core for STM32L family. In addition specific care for the design architecture has been taken to optimize the mA/DMIPS and mA/MHz ratios. This allows the ultra-low-power performance to range from 5 up to 33.3 DMIPs. 2.2.2 Shared peripherals STM8L15xxx, STM32L15xxx and STM32L162xx share identical peripherals which ensure a very easy migration from one family to another: 2.2.3 • Analog peripherals: ADC, DAC and comparators • Digital peripherals: RTC and some communication interfaces Common system strategy. To offer flexibility and optimize performance, the STM8L15xxx, STM32L15xxx and STM32L162xx family uses a common architecture: 2.2.4 • Same power supply range from 1.65 V to 3.6 V • Architecture optimized to reach ultra-low consumption both in low-power modes and Run mode • Fast startup strategy from low-power modes • Flexible system clock • Ultrasafe reset: same reset strategy including power-on reset, power-down reset, brownout reset and programmable voltage detector Features ST ultra-low-power continuum also lies in feature compatibility: • More than 15 packages with pin count from 20 to 144 pins and size down to 3 x 3 mm • Memory density ranging from 2 to 512 Kbytes DocID025882 Rev 7 11/130 53 Functional overview 3 STM32L162xE Functional overview Figure 1. Ultra-low-power STM32L162xE block diagram 75$&(&.75$&('75$&('75$&('75$&(' )PD[0+] 038 'EXV 6\VWHP 19,& *3'0$FKDQQHOV .%352*5$0 .%'$7$ .%%227 '8$/%$1. 65$0. %25 3$>@ *3,23257$ 3%>@ *3,23257% 3&>@ *3,23257& 3'>@ *3,23257' 3(>@ *3,23257( 3+>@ *3,23257+ 3)>@ *3,23257) 026,0,62 6&.166DV$) 5;7;&76576 6PDUW&DUGDV$) (;7,7 :.83 $+%$3% 86$57 $) 7HPSVHQVRU ,) 86%65$0% :LQ:$7&+'2* 7,0(5 7,0(5 /&'%RRVWHU FKDQQHOV 7,0(5 FKDQQHO 7,0(5 FKDQQHO 7,0(5 9/&' 9WR9 7,0(5 FKDQQHOV 7,0(5 FKDQQHOV 7,0(5 FKDQQHOV 7,0(56ELWV FKDQQHOV 86$57 5;7;&76576 6PDUW&DUGDV$) 86$57 5;7;&76576 6PDUW&DUGDV$) 86$57 5;7;DV$) 86$57 5;7;DV$) 63,,6 [[ELW 026,0,626&.166:6&. 0&.6'DV$) 63,,6 [[ELW 026,0,626&.166:6&. 0&.6'DV$) ,& 6&/6'$ $V$) ,& 6&/6'$60%XV30%XV $V$) 86%)6GHYLFH &DSVHQVLQJ *HQHUDOSXUSRVH WLPHUV /&'[ 23$03 86%B'3 86%B'0 3[ 6(*[ &20[ #9''$ 23$03 ELW'$& '$&B287DV$) ELW'$& '$&B287DV$) ,) ,,) ) 9,13 9,10 9287 12/130 #9'' $+%$3% 63, 9665()B$'& 7$03(5 %DFNXSLQWHUIDFH *3,23257* ELW$'& %DFNXS 5HJ $(6 #9''$ 9''5()B$'& 26&B,1 26&B287 57&B287 57&9 $:8 $3%)PD[ 0+] $) #9''$ $3%)PD[ 0+] 3*>@ 26&B287 ;7$/N+] $+%)PD[ 0+] *3&RPS 383' 26&B,1 ;7$/26& 0+] 5&/6,$ #9'' &DSVHQV &203[B,1[ #9'' 6WDQGE\ LQWHUIDFH 5&06, ,QW 1567 :'*. 5&+6, 9/&' 39' 3'5 3// &ORFN 0JPW )&/. %25%JDS 9UHI 3'5 $+%3&/. $3%3&/. +&/. 9''$ 966$ 9VV 6XSSO\PRQLWRULQJ #9''$ *3'0$FKDQQHOV 6XSSO\ PRQLWRULQJ 9'' 9WR9 ((3520ELW ,QWHUIDFH 0&38 92/75(* LEXV %XV0DWUL[06 1-7567 -7', -7&.6:&/. -7066:'$7 -7'2 DV$) #9'' 32:(5 9''&25( 7UDFH&RQWUROOHU(70 SEXV ((3520 RE O -7$* 6: 9,13 9,10 9287 DocID025882 Rev 7 06Y9 STM32L162xE 3.1 Functional overview Low-power modes The ultra-low-power STM32L162xE devices support dynamic voltage scaling to optimize its power consumption in run mode. The voltage from the internal low-drop regulator that supplies the logic can be adjusted according to the system’s maximum operating frequency and the external voltage supply. There are three power consumption ranges: • Range 1 (VDD range limited to 1.71 V - 3.6 V), with the CPU running at up to 32 MHz • Range 2 (full VDD range), with a maximum CPU frequency of 16 MHz • Range 3 (full VDD range), with a maximum CPU frequency limited to 4 MHz (generated only with the multispeed internal RC oscillator clock source) Seven low-power modes are provided to achieve the best compromise between low-power consumption, short startup time and available wakeup sources: • Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. Sleep mode power consumption at 16 MHz is about 1 mA with all peripherals off. • Low-power run mode This mode is achieved with the multispeed internal (MSI) RC oscillator set to the MSI range 0 or MSI range 1 clock range (maximum 131 kHz), execution from SRAM or Flash memory, and internal regulator in low-power mode to minimize the regulator's operating current. In low-power run mode, the clock frequency and the number of enabled peripherals are both limited. • Low-power sleep mode This mode is achieved by entering Sleep mode with the internal voltage regulator in Low-power mode to minimize the regulator’s operating current. In Low-power sleep mode, both the clock frequency and the number of enabled peripherals are limited; a typical example would be to have a timer running at 32 kHz. When wakeup is triggered by an event or an interrupt, the system reverts to the run mode with the regulator on. • Stop mode with RTC Stop mode achieves the lowest power consumption while retaining the RAM and register contents and real time clock. All clocks in the VCORE domain are stopped, the PLL, MSI RC, HSI RC and HSE crystal oscillators are disabled. The LSE or LSI is still running. The voltage regulator is in the low-power mode. The device can be woken up from Stop mode by any of the EXTI line, in 8 µs. The EXTI line source can be one of the 16 external lines. It can be the PVD output, the Comparator 1 event or Comparator 2 event (if internal reference voltage is on), it can be the RTC alarm(s), the USB wakeup, the RTC tamper events, the RTC timestamp event or the RTC wakeup. DocID025882 Rev 7 13/130 53 Functional overview • STM32L162xE Stop mode without RTC Stop mode achieves the lowest power consumption while retaining the RAM and register contents. All clocks are stopped, the PLL, MSI RC, HSI and LSI RC, LSE and HSE crystal oscillators are disabled. The voltage regulator is in the low-power mode. The device can be woken up from Stop mode by any of the EXTI line, in 8 µs. The EXTI line source can be one of the 16 external lines. It can be the PVD output, the Comparator 1 event or Comparator 2 event (if internal reference voltage is on). It can also be wakened by the USB wakeup. • Standby mode with RTC Standby mode is used to achieve the lowest power consumption and real time clock. The internal voltage regulator is switched off so that the entire VCORE domain is powered off. The PLL, MSI RC, HSI RC and HSE crystal oscillators are also switched off. The LSE or LSI is still running. After entering Standby mode, the RAM and register contents are lost except for registers in the Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE Crystal 32K osc, RCC_CSR). The device exits Standby mode in 60 µs when an external reset (NRST pin), an IWDG reset, a rising edge on one of the three WKUP pins, RTC alarm (Alarm A or Alarm B), RTC tamper event, RTC timestamp event or RTC Wakeup event occurs. • Standby mode without RTC Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire VCORE domain is powered off. The PLL, MSI RC, HSI and LSI RC, HSE and LSE crystal oscillators are also switched off. After entering Standby mode, the RAM and register contents are lost except for registers in the Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE Crystal 32K osc, RCC_CSR). The device exits Standby mode in 60 µs when an external reset (NRST pin) or a rising edge on one of the three WKUP pin occurs. Note: The RTC, the IWDG, and the corresponding clock sources are not stopped automatically by entering Stop or Standby mode. Table 3. Functionalities depending on the operating power supply range Functionalities depending on the operating power supply range(1) Operating power supply range DAC and ADC operation USB Dynamic voltage scaling range VDD= VDDA = 1.65 to 1.71 V Not functional Not functional Range 2 or Range 3 Not functional Not functional Range 1, Range 2 or Range 3 Conversion time up to 500 Ksps Not functional Range 1, Range 2 or Range 3 VDD=VDDA= 1.71 to 1.8 V(2) VDD=VDDA= 1.8 to 2.0 V 14/130 DocID025882 Rev 7 STM32L162xE Functional overview Table 3. Functionalities depending on the operating power supply range (continued) Functionalities depending on the operating power supply range(1) Operating power supply range DAC and ADC operation USB Dynamic voltage scaling range VDD=VDDA = 2.0 to 2.4 V Conversion time up to 500 Ksps Functional(3) Range 1, Range 2 or Range 3 VDD=VDDA = 2.4 to 3.6 V Conversion time up to 1 Msps Functional(3) Range 1, Range 2 or Range 3 1. The GPIO speed also depends from VDD voltage and the user has to refer to Table 44: I/O AC characteristics for more information about I/O speed. 2. CPU frequency changes from initial to final must respect “FCPU initial < 4*FCPU final” to limit VCORE drop due to current consumption peak when frequency increases. It must also respect 5 µs delay between two changes. For example to switch from 4.2 MHz to 32 MHz, the user can switch from 4.2 MHz to 16 MHz, wait 5 µs, then switch from 16 MHz to 32 MHz. 3. Should be USB compliant from I/O voltage standpoint, the minimum VDD is 3.0 V. Table 4. CPU frequency range depending on dynamic voltage scaling CPU frequency range Dynamic voltage scaling range 16 MHz to 32 MHz (1ws) 32 kHz to 16 MHz (0ws) Range 1 8 MHz to 16 MHz (1ws) 32 kHz to 8 MHz (0ws) Range 2 2.1MHz to 4.2 MHz (1ws) 32 kHz to 2.1 MHz (0ws) Range 3 DocID025882 Rev 7 15/130 53 Functional overview STM32L162xE Table 5. Functionalities depending on the working mode (from Run/active down to standby) Standby Run/Active Sleep CPU Y -- Y -- -- -- -- -- Flash Y Y Y Y -- -- -- -- RAM Y Y Y Y Y -- -- -- Backup Registers Y Y Y Y Y -- Y -- EEPROM Y Y Y Y Y -- -- -- Brown-out rest (BOR) Y Y Y Y Y Y Y -- DMA Y Y Y Y -- -- -- -- Programmable Voltage Detector (PVD) Y Y Y Y Y Y Y -- Power On Reset (POR) Y Y Y Y Y Y Y -- Power Down Rest (PDR) Y Y Y Y Y -- Y -- High Speed Internal (HSI) Y Y -- -- -- -- -- -- High Speed External (HSE) Y Y -- -- -- -- -- -- Low Speed Internal (LSI) Y Y Y Y Y -- Y -- Low Speed External (LSE) Y Y Y Y Y -- Y -- Multi-Speed Internal (MSI) Y Y Y Y -- -- -- -- Inter-Connect Controller Y Y Y Y -- -- -- -- RTC Y Y Y Y Y Y Y -- RTC Tamper Y Y Y Y Y Y Y Y Auto WakeUp (AWU) Y Y Y Y Y Y Y Y LCD Y Y Y Y Y -- -- -- USB Y Y -- -- -- Y -- -- -- -- Ips Lowpower Sleep Stop Lowpower Run Wakeup capability Wakeup capability USART Y Y Y Y Y (1) SPI Y Y Y Y -- -- -- -- I2C Y Y -- -- -- (1) -- -- 16/130 DocID025882 Rev 7 STM32L162xE Functional overview Table 5. Functionalities depending on the working mode (from Run/active down to standby) (continued) Standby Run/Active Sleep ADC Y Y -- -- -- -- -- -- DAC Y Y Y Y Y -- -- -- Tempsensor Y Y Y Y Y -- -- -- OP amp Y Y Y Y Y -- -- -- Comparators Y Y Y Y Y Y -- -- 16-bit and 32-bit Timers Y Y Y Y -- -- -- -- IWDG Y Y Y Y Y Y Y Y WWDG Y Y Y Y -- -- -- -- Touch sensing Y Y -- -- -- -- -- -- Systic Timer Y Y Y Y -- -- -- GPIOs Y Y Y Y Y -- 3 pins 0 µs 0.4 µs 3 µs 46 µs Ips Wakeup time to Run mode Consumption VDD=1.8 to 3.6 V (Typ) Down to 195 µA/MHz (from Flash) Down to 38 µA/MHz (from Flash) Down to 11 µA Lowpower Sleep Stop Lowpower Run Down to 4.6 µA Wakeup capability Y Wakeup capability < 8 µs 58 µs 0.53 µA (no RTC) VDD=1.8V 0.285 µA (no RTC) VDD=1.8V 1.2 µA (with RTC) VDD=1.8V 0.97 µA (with RTC) VDD=1.8V 0.56 µA (no RTC) VDD=3.0V 0.29 µA (no RTC) VDD=3.0V 1.4 µA (with RTC) VDD=3.0V 1.11 µA (with RTC) VDD=3.0V 1. The startup on communication line wakes the CPU which was made possible by an EXTI, this induces a delay before entering run mode. 3.2 ARM® Cortex®-M3 core with MPU The ARM® Cortex®-M3 processor is the industry leading processor for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. The ARM® Cortex®-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. DocID025882 Rev 7 17/130 53 Functional overview STM32L162xE The memory protection unit (MPU) improves system reliability by defining the memory attributes (such as read/write access permissions) for different memory regions. It provides up to eight different regions and an optional predefined background region. Owing to its embedded ARM core, the STM32L162xE devices are compatible with all ARM tools and software. Nested vectored interrupt controller (NVIC) The ultra-low-power STM32L162xE devices embed a nested vectored interrupt controller able to handle up to 56 maskable interrupt channels (not including the 16 interrupt lines of ARM® Cortex®-M3) and 16 priority levels. • Closely coupled NVIC gives low-latency interrupt processing • Interrupt entry vector table address passed directly to the core • Closely coupled NVIC core interface • Allows early processing of interrupts • Processing of late arriving, higher-priority interrupts • Support for tail-chaining • Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction overhead This hardware block provides flexible interrupt management features with minimal interrupt latency. 3.3 Reset and supply management 3.3.1 Power supply schemes 3.3.2 • VDD = 1.65 to 3.6 V: external power supply for I/Os and the internal regulator. Provided externally through VDD pins. • VSSA, VDDA = 1.65 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs and PLL (minimum voltage to be applied to VDDA is 1.8 V when the ADC is used). VDDA and VSSA must be connected to VDD and VSS, respectively. Power supply supervisor The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset (PDR) that can be coupled with a brownout reset (BOR) circuitry. The device exists in two versions: • The version with BOR activated at power-on operates between 1.8 V and 3.6 V. • The other version without BOR operates between 1.65 V and 3.6 V. After the VDD threshold is reached (1.65 V or 1.8 V depending on the BOR which is active or not at power-on), the option byte loading process starts, either to confirm or modify default thresholds, or to disable the BOR permanently: in this case, the VDD min value becomes 1.65 V (whatever the version, BOR active or not, at power-on). When BOR is active at power-on, it ensures proper operation starting from 1.8 V whatever the power ramp-up phase before it reaches 1.8 V. When BOR is not active at power-up, the power ramp-up should guarantee that 1.65 V is reached on VDD at least 1 ms after it exits the POR area. 18/130 DocID025882 Rev 7 STM32L162xE Functional overview Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To reduce the power consumption in Stop mode, it is possible to automatically switch off the internal reference voltage (VREFINT) in Stop mode. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for any external reset circuit. Note: The start-up time at power-on is typically 3.3 ms when BOR is active at power-up, the startup time at power-on can be decreased down to 1 ms typically for devices with BOR inactive at power-up. The device features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. This PVD offers 7 different levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. 3.3.3 Voltage regulator The regulator has three operation modes: main (MR), low-power (LPR) and power down. 3.3.4 • MR is used in Run mode (nominal regulation) • LPR is used in the Low-power run, Low-power sleep and Stop modes • Power down is used in Standby mode. The regulator output is high impedance, the kernel circuitry is powered down, inducing zero consumption but the contents of the registers and RAM are lost except for the standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE crystal 32K osc, RCC_CSR). Boot modes At startup, boot pins are used to select one of three boot options: • Boot from Flash memory • Boot from System memory • Boot from embedded RAM The boot from Flash usually boots at the beginning of the Flash (bank 1). An additional boot mechanism is available through user option byte, to allow booting from bank 2 when bank 2 contains valid code. This dual boot capability can be used to easily implement a secure field software update mechanism. The boot loader is located in System memory. It is used to reprogram the Flash memory by using USART1, USART2 or USB. See Application note “STM32 microcontroller system memory boot mode” (AN2606) for details. DocID025882 Rev 7 19/130 53 Functional overview 3.4 STM32L162xE Clock management The clock controller distributes the clocks coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness. It features: • Clock prescaler: to get the best trade-off between speed and current consumption, the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler. • Safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register. • Clock management: to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. • System clock source: three different clock sources can be used to drive the master clock SYSCLK: • – 1-24 MHz high-speed external crystal (HSE), that can supply a PLL – 16 MHz high-speed internal RC oscillator (HSI), trimmable by software, that can supply a PLL – Multispeed internal RC oscillator (MSI), trimmable by software, able to generate 7 frequencies (65 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.1 MHz, 4.2 MHz). When a 32.768 kHz clock source is available in the system (LSE), the MSI frequency can be trimmed by software down to a ±0.5% accuracy. Auxiliary clock source: two ultra-low-power clock sources that can be used to drive the LCD controller and the real-time clock: – 32.768 kHz low-speed external crystal (LSE) – 37 kHz low-speed internal RC (LSI), also used to drive the independent watchdog. The LSI clock can be measured using the high-speed internal RC oscillator for greater precision. • RTC and LCD clock sources: the LSI, LSE or HSE sources can be chosen to clock the RTC and the LCD, whatever the system clock. • USB clock source: the embedded PLL has a dedicated 48 MHz clock output to supply the USB interface. • Startup clock: after reset, the microcontroller restarts by default with an internal 2 MHz clock (MSI). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. • Clock security system (CSS): this feature can be enabled by software. If a HSE clock failure occurs, the master clock is automatically switched to HSI and a software interrupt is generated if enabled. • Clock-out capability (MCO: microcontroller clock output): it outputs one of the internal clocks for external use by the application. Several prescalers allow the configuration of the AHB frequency, each APB (APB1 and APB2) domains. The maximum frequency of the AHB and the APB domains is 32 MHz. See Figure 2 for details on the clock tree. 20/130 DocID025882 Rev 7 STM32L162xE Functional overview Figure 2. Clock tree 3TANDBYSUPPLIEDVOLTAGEDOMAIN ENABLE 7ATCHDOG ,3)2# ,3)TEMPO ,3%/3# ,3%TEMPO 7ATCHDOG ,3 24#ENABLE 24# 2ADIO3LEEP4IMER 2ADIO3LEEP4IMERENABLE ,3 ,3 ,3 ,3 6$$#/2% -(Z ,#$ENABLE 6 -3)2# LEVELSHIFTERS 6$$#/2% #+?!$# !$#ENABLE CK?LSI CK?LSE  #+?,#$ -#/ NOTDEEPSLEEP  #+?072 6 NOTDEEPSLEEP (3)2# NOTSLEEPOR DEEPSLEEP LEVELSHIFTERS 6$$#/2% 3YSTEM CLOCK 6 (3% /3# CK?MSI CK?HSI CK?HSE LEVELSHIFTERS 6$$#/2% !(" PRESCALER  6 CK?PLL 0,, CK?PLLIN 8  ,3 6 -(ZCLOCK DETECTOR NOTSLEEPOR DEEPSLEEP  #+?&#,+ #+?#05 #+?4)-393 !0" !0" PRESCALER PRESCALER    (3%PRESENTORNOT ,3 #+?53" LEVELSHIFTERS 6$$#/2% #LOCK SOURCE CONTROL USBENANDNOTDEEPSLEEP CK?USB6CO6COMUSTBEAT-( Z #+?4)-4'/ #+?!0" #+?!0" TIMERENANDNOTDEEPSLEEP APBPERIPHENANDNOTDEEPSLEEP IF!0"PRESC X X ELSE APBPERIPHENANDNOTDEEPSLEEP -36 DocID025882 Rev 7 21/130 53 Functional overview 3.5 STM32L162xE Low-power real-time clock and backup registers The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain the sub-second, second, minute, hour (12/24 hour), week day, date, month, year, in BCD (binary-coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are made automatically. The RTC provides two programmable alarms and programmable periodic interrupts with wakeup from Stop and Standby modes. The programmable wakeup time ranges from 120 µs to 36 hours. The RTC can be calibrated with an external 512 Hz output, and a digital compensation circuit helps reduce drift due to crystal deviation. The RTC can also be automatically corrected with a 50/60Hz stable powerline. The RTC calendar can be updated on the fly down to sub second precision, which enables network system synchronization. A time stamp can record an external event occurrence, and generates an interrupt. There are thirty-two 32-bit backup registers provided to store 128 bytes of user application data. They are cleared in case of tamper detection. Three pins can be used to detect tamper events. A change on one of these pins can reset backup register and generate an interrupt. To prevent false tamper event, like ESD event, these three tamper inputs can be digitally filtered. 3.6 GPIOs (general-purpose inputs/outputs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions, and can be individually remapped using dedicated AFIO registers. All GPIOs are high current capable. The alternate function configuration of I/Os can be locked if needed following a specific sequence in order to avoid spurious writing to the I/O registers. The I/O controller is connected to the AHB with a toggling speed of up to 16 MHz. External interrupt/event controller (EXTI) The external interrupt/event controller consists of 24 edge detector lines used to generate interrupt/event requests. Each line can be individually configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 115 GPIOs can be connected to the 16 external interrupt lines. The 8 other lines are connected to RTC, PVD, USB, comparator events or capacitive sensing acquisition. 22/130 DocID025882 Rev 7 STM32L162xE 3.7 Functional overview Memories The STM32L162xE devices have the following features: • 80 Kbytes of embedded RAM accessed (read/write) at CPU clock speed with 0 wait states. With the enhanced bus matrix, operating the RAM does not lead to any performance penalty during accesses to the system bus (AHB and APB buses). • The non-volatile memory is divided into three arrays: – 512 Kbytes of embedded Flash program memory – 16 Kbytes of data EEPROM – Options bytes Flash program and data EEPROM are divided into two banks, this enables writing in one bank while running code or reading data in the other bank. The options bytes are used to write-protect or read-out protect the memory (with 4 Kbytes granularity) and/or readout-protect the whole memory with the following options: – Level 0: no readout protection – Level 1: memory readout protection, the Flash memory cannot be read from or written to if either debug features are connected or boot in RAM is selected – Level 2: chip readout protection, debug features (ARM Cortex-M3 JTAG and serial wire) and boot in RAM selection disabled (JTAG fuse) The whole non-volatile memory embeds the error correction code (ECC) feature. 3.8 DMA (direct memory access) The flexible 12-channel, general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports circular buffer management, avoiding the generation of interrupts when the controller reaches the end of the buffer. Each channel is connected to dedicated hardware DMA requests, with software trigger support for each channel. Configuration is done by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: AES, SPI, I2C, USART, general-purpose timers, DAC and ADC. DocID025882 Rev 7 23/130 53 Functional overview 3.9 STM32L162xE LCD (liquid crystal display) The LCD drives up to 8 common terminals and 44 segment terminals to drive up to 320 pixels. 3.10 • Internal step-up converter to guarantee functionality and contrast control irrespective of VDD. This converter can be deactivated, in which case the VLCD pin is used to provide the voltage to the LCD • Supports static, 1/2, 1/3, 1/4 and 1/8 duty • Supports static, 1/2, 1/3 and 1/4 bias • Phase inversion to reduce power consumption and EMI • Up to 8 pixels can be programmed to blink • Unneeded segments and common pins can be used as general I/O pins • LCD RAM can be updated at any time owing to a double-buffer • The LCD controller can operate in Stop mode ADC (analog-to-digital converter) A 12-bit analog-to-digital converters is embedded into STM32L162xE devices with up to 40 external channels, performing conversions in single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs with up to 28 external channels in a group. The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all scanned channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. The events generated by the general-purpose timers (TIMx) can be internally connected to the ADC start triggers, to allow the application to synchronize A/D conversions and timers. An injection mode allows high priority conversions to be done by interrupting a scan mode which runs in as a background task. The ADC includes a specific low-power mode. The converter is able to operate at maximum speed even if the CPU is operating at a very low frequency and has an auto-shutdown function. The ADC’s runtime and analog front-end current consumption are thus minimized whatever the MCU operating mode. 3.10.1 Temperature sensor The temperature sensor (TS) generates a voltage VSENSE that varies linearly with temperature. The temperature sensor is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value. The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are 24/130 DocID025882 Rev 7 STM32L162xE Functional overview stored by ST in the system memory area, accessible in read-only mode. See Table 60: Temperature sensor calibration values. 3.10.2 Internal voltage reference (VREFINT) The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the ADC and Comparators. VREFINT is internally connected to the ADC_IN17 input channel. It enables accurate monitoring of the VDD value (when no external voltage, VREF+, is available for ADC). The precise voltage of VREFINT is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in readonly mode. See Table 15: Embedded internal reference voltage calibration values. 3.11 DAC (digital-to-analog converter) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in non-inverting configuration. This dual digital Interface supports the following features: • Two DAC converters: one for each output channel • 8-bit or 12-bit monotonic output • Left or right data alignment in 12-bit mode • Synchronized update capability • Noise-wave generation • Triangular-wave generation • Dual DAC channels, independent or simultaneous conversions • DMA capability for each channel (including the underrun interrupt) • External triggers for conversion • Input reference voltage VREF+ Eight DAC trigger inputs are used in the STM32L162xE devices. The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels. 3.12 Operational amplifier The STM32L162xE devices embed two operational amplifiers with external or internal follower routing capability (or even amplifier and filter capability with external components). When one operational amplifier is selected, one external ADC channel is used to enable output measurement. The operational amplifiers feature: • Low input bias current • Low offset voltage • Low-power mode • Rail-to-rail input DocID025882 Rev 7 25/130 53 Functional overview 3.13 STM32L162xE Ultra-low-power comparators and reference voltage The STM32L162xE devices embed two comparators sharing the same current bias and reference voltage. The reference voltage can be internal or external (coming from an I/O). • One comparator with fixed threshold • One comparator with rail-to-rail inputs, fast or slow mode. The threshold can be one of the following: – DAC output – External I/O – Internal reference voltage (VREFINT) or a sub-multiple (1/4, 1/2, 3/4) Both comparators can wake up from Stop mode, and be combined into a window comparator. The internal reference voltage is available externally via a low-power / low-current output buffer (driving current capability of 1 µA typical). 3.14 System configuration controller and routing interface The system configuration controller provides the capability to remap some alternate functions on different I/O ports. The highly flexible routing interface allows the application firmware to control the routing of different I/Os to the TIM2, TIM3 and TIM4 timer input captures. It also controls the routing of internal analog signals to ADC1, COMP1 and COMP2 and the internal reference voltage VREFINT. 3.15 Touch sensing The STM32L162xE devices provide a simple solution for adding capacitive sensing functionality to any application. These devices offer up to 34 capacitive sensing channels distributed over 11 analog I/O groups. Both software and timer capacitive sensing acquisition modes are supported. Capacitive sensing technology is able to detect the presence of a finger near a sensor which is protected from direct touch by a dielectric (glass, plastic...). The capacitive variation introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. It consists of charging the sensor capacitance and then transferring a part of the accumulated charges into a sampling capacitor until the voltage across this capacitor has reached a specific threshold. The capacitive sensing acquisition only requires few external components to operate. This acquisition is managed directly by the GPIOs, timers and analog I/O groups (see Section 3.14: System configuration controller and routing interface). Reliable touch sensing functionality can be quickly and easily implemented using the free STM32L1xx STMTouch touch sensing firmware library. 3.16 AES The AES Hardware Accelerator can be used to encrypt and decrypt data using the AES 26/130 DocID025882 Rev 7 STM32L162xE Functional overview algorithm (compatible with FIPS PUB 197, 2001 Nov 26). • Key scheduler • Key derivation for decryption • 128-bit data block processed • 128-bit key length • 213 clock cycles to encrypt/decrypt one 128-bit block • Electronic codebook (ECB), cypher block chaining (CBC), and counter mode (CTR) supported by hardware. AES data flow can be served by 2ch (DIN/DOUT) of the DMA2 controller 3.17 Timers and watchdogs The ultra-low-power STM32L162xE devices include seven general-purpose timers, two basic timers, and two watchdog timers. Table 6 compares the features of the general-purpose and basic timers. Table 6. Timer feature comparison DMA Capture/compare Complementary request channels outputs generation Timer Counter resolution Counter type Prescaler factor TIM2, TIM3, TIM4 16-bit Up, down, up/down Any integer between 1 and 65536 Yes 4 No TIM5 32-bit Up, down, up/down Any integer between 1 and 65536 Yes 4 No TIM9 16-bit Up, down, up/down Any integer between 1 and 65536 No 2 No TIM10, TIM11 16-bit Up Any integer between 1 and 65536 No 1 No TIM6, TIM7 16-bit Up Any integer between 1 and 65536 Yes 0 No 3.17.1 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM9, TIM10 and TIM11) There are seven synchronizable general-purpose timers embedded in the STM32L162xE devices (see Table 6 for differences). TIM2, TIM3, TIM4, TIM5 TIM2, TIM3, TIM4 are based on 16-bit auto-reload up/down counter. TIM5 is based on a 32bit auto-reload up/down counter. They include a 16-bit prescaler. They feature four independent channels each for input capture/output compare, PWM or one-pulse mode output. This gives up to 16 input captures/output compares/PWMs on the largest packages. TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together or with the TIM10, TIM11 and TIM9 general-purpose timers via the Timer Link feature for synchronization or DocID025882 Rev 7 27/130 53 Functional overview STM32L162xE event chaining. Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs. TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. TIM10, TIM11 and TIM9 TIM10 and TIM11 are based on a 16-bit auto-reload upcounter. TIM9 is based on a 16-bit auto-reload up/down counter. They include a 16-bit prescaler. TIM10 and TIM11 feature one independent channel, whereas TIM9 has two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be used as simple time bases and be clocked by the LSE clock source (32.768 kHz) to provide time bases independent from the main CPU clock. 3.17.2 Basic timers (TIM6 and TIM7) These timers are mainly used for DAC trigger generation. They can also be used as generic 16-bit time bases. 3.17.3 SysTick timer This timer is dedicated to the OS, but could also be used as a standard downcounter. It is based on a 24-bit downcounter with autoreload capability and a programmable clock source. It features a maskable system interrupt generation when the counter reaches 0. 3.17.4 Independent watchdog (IWDG) The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 37 kHz internal RC and, as it operates independently of the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. The counter can be frozen in debug mode. 3.17.5 Window watchdog (WWDG) The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 3.18 Communication interfaces 3.18.1 I²C bus Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support standard and fast modes. 28/130 DocID025882 Rev 7 STM32L162xE Functional overview They support dual slave addressing (7-bit only) and both 7- and 10-bit addressing in master mode. A hardware CRC generation/verification is embedded. They can be served by DMA and they support SM Bus 2.0/PM Bus. 3.18.2 Universal synchronous/asynchronous receiver transmitter (USART) The three USART and two UART interfaces are able to communicate at speeds of up to 4 Mbit/s. They support IrDA SIR ENDEC and have LIN Master/Slave capability. The three USARTs provide hardware management of the CTS and RTS signals and are ISO 7816 compliant. All USART/UART interfaces can be served by the DMA controller. 3.18.3 Serial peripheral interface (SPI) Up to three SPIs are able to communicate at up to 16 Mbits/s in slave and master modes in full-duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. The SPIs can be served by the DMA controller. 3.18.4 Inter-integrated sound (I2S) Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available. They can operate in master or slave mode, and can be configured to operate with a 16-/32-bit resolution as input or output channels. Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the I2S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency. The I2Ss can be served by the DMA controller. 3.18.5 Universal serial bus (USB) The STM32L162xE devices embed a USB device peripheral compatible with the USB fullspeed 12 Mbit/s. The USB interface implements a full-speed (12 Mbit/s) function interface. It has software-configurable endpoint setting and supports suspend/resume. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator). 3.19 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. DocID025882 Rev 7 29/130 53 Functional overview STM32L162xE 3.20 Development support 3.20.1 Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG JTMS and JTCK pins are shared with SWDAT and SWCLK, respectively, and a specific sequence on the JTMS pin is used to switch between JTAG-DP and SW-DP. The JTAG port can be permanently disabled with a JTAG fuse. 3.20.2 Embedded Trace Macrocell™ The ARM® Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32L162xE device through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. TPA hardware is commercially available from common development tool vendors. It operates with third party debugger software tools. 30/130 DocID025882 Rev 7 STM32L162xE 4 Pin descriptions Pin descriptions                                     6$$? 633? 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0' 6$$? 633? 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$? 633? 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0!  0!  Figure 3. STM32L162ZE LQFP144 pinout                                     ,1&0                                     6$$? 633? 0( 0!  0!  0!  0!  0!  0!  0# 0# 0# 0# 6$$? 633? 0' 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$? 633? 0$ 0$ 0$ 0$ 0$ 0$ 0" 0" 0" 0" 633? 6$$? 0& 0& 0& 0' 0' 0% 0% 0% 633? 6$$? 0% 0% 0% 0% 0% 0% 0" 0" 633? 6$$? 0!  633? 6$$? 0!  0!  0!  0!  0# 0# 0" 0" 0" 0& 0&                                     0% 0% 0% 0% 0% 7+50 6,#$ 0# 7+50 0# /3#?). 0# /3#?/54 0& 0& 0& 0& 0& 0& 633? 6$$? 0& 0& 0& 0& 0& /3#?). /3#?/54 .234 0# 0# 0# 0# 633! 62%& 62%& 6$$! 0!  7+50 0!  0!  -36 1. This figure shows the package top view. DocID025882 Rev 7 31/130 53 Pin descriptions STM32L162xE                          6$$? 633? 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! Figure 4. STM32L162VE LQFP100 pinout                          ,1&0                          6$$? 633? 0( 0! 0! 0! 0! 0! 0! 0# 0# 0# 0# 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0" 0" 0" 0" 0! 633? 6$$? 0! 0! 0! 0! 0# 0# 0" 0" 0" 0% 0% 0% 0% 0% 0% 0% 0% 0% 0" 0" 633? 6$$?                          0% 0% 0% 0% 0% 7+50 6,#$ 0# 7+50 0# /3#?). 0# /3#?/54 633? 6$$? 0( /3#?). 0( /3#?/54 .234 0# 0# 0# 0# 633! 62%& 62%& 6$$! 0! 7+50 0! 0! 1. This figure shows the package top view. 32/130 DocID025882 Rev 7 AIC STM32L162xE Pin descriptions 6$$? 633? 0" 0" "//4 0" 0" 0" 0" 0" 0$ 0# 0# 0# 0! 0! Figure 5. STM32L162RE LQFP64 pinout                                 ,1&0                                 6$$? 633?  0! 0! 0! 0! 0! 0! 0# 0# 0# 0# 0" 0" 0" 0" 0! 633? 6$$? 0! 0! 0! 0! 0# 0# 0" 0" 0" 0" 0" 633? 6$$? 6,#$ 0# 7+50 0# /3#?). 0# /3#?/54 0( /3#?). 0( /3#?/54 .234 0# 0# 0# 0# 633! 6$$! 0! 7+50 0! 0! AIC 1. This figure shows the package top view. DocID025882 Rev 7 33/130 53 Pin descriptions STM32L162xE Figure 6. STM32L162VEY WLCSP104 ballout ϭ Ϯ ϯ ϰ ϱ ϲ ϳ ϴ ϵ  s^^ͺϮ WϬ Wϰ Wϳ Wϰ Wϱ KKdϬ Wϭ sͺϯ  Wϭϱ WϭϮ Wϱ Wϲ Wϯ Wϳ WϬ sͺϯ Wϱ  sͺϮ Wϭϭ WϮ Wϯ Wϲ Wϵ s^^ͺϯ Wϰ  W,Ϯ s^^ͺϮ Wϭϰ Wϭ Wϴ WϮ Wϯ Wϭϰ K^ϯϮ/E  Wϭϭ WϭϮ Wϭϯ WϭϬ Wϲ t s^^ͺϱ & Wϵ WϭϬ Wϴ Wϵ WϬ EZ^d W,Ϭ K^/E W,ϭ K^Khd ' Wϳ Wϴ Wϭϱ Wϭϭ s sZ&н Wϯ WϮ , Wϲ Wϭϯ WϭϮ Wϴ Wϲ Wϯ sZ&Ͳ Wϭ : Wϭϰ Wϵ Wϭϯ WϭϮ WϭϬ WϬ Wϰ WϮ s^^ < WϭϬ Wϭϱ sͺϭ Wϭϱ Wϭϯ Wϭ Wϳ s^^ͺϰ WϬ t Wϭϰ s^^ͺϭ Wϭϭ Wϭϰ Wϭϭ Wϳ Wϰ sͺϰ Wϭ D s^^ͺϭ WϭϬ WϭϮ Wϵ Wϴ WϮ Wϱ Wϱ sͺϰ Wϭϯ t 2.4 V 8 VREF+ < VDDA VREF+ ≤2.4 V 1.8 V ≤VDDA ≤2.4 V Max 0.480 4 VREF+ = VDDA 8 VREF+ < VDDA 4 Voltage range 3 Unit MHz 4 Table 55. ADC characteristics Symbol VDDA Parameter Power supply Conditions Min Typ Max - 1.8 - 3.6 - VDDA VREF+ Positive reference voltage - 1.8(1) VREF- Negative reference voltage - - VSSA - IVDDA Current on the VDDA input pin - - 1000 1450 Peak - IVREF(2) VAIN Current on the VREF input pin Conversion voltage range(3) 12-bit sampling rate 10-bit sampling rate fS 8-bit sampling rate 6-bit sampling rate Average 400 700 V µA 450 - 0(4) - VREF+ Direct channels - - 1 Multiplexed channels - - 0.76 Direct channels - - 1.07 Multiplexed channels - - 0.8 Direct channels - - 1.23 Multiplexed channels - - 0.89 Direct channels - - 1.45 Multiplexed channels - - 1 DocID025882 Rev 7 Unit V Msps Msps Msps Msps 101/130 112 Electrical characteristics STM32L162xE Table 55. ADC characteristics (continued) Symbol tS(5) Parameter Sampling time tCONV Total conversion time (including sampling time) CADC Internal sample and hold capacitor fTRIG External trigger frequency Regular sequencer fTRIG External trigger frequency Injected sequencer RAIN(6) Signal source impedance Conditions Min Typ Max Direct channels 2.4 V ≤VDDA ≤3.6 V 0.25 - - Multiplexed channels 2.4 V ≤VDDA ≤3.6 V 0.56 - - Direct channels 1.8 V ≤VDDA ≤2.4 V 0.56 - - Multiplexed channels 1.8 V ≤VDDA ≤2.4 V 1 - - - 4 - 384 1/fADC fADC = 16 MHz 1 - 24.75 µs - Unit µs 4 to 384 (sampling phase) +12 (successive approximation) 1/fADC Direct channels - Multiplexed channels - 12-bit conversions - - 6/8/10-bit conversions - - 12-bit conversions - - Tconv+2 1/fADC 6/8/10-bit conversions - - Tconv+1 1/fADC - - 50 kΩ 16 - pF - Tconv+1 1/fADC Tconv 1/fADC tlat Injection trigger conversion latency fADC = 16 MHz 219 - 281 ns - 3.5 - 4.5 1/fADC tlatr Regular trigger conversion latency fADC = 16 MHz 156 - 219 ns - 2.5 - 3.5 1/fADC - - - 3.5 µs tSTAB Power-up time 1. The Vref+ input can be grounded if neither the ADC nor the DAC are used (this allows to shut down an external voltage reference). 2. The current consumption through VREF is composed of two parameters: - one constant (max 300 µA) - one variable (max 400 µA), only during sampling time + 2 first conversion pulses So, peak consumption is 300+400 = 700 µA and average consumption is 300 + [(4 sampling + 2) /16] x 400 = 450 µA at 1Msps 3. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package. Refer to Section 4: Pin descriptions for further details. 4. VSSA or VREF- must be tied to ground. 5. Minimum sampling time is reached for an external input impedance limited to a value as defined in Table 57: Maximum source impedance RAIN max. 6. External impedance has another high value limitation when using short sampling time as defined in Table 57: Maximum source impedance RAIN max. 102/130 DocID025882 Rev 7 STM32L162xE Electrical characteristics Table 56. ADC accuracy(1)(2) Symbol Parameter ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error ENOB Effective number of bits SINAD Signal-to-noise and distortion ratio SNR Signal-to-noise ratio THD Total harmonic distortion ENOB Effective number of bits SINAD Signal-to-noise and distortion ratio SNR Signal-to-noise ratio THD Total harmonic distortion Test conditions 2.4 V ≤ VDDA ≤ 3.6 V 2.4 V ≤ VREF+ ≤ 3.6 V fADC = 8 MHz, RAIN = 50 Ω TA = -40 to 105 ° C 2.4 V ≤ VDDA ≤ 3.6 V VDDA = VREF+ fADC = 16 MHz, RAIN = 50 Ω TA = -40 to 105 ° C Finput=10kHz 1.8 V ≤ VDDA ≤ 2.4 V VDDA = VREF+ fADC = 8 MHz or 4 MHz, RAIN = 50 Ω TA = -40 to 105 ° C Finput=10kHz Min(3) Typ Max(3) - 2.5 4 - 1 2 - 1.5 3.5 - 1 2 - 2.2 3 9.2 10 - 57.5 62 - 57.5 62 - - -70 -65 9.2 10 - 57.5 62 - 57.5 62 - - -70 -65 - 4 6.5 - 1.5 4 - 3.5 6 - 1 2 ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error - 2.5 3 ET Total unadjusted error - 2 3 EO Offset error - 1 1.5 EG Gain error - 1.5 2 ED Differential linearity error - 1 2 EL Integral linearity error - 2.2 3 2.4 V ≤ VDDA ≤ 3.6 V 1.8 V ≤ VREF+ ≤ 2.4 V fADC = 4 MHz, RAIN = 50 Ω TA = -40 to 105 ° C 1.8 V ≤ VDDA ≤ 2.4 V 1.8 V ≤ VREF+ ≤ 2.4 V fADC = 4 MHz, RAIN = 50 Ω TA = -40 to 105 ° C Unit LSB bits dB bits dB LSB LSB 1. ADC DC accuracy values are measured after internal calibration. 2. ADC accuracy vs. negative injection current: Injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.12 does not affect the ADC accuracy. 3. Guaranteed by characterization results. DocID025882 Rev 7 103/130 112 Electrical characteristics STM32L162xE Figure 26. ADC accuracy characteristics 9''$ 95() RUGHSHQGLQJRQSDFNDJH >/6%,'($/    (* ([DPSOHRIDQDFWX DOWUDQVIH UFXUYH 7KHLGHDOWUDQVIHUFX UYH (QGSRLQWFRUUHODWLRQOLQH    (7 7RWDOXQDGMXVWHG(UURUPD[LPXPGHYLDWLRQ EHWZHHQWKHDFWXDODQGWKHLGHDOWUDQVIHUFXUYHV (2 2IIVHW(UURUGHYLDWLRQEHWZHHQWKHILUVWDFWXDO WUDQVLWLRQDQGWKHODVWDFWXDORQH (* *DLQ(UURUGHYLDWLRQEHWZHHQWKHODVWLGHDO WUDQVLWLRQDQGWKHODVWDFWXDORQH (' 'LIIHUHQWLDO/LQHDULW\(UURUPD[LPXPGHYLDWLRQ EHWZHHQDFWXDOVWHSVDQGWKHLGHDORQH (/ ,QWHJUDO/LQHDULW\(UURUPD[LPXPGHYLDWLRQ EHWZHHQDQ\DFWXDOWUDQVLWLRQDQGWKHHQGSRLQW FRUUHODWLRQOLQH  (7      (2  (/  ('  /6%,'($/   966$            9''$ DLH Figure 27. Typical connection diagram using the ADC 9''$ 670/[[ 6DPSOHDQGKROG $'&FRQYHUWHU 5$,1 9$,1 $,1[ &SDUDVLWLF ,/“Q$ ELW FRQYHUWHU &$'& DLH 1. Refer to Table 57: Maximum source impedance RAIN max for the value of RAIN and Table 55: ADC characteristics for the value of CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. 104/130 DocID025882 Rev 7 STM32L162xE Electrical characteristics Figure 28. Maximum dynamic current consumption on VREF+ supply pin during ADC conversion Sampling (n cycles) Conversion (12 cycles) ADC clock Iref+ 700µA 300µA MS36686V1 Table 57. Maximum source impedance RAIN max(1) RAIN max (kΩ) Ts (µs) Multiplexed channels Ts (cycles) Direct channels fADC=16 MHz(2) 2.4 V < VDDA < 3.6 V 1.8 V < VDDA < 2.4 V 2.4 V < VDDA < 3.6 V 1.8 V < VDDA < 2.4 V 0.25 Not allowed Not allowed 0.7 Not allowed 4 0.5625 0.8 Not allowed 2.0 1.0 9 1 2.0 0.8 4.0 3.0 16 1.5 3.0 1.8 6.0 4.5 24 3 6.8 4.0 15.0 10.0 48 6 15.0 10.0 30.0 20.0 96 12 32.0 25.0 50.0 40.0 192 24 50.0 50.0 50.0 50.0 384 1. Guaranteed by design. 2. Number of samples calculated for fADC = 16 MHz. For fADC = 8 and 4 MHz the number of sampling cycles can be reduced with respect to the minimum sampling time Ts (µs), General PCB design guidelines Power supply decoupling should be performed as shown in Figure 10. The applicable procedure depends on whether VREF+ is connected to VDDA or not. The 100 nF capacitors should be ceramic (good quality). They should be placed as close as possible to the chip. DocID025882 Rev 7 105/130 112 Electrical characteristics 6.3.18 STM32L162xE DAC electrical specifications Data guaranteed by design, unless otherwise specified. Table 58. DAC characteristics Symbol Parameter Conditions Min Typ Max - 1.8 - 3.6 1.8 - 3.6 VDDA Analog supply voltage VREF+ Reference supply voltage VREF- Lower reference voltage IDDVREF+(1) Current consumption on No load, middle code (0x800) VREF+ supply No load, worst code (0x000) VREF+ = 3.3 V - 130 220 - 220 350 IDDA(1) Current consumption on No load, middle code (0x800) VDDA supply No load, worst code (0xF1C) VDDA = 3.3 V - 210 320 - 320 520 5 - - 25 - - RL Resistive load VREF+ must always be below VDDA - Connected to DAC output VSSA buffer ON Conected to VDDA CL (2) RO VDAC_OUT DNL(1) INL(1) Offset(1) Offset1(1) 106/130 Unit V VSSA µA kΩ Capacitive load DAC output buffer ON - - 50 pF Output impedance DAC output buffer OFF 12 16 20 kΩ DAC output buffer ON 0.2 - VDDA – 0.2 V DAC output buffer OFF 0.5 - VREF+ – 1LSB mV CL ≤ 50 pF, RL ≥ 5 kΩ DAC output buffer ON - 1.5 3 No RL, CL ≤ 50 pF DAC output buffer OFF - 1.5 3 CL ≤ 50 pF, RL ≥ 5 kΩ DAC output buffer ON - 2 4 No RL, CL ≤ 50 pF DAC output buffer OFF - 2 4 CL ≤ 50 pF, RL ≥ 5 kΩ DAC output buffer ON - ±10 ±25 No RL, CL ≤ 50 pF DAC output buffer OFF - ±5 ±8 No RL, CL ≤ 50 pF DAC output buffer OFF - ±1.5 ±5 Voltage on DAC_OUT output Differential non linearity(3) Integral non linearity(4) Offset error at code 0x800 (5) Offset error at code 0x001(6) DocID025882 Rev 7 LSB STM32L162xE Electrical characteristics Table 58. DAC characteristics (continued) Symbol Parameter Conditions VDDA = 3.3V VREF+ = 3.0V TA = 0 to 50 ° C DAC output buffer OFF Offset error temperature dOffset/dT(1) coefficient (code 0x800) V = 3.3V Min Typ Max -20 -10 0 Unit µV/°C DDA VREF+ = 3.0V TA = 0 to 50 ° C DAC output buffer ON 0 20 50 CL ≤ 50 pF, RL ≥ 5 kΩ DAC output buffer ON - No RL, CL ≤ 50 pF DAC output buffer OFF - +0 / -0.2% +0 / -0.4% VDDA = 3.3V VREF+ = 3.0V TA = 0 to 50 ° C DAC output buffer OFF -10 -2 0 VDDA = 3.3V VREF+ = 3.0V TA = 0 to 50 ° C DAC output buffer ON -40 -8 0 CL ≤ 50 pF, RL ≥ 5 kΩ DAC output buffer ON - 12 30 No RL, CL ≤ 50 pF DAC output buffer OFF - 8 12 tSETTLING Settling time (full scale: for a 12-bit code transition between the lowest and the highest CL ≤ 50 pF, RL ≥ 5 kΩ input codes till DAC_OUT reaches final value ±1LSB - 7 12 µs Update rate Max frequency for a correct DAC_OUT change (95% of final value) with 1 LSB variation in the input code CL ≤ 50 pF, RL ≥ 5 kΩ - - 1 Msps tWAKEUP Wakeup time from off state (setting the ENx bit CL ≤ 50 pF, RL ≥ 5 kΩ in the DAC Control (8) register) - 9 15 µs PSRR+ VDDA supply rejection ratio (static DC measurement) - -60 -35 dB Gain(1) dGain/dT(1) TUE(1) Gain error(7) Gain error temperature coefficient Total unadjusted error CL ≤ 50 pF, RL ≥ 5 kΩ +0.1 / -0.2% +0.2 / -0.5% % µV/°C LSB 1. Data based on characterization results. 2. Connected between DAC_OUT and VSSA. 3. Difference between two consecutive codes - 1 LSB. DocID025882 Rev 7 107/130 112 Electrical characteristics STM32L162xE 4. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095. 5. Difference between the value measured at Code (0x800) and the ideal value = VREF+/2. 6. Difference between the value measured at Code (0x001) and the ideal value. 7. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when buffer is OFF, and from code giving 0.2 V and (VDDA – 0.2) V when buffer is ON. 8. In buffered mode, the output can overshoot above the final value for low input code (starting from min value). Figure 29. 12-bit buffered /non-buffered DAC %XIIHUHG1RQEXIIHUHG'$& %XIIHU 5/ '$&B287[ ELW GLJLWDOWR DQDORJ FRQYHUWHU &/ AI6 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 6.3.19 Operational amplifier characteristics Table 59. Operational amplifier characteristics Symbol CMIR VIOFFSET Condition(1) Min(2) Typ Max(2) - 0 - VDD Maximum calibration range - - - ±15 After offset calibration - - - ±1.5 - - - ±40 - - - ±80 - - 1 - - 10 Parameter Common mode input range Input offset voltage ΔVIOFFSET Input offset voltage Normal mode drift Low-power mode IIB Input current bias ILOAD Drive current IDD Consumption CMRR Common mode rejection ration mV Dedicated input 108/130 General purpose input 75 °C Normal mode - - - 500 Low-power mode - - - 100 - 100 220 - 30 60 Normal mode Low-power mode Unit No load, quiescent mode Normal mode - - -85 - Low-power mode - - -90 - DocID025882 Rev 7 µV/°C nA µA µA dB STM32L162xE Electrical characteristics Table 59. Operational amplifier characteristics (continued) Symbol PSRR Condition(1) Parameter Power supply rejection ratio Normal mode Low-power mode Normal mode GBW Bandwidth Low-power mode Normal mode Low-power mode SR Slew rate RL Resistive load CL Capacitive load VOHSAT High saturation voltage VDD2.4 V (between 0.1 V and VDD-0.1 V) - 700 - Low-power mode VDD>2.4 V - 100 - - 300 - - 50 - Normal mode 55 100 - Low-power mode 65 110 - 4 - - 20 - - - - 50 VDD100 - - VDD-50 - - - - 100 - - 50 Low-power mode Open loop gain VDD>2.4 V Typ Normal mode Normal mode AO DC Min(2) Normal mode Low-power mode VDD