STM32L431KBU3

STM32L431xx Ultra-low-power Arm® Cortex®-M4 32-bit MCU+FPU, 100DMIPS, up to 256KB Flash, 64KB SRAM, analog, audio Datasheet - production data Features • Ultra-low-power with FlexPowerControl – 1.71 V to 3.6 V power supply – -40 °C to 85/105/125 °C temperature range – 200 nA in VBAT mode: supply for RTC and 32x32-bit backup registers – 8 nA Shutdown mode (5 wakeup pins) – 28 nA Standby mode (5 wakeup pins) – 280 nA Standby mode with RTC – 1.0 µA Stop 2 mode, 1.28 µA with RTC – 84 µA/MHz run mode – Batch acquisition mode (BAM) – 4 µs wakeup from Stop mode – Brown out reset (BOR) – Interconnect matrix • Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait-state execution from Flash memory, frequency up to 80 MHz, MPU, 100DMIPS and DSP instructions • Performance benchmark – 1.25 DMIPS/MHz (Drystone 2.1) – 273.55 CoreMark® (3.42 CoreMark/MHz @ 80 MHz) • Energy benchmark – 176.7 ULPBench® score • Clock Sources – 4 to 48 MHz crystal oscillator – 32 kHz crystal oscillator for RTC (LSE) – Internal 16 MHz factory-trimmed RC (±1%) – Internal low-power 32 kHz RC (±5%) – Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by LSE (better than ±0.25 % accuracy) – Internal 48 MHz with clock recovery – 2 PLLs for system clock, audio, ADC LQFP100 (14x14) LQFP64 (10x10) UFQFPN32 (5x5) UFBGA100 (7×7) WLCSP64 LQFP48 (7x7) UFQFPN48 (7x7) UFBGA64 (5x5) WLCSP49 • Up to 83 fast I/Os, most 5 V-tolerant • RTC with HW calendar, alarms and calibration • Up to 21 capacitive sensing channels: support touchkey, linear and rotary touch sensors • 11x timers: 1x 16-bit advanced motor-control, 1x 32-bit and 2x 16-bit general purpose, 2x 16bit basic, 2x low-power 16-bit timers (available in Stop mode), 2x watchdogs, SysTick timer • Memories – Up to 256 KB single bank Flash, proprietary code readout protection – 64 KB of SRAM including 16 KB with hardware parity check – Quad SPI memory interface • Rich analog peripherals (independent supply) – 1x 12-bit ADC 5 Msps, up to 16-bit with hardware oversampling, 200 µA/Msps – 2x 12-bit DAC output channels, low-power sample and hold – 1x operational amplifier with built-in PGA – 2x ultra-low-power comparators • 16x communication interfaces – 1x SAI (serial audio interface) – 3x I2C FM+(1 Mbit/s), SMBus/PMBus – 4x USARTs (ISO 7816, LIN, IrDA, modem) – 1x LPUART (Stop 2 wake-up) – 3x SPIs (and 1x Quad SPI) – CAN (2.0B Active) and SDMMC interface – SWPMI single wire protocol master I/F – IRTIM (Infrared interface) • 14-channel DMA controller • True random number generator • CRC calculation unit, 96-bit unique ID May 2018 This is information on a product in full production. DS11453 Rev 3 1/208 www.st.com STM32L431xx • Development support: serial wire debug • All packages are ECOPACK2® compliant (SWD), JTAG, Embedded Trace Macrocell™ Table 1. Device summary Reference STM32L431xx 2/208 Part numbers STM32L431CC, STM32L431KC, STM32L431RC, STM32L431VC, STM32L431CB, STM32L431KB, STM32L431RB DS11453 Rev 3 STM32L431xx Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 Arm® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 17 3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.5 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.6 Firewall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.7 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.8 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 20 3.9 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.9.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.9.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.9.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.9.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.9.5 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.9.6 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.10 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.11 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.12 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.13 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.14 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.15 3.16 3.14.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 37 3.14.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 37 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.15.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.15.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.15.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 DS11453 Rev 3 3/208 6 Contents STM32L431xx 3.17 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.18 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.19 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.20 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.21 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.22 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.22.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.22.2 General-purpose timers (TIM2, TIM15, TIM16) . . . . . . . . . . . . . . . . . . . 44 3.22.3 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.22.4 Low-power timer (LPTIM1 and LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . . 44 3.22.5 Infrared interface (IRTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.22.6 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.22.7 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.22.8 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.23 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 46 3.24 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.25 Universal synchronous/asynchronous receiver transmitter (USART) . . . 48 3.26 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 49 3.27 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.28 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.29 Single wire protocol master interface (SWPMI) . . . . . . . . . . . . . . . . . . . . 51 3.30 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.31 Secure digital input/output and MultiMediaCards Interface (SDMMC) . . . 52 3.32 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.33 Quad SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.34 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.34.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.34.2 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.1 4/208 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 DS11453 Rev 3 STM32L431xx Contents 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 89 6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 89 6.3.4 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.3.6 Wakeup time from low-power modes and voltage scaling transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 119 6.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 6.3.10 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 6.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 6.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 6.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 6.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 6.3.16 Extended interrupt and event controller input (EXTI) characteristics . . 137 6.3.17 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 6.3.18 Analog-to-Digital converter characteristics . . . . . . . . . . . . . . . . . . . . . 138 6.3.19 Digital-to-Analog converter characteristics . . . . . . . . . . . . . . . . . . . . . 151 6.3.20 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 156 6.3.21 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 6.3.22 Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 159 6.3.23 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 6.3.24 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 6.3.25 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 6.3.26 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 164 DS11453 Rev 3 5/208 6 Contents 7 STM32L431xx Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 7.1 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 7.2 UFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 7.3 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 7.4 UFBGA64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 7.5 WLCSP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 7.6 WLCSP49 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 7.7 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 7.8 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 7.9 UFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 7.10 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 7.10.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 7.10.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 204 8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 6/208 DS11453 Rev 3 STM32L431xx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 STM32L431xx family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . 13 Access status versus readout protection level and execution modes. . . . . . . . . . . . . . . . . 18 STM32L431xx modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Functionalities depending on the working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 STM32L431xx peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 STM32L431xx USART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 SAI implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 STM32L431xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Alternate function AF0 to AF7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Alternate function AF8 to AF15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 STM32L431xx memory map and peripheral register boundary addresses . . . . . . . . . . . . 81 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 89 Embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Current consumption in Run and Low-power run modes, code with data processing running from Flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . . 94 Current consumption in Run and Low-power run modes, code with data processing running from Flash, ART disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Current consumption in Run and Low-power run modes, code with data processing running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . . 97 Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Typical current consumption in Run and Low-power run modes, with different codes running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Current consumption in Sleep and Low-power sleep modes, Flash ON . . . . . . . . . . . . . . 99 Current consumption in Low-power sleep modes, Flash in power-down . . . . . . . . . . . . . 100 Current consumption in Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Current consumption in Stop 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 DS11453 Rev 3 7/208 9 List of tables Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. 8/208 STM32L431xx Wakeup time using USART/LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 PLL, PLLSAI1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 EXTI Input Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Analog switches booster characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 ADC accuracy - limited test conditions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 ADC accuracy - limited test conditions 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 ADC accuracy - limited test conditions 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 ADC accuracy - limited test conditions 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 OPAMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 IWDG min/max timeout period at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 WWDG min/max timeout value at 80 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Quad SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 QUADSPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 SD / MMC dynamic characteristics, VDD=2.7 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . 174 eMMC dynamic characteristics, VDD = 1.71 V to 1.9 V . . . . . . . . . . . . . . . . . . . . . . . . . . 175 SWPMI electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 DS11453 Rev 3 STM32L431xx Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. List of tables UFBGA100 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 181 LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 UFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 UFBGA64 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . 186 WLCSP64 - 64-ball, 3.141 x 3.127 mm, 0.35 mm pitch wafer level chip scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 WLCSP64 recommended PCB design rules (0.35 mm pitch) . . . . . . . . . . . . . . . . . . . . . 189 WLCSP49 - 49-ball, 3.141 x 3.127 mm, 0.4 mm pitch wafer level chip scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 WLCSP49 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . . 193 LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 STM32L431xx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 DS11453 Rev 3 9/208 9 List of figures STM32L431xx List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. 10/208 STM32L431xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Power-up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Voltage reference buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 STM32L431Vx LQFP100 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 STM32L431Vx UFBGA100 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 STM32L431Rx LQFP64 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 STM32L431Rx UFBGA64 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 STM32L431Rx WLCSP64 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 STM32L431Cx WLCSP49 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 STM32L431Cx LQFP48 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 STM32L431Cx UFQFPN48 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 STM32L431Kx UFQFPN32 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 STM32L431xx memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 VREFINT versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 HSI16 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Typical current consumption versus MSI frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 HSI48 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 I/O AC characteristics definition(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Quad SPI timing diagram - SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Quad SPI timing diagram - DDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . 177 LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 LQFP100 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 DS11453 Rev 3 STM32L431xx Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. List of figures UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 UFBGA100 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 183 LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 LQFP64 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 UFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 UFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 UFBGA64 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 WLCSP64 - 64-ball, 3.141 x 3.127 mm, 0.35 mm pitch wafer level chip scale package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 WLCSP64 - 64-ball, 3.141 x 3.127 mm, 0.35 mm pitch wafer level chip scale package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 WLCSP64 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 WLCSP49 - 49-ball, 3.141 x 3.127 mm, 0.4 mm pitch wafer level chip scale package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 WLCSP49 - 49-ball, 3.141 x 3.127 mm, 0.4 mm pitch wafer level chip scale package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 WLCSP49 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 194 LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 LQFP48 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 UFQFPN48 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 UFQFPN32 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 LQFP64 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 DS11453 Rev 3 11/208 11 Introduction 1 STM32L431xx Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32L431xx microcontrollers. This document should be read in conjunction with the STM32L43xxx/44xxx/45xxx/46xxx reference manual (RM0394). The reference manual is available from the STMicroelectronics website www.st.com. For information on the Arm®(a) Cortex®-M4 core, please refer to the Cortex®-M4 Technical Reference Manual, available from the www.arm.com website. a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. 12/208 DS11453 Rev 3 STM32L431xx 2 Description Description The STM32L431xx devices are the ultra-low-power microcontrollers based on the highperformance Arm® Cortex®-M4 32-bit RISC core operating at a frequency of up to 80 MHz. The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all Arm® single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security. The STM32L431xx devices embed high-speed memories (Flash memory up to 256 Kbyte, 64 Kbyte of SRAM), a Quad SPI flash memories interface (available on all packages) and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix. The STM32L431xx devices embed several protection mechanisms for embedded Flash memory and SRAM: readout protection, write protection, proprietary code readout protection and Firewall. The devices offer a fast 12-bit ADC (5 Msps), two comparators, one operational amplifier, two DAC channels, an internal voltage reference buffer, a low-power RTC, one generalpurpose 32-bit timer, one 16-bit PWM timer dedicated to motor control, four general-purpose 16-bit timers, and two 16-bit low-power timers. In addition, up to 21 capacitive sensing channels are available. They also feature standard and advanced communication interfaces. • Three I2Cs • Three SPIs • Three USARTs and one Low-Power UART. • One SAI (Serial Audio Interfaces) • One SDMMC • One CAN • One SWPMI (Single Wire Protocol Master Interface) The STM32L431xx operates in the -40 to +85 °C (+105 °C junction), -40 to +105 °C (+125 °C junction) and -40 to +125 °C (+130 °C junction) temperature ranges from a 1.71 to 3.6 V power supply. A comprehensive set of power-saving modes allows the design of lowpower applications. Some independent power supplies are supported: analog independent supply input for ADC, DAC, OPAMP and comparators. A VBAT input allows to backup the RTC and backup registers. The STM32L431xx family offers nine packages from 32 to 100-pin packages. Table 2. STM32L431xx family device features and peripheral counts Peripheral Flash memory STM32L431Vx 256KB STM32L431Rx 128KB 256KB SRAM STM32L431Cx 128KB 256KB STM32L431Kx 128KB 256KB 64KB Quad SPI Yes DS11453 Rev 3 13/208 54 Description STM32L431xx Table 2. STM32L431xx family device features and peripheral counts (continued) Peripheral Timers STM32L431Vx STM32L431Rx STM32L431Cx Advanced control 1 (16-bit) General purpose 2 (16-bit) 1 (32-bit) Basic 2 (16-bit) Low power 2 (16-bit) SysTick timer 1 Watchdog timers (indepen dent, window) 2 SPI 3 2 I2C 3 2 USART LPUART 3 1 2 1 Comm. interfaces SAI 1 CAN 1 SDMMC Yes No SWPMI Yes RTC Tamper pins Yes 3 2 Random generator 2 1 Yes GPIOs Wakeup pins 83 5 52 4 38 or 39(1) 3 26 2 Capacitive sensing Number of channels 21 12 6 3 12-bit ADC Number of channels 1 16 1 16 1 10 1 10 12-bit DAC channels Internal voltage reference buffer 2 No Yes Analog comparator 2 Operational amplifiers 1 Max. CPU frequency Operating voltage 14/208 STM32L431Kx 80 MHz 1.71 to 3.6 V DS11453 Rev 3 STM32L431xx Description Table 2. STM32L431xx family device features and peripheral counts (continued) Peripheral Operating temperature STM32L431Vx STM32L431Rx STM32L431Cx STM32L431Kx Ambient operating temperature: -40 to 85 °C / -40 to 105 °C / -40 to 125 °C Junction temperature: -40 to 105 °C / -40 to 125 °C / -40 to 130 °C Packages LQFP100 UFBGA100 WLCSP64 LQFP64 UFBGA64 WLCSP49 LQFP48 UFQFPN48 UFQFPN32 1. For WLCSP49 package. DS11453 Rev 3 15/208 54 Description STM32L431xx Figure 1. STM32L431xx block diagram D0[3:0], D1[3:0], CLK0, CLK1 CS NJTRST, JTDI, JTCK/SWCLK Quad SPI memory interface JTAG & SW MPU ETM NVIC JTDO/SWD, JTDO TRACECLK D-BUS TRACED[3:0] ARM Cortex-M4 80 MHz FPU I-BUS ART ACCEL/ CACHE RNG Flash up to 256 KB AHB bus-matrix S-BUS SRAM 48 KB SRAM 16 KB VDD AHB2 80 MHz DMA2 Power management Voltage regulator 3.3 to 1.2 V VDD = 1.71 to 3.6 V VSS DMA1 @ VDD @ VDD 7 Groups of 3 channels max as AF supervision RC HSI Touch sensing controller Supply reset MSI Int VDDA, VSSA BOR VDD, VSS, NRST RC LSI GPIO PORT A PB[15:0] GPIO PORT B PC[15:0] GPIO PORT C PVD, PVM PLL 1&2 AHB1 80 MHz PA[15:0] @VDD HSI48 OSC_IN XTAL OSC OSC_OUT 4- 16MHz IWDG PD[15:0] GPIO PORT D PE[15:0] GPIO PORT E VBAT = 1.55 to 3.6 V Standby PH[1:0], PH[3] interface Reset & clock M AN AGT control @VBAT GPIO PORT H XTAL 32 kHz OSC32_IN OSC32_OUT PCLKx HCLKx FCLK RTC RTC_TS AWU Backup register RTC_TAMPx RTC_OUT @ VDD TIM2 U STemperature AR T 2 M sensor Bps CRC 32b 4 channels, ETR as AF @ VDDA ADC1 16 external analog inputs ITF CRS_SYNC CRS @ VDDA VREF+ VREF Buffer 83 AF AHB/APB2 AHB/APB1 USART2 SDIO / MMC FIFO USART3 D[7:0] CMD, CK as AF 3 compl. channels (TIM1_CH[1:3]N), 4 channels (TIM1_CH[1:4]), ETR, BKIN, BKIN2 as AF TIM1 / PWM 16b WWDG TIM16 smcard 16b USART1 IrDA SPI1 MCLK_A, SD_A, FS_A, SCK_A, EXTCLK MCLK_B, SD_B, FS_B, SCK_B as AF SAI1 TIM6 16b TIM7 16b A 60PM B Hz 2 MOSI, MISO, SCK, NSS as AF @ VDDA INP, INM, OUT smcard RX, TX, CK, CTS, RTS as AF RX, TX, CK, CTS, RTS as AF IrDA SPI2 MOSI, MISO, SCK, NSS as AF SPI3 MOSI, MISO, SCK, NSS as AF I2C1/SMBUS SCL, SDA, SMBA as AF I2C2/SMBUS SCL, SDA, SMBA as AF I2C3/SMBUS SCL, SDA, SMBA as AF bxCAN1 DAC1 COMP2 TX, RX as AF @VDDA OpAmp1 VOUT, VINM, VINP LPUART1 RX, TX, CTS, RTS as AF SWPMI1 IO RX, TX, SUSPEND as AF LPTIM1 IN1, IN2, OUT, ETR as AF LPTIM2 IN1, OUT, ETR as AF @ VDDA COMP1 FIFO 1 channel, 1 compl. channel, BKIN as AF INP, INM, OUT IrDA 16b A P B(max) 1 3 0 M Hz APB1 80 MHz TIM15 APB2 80MHz 2 channels, 1 compl. channel, BKIN as AF RX, TX, CK,CTS, RTS as AF smcard EXT IT. WKUP ITF DAC2 FIREWALL OUT1 Note: 16/208 OUT2 AF: alternate function on I/O pins. DS11453 Rev 3 MSv39204V2 STM32L431xx Functional overview 3 Functional overview 3.1 Arm® Cortex®-M4 core with FPU The Arm® Cortex®-M4 with FPU processor is the latest generation of Arm® processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. The Arm® Cortex®-M4 with FPU 32-bit RISC processor features exceptional codeefficiency, delivering the high-performance expected from an Arm® core in the memory size usually associated with 8- and 16-bit devices. The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution. Its single precision FPU speeds up software development by using metalanguage development tools, while avoiding saturation. With its embedded Arm® core, the STM32L431xx family is compatible with all Arm® tools and software. Figure 1 shows the general block diagram of the STM32L431xx family devices. 3.2 Adaptive real-time memory accelerator (ART Accelerator™) The ART Accelerator™ is a memory accelerator which is optimized for STM32 industrystandard Arm® Cortex®-M4 processors. It balances the inherent performance advantage of the Arm® Cortex®-M4 over Flash memory technologies, which normally requires the processor to wait for the Flash memory at higher frequencies. To release the processor near 100 DMIPS performance at 80MHz, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 64-bit Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 80 MHz. 3.3 Memory protection unit The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it. DS11453 Rev 3 17/208 54 Functional overview 3.4 STM32L431xx Embedded Flash memory STM32L431xx devices feature up to 256 Kbyte of embedded Flash memory available for storing programs and data in single bank architecture. The Flash memory contains 128 pages of 2 Kbyte. Flexible protections can be configured thanks to option bytes: • Readout protection (RDP) to protect the whole memory. Three levels are available: – Level 0: no readout protection – Level 1: memory readout protection: the Flash memory cannot be read from or written to if either debug features are connected, boot in RAM or bootloader is selected – Level 2: chip readout protection: debug features (Cortex-M4 JTAG and serial wire), boot in RAM and bootloader selection are disabled (JTAG fuse). This selection is irreversible. Table 3. Access status versus readout protection level and execution modes Area Debug, boot from RAM or boot from system memory (loader) User execution Protection level Read Write Erase Read Write Erase Main memory 1 Yes Yes Yes No No No 2 Yes Yes Yes N/A N/A N/A System memory 1 Yes No No Yes No No 2 Yes No No N/A N/A N/A Option bytes 1 Yes Yes Yes Yes Yes Yes 2 Yes No No N/A N/A N/A No No N/A(1) Backup registers SRAM2 (1) 1 Yes Yes N/A 2 Yes Yes N/A N/A N/A N/A 1 Yes Yes Yes(1) No No No(1) 2 Yes Yes Yes N/A N/A N/A 1. Erased when RDP change from Level 1 to Level 0. 18/208 • Write protection (WRP): the protected area is protected against erasing and programming. Two areas can be selected, with 2-Kbyte granularity. • Proprietary code readout protection (PCROP): a part of the flash memory can be protected against read and write from third parties. The protected area is execute-only: it can only be reached by the STM32 CPU, as an instruction code, while all other accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited. The PCROP area granularity is 64-bit wide. An additional option bit (PCROP_RDP) allows to select if the PCROP area is erased or not when the RDP protection is changed from Level 1 to Level 0. DS11453 Rev 3 STM32L431xx Functional overview The whole non-volatile memory embeds the error correction code (ECC) feature supporting: 3.5 • single error detection and correction • double error detection. • The address of the ECC fail can be read in the ECC register Embedded SRAM STM32L431xx devices feature 64 Kbyte of embedded SRAM. This SRAM is split into two blocks: • 48 Kbyte mapped at address 0x2000 0000 (SRAM1) • 16 Kbyte located at address 0x1000 0000 with hardware parity check (SRAM2). This memory is also mapped at address 0x2000 C000, offering a contiguous address space with the SRAM1 (16 Kbyte aliased by bit band) This block is accessed through the ICode/DCode buses for maximum performance. These 16 Kbyte SRAM can also be retained in Standby mode. The SRAM2 can be write-protected with 1 Kbyte granularity. The memory can be accessed in read/write at CPU clock speed with 0 wait states. 3.6 Firewall The device embeds a Firewall which protects code sensitive and secure data from any access performed by a code executed outside of the protected areas. Each illegal access generates a reset which kills immediately the detected intrusion. The Firewall main features are the following: • Three segments can be protected and defined thanks to the Firewall registers: – Code segment (located in Flash or SRAM1 if defined as executable protected area) – Non-volatile data segment (located in Flash) – Volatile data segment (located in SRAM1) • The start address and the length of each segments are configurable: – Code segment: up to 1024 Kbyte with granularity of 256 bytes – Non-volatile data segment: up to 1024 Kbyte with granularity of 256 bytes – Volatile data segment: up to 48 Kbyte with a granularity of 64 bytes • Specific mechanism implemented to open the Firewall to get access to the protected areas (call gate entry sequence) • Volatile data segment can be shared or not with the non-protected code • Volatile data segment can be executed or not depending on the Firewall configuration The Flash readout protection must be set to level 2 in order to reach the expected level of protection. DS11453 Rev 3 19/208 54 Functional overview 3.7 STM32L431xx Boot modes At startup, BOOT0 pin or nSWBOOT0 option bit, and BOOT1 option bit are used to select one of three boot options: • Boot from user Flash • Boot from system memory • Boot from embedded SRAM BOOT0 value may come from the PH3-BOOT0 pin or from an option bit depending on the value of a user option bit to free the GPIO pad if needed. A Flash empty check mechanism is implemented to force the boot from system flash if the first flash memory location is not programmed and if the boot selection is configured to boot from main flash. The boot loader is located in system memory. It is used to reprogram the Flash memory by using USART, I2C, SPI or CAN. 3.8 Cyclic redundancy check calculation unit (CRC) The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. 3.9 Power supply management 3.9.1 Power supply schemes • VDD = 1.71 to 3.6 V: external power supply for I/Os (VDDIO1), the internal regulator and the system analog such as reset, power management and internal clocks. It is provided externally through VDD pins. • VDDA = 1.62 V (ADCs/COMPs) / 1.8 (DAC/OPAMP) to 3.6 V: external analog power supply for ADCs, DAC, OPAMPs, Comparators and Voltage reference buffer. The VDDA voltage level is independent from the VDD voltage. • VBAT = 1.55 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. Note: When the functions supplied by VDDA are not used, this supply should preferably be shorted to VDD. Note: If these supplies are tied to ground, the I/Os supplied by these power supplies are not 5 V tolerant (refer to Table 19: Voltage characteristics). Note: VDDIOx is the I/Os general purpose digital functions supply. VDDIOx represents VDDIO1, with VDDIO1 = VDD. 20/208 DS11453 Rev 3 STM32L431xx Functional overview Figure 2. Power supply overview VDDA domain VDDA VSSA A/D converters Comparators D/A converters Operational amplifiers Voltage reference buffer VDD domain VDD VDDIO1 I/O ring Reset block Temp. sensor PLL, HSI, MSI, HSI48 VSS Standby circuitry (Wakeup logic, IWDG) Voltage regulator VCORE VCORE domain Core Memories Digital peripherals Low voltage detector Backup domain VBAT LSE crystal 32 K osc BKP registers RCC BDCR register RTC MSv39205V2 During power-up and power-down phases, the following power sequence requirements must be respected: • When VDD is below 1 V, other power supplies (VDDA) must remain below VDD + 300 mV. • When VDD is above 1 V, all power supplies are independent. During the power-down phase, VDD can temporarily become lower than other supplies only if the energy provided to the MCU remains below 1 mJ; this allows external decoupling capacitors to be discharged with different time constants during the power- down transient phase. DS11453 Rev 3 21/208 54 Functional overview STM32L431xx Figure 3. Power-up/down sequence V 3.6 VDDX(1) VDD VBOR0 1 0.3 Power-on Invalid supply area Operating mode VDDX < VDD + 300 mV Power-down VDDX independent from VDD time MSv47490V1 1. VDDX refers to VDDA. 3.9.2 Power supply supervisor The device has an integrated ultra-low-power brown-out reset (BOR) active in all modes except Shutdown and ensuring proper operation after power-on and during power down. The device remains in reset mode when the monitored supply voltage VDD is below a specified threshold, without the need for an external reset circuit. The lowest BOR level is 1.71V at power on, and other higher thresholds can be selected through option bytes.The device features an embedded programmable voltage detector (PVD) that monitors the VDD power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. In addition, the device embeds a Peripheral Voltage Monitor which compares the independent supply voltage VDDA with a fixed threshold in order to ensure that the peripheral is in its functional supply range. 22/208 DS11453 Rev 3 STM32L431xx 3.9.3 Functional overview Voltage regulator Two embedded linear voltage regulators supply most of the digital circuitries: the main regulator (MR) and the low-power regulator (LPR). • The MR is used in the Run and Sleep modes and in the Stop 0 mode. • The LPR is used in Low-Power Run, Low-Power Sleep, Stop 1 and Stop 2 modes. It is also used to supply the 16 Kbyte SRAM2 in Standby with SRAM2 retention. • Both regulators are in power-down in Standby and Shutdown modes: the regulator output is in high impedance, and the kernel circuitry is powered down thus inducing zero consumption. The ultralow-power STM32L431xx supports dynamic voltage scaling to optimize its power consumption in run mode. The voltage from the Main Regulator that supplies the logic (VCORE) can be adjusted according to the system’s maximum operating frequency. There are two power consumption ranges: • Range 1 with the CPU running at up to 80 MHz. • Range 2 with a maximum CPU frequency of 26 MHz. All peripheral clocks are also limited to 26 MHz. The VCORE can be supplied by the low-power regulator, the main regulator being switched off. The system is then in Low-power run mode. • 3.9.4 Low-power run mode with the CPU running at up to 2 MHz. Peripherals with independent clock can be clocked by HSI16. Low-power modes The ultra-low-power STM32L431xx supports seven low-power modes to achieve the best compromise between low-power consumption, short startup time, available peripherals and available wakeup sources. DS11453 Rev 3 23/208 54 Mode Run LPRun Sleep LPSleep Regulator(1) MR range 1 MR range2 LPR MR range 1 MR range2 LPR DS11453 Rev 3 Flash SRAM Clocks Yes ON(4) ON Any Yes ON(4) ON Any except PLL No ON(4) ON(5) Any No ON(4) ON(5) Any except PLL All except USB_FS, RNG Any interrupt or event LSE LSI BOR, PVD, PVM RTC, IWDG COMPx (x=1,2) DAC1 OPAMPx (x=1) USARTx (x=1...3)(6) LPUART1(6) I2Cx (x=1...3)(7) LPTIMx (x=1,2) *** All other peripherals are frozen. Reset pin, all I/Os BOR, PVD, PVM RTC, IWDG COMPx (x=1..2) USARTx (x=1...3)(6) LPUART1(6) I2Cx (x=1...3)(7) LPTIMx (x=1,2) SWPMI1(8) MR Range 1 Stop 0 No MR Range 2 DMA & Peripherals(2) CPU OFF ON All All except RNG Wakeup source N/A Consumption(3) 97 µA/MHz 84 µA/MHz All except USB_FS, RNG N/A 94 µA/MHz All Any interrupt or event 28 µA/MHz All except RNG 26 µA/MHz 29 µA/MHz Wakeup time N/A to Range 1: 4 µs to Range 2: 64 µs Functional overview 24/208 Table 4. STM32L431xx modes overview 6 cycles 6 cycles 108 µA 2.4 µs in SRAM 4.1 µs in Flash 108 µA STM32L431xx Mode Stop 1 DS11453 Rev 3 Stop 2 Regulator LPR LPR CPU No No DMA & Peripherals(2) Wakeup source Consumption(3) Wakeup time LSE LSI BOR, PVD, PVM RTC, IWDG COMPx (x=1,2) DAC1 OPAMPx (x=1) USARTx (x=1...3)(6) LPUART1(6) I2Cx (x=1...3)(7) LPTIMx (x=1,2) *** All other peripherals are frozen. Reset pin, all I/Os BOR, PVD, PVM RTC, IWDG COMPx (x=1..2) USARTx (x=1...3)(6) LPUART1(6) I2Cx (x=1...3)(7) LPTIMx (x=1,2) SWPMI1(8) 4.34 µA w/o RTC 4.63 µA w RTC 6.3 µs in SRAM 7.8 µs in Flash LSE LSI BOR, PVD, PVM RTC, IWDG COMPx (x=1..2) I2C3(7) LPUART1(6) LPTIM1 *** All other peripherals are frozen. Reset pin, all I/Os BOR, PVD, PVM RTC, IWDG COMPx (x=1..2) I2C3(7) LPUART1(6) LPTIM1 1.3 µA w/o RTC 1.4 µA w/RTC 6.8 µs in SRAM 8.2 µs in Flash Flash SRAM Clocks Off Off ON ON STM32L431xx Table 4. STM32L431xx modes overview (continued) (1) Functional overview 25/208 Mode Regulator CPU Flash SRAM Clocks Standby OFF Shutdown OFF Power ed Off Power ed Off Off Off Power ed Off Power ed Off Wakeup source Consumption(3) Wakeup time 0.20 µA w/o RTC 0.46 µA w/ RTC DS11453 Rev 3 LSE LSI BOR, RTC, IWDG *** All other peripherals are powered off. *** I/O configuration can be floating, pull-up or pull-down Reset pin 5 I/Os (WKUPx)(9) BOR, RTC, IWDG LSE RTC *** All other peripherals are powered off. *** I/O configuration can be floating, pull-up or pulldown(10) Reset pin 5 I/Os (WKUPx)(9) RTC SRAM 2 ON LPR DMA & Peripherals(2) 0.03 µA w/o RTC 0.29 µA w/ RTC 0.01 µA w/o RTC 0.20 µA w/ RTC 12.2 µs Functional overview 26/208 Table 4. STM32L431xx modes overview (continued) (1) 262 µs 1. LPR means Main regulator is OFF and Low-power regulator is ON. 2. All peripherals can be active or clock gated to save power consumption. 3. Typical current at VDD = 1.8 V, 25°C. Consumptions values provided running from SRAM, Flash memory Off, 80 MHz in Range 1, 26 MHz in Range 2, 2 MHz in LPRun/LPSleep. 4. The Flash memory can be put in power-down and its clock can be gated off when executing from SRAM. 5. The SRAM1 and SRAM2 clocks can be gated on or off independently. 6. U(S)ART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event. 7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match. 8. SWPMI1 wakeup by resume from suspend. 9. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5. 10. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode. STM32L431xx STM32L431xx Functional overview By default, the microcontroller is in Run mode after a system or a power Reset. It is up to the user to select one of the low-power modes described below: • Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. • Low-power run mode This mode is achieved with VCORE supplied by the low-power regulator to minimize the regulator's operating current. The code can be executed from SRAM or from Flash, and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can be clocked by HSI16. • Low-power sleep mode This mode is entered from the low-power run mode. Only the CPU clock is stopped. When wakeup is triggered by an event or an interrupt, the system reverts to the lowpower run mode. • Stop 0, Stop 1 and Stop 2 modes Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the VCORE domain are stopped, the PLL, the MSI RC, the HSI16 RC and the HSE crystal oscillators are disabled. The LSE or LSI is still running. The RTC can remain active (Stop mode with RTC, Stop mode without RTC). Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode to detect their wakeup condition. Three Stop modes are available: Stop 0, Stop 1 and Stop 2 modes. In Stop 2 mode, most of the VCORE domain is put in a lower leakage mode. Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller wakeup time but a higher consumption than Stop 2. In Stop 0 mode, the main regulator remains ON, allowing a very fast wakeup time but with much higher consumption. The system clock when exiting from Stop 0, Stop 1 or Stop 2 modes can be either MSI up to 48 MHz or HSI16, depending on software configuration. • Standby mode The Standby mode is used to achieve the lowest power consumption with BOR. The internal regulator is switched off so that the VCORE domain is powered off. The PLL, the MSI RC, the HSI16 RC and the HSE crystal oscillators are also switched off. The RTC can remain active (Standby mode with RTC, Standby mode without RTC). The brown-out reset (BOR) always remains active in Standby mode. The state of each I/O during standby mode can be selected by software: I/O with internal pull-up, internal pull-down or floating. After entering Standby mode, SRAM1 and register contents are lost except for registers in the Backup domain and Standby circuitry. Optionally, SRAM2 can be retained in Standby mode, supplied by the low-power Regulator (Standby with SRAM2 retention mode). The device exits Standby mode when an external reset (NRST pin), an IWDG reset, WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic wakeup, timestamp, tamper) or a failure is detected on LSE (CSS on LSE). The system clock after wakeup is MSI up to 8 MHz. DS11453 Rev 3 27/208 54 Functional overview • STM32L431xx Shutdown mode The Shutdown mode allows to achieve the lowest power consumption. The internal regulator is switched off so that the VCORE domain is powered off. The PLL, the HSI16, the MSI, the LSI and the HSE oscillators are also switched off. The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC). The BOR is not available in Shutdown mode. No power voltage monitoring is possible in this mode, therefore the switch to Backup domain is not supported. SRAM1, SRAM2 and register contents are lost except for registers in the Backup domain. The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic wakeup, timestamp, tamper). The system clock after wakeup is MSI at 4 MHz. 28/208 DS11453 Rev 3 STM32L431xx Functional overview Table 5. Functionalities depending on the working mode(1) - - Y - Y - - - - - - - - - - O(2) O(2) O(2) O(2) - - - - - - - - - SRAM1 (48 KB) Y Y(3) Y Y(3) Y - Y - - - - - - SRAM2 (16 KB) Y Y(3) Y Y(3) Y - Y - O(4) - - - - Quad SPI O O O O - - - - - - - - - Backup Registers Y Y Y Y Y - Y - Y - Y - Y Brown-out reset (BOR) Y Y Y Y Y Y Y Y Y Y - - - Programmable Voltage Detector (PVD) O O O O O O O O - - - - - Peripheral Voltage Monitor (PVMx; x=1,3,4) O O O O O O O O - - - - - DMA O O O O - - - - - - - - - High Speed Internal (HSI16) O O O O (5) - (5) - - - - - - Oscillator RC48 O O - - - - - - - - - - - High Speed External (HSE) O O O O - - - - - - - - - Low Speed Internal (LSI) O O O O O - O - O - - - - Low Speed External (LSE) O O O O O - O - O - O - O Multi-Speed Internal (MSI) O O O O - - - - - - - - - Clock Security System (CSS) O O O O - - - - - - - - - Clock Security System on LSE O O O O O O O O O O - - - RTC / Auto wakeup O O O O O O O O O O O O O Number of RTC Tamper pins 3 3 3 3 3 O 3 O 3 O 3 O 3 USARTx (x=1,2,3) O O O O - - - - - - - Peripheral CPU Flash memory (up to 256 KB) Run Sleep Lowpower run Lowpower sleep - O(6) O(6) DS11453 Rev 3 Wakeup capability - Wakeup capability Standby Shutdown Wakeup capability Stop 2 Wakeup capability Stop 0/1 VBAT 29/208 54 Functional overview STM32L431xx Table 5. Functionalities depending on the working mode(1) (continued) O O O O O(6) O(6) O(6) O(6) - - - - - I2Cx (x=1,2) O O O O O(7) O(7) - - - - - - - O(7) O(7) O(7) - - - - - Sleep Lowpower run Lowpower sleep - - - Wakeup capability Wakeup capability Standby Shutdown Low-power UART (LPUART) Run Wakeup capability Stop 2 - Peripheral Wakeup capability Stop 0/1 VBAT I2C3 O O O O O(7) SPIx (x=1,2,3) O O O O - - - - - - - - - CAN O O O O - - - - - - - - - SDMMC1 O O O O - - - - - - - - - SWPMI1 O O O O - O - - - - - - - SAIx (x=1) O O O O - - - - - - - - - ADCx (x=1) O O O O - - - - - - - - - DAC1 O O O O O - - - - - - - - VREFBUF O O O O O - - - - - - - - OPAMPx (x=1) O O O O O - - - - - - - - COMPx (x=1,2) O O O O O O O O - - - - - Temperature sensor O O O O - - - - - - - - - Timers (TIMx) O O O O - - - - - - - - - Low-power timer 1 (LPTIM1) O O O O O O O O - - - - - Low-power timer 2 (LPTIM2) O O O O O O - - - - - - - Independent watchdog (IWDG) O O O O O O O O O O - - - Window watchdog (WWDG) O O O O - - - - - - - - - SysTick timer O O O O - - - - - - - - - Touch sensing controller (TSC) O O O O - - - - - - - - - Random number generator (RNG) O(8) O(8) - - - - - - - - - - - CRC calculation unit O O O O - - - - - - - - - GPIOs O O O O O O O O (9) 5 pins (11) 5 pins - 30/208 DS11453 Rev 3 (10) (10) STM32L431xx Functional overview 1. Legend: Y = Yes (Enable). O = Optional (Disable by default. Can be enabled by software). - = Not available. 2. The Flash can be configured in power-down mode. By default, it is not in power-down mode. 3. The SRAM clock can be gated on or off. 4. SRAM2 content is preserved when the bit RRS is set in PWR_CR3 register. 5. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not need it anymore. 6. UART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event. 7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match. 8. Voltage scaling Range 1 only. 9. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode. 10. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5. 11. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode. 3.9.5 Reset mode In order to improve the consumption under reset, the I/Os state under and after reset is “analog state” (the I/O schmitt trigger is disable). In addition, the internal reset pull-up is deactivated when the reset source is internal. 3.9.6 VBAT operation The VBAT pin allows to power the device VBAT domain from an external battery, an external supercapacitor, or from VDD when no external battery and an external supercapacitor are present. The VBAT pin supplies the RTC with LSE and the backup registers. Three antitamper detection pins are available in VBAT mode. VBAT operation is automatically activated when VDD is not present. An internal VBAT battery charging circuit is embedded and can be activated when VDD is present. Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events do not exit it from VBAT operation. 3.10 Interconnect matrix Several peripherals have direct connections between them. This allows autonomous communication between peripherals, saving CPU resources thus power supply consumption. In addition, these hardware connections allow fast and predictable latency. Depending on peripherals, these interconnections can operate in Run, Sleep, low-power run and sleep, Stop 0, Stop 1 and Stop 2 modes. DS11453 Rev 3 31/208 54 Functional overview STM32L431xx Run Sleep Low-power run Low-power sleep Stop 0 / Stop 1 Stop 2 Table 6. STM32L431xx peripherals interconnect matrix TIMx Timers synchronization or chaining Y Y Y Y - - ADCx DAC1 Conversion triggers Y Y Y Y - - DMA Memory to memory transfer trigger Y Y Y Y - - COMPx Comparator output blanking Y Y Y Y - - IRTIM Infrared interface output generation Y Y Y Y - - TIM1 TIM2 Timer input channel, trigger, break from analog signals comparison Y Y Y Y - - LPTIMERx Low-power timer triggered by analog signals comparison Y Y Y Y Y (1) TIM1 Timer triggered by analog watchdog Y Y Y Y - - TIM16 Timer input channel from RTC events Y Y Y Y - - LPTIMERx Low-power timer triggered by RTC alarms or tampers Y Y Y Y Y (1) All clocks sources (internal TIM2 and external) TIM15, 16 Clock source used as input channel for RC measurement and trimming Y Y Y Y - - CSS CPU (hard fault) RAM (parity error) TIM1 Flash memory (ECC error) TIM15,16 COMPx PVD Timer break Y Y Y Y - - TIMx External trigger Y Y Y Y - - LPTIMERx External trigger Y Y Y Y Y (1) ADCx DAC1 Conversion external trigger Y Y Y Y - - Interconnect source TIMx TIM15/TIM16 COMPx ADCx RTC Interconnect destination Interconnect action Y Y Y GPIO 1. LPTIM1 only. 32/208 DS11453 Rev 3 STM32L431xx 3.11 Functional overview Clocks and startup The clock controller (see Figure 4) distributes the clocks coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness. It features: • Clock prescaler: to get the best trade-off between speed and current consumption, the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler • Safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register. • Clock management: to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. • System clock source: four different clock sources can be used to drive the master clock SYSCLK: – 4-48 MHz high-speed external crystal or ceramic resonator (HSE), that can supply a PLL. The HSE can also be configured in bypass mode for an external clock. – 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software, that can supply a PLL – Multispeed internal RC oscillator (MSI), trimmable by software, able to generate 12 frequencies from 100 kHz to 48 MHz. When a 32.768 kHz clock source is available in the system (LSE), the MSI frequency can be automatically trimmed by hardware to reach better than ±0.25% accuracy. The MSI can supply a PLL. – System PLL which can be fed by HSE, HSI16 or MSI, with a maximum frequency at 80 MHz. • RC48 with clock recovery system (HSI48): internal RC48 MHz clock source can be used to drive the SDMMC or the RNG peripherals. This clock can be output on the MCO. • Auxiliary clock source: two ultralow-power clock sources that can be used to drive the real-time clock: – 32.768 kHz low-speed external crystal (LSE), supporting four drive capability modes. The LSE can also be configured in bypass mode for an external clock. – 32 kHz low-speed internal RC (LSI), also used to drive the independent watchdog. The LSI clock accuracy is ±5% accuracy. • Peripheral clock sources: Several peripherals (SDMMC, RNG, SAI, USARTs, I2Cs, LPTimers, ADC, SWPMI) have their own independent clock whatever the system clock. Two PLLs, each having three independent outputs allowing the highest flexibility, can generate independent clocks for the ADC, the SDMMC/RNG and the SAI. • Startup clock: after reset, the microcontroller restarts by default with an internal 4 MHz clock (MSI). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. • Clock security system (CSS): this feature can be enabled by software. If a HSE clock failure occurs, the master clock is automatically switched to HSI16 and a software DS11453 Rev 3 33/208 54 Functional overview STM32L431xx interrupt is generated if enabled. LSE failure can also be detected and generated an interrupt. • Clock-out capability: – MCO: microcontroller clock output: it outputs one of the internal clocks for external use by the application. Low frequency clocks (LSI, LSE) are available down to Stop 1 low power state. – LSCO: low speed clock output: it outputs LSI or LSE in all low-power modes down to Standby mode. LSE can also be output on LSCO in Shutdown mode. LSCO is not available in VBAT mode. Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the APB domains is 80 MHz. 34/208 DS11453 Rev 3 STM32L431xx Functional overview Figure 4. Clock tree to IWDG LSI RC 32 kHz LSCO to RTC OSC32_OUT LSE OSC 32.768 kHz /32 OSC32_IN LSE LSI HSE to PWR SYSCLK MCO / 1→16 MSI HSI16 Clock source control HSI48 OSC_OUT HSE OSC 4-48 MHz OSC_IN PLLCLK to AHB bus, core, memory and DMA AHB PRESC / 1,2,..512 HCLK to Cortex system timer HSE Clock detector FCLK Cortex free running clock /8 MSI SYSCLK APB1 PRESC / 1,2,4,8,16 HSI16 PCLK1 to APB1 peripherals x1 or x2 HSI RC 16 MHz LSE HSI16 SYSCLK to USARTx x=2..3 to LPUART1 HSI16 SYSCLK MSI RC 100 kHz – 48 MHz to TIMx x=2,6,7 to I2Cx x=1,2,3 LSI LSE HSI16 to LPTIMx x=1,2 HSI16 to SWPMI MSI PLL /M VCO FVCO PLLSAI1 VCO FVCO /P PLLSAI1CLK /Q PLL48M1CLK /R PLLCLK /P PLLSAI2CLK /Q PLL48M2CLK /R PLLADC1CLK PCLK2 HSI16 APB2 PRESC / 1,2,4,8,16 HSE to APB2 peripherals x1 or x2 LSE HSI16 SYSCLK SYSCLK HSI RC 48 MHz HSI16 to TIMx x=1,15,16 to USART1 to ADC MSI CRS 48 MHz clock to RNG, SDMMC HSI16 to SAI1 SAI1_EXTCLK MSv39206V3 DS11453 Rev 3 35/208 54 Functional overview 3.12 STM32L431xx General-purpose inputs/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be achieved thanks to their mapping on the AHB2 bus. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. 3.13 Direct memory access controller (DMA) The device embeds 2 DMAs. Refer to Table 7: DMA implementation for the features implementation. Direct memory access (DMA) is used in order to provide high-speed data transfer between peripherals and memory as well as memory to memory. Data can be quickly moved by DMA without any CPU actions. This keeps CPU resources free for other operations. The two DMA controllers have 14 channels in total, each dedicated to managing memory access requests from one or more peripherals. Each has an arbiter for handling the priority between DMA requests. The DMA supports: • 14 independently configurable channels (requests) • Each channel is connected to dedicated hardware DMA requests, software trigger is also supported on each channel. This configuration is done by software. • Priorities between requests from channels of one DMA are software programmable (4 levels consisting of very high, high, medium, low) or hardware in case of equality (request 1 has priority over request 2, etc.) • Independent source and destination transfer size (byte, half word, word), emulating packing and unpacking. Source/destination addresses must be aligned on the data size. • Support for circular buffer management • 3 event flags (DMA Half Transfer, DMA Transfer complete and DMA Transfer Error) logically ORed together in a single interrupt request for each channel • Memory-to-memory transfer • Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral transfers • Access to Flash, SRAM, APB and AHB peripherals as source and destination • Programmable number of data to be transferred: up to 65536. Table 7. DMA implementation 36/208 DMA features DMA1 DMA2 Number of regular channels 7 7 DS11453 Rev 3 STM32L431xx Functional overview 3.14 Interrupts and events 3.14.1 Nested vectored interrupt controller (NVIC) The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 67 maskable interrupt channels plus the 16 interrupt lines of the Cortex®M4. The NVIC benefits are the following: • Closely coupled NVIC gives low latency interrupt processing • Interrupt entry vector table address passed directly to the core • Allows early processing of interrupts • Processing of late arriving higher priority interrupts • Support for tail chaining • Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction overhead The NVIC hardware block provides flexible interrupt management features with minimal interrupt latency. 3.14.2 Extended interrupt/event controller (EXTI) The extended interrupt/event controller consists of 37 edge detector lines used to generate interrupt/event requests and wake-up the system from Stop mode. Each external line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The internal lines are connected to peripherals with wakeup from Stop mode capability. The EXTI can detect an external line with a pulse width shorter than the internal clock period. Up to 83 GPIOs can be connected to the 16 external interrupt lines. DS11453 Rev 3 37/208 54 Functional overview 3.15 STM32L431xx Analog to digital converter (ADC) The device embeds a successive approximation analog-to-digital converter with the following features: • 12-bit native resolution, with built-in calibration • 5.33 Msps maximum conversion rate with full resolution Down to 18.75 ns sampling time – Increased conversion rate for lower resolution (up to 8.88 Msps for 6-bit resolution) • Up to 16 external channels. • 5 internal channels: internal reference voltage, temperature sensor, VBAT/3, DAC1_OUT1 and DAC1_OUT2. • One external reference pin is available on some package, allowing the input voltage range to be independent from the power supply • Single-ended and differential mode inputs • Low-power design • 3.15.1 – – Capable of low-current operation at low conversion rate (consumption decreases linearly with speed) – Dual clock domain architecture: ADC speed independent from CPU frequency Highly versatile digital interface – Single-shot or continuous/discontinuous sequencer-based scan mode: 2 groups of analog signals conversions can be programmed to differentiate background and high-priority real-time conversions – ADC supports multiple trigger inputs for synchronization with on-chip timers and external signals – Results stored into data register or in RAM with DMA controller support – Data pre-processing: left/right alignment and per channel offset compensation – Built-in oversampling unit for enhanced SNR – Channel-wise programmable sampling time – Three analog watchdog for automatic voltage monitoring, generating interrupts and trigger for selected timers – Hardware assistant to prepare the context of the injected channels to allow fast context switching Temperature sensor The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature. The temperature sensor is internally connected to the ADC1_IN17 input channel which is used to convert the sensor output voltage into a digital value. The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode. 38/208 DS11453 Rev 3 STM32L431xx Functional overview Table 8. Temperature sensor calibration values 3.15.2 Calibration value name Description Memory address TS_CAL1 TS ADC raw data acquired at a temperature of 30 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV) 0x1FFF 75A8 - 0x1FFF 75A9 TS_CAL2 TS ADC raw data acquired at a temperature of 130 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV) 0x1FFF 75CA - 0x1FFF 75CB Internal voltage reference (VREFINT) The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the ADC and Comparators. VREFINT is internally connected to the ADC1_IN0 input channel. The precise voltage of VREFINT is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode. Table 9. Internal voltage reference calibration values 3.15.3 Calibration value name Description Memory address VREFINT Raw data acquired at a temperature of 30 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV) 0x1FFF 75AA - 0x1FFF 75AB VBAT battery voltage monitoring This embedded hardware feature allows the application to measure the VBAT battery voltage using the internal ADC channel ADC1_IN18. As the VBAT voltage may be higher than VDDA, and thus outside the ADC input range, the VBAT pin is internally connected to a bridge divider by 3. As a consequence, the converted digital value is one third the VBAT voltage. 3.16 Digital to analog converter (DAC) Two 12-bit buffered DAC channels can be used to convert digital signals into analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration. DS11453 Rev 3 39/208 54 Functional overview STM32L431xx This digital interface supports the following features: • Up to two DAC output channels • 8-bit or 12-bit output mode • Buffer offset calibration (factory and user trimming) • Left or right data alignment in 12-bit mode • Synchronized update capability • Noise-wave generation • Triangular-wave generation • Dual DAC channel independent or simultaneous conversions • DMA capability for each channel • External triggers for conversion • Sample and hold low-power mode, with internal or external capacitor The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels. 3.17 Voltage reference buffer (VREFBUF) The STM32L431xx devices embed an voltage reference buffer which can be used as voltage reference for ADCs, DAC and also as voltage reference for external components through the VREF+ pin. The internal voltage reference buffer supports two voltages: • 2.048 V • 2.5 V An external voltage reference can be provided through the VREF+ pin when the internal voltage reference buffer is off. The VREF+ pin is double-bonded with VDDA on some packages. In these packages the internal voltage reference buffer is not available. Figure 5. Voltage reference buffer VREFBUF VDDA Bandgap + DAC, ADC VREF+ Low frequency cut-off capacitor 100 nF MSv40197V1 40/208 DS11453 Rev 3 STM32L431xx 3.18 Functional overview Comparators (COMP) The STM32L431xx devices embed two rail-to-rail comparators with programmable reference voltage (internal or external), hysteresis and speed (low speed for low-power) and with selectable output polarity. The reference voltage can be one of the following: • External I/O • DAC output channels • Internal reference voltage or submultiple (1/4, 1/2, 3/4). All comparators can wake up from Stop mode, generate interrupts and breaks for the timers and can be also combined into a window comparator. 3.19 Operational amplifier (OPAMP) The STM32L431xx embeds one operational amplifier with external or internal follower routing and PGA capability. The operational amplifier features: 3.20 • Low input bias current • Low offset voltage • Low-power mode • Rail-to-rail input Touch sensing controller (TSC) The touch sensing controller provides a simple solution for adding capacitive sensing functionality to any application. Capacitive sensing technology is able to detect finger presence near an electrode which is protected from direct touch by a dielectric (glass, plastic, ...). The capacitive variation introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. The touch sensing controller is fully supported by the STMTouch touch sensing firmware library which is free to use and allows touch sensing functionality to be implemented reliably in the end application. DS11453 Rev 3 41/208 54 Functional overview STM32L431xx The main features of the touch sensing controller are the following: • Proven and robust surface charge transfer acquisition principle • Supports up to 21 capacitive sensing channels • Up to 3 capacitive sensing channels can be acquired in parallel offering a very good response time • Spread spectrum feature to improve system robustness in noisy environments • Full hardware management of the charge transfer acquisition sequence • Programmable charge transfer frequency • Programmable sampling capacitor I/O pin • Programmable channel I/O pin • Programmable max count value to avoid long acquisition when a channel is faulty • Dedicated end of acquisition and max count error flags with interrupt capability • One sampling capacitor for up to 3 capacitive sensing channels to reduce the system components • Compatible with proximity, touchkey, linear and rotary touch sensor implementation • Designed to operate with STMTouch touch sensing firmware library Note: The number of capacitive sensing channels is dependent on the size of the packages and subject to I/O availability. 3.21 Random number generator (RNG) All devices embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit. 3.22 Timers and watchdogs The STM32L431xx includes one advanced control timers, up to five general-purpose timers, two basic timers, two low-power timers, two watchdog timers and a SysTick timer. The table below compares the features of the advanced control, general purpose and basic timers. Table 10. Timer feature comparison Timer type Timer Counter resolution Counter type Prescaler factor DMA request generation Capture/ compare channels Complementary outputs Advanced control TIM1 16-bit Up, down, Up/down Any integer between 1 and 65536 Yes 4 3 Generalpurpose TIM2 32-bit Up, down, Up/down Any integer between 1 and 65536 Yes 4 No Generalpurpose TIM15 16-bit Up Any integer between 1 and 65536 Yes 2 1 42/208 DS11453 Rev 3 STM32L431xx Functional overview Table 10. Timer feature comparison (continued) Timer type Timer Counter resolution Counter type Prescaler factor DMA request generation Capture/ compare channels Complementary outputs Generalpurpose TIM16 16-bit Up Any integer between 1 and 65536 Yes 1 1 Basic TIM6, TIM7 16-bit Up Any integer between 1 and 65536 Yes 0 No 3.22.1 Advanced-control timer (TIM1) The advanced-control timer can each be seen as a three-phase PWM multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted deadtimes. They can also be seen as complete general-purpose timers. The 4 independent channels can be used for: • Input capture • Output compare • PWM generation (edge or center-aligned modes) with full modulation capability (0100%) • One-pulse mode output In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled to turn off any power switches driven by these outputs. Many features are shared with those of the general-purpose TIMx timers (described in Section 3.22.2) using the same architecture, so the advanced-control timer can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining. DS11453 Rev 3 43/208 54 Functional overview 3.22.2 STM32L431xx General-purpose timers (TIM2, TIM15, TIM16) There are up to three synchronizable general-purpose timers embedded in the STM32L431xx (see Table 10 for differences). Each general-purpose timer can be used to generate PWM outputs, or act as a simple time base. • TIM2 It is a full-featured general-purpose timer: TIM2 has a 32-bit auto-reload up/downcounter and 32-bit prescaler. This timer features 4 independent channels for input capture/output compare, PWM or one-pulse mode output. It can work with the other general-purpose timers via the Timer Link feature for synchronization or event chaining. The counter can be frozen in debug mode. It has independent DMA request generation and support quadrature encoder. • TIM15 and 16 They are general-purpose timers with mid-range features: They have 16-bit auto-reload upcounters and 16-bit prescalers. – TIM15 has 2 channels and 1 complementary channel – TIM16 has 1 channel and 1 complementary channel All channels can be used for input capture/output compare, PWM or one-pulse mode output. The timers can work together via the Timer Link feature for synchronization or event chaining. The timers have independent DMA request generation. The counters can be frozen in debug mode. 3.22.3 Basic timers (TIM6 and TIM7) The basic timers are mainly used for DAC trigger generation. They can also be used as generic 16-bit timebases. 3.22.4 Low-power timer (LPTIM1 and LPTIM2) The devices embed two low-power timers. These timers have an independent clock and are running in Stop mode if they are clocked by LSE, LSI or an external clock. They are able to wakeup the system from Stop mode. LPTIM1 is active in Stop 0, Stop 1 and Stop 2 modes. LPTIM2 is active in Stop 0 and Stop 1 mode. 44/208 DS11453 Rev 3 STM32L431xx Functional overview This low-power timer supports the following features: 3.22.5 • 16-bit up counter with 16-bit autoreload register • 16-bit compare register • Configurable output: pulse, PWM • Continuous/ one shot mode • Selectable software/hardware input trigger • Selectable clock source – Internal clock sources: LSE, LSI, HSI16 or APB clock – External clock source over LPTIM input (working even with no internal clock source running, used by pulse counter application). • Programmable digital glitch filter • Encoder mode (LPTIM1 only) Infrared interface (IRTIM) The STM32L431xx includes one infrared interface (IRTIM). It can be used with an infrared LED to perform remote control functions. It uses TIM15 and TIM16 output channels to generate output signal waveforms on IR_OUT pin. 3.22.6 Independent watchdog (IWDG) The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC (LSI) and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode. 3.22.7 System window watchdog (WWDG) The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 3.22.8 SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features: • A 24-bit down counter • Autoreload capability • Maskable system interrupt generation when the counter reaches 0. • Programmable clock source DS11453 Rev 3 45/208 54 Functional overview 3.23 STM32L431xx Real-time clock (RTC) and backup registers The RTC is an independent BCD timer/counter. It supports the following features: • Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format. • Automatic correction for 28, 29 (leap year), 30, and 31 days of the month. • Two programmable alarms. • On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master clock. • Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision. • Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal inaccuracy. • Three anti-tamper detection pins with programmable filter. • Timestamp feature which can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to VBAT mode. • 17-bit auto-reload wakeup timer (WUT) for periodic events with programmable resolution and period. The RTC and the 32 backup registers are supplied through a switch that takes power either from the VDD supply when present or from the VBAT pin. The backup registers are 32-bit registers used to store 128 bytes of user application data when VDD power is not present. They are not reset by a system or power reset, or when the device wakes up from Standby or Shutdown mode. The RTC clock sources can be: • A 32.768 kHz external crystal (LSE) • An external resonator or oscillator (LSE) • The internal low power RC oscillator (LSI, with typical frequency of 32 kHz) • The high-speed external clock (HSE) divided by 32. The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in all low-power modes except Shutdown mode. All RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt and wakeup the device from the low-power modes. 46/208 DS11453 Rev 3 STM32L431xx 3.24 Functional overview Inter-integrated circuit interface (I2C) The device embeds three I2C. Refer to Table 11: I2C implementation for the features implementation. The I2C bus interface handles communications between the microcontroller and the serial I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing. The I2C peripheral supports: • • I2C-bus specification and user manual rev. 5 compatibility: – Slave and master modes, multimaster capability – Standard-mode (Sm), with a bitrate up to 100 kbit/s – Fast-mode (Fm), with a bitrate up to 400 kbit/s – Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os – 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses – Programmable setup and hold times – Optional clock stretching System Management Bus (SMBus) specification rev 2.0 compatibility: – Hardware PEC (Packet Error Checking) generation and verification with ACK control – Address resolution protocol (ARP) support – SMBus alert • Power System Management Protocol (PMBusTM) specification rev 1.1 compatibility • Independent clock: a choice of independent clock sources allowing the I2C communication speed to be independent from the PCLK reprogramming. Refer to Figure 4: Clock tree. • Wakeup from Stop mode on address match • Programmable analog and digital noise filters • 1-byte buffer with DMA capability Table 11. I2C implementation I2C features(1) I2C1 I2C2 I2C3 Standard-mode (up to 100 kbit/s) X X X Fast-mode (up to 400 kbit/s) X X X Fast-mode Plus with 20mA output drive I/Os (up to 1 Mbit/s) X X X Programmable analog and digital noise filters X X X SMBus/PMBus hardware support X X X Independent clock X X X Wakeup from Stop 0 / Stop 1 mode on address match X X X Wakeup from Stop 2 mode on address match - - X 1. X: supported DS11453 Rev 3 47/208 54 Functional overview 3.25 STM32L431xx Universal synchronous/asynchronous receiver transmitter (USART) The STM32L431xx devices have three embedded universal synchronous receiver transmitters (USART1, USART2 and USART3). These interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. They provide hardware management of the CTS and RTS signals, and RS485 Driver Enable. They are able to communicate at speeds of up to 10Mbit/s. USART1, USART2 and USART3 also provide Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All USART have a clock domain independent from the CPU clock, allowing the USARTx (x=1,2,3) to wake up the MCU from Stop mode using baudrates up to 204 Kbaud. The wake up events from Stop mode are programmable and can be: • Start bit detection • Any received data frame • A specific programmed data frame All USART interfaces can be served by the DMA controller. Table 12. STM32L431xx USART/LPUART features USART modes/features(1) USART1 USART2 USART3 LPUART1 Hardware flow control for modem X X X X Continuous communication using DMA X X X X Multiprocessor communication X X X X Synchronous mode X X X - Smartcard mode X X X - Single-wire half-duplex communication X X X X IrDA SIR ENDEC block X X X - LIN mode X X X - Dual clock domain X X X X Wakeup from Stop 0 / Stop 1 modes X X X X Wakeup from Stop 2 mode - - - X Receiver timeout interrupt X X X - Modbus communication X X X - Auto baud rate detection X (4 modes) Driver Enable X LPUART/USART data length X 7, 8 and 9 bits 1. X = supported. 48/208 X - DS11453 Rev 3 X STM32L431xx 3.26 Functional overview Low-power universal asynchronous receiver transmitter (LPUART) The device embeds one Low-Power UART. The LPUART supports asynchronous serial communication with minimum power consumption. It supports half duplex single wire communication and modem operations (CTS/RTS). It allows multiprocessor communication. The LPUART has a clock domain independent from the CPU clock, and can wakeup the system from Stop mode using baudrates up to 220 Kbaud. The wake up events from Stop mode are programmable and can be: • Start bit detection • Any received data frame • A specific programmed data frame Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while having an extremely low energy consumption. Higher speed clock can be used to reach higher baudrates. LPUART interface can be served by the DMA controller. DS11453 Rev 3 49/208 54 Functional overview 3.27 STM32L431xx Serial peripheral interface (SPI) Three SPI interfaces allow communication up to 40 Mbits/s in master and up to 24 Mbits/s slave modes, in half-duplex, full-duplex and simplex modes. The 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits. The SPI interfaces support NSS pulse mode, TI mode and Hardware CRC calculation. All SPI interfaces can be served by the DMA controller. 3.28 Serial audio interfaces (SAI) The device embeds 1 SAI. Refer to Table 13: SAI implementation for the features implementation. The SAI bus interface handles communications between the microcontroller and the serial audio protocol. The SAI peripheral supports: • Two independent audio sub-blocks which can be transmitters or receivers with their respective FIFO. • 8-word integrated FIFOs for each audio sub-block. • Synchronous or asynchronous mode between the audio sub-blocks. • Master or slave configuration independent for both audio sub-blocks. • Clock generator for each audio block to target independent audio frequency sampling when both audio sub-blocks are configured in master mode. • Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit. • Peripheral with large configurability and flexibility allowing to target as example the following audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF out. • Up to 16 slots available with configurable size and with the possibility to select which ones are active in the audio frame. • Number of bits by frame may be configurable. • Frame synchronization active level configurable (offset, bit length, level). • First active bit position in the slot is configurable. • LSB first or MSB first for data transfer. • Mute mode. • Stereo/Mono audio frame capability. • Communication clock strobing edge configurable (SCK). • Error flags with associated interrupts if enabled respectively. • • 50/208 – Overrun and underrun detection. – Anticipated frame synchronization signal detection in slave mode. – Late frame synchronization signal detection in slave mode. – Codec not ready for the AC’97 mode in reception. Interruption sources when enabled: – Errors. – FIFO requests. DMA interface with 2 dedicated channels to handle access to the dedicated integrated FIFO of each SAI audio sub-block. DS11453 Rev 3 STM32L431xx Functional overview Table 13. SAI implementation SAI features Support(1) I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 X Mute mode X Stereo/Mono audio frame capability. X 16 slots X Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit X FIFO Size X (8 Word) SPDIF X 1. X: supported 3.29 Single wire protocol master interface (SWPMI) The Single wire protocol master interface (SWPMI) is the master interface corresponding to the Contactless Frontend (CLF) defined in the ETSI TS 102 613 technical specification. The main features are: • full-duplex communication mode • automatic SWP bus state management (active, suspend, resume) • configurable bitrate up to 2 Mbit/s • automatic SOF, EOF and CRC handling SWPMI can be served by the DMA controller. 3.30 Controller area network (CAN) The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and 14 scalable filter banks. DS11453 Rev 3 51/208 54 Functional overview STM32L431xx The CAN peripheral supports: • Supports CAN protocol version 2.0 A, B Active • Bit rates up to 1 Mbit/s • Transmission • • • 3.31 – Three transmit mailboxes – Configurable transmit priority Reception – Two receive FIFOs with three stages – 14 Scalable filter banks – Identifier list feature – Configurable FIFO overrun Time-triggered communication option – Disable automatic retransmission mode – 16-bit free running timer – Time Stamp sent in last two data bytes Management – Maskable interrupts – Software-efficient mailbox mapping at a unique address space Secure digital input/output and MultiMediaCards Interface (SDMMC) The card host interface (SDMMC) provides an interface between the APB peripheral bus and MultiMediaCards (MMCs), SD memory cards and SDIO cards. The SDMMC features include the following: 3.32 • Full compliance with MultiMediaCard System Specification Version 4.2. Card support for three different databus modes: 1-bit (default), 4-bit and 8-bit • Full compatibility with previous versions of MultiMediaCards (forward compatibility) • Full compliance with SD Memory Card Specifications Version 2.0 • Full compliance with SD I/O Card Specification Version 2.0: card support for two different databus modes: 1-bit (default) and 4-bit • Data transfer up to 48 MHz for the 8 bit mode • Data write and read with DMA capability Clock recovery system (CRS) The STM32L431xx devices embed a special block which allows automatic trimming of the internal 48 MHz oscillator to guarantee its optimal accuracy over the whole device operational range. This automatic trimming is based on the external synchronization signal, which could be either derived from LSE oscillator, from an external signal on CRS_SYNC pin or generated by user software. For faster lock-in during startup it is also possible to combine automatic trimming with manual trimming action. 52/208 DS11453 Rev 3 STM32L431xx 3.33 Functional overview Quad SPI memory interface (QUADSPI) The Quad SPI is a specialized communication interface targeting single, dual or quad SPI flash memories. It can operate in any of the three following modes: • Indirect mode: all the operations are performed using the QUADSPI registers • Status polling mode: the external flash status register is periodically read and an interrupt can be generated in case of flag setting • Memory-mapped mode: the external Flash is memory mapped and is seen by the system as if it were an internal memory Both throughput and capacity can be increased two-fold using dual-flash mode, where two Quad SPI flash memories are accessed simultaneously. The Quad SPI interface supports: • Three functional modes: indirect, status-polling, and memory-mapped • Dual-flash mode, where 8 bits can be sent/received simultaneously by accessing two flash memories in parallel. • SDR and DDR support • Fully programmable opcode for both indirect and memory mapped mode • Fully programmable frame format for both indirect and memory mapped mode • Each of the 5 following phases can be configured independently (enable, length, single/dual/quad communication) – Instruction phase – Address phase – Alternate bytes phase – Dummy cycles phase – Data phase • Integrated FIFO for reception and transmission • 8, 16, and 32-bit data accesses are allowed • DMA channel for indirect mode operations • Programmable masking for external flash flag management • Timeout management • Interrupt generation on FIFO threshold, timeout, status match, operation complete, and access error DS11453 Rev 3 53/208 54 Functional overview STM32L431xx 3.34 Development support 3.34.1 Serial wire JTAG debug port (SWJ-DP) The Arm® SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 3.34.2 Embedded Trace Macrocell™ The Arm® Embedded Trace Macrocell™ provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32L431xx through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. Real-time instruction and data flow activity be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors. The Embedded Trace Macrocell™ operates with third party debugger software tools. 54/208 DS11453 Rev 3 STM32L431xx Pinouts and pin description VDD VSS PE1 PE0 PB9 PB8 PH3/BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 Figure 6. STM32L431Vx LQFP100 pinout(1) PE2 1 75 VDD PE3 2 74 VSS PE4 3 73 VDD PE5 4 72 PA13 PE6 5 71 PA12 VBAT 6 70 PA11 PC13 7 69 PA10 PC14-OSC32_IN 8 68 PA9 PC15-OSC32_OUT 9 67 PA8 VSS 10 66 PC9 VDD 11 65 PC8 PH0-OSC_IN 12 64 PC7 PH1-OSC_OUT 13 63 PC6 NRST 14 62 PD15 PC0 15 61 PD14 PC1 16 60 PD13 PC2 17 59 PD12 PC3 18 58 PD11 VSSA 19 57 PD10 VREF- 20 56 PD9 VREF+ 21 55 PD8 VDDA 22 54 PB15 PA0 23 53 PB14 PA1 24 52 PB13 PA2 25 51 PB12 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PA3 VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS VDD LQFP100 VSS 4 Pinouts and pin description MSv39214V2 1. The above figure shows the package top view. DS11453 Rev 3 55/208 83 Pinouts and pin description STM32L431xx Figure 7. STM32L431Vx UFBGA100 ballout(1) 1 2 3 4 5 6 7 8 9 10 11 12 A PE3 PE1 PB8 PH3/BOOT0 PD7 PD5 PB4 PB3 PA15 PA14 PA13 PA12 B PE4 PE2 PB9 PB7 PB6 PD6 PD4 PD3 PD1 PC12 PC10 PA11 C PC13 PE5 PE0 VDD PB5 PD2 PD0 PC11 VDD PA10 D PC14OSC32_IN PE6 VSS PA9 PA8 PC9 E PC15OSC32_OUT VBAT VSS PC8 PC7 PC6 F PH0-OSC_IN VSS VSS VSS VDD VDD UFBGA100 G PH1OSC_OUT VDD H PC0 NRST VDD PD15 PD14 PD13 J VSSA PC1 PC2 PD12 PD11 PD10 K VREF- PC3 PA2 PA5 PC4 L VREF+ PA0 PA3 PA6 PC5 PB2 M VDDA PA1 PA4 PA7 PB0 PB1 PD9 PD8 PB15 PB14 PB13 PE8 PE10 PE12 PB10 PB11 PB12 PE7 PE9 PE11 PE13 PE14 PE15 MSv39213V2 1. The above figure shows the package top view. VDD VSS PB9 PB8 PH3/BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Figure 8. STM32L431Rx LQFP64 pinout(1) VBAT 1 48 VDD PC13 2 47 VSS PC14-OSC32_IN 3 46 PA13 PC15-OSC32_OUT 4 45 PA12 PH0-OSC_IN 5 44 PA11 PH1-OSC_OUT 6 43 PA10 NRST 7 42 PA9 PC0 8 41 PA8 PC1 9 40 PC9 PC2 10 39 PC8 PC3 11 38 PC7 VSSA/VREF- 12 37 PC6 VDDA/VREF+ 13 36 PB15 PA0 14 35 PB14 PA1 15 34 PB13 PA2 16 33 PB12 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VSS VDD LQFP64 MSv39212V2 1. The above figure shows the package top view. 56/208 DS11453 Rev 3 STM32L431xx Pinouts and pin description Figure 9. STM32L431Rx UFBGA64 ballout(1) 1 2 3 4 5 6 7 8 A PC14OSC32_IN PC13 PB9 PB4 PB3 PA15 PA14 PA13 B PC15OSC32_OUT VBAT PB8 PH3/BOOT0 PD2 PC11 PC10 PA12 C PH0-OSC_IN VSS PB7 PB5 PC12 PA10 PA9 PA11 D PH1OSC_OUT VDD PB6 VSS VSS VSS PA8 PC9 E NRST PC1 PC0 VDD VDD VDD PC7 PC8 F VSSA/VREF- PC2 PA2 PA5 PB0 PC6 PB15 PB14 G PC3 PA0 PA3 PA6 PB1 PB2 PB10 PB13 H VDDA/VREF+ PA1 PA4 PA7 PC4 PC5 PB11 PB12 MSv39211V2 1. The above figure shows the package top view. Figure 10. STM32L431Rx WLCSP64 pinout(1) 1 2 3 4 5 6 7 8 A VDD PA15 PC12 PD2 PB3 PB7 VSS VDD B VSS PA14 PC11 PB4 PB6 PB9 VBAT PC13 C PA12 PA13 PC10 PB5 PH3/BOOT0 PB8 PC15OSC32_OUT PC14OSC32_IN D PA9 PA10 PA11 PC4 PC0 NRST PH1OSC_OUT PH0-OSC_IN E PC7 PC9 PA8 PC5 PA4 PC3 PC2 PC1 F PC6 PB15 PC8 PB0 PA5 PA2 PA0 VSSA/VREF- G PB14 PB13 PB12 PB2 PA6 PA3 PA1 VDDA/VREF+ H VDD VSS PB11 PB10 PB1 PA7 VDD VSS MSv39210V2 1. The above figure shows the package top view. Figure 11. STM32L431Cx WLCSP49 pinout(1) 1 2 3 4 5 6 7 A VDD PA14 PB3 PB4 PH3/BOOT0 VSS VDD B VSS PA13 PA15 PB5 PB8 VBAT PC13 C PA11 PA10 PA12 PB6 PB9 PC15OSC32_OUT PC14OSC32_IN D PA8 PA9 PB15 PB7 NRST PH1OSC_OUT PH0-OSC_IN E PB14 PB13 PB10 PA3 PA2 PC3 VSSA/VREF- F PB12 PB11 PA7 PA6 PA5 PA0 VDDA/VREF+ G VDD VSS PB2 PB1 PB0 PA4 PA1 MSv39209V2 1. The above figure shows the package top view. DS11453 Rev 3 57/208 83 Pinouts and pin description STM32L431xx VDD VSS PB9 PB8 PH3/BOOT0 PB7 PB6 PB5 PB4 PB3 PA15 PA14 48 47 46 45 44 43 42 41 40 39 38 37 Figure 12. STM32L431Cx LQFP48 pinout(1) VBAT 1 36 VDD PC13 2 35 VSS PC14-OSC32_IN 3 34 PA13 PC15-OSC32_OUT 4 33 PA12 PH0-OSC_IN 5 32 PA11 PH1-OSC_OUT 6 31 PA10 NRST 7 30 PA9 VSSA/VREF- 8 29 PA8 VDDA/VREF+ 9 28 PB15 PA0 10 27 PB14 PA1 11 26 PB13 PA2 12 25 PB12 13 14 15 16 17 18 19 20 21 22 23 24 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB10 PB11 VSS VDD LQFP48 MSv39208V2 1. The above figure shows the package top view. VDD VSS PB9 PB8 PH3/BOOT0 PB7 PB6 PB5 PB4 PB3 PA15 PA14 48 47 46 45 44 43 42 41 40 39 38 37 Figure 13. STM32L431Cx UFQFPN48 pinout(1) VBAT 1 36 VDD PC13 2 35 VSS PC14-OSC32_IN 3 34 PA13 PC15-OSC32_OUT 4 33 PA12 PH0-OSC_IN 5 32 PA11 PH1-OSC_OUT 6 31 PA10 NRST 7 30 PA9 VSSA/VREF- 8 29 PA8 VDDA/VREF+ 9 28 PB15 PA0 10 27 PB14 PA1 11 26 PB13 PA2 12 25 PB12 13 14 15 16 17 18 19 20 21 22 23 24 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB10 PB11 VSS VDD UFQFPN48 MSv39207V2 1. The above figure shows the package top view. 58/208 DS11453 Rev 3 STM32L431xx Pinouts and pin description VSS PH3/BOOT0 PB7 PB6 PB5 PB4 PB3 PA15 32 31 30 29 28 27 26 25 Figure 14. STM32L431Kx UFQFPN32 pinout(1) VDD 1 24 PA14 PC14-OSC32_IN 2 23 PA13 PC15-OSC32_OUT 3 22 PA12 NRST 4 21 PA11 VDDA/VREF+ 5 20 PA10 PA0/CK_IN 6 19 PA9 PA1 7 18 PA8 PA2 8 17 VDD 9 10 11 12 13 14 15 16 PA3 PA4 PA5 PA6 PA7 PB0 PB1 VSS UFQFPN32 MSv37605V2 1. The above figure shows the package top view. Table 14. Legend/abbreviations used in the pinout table Name Pin name Pin type Abbreviation Definition Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name S Supply pin I Input only pin I/O Input / output pin FT 5 V tolerant I/O TT 3.6 V tolerant I/O RST Bidirectional reset pin with embedded weak pull-up resistor I/O structure Notes Option for TT or FT I/Os _f (1) I/O, Fm+ capable _a (2) I/O, with Analog switch function supplied by VDDA Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset. Alternate Functions selected through GPIOx_AFR registers functions Pin functions Additional Functions directly selected/enabled through peripheral registers functions 1. The related I/O structures in Table 15 are: FT_f, FT_fa. 2. The related I/O structures in Table 15 are: FT_a, FT_fa, TT_a. DS11453 Rev 3 59/208 83 Pinouts and pin description STM32L431xx Table 15. STM32L431xx pin definitions Notes Pin functions I/O structure Pin name (function after reset) Pin type UFBGA100 LQFP100 UFBGA64 LQFP64 WLCSP64 WLCSP49 UFQFPN48 LQFP48 UFQFPN32 Pin Number Alternate functions Additional functions - - - - - - - - 1 B2 PE2 I/O FT - TRACECK, TSC_G7_IO1, SAI1_MCLK_A, EVENTOUT - - - - - - - 2 A1 PE3 I/O FT - TRACED0, TSC_G7_IO2, SAI1_SD_B, EVENTOUT - - - - - - - - 3 B1 PE4 I/O FT - TRACED1, TSC_G7_IO3, SAI1_FS_A, EVENTOUT - - - - - - - - - 4 C2 PE5 I/O FT - TRACED2, TSC_G7_IO4, SAI1_SCK_A, EVENTOUT - - - - - - - 5 D2 PE6 I/O FT - TRACED3, SAI1_SD_A, EVENTOUT RTC_TAMP3, WKUP3 - 1 1 1 B2 6 E2 VBAT S - - - - EVENTOUT RTC_TAMP1, RTC_TS, RTC_OUT, WKUP2 EVENTOUT OSC32_IN (2) EVENTOUT OSC32_OUT B6 B7 - 2 2 B7 B8 2 A2 7 C1 PC13 I/O FT 2 3 3 C7 C8 3 A1 8 D1 PC14OSC32_I N (PC14) I/O FT I/O FT 3 4 4 - - - - - - - - - 5 5 (2) (1) (2) 4 B1 9 E1 PC15OSC32_ OUT (PC15) - - - 10 F2 VSS S - - - - - - - 11 G2 VDD S - - - - 5 C1 12 F1 PH0OSC_ IN (PH0) I/O FT - EVENTOUT OSC_IN I/O FT - EVENTOUT OSC_OUT I/O RST - - - C6 C7 D7 D8 - 6 6 D6 D7 6 D1 13 G1 PH1OSC_ OUT (PH1) 4 7 7 D5 D6 7 E1 14 H2 NRST 60/208 (1) DS11453 Rev 3 (1) STM32L431xx Pinouts and pin description Table 15. STM32L431xx pin definitions (continued) - - - - D5 8 E3 15 H1 PC0 Pin functions I/O FT_fa Alternate functions Additional functions - LPTIM1_IN1, I2C3_SCL, LPUART1_RX, LPTIM2_IN1, EVENTOUT ADC1_IN1 ADC1_IN2 Notes I/O structure Pin name (function after reset) Pin type UFBGA100 LQFP100 UFBGA64 LQFP64 WLCSP64 WLCSP49 UFQFPN48 LQFP48 UFQFPN32 Pin Number - - - - E8 E2 16 J2 PC1 I/O FT_fa - LPTIM1_OUT, I2C3_SDA, LPUART1_TX, EVENTOUT - - - - E7 10 F2 17 J3 PC2 I/O FT_a - LPTIM1_IN2, SPI2_MISO, EVENTOUT ADC1_IN3 ADC1_IN4 9 - - - - - - - - - - - - - - - - 8 8 - - - - - - - - - - - - 5 9 9 - 6 7 18 K2 PC3 I/O FT_a - LPTIM1_ETR, SPI2_MOSI, SAI1_SD_A, LPTIM2_ETR, EVENTOUT - 19 J1 VSSA S - - - - - 20 K1 VREF- S - - - - - - VSSA/ VREF- S - - - - - 21 L1 VREF+ S - - - VREFBUF_ OUT - 22 M1 VDDA S - - - - - - VDDA/ VREF+ S - - - - - TIM2_CH1, USART2_CTS, COMP1_OUT, SAI1_EXTCLK, TIM2_ETR, EVENTOUT OPAMP1_ VINP, COMP1_INM, ADC1_IN5, RTC_TAMP2, WKUP1 - TIM2_CH1, USART2_CTS, COMP1_OUT, SAI1_EXTCLK, TIM2_ETR, EVENTOUT OPAMP1_ VINP, COMP1_INM, ADC1_IN5, RTC_TAMP2, WKUP1, CK_IN - TIM2_CH2, I2C1_SMBA, SPI1_SCK, USART2_RTS_DE, TIM15_CH1N, EVENTOUT OPAMP1_ VINM, COMP1_INP, ADC1_IN6 E6 E6 11 G1 E7 F8 12 F1 F7 G8 13 H1 10 10 F6 F7 14 G2 - - - - - - 11 11 G7 G7 15 H2 23 - 24 L2 - M2 PA0 PA0/ CK_IN PA1 I/O I/O I/O FT_a FT_a FT_a DS11453 Rev 3 61/208 83 Pinouts and pin description STM32L431xx Table 15. STM32L431xx pin definitions (continued) 8 12 12 E5 F6 16 F3 25 K3 PA2 I/O FT_a Notes Pin functions I/O structure Pin name (function after reset) Pin type UFBGA100 LQFP100 UFBGA64 LQFP64 WLCSP64 WLCSP49 UFQFPN48 LQFP48 UFQFPN32 Pin Number Alternate functions Additional functions - TIM2_CH3, USART2_TX, COMP2_INM, LPUART1_TX, ADC1_IN7, QUADSPI_BK1_NCS, WKUP4, COMP2_OUT, LSCO TIM15_CH1, EVENTOUT OPAMP1_ VOUT, COMP2_INP, ADC1_IN8 9 13 13 E4 G6 17 G3 26 L3 PA3 I/O TT_a - TIM2_CH4, USART2_RX, LPUART1_RX, QUADSPI_CLK, SAI1_MCLK_A, TIM15_CH2, EVENTOUT - - - - H8 18 C2 27 E3 VSS S - - - - - - - - H7 19 D2 28 H3 VDD S - - - - - SPI1_NSS, SPI3_NSS, USART2_CK, SAI1_FS_B, LPTIM2_OUT, EVENTOUT COMP1_INM, COMP2_INM, ADC1_IN9, DAC1_OUT1 - TIM2_CH1, TIM2_ETR, SPI1_SCK, LPTIM2_ETR, EVENTOUT COMP1_INM, COMP2_INM, ADC1_IN10, DAC1_OUT2 - TIM1_BKIN, SPI1_MISO, COMP1_OUT, USART3_CTS, LPUART1_CTS, QUADSPI_BK1_IO3, TIM1_BKIN_COMP2, TIM16_CH1, EVENTOUT ADC1_IN11 ADC1_IN12 10 14 14 G6 E5 20 H3 11 15 15 F5 F5 21 F4 12 16 16 F4 G5 22 G4 13 17 17 F3 H6 23 H4 29 30 31 M3 K4 L4 PA4 PA5 PA6 I/O I/O I/O TT_a TT_a FT_a 32 M4 PA7 I/O FT_fa - TIM1_CH1N, I2C3_SCL, SPI1_MOSI, QUADSPI_BK1_IO2, COMP2_OUT, EVENTOUT - - - - D4 24 H5 33 K5 PC4 I/O FT_a - USART3_TX, EVENTOUT COMP1_INM, ADC1_IN13 - - - - E4 25 H6 34 L5 PC5 I/O FT_a - USART3_RX, EVENTOUT COMP1_INP, ADC1_IN14, WKUP5 62/208 DS11453 Rev 3 STM32L431xx Pinouts and pin description Table 15. STM32L431xx pin definitions (continued) 14 18 18 G5 F4 26 F5 15 19 19 G4 H5 27 G5 - 20 20 G3 G4 28 G6 35 M5 PB0 Pin functions I/O FT_a Alternate functions Additional functions - TIM1_CH2N, SPI1_NSS, USART3_CK, QUADSPI_BK1_IO1, COMP1_OUT, SAI1_EXTCLK, EVENTOUT ADC1_IN15 COMP1_INM, ADC1_IN16 Notes I/O structure Pin name (function after reset) Pin type UFBGA100 LQFP100 UFBGA64 LQFP64 WLCSP64 WLCSP49 UFQFPN48 LQFP48 UFQFPN32 Pin Number 36 M6 PB1 I/O FT_a - TIM1_CH3N, USART3_RTS_DE, LPUART1_RTS_DE, QUADSPI_BK1_IO0, LPTIM2_IN1, EVENTOUT 37 L6 PB2 I/O FT_a - RTC_OUT, LPTIM1_OUT, I2C3_SMBA, EVENTOUT COMP1_INP - - - - - - - 38 M7 PE7 I/O FT - TIM1_ETR, SAI1_SD_B, EVENTOUT - - - - - - - - 39 L7 PE8 I/O FT - TIM1_CH1N, SAI1_SCK_B, EVENTOUT - - - - - - - - 40 M8 PE9 I/O FT - TIM1_CH1, SAI1_FS_B, EVENTOUT - - TIM1_CH2N, TSC_G5_IO1, QUADSPI_CLK, SAI1_MCLK_B, EVENTOUT - - TIM1_CH2, TSC_G5_IO2, QUADSPI_BK1_NCS, EVENTOUT - - TIM1_CH3N, SPI1_NSS, TSC_G5_IO3, QUADSPI_BK1_IO0, EVENTOUT - - TIM1_CH3, SPI1_SCK, TSC_G5_IO4, QUADSPI_BK1_IO1, EVENTOUT - - TIM1_CH4, TIM1_BKIN2, TIM1_BKIN2_COMP2, SPI1_MISO, QUADSPI_BK1_IO2, EVENTOUT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 41 42 43 L8 M9 L9 44 M10 45 M11 PE10 PE11 PE12 PE13 PE14 I/O I/O I/O I/O I/O FT FT FT FT FT DS11453 Rev 3 63/208 83 Pinouts and pin description STM32L431xx Table 15. STM32L431xx pin definitions (continued) - - - - - - - - 21 21 E3 H4 29 G7 46 M12 47 L10 PE15 PB10 Pin functions I/O I/O FT FT_f Alternate functions Additional functions - TIM1_BKIN, TIM1_BKIN_COMP1, SPI1_MOSI, QUADSPI_BK1_IO3, EVENTOUT - - TIM2_CH3, I2C2_SCL, SPI2_SCK, USART3_TX, LPUART1_RX, TSC_SYNC, QUADSPI_CLK, COMP1_OUT, SAI1_SCK_A, EVENTOUT - - Notes I/O structure Pin name (function after reset) Pin type UFBGA100 LQFP100 UFBGA64 LQFP64 WLCSP64 WLCSP49 UFQFPN48 LQFP48 UFQFPN32 Pin Number 22 22 F2 H3 30 H7 48 L11 PB11 I/O FT_f - TIM2_CH4, I2C2_SDA, USART3_RX, LPUART1_TX, QUADSPI_BK1_NCS, COMP2_OUT, EVENTOUT 16 23 23 G2 H2 31 D6 49 F12 VSS S - - - - 17 24 24 G1 H1 32 E6 50 G12 VDD S - - - - - TIM1_BKIN, TIM1_BKIN_COMP2, I2C2_SMBA, SPI2_NSS, USART3_CK, LPUART1_RTS_DE, TSC_G1_IO1, SWPMI1_IO, SAI1_FS_A, TIM15_BKIN, EVENTOUT - - TIM1_CH1N, I2C2_SCL, SPI2_SCK, USART3_CTS, LPUART1_CTS, TSC_G1_IO2, SWPMI1_TX, SAI1_SCK_A, TIM15_CH1N, EVENTOUT - - - - 25 25 F1 G3 33 H8 26 26 E2 G2 34 G8 64/208 51 52 L12 K12 PB12 PB13 I/O I/O FT FT_f DS11453 Rev 3 STM32L431xx Pinouts and pin description Table 15. STM32L431xx pin definitions (continued) - - 27 27 E1 G1 35 F8 28 28 D3 F2 36 F7 53 K11 PB14 Pin functions I/O FT_f Alternate functions Additional functions - TIM1_CH2N, I2C2_SDA, SPI2_MISO, USART3_RTS_DE, TSC_G1_IO3, SWPMI1_RX, SAI1_MCLK_A, TIM15_CH1, EVENTOUT - - Notes I/O structure Pin name (function after reset) Pin type UFBGA100 LQFP100 UFBGA64 LQFP64 WLCSP64 WLCSP49 UFQFPN48 LQFP48 UFQFPN32 Pin Number 54 K10 PB15 I/O FT - RTC_REFIN, TIM1_CH3N, SPI2_MOSI, TSC_G1_IO4, SWPMI1_SUSPEND, SAI1_SD_A, TIM15_CH2, EVENTOUT - - - - - - - 55 K9 PD8 I/O FT - USART3_TX, EVENTOUT - - - - - - - - 56 K8 PD9 I/O FT - USART3_RX, EVENTOUT - - - - - - - - 57 J12 PD10 I/O FT - USART3_CK, TSC_G6_IO1, EVENTOUT - - USART3_CTS, TSC_G6_IO2, LPTIM2_ETR, EVENTOUT - - - - - - - - - 58 J11 PD11 I/O FT - - - - - - - 59 J10 PD12 I/O FT - USART3_RTS_DE, TSC_G6_IO3, LPTIM2_IN1, EVENTOUT - - - - - - - 60 H12 PD13 I/O FT - TSC_G6_IO4, LPTIM2_OUT, EVENTOUT - - - - - - - - 61 H11 PD14 I/O FT - EVENTOUT - - - - - - - - 62 H10 PD15 I/O FT - EVENTOUT - - - - - F1 37 F6 63 E12 PC6 I/O FT - TSC_G4_IO1, SDMMC1_D6, EVENTOUT - - - - - E1 38 E7 64 E11 PC7 I/O FT - TSC_G4_IO2, SDMMC1_D7, EVENTOUT - DS11453 Rev 3 65/208 83 Pinouts and pin description STM32L431xx Table 15. STM32L431xx pin definitions (continued) UFBGA64 LQFP100 UFBGA100 Pin type I/O structure Notes - - - F3 39 E8 65 E10 PC8 I/O FT - TSC_G4_IO3, SDMMC1_D0, EVENTOUT - - - - - E2 40 D8 66 D12 PC9 I/O FT - TSC_G4_IO4, SDMMC1_D1, EVENTOUT - - MCO, TIM1_CH1, USART1_CK, SWPMI1_IO, SAI1_SCK_A, LPTIM2_OUT, EVENTOUT - - LQFP64 WLCSP49 - WLCSP64 UFQFPN48 Pin functions LQFP48 Pin name (function after reset) UFQFPN32 Pin Number 18 29 29 D1 E3 41 D7 67 D11 PA8 I/O FT Alternate functions Additional functions 19 30 30 D2 D1 42 C7 68 D10 PA9 I/O FT_f - TIM1_CH2, I2C1_SCL, USART1_TX, SAI1_FS_A, TIM15_BKIN, EVENTOUT 20 31 31 C2 D2 43 C6 69 C12 PA10 I/O FT_f - TIM1_CH3, I2C1_SDA, USART1_RX, SAI1_SD_A, EVENTOUT - - 21 32 32 C1 D3 44 C8 70 B12 PA11 I/O FT - TIM1_CH4, TIM1_BKIN2, SPI1_MISO, COMP1_OUT, USART1_CTS, CAN1_RX, TIM1_BKIN2_COMP1, EVENTOUT 22 33 33 C3 C1 45 B8 71 A12 PA12 I/O FT - TIM1_ETR, SPI1_MOSI, USART1_RTS_DE, CAN1_TX, EVENTOUT - 23 34 34 B2 C2 46 A8 72 A11 PA13 (JTMSSWDIO) I/O FT (3) JTMS-SWDIO, IR_OUT, SWPMI1_TX, SAI1_SD_B, EVENTOUT - - 35 35 B1 B1 47 D5 - - VSS S - - - - - 36 36 A1 A1 48 E5 73 C11 VDD S - - - - - - - - - - - 74 F11 VSS S - - - - - - - - - - - 75 G11 VDD S - - - - A10 PA14 (JTCKSWCLK) 24 37 37 A2 B2 49 A7 66/208 76 I/O FT DS11453 Rev 3 JTCK-SWCLK, LPTIM1_OUT, (3) I2C1_SMBA, SWPMI1_RX, SAI1_FS_B, EVENTOUT - STM32L431xx Pinouts and pin description Table 15. STM32L431xx pin definitions (continued) 25 38 38 B3 A2 50 A6 - - - - - - - - C3 51 B7 B3 52 B6 - - - - - - - - - - - - - - - - - - - - - - - - 78 79 B11 C10 PA15 (JTDI) PC10 PC11 I/O I/O I/O Notes I/O structure Pin type UFBGA100 A9 Pin functions Alternate functions Additional functions FT JTDI, TIM2_CH1, TIM2_ETR, USART2_RX, SPI1_NSS, SPI3_NSS, (3) USART3_RTS_DE, TSC_G3_IO1, SWPMI1_SUSPEND, EVENTOUT - FT - SPI3_SCK, USART3_TX, TSC_G3_IO2, SDMMC1_D2, EVENTOUT - - SPI3_MISO, USART3_RX, TSC_G3_IO3, SDMMC1_D3, EVENTOUT - - FT 80 B10 PC12 I/O FT - - 81 C9 PD0 I/O FT - SPI2_NSS, CAN1_RX, EVENTOUT - - 82 B9 PD1 I/O FT - SPI2_SCK, CAN1_TX, EVENTOUT - - USART3_RTS_DE, TSC_SYNC, SDMMC1_CMD, EVENTOUT - - SPI2_MISO, USART2_CTS, QUADSPI_BK2_NCS, EVENTOUT - - A4 54 B5 - 77 Pin name (function after reset) SPI3_MOSI, USART3_CK, TSC_G3_IO4, SDMMC1_CK, EVENTOUT A3 53 C5 - LQFP100 UFBGA64 LQFP64 WLCSP64 WLCSP49 UFQFPN48 LQFP48 UFQFPN32 Pin Number - 83 84 C8 B8 PD2 PD3 I/O I/O FT FT - - - - - - - 85 B7 PD4 I/O FT - SPI2_MOSI, USART2_RTS_DE, QUADSPI_BK2_IO0, EVENTOUT - - - - - - - 86 A6 PD5 I/O FT - USART2_TX, QUADSPI_BK2_IO1, EVENTOUT - - - - - - - - 87 B6 PD6 I/O FT - USART2_RX, QUADSPI_BK2_IO2, SAI1_SD_A, EVENTOUT - DS11453 Rev 3 67/208 83 Pinouts and pin description STM32L431xx Table 15. STM32L431xx pin definitions (continued) WLCSP49 WLCSP64 LQFP64 UFBGA64 LQFP100 UFBGA100 - - - - - 88 A5 26 39 39 A3 A5 55 A5 27 40 40 A4 B4 56 A4 28 41 41 B4 C4 57 C4 29 42 42 C4 B5 58 D3 89 90 91 92 PD7 A8 PB3 (JTDOTRACE SWO) A7 C5 B5 PB4 (NJTRST) PB5 PB6 Notes UFQFPN48 - Pin functions I/O structure LQFP48 - Pin name (function after reset) Pin type UFQFPN32 Pin Number I/O FT - Alternate functions Additional functions USART2_CK, QUADSPI_BK2_IO3, EVENTOUT - JTDO-TRACESWO, TIM2_CH2, SPI1_SCK, SPI3_SCK, USART1_RTS_DE, SAI1_SCK_B, EVENTOUT COMP2_INM I/O FT_a (3) I/O NJTRST, I2C3_SDA, SPI1_MISO, SPI3_MISO, USART1_CTS, FT_fa (3) TSC_G2_IO1, SAI1_MCLK_B, EVENTOUT I/O - LPTIM1_IN1, I2C1_SMBA, SPI1_MOSI, SPI3_MOSI, USART1_CK, TSC_G2_IO2, COMP2_OUT, SAI1_SD_B, TIM16_BKIN, EVENTOUT - - LPTIM1_ETR, I2C1_SCL, USART1_TX, TSC_G2_IO3, SAI1_FS_B, TIM16_CH1N, EVENTOUT COMP2_INP COMP2_INM, PVD_IN I/O FT FT_fa COMP2_INP 30 43 43 D4 A6 59 C3 93 B4 PB7 I/O FT_fa - LPTIM1_IN2, I2C1_SDA, USART1_RX, TSC_G2_IO4, EVENTOUT 31 44 44 A5 C5 60 B4 94 A4 PH3/ BOOT0 I/O FT - EVENTOUT BOOT0 - I2C1_SCL, CAN1_RX, SDMMC1_D4, SAI1_MCLK_A, TIM16_CH1, EVENTOUT - - IR_OUT, I2C1_SDA, SPI2_NSS, CAN1_TX, SDMMC1_D5, SAI1_FS_A, EVENTOUT - - - 45 45 B5 C6 61 B3 46 46 C5 B6 62 A3 68/208 95 96 A3 B3 PB8 PB9 I/O I/O FT_f FT_f DS11453 Rev 3 STM32L431xx Pinouts and pin description Table 15. STM32L431xx pin definitions (continued) UFQFPN48 WLCSP49 WLCSP64 LQFP64 UFBGA64 LQFP100 UFBGA100 Pin type I/O structure Notes Pin functions LQFP48 Pin name (function after reset) UFQFPN32 Pin Number Alternate functions - - - - - - - 97 C3 PE0 I/O FT - TIM16_CH1, EVENTOUT - - - - - - - - 98 A2 PE1 I/O FT - EVENTOUT - 99 D3 VSS S - - - - 1 48 48 A7 A8 64 E4 100 C4 VDD S - - - - 32 47 47 A6 A7 63 D4 Additional functions 1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: - The speed should not exceed 2 MHz with a maximum load of 30 pF - These GPIOs must not be used as current sources (e.g. to drive an LED). 2. After a Backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers which are not reset by the system reset. For details on how to manage these GPIOs, refer to the Backup domain and RTC register descriptions in the RM0394 reference manual. 3. After reset, these pins are configured as JTAG/SW debug alternate functions, and the internal pull-up on PA15, PA13, PB4 pins and the internal pull-down on PA14 pin are activated. DS11453 Rev 3 69/208 83 AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 SYS_AF TIM1/TIM2/ LPTIM1 TIM1/TIM2 USART2 I2C1/I2C2/I2C3 SPI1/SPI2 SPI3 USART1/ USART2/ USART3 PA0 - TIM2_CH1 - - - - - USART2_CTS PA1 - TIM2_CH2 - - I2C1_SMBA SPI1_SCK - USART2_RTS_ DE PA2 - TIM2_CH3 - - - - - USART2_TX PA3 - TIM2_CH4 - - - - - USART2_RX PA4 - - - - - SPI1_NSS SPI3_NSS USART2_CK PA5 - TIM2_CH1 TIM2_ETR - - SPI1_SCK - - PA6 - TIM1_BKIN - - - SPI1_MISO COMP1_OUT USART3_CTS PA7 - TIM1_CH1N - - I2C3_SCL SPI1_MOSI - - PA8 MCO TIM1_CH1 - - - - - USART1_CK PA9 - TIM1_CH2 - - I2C1_SCL - - USART1_TX PA10 - TIM1_CH3 - - I2C1_SDA - - USART1_RX PA11 - TIM1_CH4 TIM1_BKIN2 - - SPI1_MISO COMP1_OUT USART1_CTS PA12 - TIM1_ETR - - - SPI1_MOSI - USART1_RTS_ DE PA13 JTMS-SWDIO IR_OUT - - - - - - PA14 JTCK-SWCLK LPTIM1_OUT - - I2C1_SMBA - - - PA15 JTDI TIM2_CH1 TIM2_ETR USART2_RX - SPI1_NSS SPI3_NSS USART3_RTS_ DE Port DS11453 Rev 3 Port A Pinouts and pin description 70/208 Table 16. Alternate function AF0 to AF7(1) STM32L431xx AF1 AF2 AF3 AF4 AF5 AF6 AF7 SYS_AF TIM1/TIM2/ LPTIM1 TIM1/TIM2 USART2 I2C1/I2C2/I2C3 SPI1/SPI2 SPI3 USART1/ USART2/ USART3 PB0 - TIM1_CH2N - - - SPI1_NSS - USART3_CK PB1 - TIM1_CH3N - - - - - USART3_RTS_ DE PB2 RTC_OUT LPTIM1_OUT - - I2C3_SMBA - - - PB3 JTDOTRACESWO TIM2_CH2 - - - SPI1_SCK SPI3_SCK USART1_RTS_ DE PB4 NJTRST - - - I2C3_SDA SPI1_MISO SPI3_MISO USART1_CTS PB5 - LPTIM1_IN1 - - I2C1_SMBA SPI1_MOSI SPI3_MOSI USART1_CK PB6 - LPTIM1_ETR - - I2C1_SCL - - USART1_TX PB7 - LPTIM1_IN2 - - I2C1_SDA - - USART1_RX PB8 - - - - I2C1_SCL - - - PB9 - IR_OUT - - I2C1_SDA SPI2_NSS - - PB10 - TIM2_CH3 - - I2C2_SCL SPI2_SCK - USART3_TX PB11 - TIM2_CH4 - - I2C2_SDA - - USART3_RX PB12 - TIM1_BKIN - TIM1_BKIN_ COMP2 I2C2_SMBA SPI2_NSS - USART3_CK PB13 - TIM1_CH1N - - I2C2_SCL SPI2_SCK - USART3_CTS PB14 - TIM1_CH2N - - I2C2_SDA SPI2_MISO - USART3_RTS_ DE PB15 RTC_REFIN TIM1_CH3N - - - SPI2_MOSI - - Port Port B DS11453 Rev 3 Port B 71/208 Pinouts and pin description AF0 STM32L431xx Table 16. Alternate function AF0 to AF7(1) (continued) AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 SYS_AF TIM1/TIM2/ LPTIM1 TIM1/TIM2 USART2 I2C1/I2C2/I2C3 SPI1/SPI2 SPI3 USART1/ USART2/ USART3 PC0 - LPTIM1_IN1 - - I2C3_SCL - - - PC1 - LPTIM1_OUT - - I2C3_SDA - - - PC2 - LPTIM1_IN2 - - - SPI2_MISO - - PC3 - LPTIM1_ETR - - - SPI2_MOSI - - PC4 - - - - - - - USART3_TX PC5 - - - - - - - USART3_RX PC6 - - - - - - - - PC7 - - - - - - - - PC8 - - - - - - - - PC9 - - - - - - - - PC10 - - - - - - SPI3_SCK USART3_TX PC11 - - - - - - SPI3_MISO USART3_RX PC12 - - - - - - SPI3_MOSI USART3_CK PC13 - - - - - - - - PC14 - - - - - - - - PC15 - - - - - - - - Port Port C DS11453 Rev 3 Port C Pinouts and pin description 72/208 Table 16. Alternate function AF0 to AF7(1) (continued) STM32L431xx AF1 AF2 AF3 AF4 AF5 AF6 AF7 SYS_AF TIM1/TIM2/ LPTIM1 TIM1/TIM2 USART2 I2C1/I2C2/I2C3 SPI1/SPI2 SPI3 USART1/ USART2/ USART3 PD0 - - - - - SPI2_NSS - - PD1 - - - - - SPI2_SCK - - PD2 - - - - - - - USART3_RTS_ DE PD3 - - - - - SPI2_MISO - USART2_CTS PD4 - - - - - SPI2_MOSI - USART2_RTS_ DE PD5 - - - - - - - USART2_TX PD6 - - - - - - - USART2_RX PD7 - - - - - - - USART2_CK PD8 - - - - - - - USART3_TX PD9 - - - - - - - USART3_RX PD10 - - - - - - - USART3_CK PD11 - - - - - - - USART3_CTS PD12 - - - - - - - USART3_RTS_ DE PD13 - - - - - - - - PD14 - - - - - - - - PD15 - - - - - - - - PE0 - - - - - - - - Port DS11453 Rev 3 Port D Port E 73/208 Pinouts and pin description AF0 STM32L431xx Table 16. Alternate function AF0 to AF7(1) (continued) AF1 AF2 AF3 AF4 AF5 AF6 AF7 SYS_AF TIM1/TIM2/ LPTIM1 TIM1/TIM2 USART2 I2C1/I2C2/I2C3 SPI1/SPI2 SPI3 USART1/ USART2/ USART3 PE1 - - - - - - - - PE2 TRACECK - - - - - - - PE3 TRACED0 - - - - - - - PE4 TRACED1 - - - - - - - PE5 TRACED2 - - - - - - - PE6 TRACED3 - - - - - - - PE7 - TIM1_ETR - - - - - - PE8 - TIM1_CH1N - - - - - - PE9 - TIM1_CH1 - - - - - - PE10 - TIM1_CH2N - - - - - - PE11 - TIM1_CH2 - - - - - - PE12 - TIM1_CH3N - - - SPI1_NSS - - PE13 - TIM1_CH3 - - - SPI1_SCK - - PE14 - TIM1_CH4 TIM1_BKIN2 TIM1_BKIN2_ COMP2 - SPI1_MISO - - PE15 - TIM1_BKIN - TIM1_BKIN_ COMP1 - SPI1_MOSI - - PH0 - - - - - - - - PH1 - - - - - - - - PH3 - - - - - - - - Port DS11453 Rev 3 Port E Port H 1. Please refer to Table 17 for AF8 to AF15. STM32L431xx AF0 Pinouts and pin description 74/208 Table 16. Alternate function AF0 to AF7(1) (continued) AF8 AF9 AF10 AF11 Port DS11453 Rev 3 Port A AF12 AF13 AF14 AF15 SDMMC1/ COMP1/ COMP2/ SWPMI1 SAI1 TIM2/TIM15/ TIM16/LPTIM2 EVENTOUT COMP1_OUT SAI1_EXTCLK TIM2_ETR EVENTOUT CAN1/TSC QUADSPI PA0 - - - PA1 - - - - - TIM15_CH1N EVENTOUT PA2 LPUART1_TX - QUADSPI_ BK1_NCS COMP2_OUT - TIM15_CH1 EVENTOUT PA3 LPUART1_RX - QUADSPI_CLK - SAI1_MCLK_A TIM15_CH2 EVENTOUT PA4 - - - - - SAI1_FS_B LPTIM2_OUT EVENTOUT PA5 - - - - - - LPTIM2_ETR EVENTOUT PA6 LPUART1_CTS - QUADSPI_ BK1_IO3 TIM1_BKIN_ COMP2 - TIM16_CH1 EVENTOUT PA7 - - QUADSPI_ BK1_IO2 COMP2_OUT - - EVENTOUT PA8 - - - SWPMI1_IO SAI1_SCK_A LPTIM2_OUT EVENTOUT PA9 - - - - SAI1_FS_A TIM15_BKIN EVENTOUT PA10 - - - SAI1_SD_A - EVENTOUT PA11 - CAN1_RX - TIM1_BKIN2_ COMP1 - - EVENTOUT PA12 - CAN1_TX - - - - EVENTOUT PA13 - - - SWPMI1_TX SAI1_SD_B - EVENTOUT PA14 - - - - SWPMI1_RX SAI1_FS_B - EVENTOUT PA15 - TSC_G3_IO1 - SWPMI1_ SUSPEND - - EVENTOUT - 75/208 Pinouts and pin description LPUART1 STM32L431xx Table 17. Alternate function AF8 to AF15(1) AF8 AF9 AF10 AF11 AF13 AF14 AF15 SAI1 TIM2/TIM15/ TIM16/LPTIM2 EVENTOUT CAN1/TSC QUADSPI PB0 - - QUADSPI_ BK1_IO1 COMP1_OUT SAI1_EXTCLK - EVENTOUT PB1 LPUART1_RTS _DE - QUADSPI_ BK1_IO0 - - LPTIM2_IN1 EVENTOUT PB2 - - - - - - EVENTOUT PB3 - - - - SAI1_SCK_B - EVENTOUT PB4 - TSC_G2_IO1 - - SAI1_MCLK_B - EVENTOUT PB5 - TSC_G2_IO2 - COMP2_OUT SAI1_SD_B TIM16_BKIN EVENTOUT PB6 - TSC_G2_IO3 - - SAI1_FS_B TIM16_CH1N EVENTOUT PB7 - TSC_G2_IO4 - - - - EVENTOUT PB8 - CAN1_RX - SDMMC1_D4 SAI1_MCLK_A TIM16_CH1 EVENTOUT PB9 - CAN1_TX - SDMMC1_D5 SAI1_FS_A - EVENTOUT PB10 LPUART1_RX TSC_SYNC QUADSPI_CLK COMP1_OUT SAI1_SCK_A - EVENTOUT PB11 LPUART1_TX - QUADSPI_ BK1_NCS COMP2_OUT - - EVENTOUT PB12 LPUART1_RTS _DE TSC_G1_IO1 - SWPMI1_IO SAI1_FS_A TIM15_BKIN EVENTOUT PB13 LPUART1_CTS TSC_G1_IO2 - SWPMI1_TX SAI1_SCK_A TIM15_CH1N EVENTOUT PB14 - TSC_G1_IO3 - SWPMI1_RX SAI1_MCLK_A TIM15_CH1 EVENTOUT PB15 - TSC_G1_IO4 - SWPMI1_ SUSPEND SAI1_SD_A TIM15_CH2 EVENTOUT DS11453 Rev 3 - STM32L431xx LPUART1 SDMMC1/ COMP1/ COMP2/ SWPMI1 Port Port B AF12 Pinouts and pin description 76/208 Table 17. Alternate function AF8 to AF15(1) (continued) AF8 AF9 AF10 AF11 DS11453 Rev 3 Port C AF14 AF15 SAI1 TIM2/TIM15/ TIM16/LPTIM2 EVENTOUT LPUART1 CAN1/TSC QUADSPI PC0 LPUART1_RX - - - - LPTIM2_IN1 EVENTOUT PC1 LPUART1_TX - - - - - EVENTOUT PC2 - - - - - - EVENTOUT PC3 - - - - SAI1_SD_A LPTIM2_ETR EVENTOUT PC4 - - - - - - EVENTOUT PC5 - - - - - - EVENTOUT PC6 - TSC_G4_IO1 - SDMMC1_D6 - - EVENTOUT PC7 - TSC_G4_IO2 - SDMMC1_D7 - - EVENTOUT PC8 - TSC_G4_IO3 - SDMMC1_D0 - - EVENTOUT PC9 - TSC_G4_IO4 SDMMC1_D1 - - EVENTOUT PC10 - TSC_G3_IO2 - SDMMC1_D2 - - EVENTOUT PC11 - TSC_G3_IO3 - SDMMC1_D3 - - EVENTOUT PC12 - TSC_G3_IO4 - SDMMC1_CK - - EVENTOUT PC13 - - - - - - - EVENTOUT PC14 - - - - - - - EVENTOUT PC15 - - - - - - - EVENTOUT PD0 - CAN1_RX - - - - - EVENTOUT PD1 - CAN1_TX - - - - - EVENTOUT PD2 - TSC_SYNC - SDMMC1_ CMD - - EVENTOUT 77/208 Pinouts and pin description Port D AF13 SDMMC1/ COMP1/ COMP2/ SWPMI1 Port Port C AF12 STM32L431xx Table 17. Alternate function AF8 to AF15(1) (continued) AF8 AF9 AF10 AF11 Port AF13 AF14 AF15 SDMMC1/ COMP1/ COMP2/ SWPMI1 SAI1 TIM2/TIM15/ TIM16/LPTIM2 EVENTOUT DS11453 Rev 3 CAN1/TSC QUADSPI PD3 - - QUADSPI_BK2 _NCS - - - - EVENTOUT PD4 - - QUADSPI_BK2 _IO0 - - - - EVENTOUT PD5 - - QUADSPI_BK2 _IO1 - - - - EVENTOUT PD6 - - QUADSPI_BK2 _IO2 - - SAI1_SD_A - EVENTOUT PD7 - - QUADSPI_BK2 _IO3 - - - - EVENTOUT PD8 - - - - - - EVENTOUT PD9 - - - - - - EVENTOUT PD10 - TSC_G6_IO1 - - - - EVENTOUT PD11 - TSC_G6_IO2 - - - LPTIM2_ETR EVENTOUT PD12 - TSC_G6_IO3 - - - LPTIM2_IN1 EVENTOUT PD13 - TSC_G6_IO4 - - - LPTIM2_OUT EVENTOUT PD14 - - - - - - EVENTOUT PD15 - - - - - - EVENTOUT PE0 - - - - - TIM16_CH1 EVENTOUT PE1 - - - - - - EVENTOUT PE2 - TSC_G7_IO1 - - SAI1_MCLK_A - EVENTOUT PE3 - TSC_G7_IO2 - - SAI1_SD_B - EVENTOUT PE4 - TSC_G7_IO3 - - SAI1_FS_A - EVENTOUT - STM32L431xx LPUART1 Port D Port E AF12 Pinouts and pin description 78/208 Table 17. Alternate function AF8 to AF15(1) (continued) AF8 AF9 AF10 AF11 Port DS11453 Rev 3 Port E AF13 AF14 AF15 SDMMC1/ COMP1/ COMP2/ SWPMI1 SAI1 TIM2/TIM15/ TIM16/LPTIM2 EVENTOUT LPUART1 CAN1/TSC QUADSPI PE5 - TSC_G7_IO4 - - - SAI1_SCK_A - EVENTOUT PE6 - - - - - SAI1_SD_A - EVENTOUT PE7 - - - - - SAI1_SD_B - EVENTOUT PE8 - - - - - SAI1_SCK_B - EVENTOUT PE9 - - - - - SAI1_FS_B - EVENTOUT PE10 - TSC_G5_IO1 QUADSPI_CLK - - SAI1_MCLK_B - EVENTOUT PE11 - TSC_G5_IO2 QUADSPI_BK1 _NCS - - - - EVENTOUT PE12 - TSC_G5_IO3 QUADSPI_BK1 _IO0 - - - - EVENTOUT PE13 - TSC_G5_IO4 QUADSPI_BK1 _IO1 - - - - EVENTOUT PE14 - - QUADSPI_BK1 _IO2 - - - - EVENTOUT PE15 - - QUADSPI_BK1 _IO3 - - - - EVENTOUT PH0 - - - - - - - EVENTOUT PH1 - - - - - - - EVENTOUT PH3 - - - - - - - EVENTOUT 1. Please refer to Table 16 for AF0 to AF7. 79/208 Pinouts and pin description Port H AF12 STM32L431xx Table 17. Alternate function AF8 to AF15(1) (continued) Memory mapping 5 STM32L431xx Memory mapping Figure 15. STM32L431xx memory map 0xFFFF FFFF 0xBFFF FFFF Reserved Cortex™-M4 with FPU Internal Peripherals 7 0xA000 1400 QUADSPI registers 0xA000 1000 0xE000 0000 0x5FFF FFFF Reserved 6 0x5006 0C00 AHB2 0x4800 0000 Reserved 0xC000 0000 0x4002 4400 QUADSPI registers 5 AHB1 0x4002 0000 0xA000 1000 0x4001 5800 0xA000 0000 APB2 0x4001 0000 QUADSPI Flash bank 4 Reserved Reserved 0x4000 9800 0x9000 0000 APB1 0x4000 0000 0x1FFF FFFF 0x8000 0000 3 Reserved 0x6000 0000 0x1FFF 7810 Options Bytes 2 0x1FFF 7800 Reserved 0x1FFF 7400 Peripherals OTP area 0x4000 0000 0x1FFF 7000 System memory 1 0x2000 C000 0x1FFF 0000 SRAM2 Reserved 0x1000 4000 SRAM1 SRAM2 0x2000 0000 0x1000 0000 Reserved 0 0x0804 0000 CODE Flash memory 0x0800 0000 0x0000 0000 0x0004 0000 0x0000 0000 Reserved Reserved Flash, system memory or SRAM, depending on BOOT configuration MSv36892V2 80/208 DS11453 Rev 3 STM32L431xx Memory mapping Table 18. STM32L431xx memory map and peripheral register boundary addresses(1) Bus AHB2 - AHB1 APB2 Boundary address Size(bytes) Peripheral 0x5006 0800 - 0x5006 0BFF 1 KB 0x5004 0400 - 0x5006 07FF 158 KB 0x5004 0000 - 0x5004 03FF 1 KB ADC 0x5000 0000 - 0x5003 FFFF 16 KB Reserved 0x4800 2000 - 0x4FFF FFFF ~127 MB Reserved 0x4800 1C00 - 0x4800 1FFF 1 KB GPIOH 0x4800 1400 - 0x4800 1BFF 2 KB Reserved 0x4800 1000 - 0x4800 13FF 1 KB GPIOE 0x4800 0C00 - 0x4800 0FFF 1 KB GPIOD 0x4800 0800 - 0x4800 0BFF 1 KB GPIOC 0x4800 0400 - 0x4800 07FF 1 KB GPIOB 0x4800 0000 - 0x4800 03FF 1 KB GPIOA 0x4002 4400 - 0x47FF FFFF ~127 MB 0x4002 4000 - 0x4002 43FF 1 KB TSC 0x4002 3400 - 0x4002 3FFF 1 KB Reserved 0x4002 3000 - 0x4002 33FF 1 KB CRC 0x4002 2400 - 0x4002 2FFF 3 KB Reserved 0x4002 2000 - 0x4002 23FF 1 KB FLASH registers 0x4002 1400 - 0x4002 1FFF 3 KB Reserved 0x4002 1000 - 0x4002 13FF 1 KB RCC 0x4002 0800 - 0x4002 0FFF 2 KB Reserved 0x4002 0400 - 0x4002 07FF 1 KB DMA2 0x4002 0000 - 0x4002 03FF 1 KB DMA1 0x4001 5800 - 0x4001 FFFF 42 KB Reserved 0x4001 5400 - 0x4000 57FF 1 KB SAI1 0x4001 4800 - 0x4000 53FF 3 KB Reserved 0x4001 4400 - 0x4001 47FF 1 KB TIM16 0x4001 4000 - 0x4001 43FF 1 KB TIM15 0x4001 3C00 - 0x4001 3FFF 1 KB Reserved 0x4001 3800 - 0x4001 3BFF 1 KB USART1 0x4001 3400 - 0x4001 37FF 1 KB Reserved DS11453 Rev 3 RNG Reserved Reserved 81/208 83 Memory mapping STM32L431xx Table 18. STM32L431xx memory map and peripheral register boundary addresses(1) (continued) Bus APB2 Boundary address Size(bytes) 0x4001 3000 - 0x4001 33FF 1 KB SPI1 0x4001 2C00 - 0x4001 2FFF 1 KB TIM1 0x4001 2800 - 0x4001 2BFF 1 KB SDMMC1 0x4001 2000 - 0x4001 27FF 2 KB Reserved 0x4001 1C00 - 0x4001 1FFF 1 KB FIREWALL 0x4001 0800- 0x4001 1BFF 5 KB Reserved 0x4001 0400 - 0x4001 07FF 1 KB EXTI 0x4001 0200 - 0x4001 03FF 0x4001 0030 - 0x4001 01FF COMP 1 KB 0x4001 0000 - 0x4001 002F APB1 82/208 Peripheral VREFBUF SYSCFG 0x4000 9800 - 0x4000 FFFF 26 KB Reserved 0x4000 9400 - 0x4000 97FF 1 KB LPTIM2 0x4000 8C00 - 0x4000 93FF 2 KB Reserved 0x4000 8800 - 0x4000 8BFF 1 KB SWPMI1 0x4000 8400 - 0x4000 87FF 1 KB Reserved 0x4000 8000 - 0x4000 83FF 1 KB LPUART1 0x4000 7C00 - 0x4000 7FFF 1 KB LPTIM1 0x4000 7800 - 0x4000 7BFF 1 KB OPAMP 0x4000 7400 - 0x4000 77FF 1 KB DAC1 0x4000 7000 - 0x4000 73FF 1 KB PWR 0x4000 6800 - 0x4000 6FFF 2 KB Reserved 0x4000 6400 - 0x4000 67FF 1 KB CAN1 0x4000 6000 - 0x4000 63FF 1 KB CRS 0x4000 5C00- 0x4000 5FFF 1 KB I2C3 0x4000 5800 - 0x4000 5BFF 1 KB I2C2 0x4000 5400 - 0x4000 57FF 1 KB I2C1 0x4000 4C00 - 0x4000 53FF 2 KB Reserved 0x4000 4800 - 0x4000 4BFF 1 KB USART3 0x4000 4400 - 0x4000 47FF 1 KB USART2 0x4000 4000 - 0x4000 43FF 1 KB Reserved 0x4000 3C00 - 0x4000 3FFF 1 KB SPI3 0x4000 3800 - 0x4000 3BFF 1 KB SPI2 0x4000 3400 - 0x4000 37FF 1 KB Reserved 0x4000 3000 - 0x4000 33FF 1 KB IWDG DS11453 Rev 3 STM32L431xx Memory mapping Table 18. STM32L431xx memory map and peripheral register boundary addresses(1) (continued) Bus APB1 Boundary address Size(bytes) Peripheral 0x4000 2C00 - 0x4000 2FFF 1 KB WWDG 0x4000 2800 - 0x4000 2BFF 1 KB RTC 0x4000 1800 - 0x4000 27FF 4 KB Reserved 0x4000 1400 - 0x4000 17FF 1 KB TIM7 0x4000 1000 - 0x4000 13FF 1 KB TIM6 0x4000 0400- 0x4000 0FFF 3 KB Reserved 0x4000 0000 - 0x4000 03FF 1 KB TIM2 1. The gray color is used for reserved boundary addresses. DS11453 Rev 3 83/208 83 Electrical characteristics STM32L431xx 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ±3σ). 6.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3 V. They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ±2σ). 6.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 16. 6.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 17. Figure 16. Pin loading conditions Figure 17. Pin input voltage MCU pin MCU pin C = 50 pF VIN MS19210V1 84/208 DS11453 Rev 3 MS19211V1 STM32L431xx 6.1.6 Electrical characteristics Power supply scheme Figure 18. Power supply scheme VBAT Backup circuitry (LSE, RTC, Backup registers) 1.55 – 3.6 V Power switch VDD VCORE n x VDD Regulator OUT n x 100 nF GPIOs IN +1 x 4.7 μF Level shifter VDDIO1 IO logic Kernel logic (CPU, Digital & Memories) n x VSS VDDA VDDA VREF 10 nF +1 μF VREF+ VREF- 100 nF +1 μF ADCs/ DACs/ OPAMPs/ COMPs/ VREFBUF VSSA MSv41628V1 Caution: Each power supply pair (VDD/VSS, VDDA/VSSA etc.) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device. DS11453 Rev 3 85/208 176 Electrical characteristics 6.1.7 STM32L431xx Current consumption measurement Figure 19. Current consumption measurement scheme IDD_VBAT VBAT IDD VDD IDDA VDDA MSv41629V1 The IDD_ALL parameters given in Table 26 to Table 38 represent the total MCU consumption including the current supplying VDD, VDDA and VBAT. 6.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 19: Voltage characteristics, Table 20: Current characteristics and Table 21: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 qualification standard, extended mission profiles are available on demand. Table 19. Voltage characteristics(1) Symbol VDDX - VSS VIN(2) |∆VDDx| |VSSx-VSS| Ratings Min Max Unit -0.3 4.0 V Input voltage on FT_xxx pins VSS-0.3 min (VDD, VDDA) + 4.0(3)(4) Input voltage on TT_xx pins VSS-0.3 4.0 Input voltage on any other pins VSS-0.3 4.0 Variations between different VDDX power pins of the same domain - 50 mV Variations between all the different ground pins(5) - 50 mV External main supply voltage (including VDD, VDDA, VBAT) V 1. All main power (VDD, VDDA, VBAT) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. VIN maximum must always be respected. Refer to Table 20: Current characteristics for the maximum allowed injected current values. 3. This formula has to be applied only on the power supplies related to the IO structure described in the pin definition table. 4. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled. 86/208 DS11453 Rev 3 STM32L431xx Electrical characteristics 5. Include VREF- pin. Table 20. Current characteristics Symbol Ratings Max ∑IVDD Total current into sum of all VDD power lines (source) (1) 140 ∑IVSS Total current out of sum of all VSS ground lines (sink)(1) 140 IVDD(PIN) IVSS(PIN) IIO(PIN) ∑IIO(PIN) IINJ(PIN)(3) (1) 100 (1) 100 Maximum current into each VDD power pin (source) Maximum current out of each VSS ground pin (sink) Output current sunk by any I/O and control pin except FT_f 20 Output current sunk by any FT_f pin 20 Output current sourced by any I/O and control pin 20 Total output current sunk by sum of all I/Os and control pins(2) mA 100 (2) Total output current sourced by sum of all I/Os and control pins 100 Injected current on FT_xxx, TT_xx, RST and B pins, except PA4, PA5 -5/+0(4) Injected current on PA4, PA5 ∑|IINJ(PIN)| Unit -5/0 Total injected current (sum of all I/Os and control pins) (5) 25 1. All main power (VDD, VDDA, VBAT) and ground (VSS, VSSA) pins must always be connected to the external power supplies, in the permitted range. 2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages. 3. Positive injection (when VIN > VDDIOx) is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. 4. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 19: Voltage characteristics for the maximum allowed input voltage values. 5. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of the negative injected currents (instantaneous values). Table 21. Thermal characteristics Symbol TSTG TJ Ratings Storage temperature range Maximum junction temperature DS11453 Rev 3 Value Unit –65 to +150 °C 150 °C 87/208 176 Electrical characteristics STM32L431xx 6.3 Operating conditions 6.3.1 General operating conditions Table 22. General operating conditions Symbol Parameter Conditions Min Max fHCLK Internal AHB clock frequency - 0 80 fPCLK1 Internal APB1 clock frequency - 0 80 fPCLK2 Internal APB2 clock frequency - 0 80 Standard operating voltage - VDD VDDA Analog supply voltage 1.71 VIN V 3.6 V 1.55 3.6 V TT_xx I/O -0.3 VDDIOx+0.3 All I/O except TT_xx -0.3 Min(Min(VDD, VDDA)+3.6 V, 5.5 V)(2)(3) LQFP100 - 476 LQFP64 - 444 LQFP48 - 350 UFBGA100 - 350 UFBGA64 - 307 UFQFPN48 - 606 UFQFPN32 - 523 WLCSP64 - 434 WLCSP49 - 416 ADC or COMP used 1.62 DAC or OPAMP used 1.8 VREFBUF used 2.4 PD TA TJ 88/208 Backup operating voltage I/O input voltage Power dissipation at TA = 85 °C for suffix 6 or TA = 105 °C for suffix 7(4) - 0 Ambient temperature for the suffix 6 version Maximum power dissipation –40 85 Low-power dissipation(5) –40 105 Ambient temperature for the suffix 7 version Maximum power dissipation –40 105 –40 125 Ambient temperature for the suffix 3 version Maximum power dissipation –40 125 Low-power dissipation(5) –40 130 Suffix 6 version –40 105 Suffix 7 version –40 125 Suffix 3 version –40 130 Junction temperature range MHz 3.6 (1) ADC, DAC, OPAMP, COMP, VREFBUF not used VBAT Unit Low-power dissipation (5) DS11453 Rev 3 V mW °C °C STM32L431xx Electrical characteristics 1. When RESET is released functionality is guaranteed down to VBOR0 Min. 2. This formula has to be applied only on the power supplies related to the IO structure described by the pin definition table. Maximum I/O input voltage is the smallest value between Min(VDD, VDDA)+3.6 V and 5.5V. 3. For operation with voltage higher than Min (VDD, VDDA) +0.3 V, the internal Pull-up and Pull-Down resistors must be disabled. 4. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Section 7.10: Thermal characteristics). 5. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 7.10: Thermal characteristics). 6.3.2 Operating conditions at power-up / power-down The parameters given in Table 23 are derived from tests performed under the ambient temperature condition summarized in Table 22. Table 23. Operating conditions at power-up / power-down Symbol Parameter Conditions VDD rise time rate tVDD Max 0 ∞ 10 ∞ 0 ∞ 10 ∞ - VDD fall time rate VDDA rise time rate tVDDA Min - VDDA fall time rate Unit µs/V The requirements for power-up/down sequence specified in Section 3.9.1: Power supply schemes must be respected. 6.3.3 Embedded reset and power control block characteristics The parameters given in Table 24 are derived from tests performed under the ambient temperature conditions summarized in Table 22: General operating conditions. Table 24. Embedded reset and power control block characteristics Symbol tRSTTEMPO(2) Parameter Reset temporization after BOR0 is detected VBOR0(2) Brown-out reset threshold 0 VBOR1 Brown-out reset threshold 1 VBOR2 Brown-out reset threshold 2 VBOR3 Brown-out reset threshold 3 VBOR4 Brown-out reset threshold 4 Conditions(1) Min Typ Max Unit - 250 400 μs Rising edge 1.62 1.66 1.7 Falling edge 1.6 1.64 1.69 Rising edge 2.06 2.1 2.14 Falling edge 1.96 2 2.04 Rising edge 2.26 2.31 2.35 Falling edge 2.16 2.20 2.24 Rising edge 2.56 2.61 2.66 Falling edge 2.47 2.52 2.57 Rising edge 2.85 2.90 2.95 Falling edge 2.76 2.81 2.86 VDD rising DS11453 Rev 3 V V V V V 89/208 176 Electrical characteristics STM32L431xx Table 24. Embedded reset and power control block characteristics (continued) Conditions(1) Min Typ Max Rising edge 2.1 2.15 2.19 Falling edge 2 2.05 2.1 Rising edge 2.26 2.31 2.36 Falling edge 2.15 2.20 2.25 Rising edge 2.41 2.46 2.51 Falling edge 2.31 2.36 2.41 Rising edge 2.56 2.61 2.66 Falling edge 2.47 2.52 2.57 Rising edge 2.69 2.74 2.79 Falling edge 2.59 2.64 2.69 Rising edge 2.85 2.91 2.96 Falling edge 2.75 2.81 2.86 Rising edge 2.92 2.98 3.04 Falling edge 2.84 2.90 2.96 Hysteresis in continuous Hysteresis voltage of BORH0 mode - 20 - Hysteresis in other mode - 30 - Symbol Parameter VPVD0 Programmable voltage detector threshold 0 VPVD1 PVD threshold 1 VPVD2 PVD threshold 2 VPVD3 PVD threshold 3 VPVD4 PVD threshold 4 VPVD5 PVD threshold 5 VPVD6 PVD threshold 6 Vhyst_BORH0 Unit V V V V V V V mV Hysteresis voltage of BORH (except BORH0) and PVD - - 100 - mV IDD BOR(3) (except BOR0) and (BOR_PVD)(2) PVD consumption from VDD - - 1.1 1.6 µA Vhyst_BOR_PVD VPVM3 VDDA peripheral voltage monitoring Rising edge 1.61 1.65 1.69 Falling edge 1.6 1.64 1.68 VPVM4 VDDA peripheral voltage monitoring Rising edge 1.78 1.82 1.86 Falling edge 1.77 1.81 1.85 V V Vhyst_PVM3 PVM3 hysteresis - - 10 - mV Vhyst_PVM4 PVM4 hysteresis - - 10 - mV PVM1 consumption from VDD - - 0.2 - µA - - 2 - µA IDD (PVM1) (2) IDD PVM3 and PVM4 (PVM3/PVM4) consumption from VDD (2) 1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes. 2. Guaranteed by design. 3. BOR0 is enabled in all modes (except shutdown) and its consumption is therefore included in the supply current characteristics tables. 90/208 DS11453 Rev 3 STM32L431xx 6.3.4 Electrical characteristics Embedded voltage reference The parameters given in Table 25 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 22: General operating conditions. Table 25. Embedded internal voltage reference Symbol VREFINT Parameter Internal reference voltage Conditions –40 °C < TA < +130 °C Min Typ Max Unit 1.182 1.212 1.232 V tS_vrefint (1) ADC sampling time when reading the internal reference voltage - 4(2) - - µs tstart_vrefint Start time of reference voltage buffer when ADC is enable - - 8 12(2) µs - - 12.5 20(2) µA VREFINT buffer consumption from VDD when converted by IDD(VREFINTBUF) ADC ∆VREFINT TCoeff Internal reference voltage spread over the temperature range VDD = 3 V - 5 7.5(2) mV Temperature coefficient –40°C < TA < +130°C - 30 50(2) ppm/°C ppm ppm/V ACoeff Long term stability 1000 hours, T = 25°C - 300 1000(2) VDDCoeff Voltage coefficient 3.0 V < VDD < 3.6 V - 250 1200(2) 24 25 26 49 50 51 74 75 76 VREFINT_DIV1 1/4 reference voltage VREFINT_DIV2 1/2 reference voltage VREFINT_DIV3 3/4 reference voltage - % VREFINT 1. The shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design. DS11453 Rev 3 91/208 176 Electrical characteristics STM32L431xx Figure 20. VREFINT versus temperature V 1.235 1.23 1.225 1.22 1.215 1.21 1.205 1.2 1.195 1.19 1.185 -40 -20 0 20 40 Mean 60 Min 80 100 120 °C Max MSv40169V1 92/208 DS11453 Rev 3 STM32L431xx 6.3.5 Electrical characteristics Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 19: Current consumption measurement scheme. Typical and maximum current consumption The MCU is placed under the following conditions: • All I/O pins are in analog input mode • All peripherals are disabled except when explicitly mentioned • The Flash memory access time is adjusted with the minimum wait states number, depending on the fHCLK frequency (refer to the table “Number of wait states according to CPU clock (HCLK) frequency” available in the RM0394 reference manual). • When the peripherals are enabled fPCLK = fHCLK The parameters given in Table 26 to Table 39 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 22: General operating conditions. DS11453 Rev 3 93/208 176 running from Flash, ART enable (Cache ON Prefetch OFF) Conditions Symbol Parameter - Voltage scaling DS11453 Rev 3 IDD_ALL (LPRun) Unit 55 °C 85 °C 2.7 2.7 2.8 2.9 3.2 1.79 1.7 1.7 1.8 2.0 2.3 0.94 1.08 0.9 0.9 1.0 1.2 1.5 0.52 0.59 0.73 0.5 0.6 0.6 0.8 1.1 0.3 0.34 0.41 0.55 0.3 0.4 0.4 0.6 0.9 0.2 0.21 0.25 0.32 0.46 0.2 0.3 0.3 0.5 0.8 100 kHz 0.12 0.13 0.17 0.24 0.38 0.1 0.2 0.2 0.4 0.7 80 MHz 8.53 8.56 8.64 8.74 8.92 9.5 9.6 9.7 9.9 10.3 72 MHz 7.7 7.73 7.8 7.9 8.08 8.6 8.6 8.7 8.9 9.3 64 MHz 6.86 6.9 6.97 7.06 7.23 7.7 7.7 7.8 8.0 8.3 Range 1 48 MHz 5.13 5.16 5.23 5.32 5.49 5.8 5.8 6.0 6.1 6.5 32 MHz 3.46 3.48 3.55 3.64 3.8 3.9 4.0 4.1 4.2 4.6 24 MHz 2.63 2.64 2.71 2.79 2.96 3.0 3.0 3.1 3.3 3.6 16 MHz 1.8 1.81 1.87 1.96 2.12 2.0 2.1 2.2 2.3 2.7 2 MHz 211 230 280 355 506 273.8 301.1 360.4 502.7 815.9 1 MHz 117 134 179 254 404 154.7 184.6 249.6 398.4 712.4 400 kHz 58.5 70.4 116 189 338 80.2 111.5 179.7 330.8 643.4 100 kHz 30 41.1 85.2 159 308 46.5 76.6 147.1 299.1 611.2 Range 2 IDD_ALL (Run) MAX(1) TYP fHCLK = fHSE up to 48MHz included, Supply bypass mode current in PLL ON above Run mode 48 MHz all peripherals disable Supply current in fHCLK = fMSI Low-power all peripherals disable run mode 25 °C 55 °C 85 °C 26 MHz 2.37 2.38 2.44 2.52 2.66 16 MHz 1.5 1.52 1.57 1.64 8 MHz 0.81 0.82 0.87 4 MHz 0.46 0.47 2 MHz 0.29 1 MHz fHCLK 105 °C 125 °C mA µA STM32L431xx 1. Guaranteed by characterization results, unless otherwise specified. 105 °C 125 °C 25 °C Electrical characteristics 94/208 Table 26. Current consumption in Run and Low-power run modes, code with data processing running from Flash, ART disable Conditions Symbol Parameter - Voltage scaling Range 2 IDD_ALL (Run) DS11453 Rev 3 IDD_ALL (LPRun) fHCLK = fHSE up to 48MHz included, Supply bypass mode current in PLL ON above Run mode 48 MHz all peripherals disable MAX(1) TYP Unit 25 °C 55 °C 85 °C 26 MHz 2.66 2.68 2.73 2.81 2.96 16 MHz 1.88 1.9 1.94 2.02 8 MHz 1.05 1.06 1.11 1.18 4 MHz 0.6 0.62 0.66 fHCLK 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C 3.0 3.1 3.2 3.3 3.6 2.17 2.1 2.2 2.3 2.4 2.7 1.33 1.2 1.2 1.3 1.4 1.7 0.73 0.87 0.7 0.7 0.8 0.9 1.2 2 MHz 0.36 0.37 0.34 0.48 0.62 0.4 0.4 0.5 0.6 0.9 1 MHz 0.23 0.25 0.25 0.36 0.5 0.3 0.3 0.4 0.5 0.8 100 kHz 0.12 0.14 0.17 0.25 0.39 0.1 0.2 0.2 0.4 0.7 80 MHz 8.56 8.61 8.69 8.79 8.97 9.6 9.7 9.8 10.0 10.3 72 MHz 7.74 7.79 7.86 7.96 8.14 8.7 8.7 8.8 9.0 9.4 64 MHz 7.63 7.68 7.75 7.85 8.04 8.6 8.6 8.7 8.9 9.3 Range 1 48 MHz 6.36 6.4 6.48 6.58 6.76 7.2 7.3 7.4 7.6 7.9 32 MHz 4.56 4.6 4.66 4.76 4.93 5.2 5.2 5.3 5.5 5.8 24 MHz 3.45 3.48 3.54 3.64 3.8 3.9 4.0 4.1 4.2 4.6 16 MHz 2.48 2.51 2.56 2.65 2.82 2.8 2.9 3.0 3.1 3.5 2 MHz 310 317 364 440 593 375.3 400.9 456.7 595.3 909.6 1 MHz 157 173 226 296 448 204.8 234.2 298.2 445.8 758.9 400 kHz 72.6 89 130 206 356 99.7 131.2 199.7 349.3 663.7 100 kHz 32.3 46 89.7 164 314 52.4 82.1 153.3 301.2 616.9 Supply current in fHCLK = fMSI Low-power all peripherals disable run mA µA 95/208 Electrical characteristics 1. Guaranteed by characterization results, unless otherwise specified. STM32L431xx Table 27. Current consumption in Run and Low-power run modes, code with data processing Conditions Symbol Parameter - Voltage scaling Range 2 IDD_ALL (Run) Supply current in Run mode DS11453 Rev 3 fHCLK = fHSE up to 48MHz included, bypass mode PLL ON above 48 MHz all peripherals disable Range 1 IDD_ALL (LPRun) Supply current in low-power run mode fHCLK = fMSI all peripherals disable FLASH in power-down MAX(1) TYP fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 26 MHz 2.42 2.43 2.49 16 MHz 1.54 1.55 1.6 2.56 2.71 2.7 1.67 1.82 1.7 85 °C 105 °C 2.7 2.8 3.0 3.3 1.7 1.8 2.0 2.3 55 °C 125 °C 8 MHz 0.82 0.84 0.88 0.95 1.1 0.9 1.0 1.0 1.2 1.5 4 MHz 0.47 0.48 0.52 0.59 0.73 0.5 0.6 0.6 0.8 1.1 2 MHz 0.29 0.3 0.34 0.41 0.55 0.3 0.4 0.4 0.6 0.9 1 MHz 0.2 0.21 0.25 0.32 0.46 0.2 0.3 0.3 0.5 0.8 100 kHz 0.12 0.13 0.17 0.24 0.38 0.1 0.2 0.2 0.4 0.7 80 MHz 8.63 8.68 8.74 8.84 9.01 9.5 9.6 9.7 9.9 10.2 72 MHz 7.79 7.83 7.9 7.99 8.17 8.6 8.6 8.8 8.9 9.3 64 MHz 6.95 6.99 7.05 7.15 7.32 7.7 7.7 7.9 8.0 8.4 48 MHz 5.19 5.22 5.29 5.38 5.55 5.8 5.8 5.9 6.1 6.5 32 MHz 3.51 3.53 3.6 3.68 3.85 3.9 4.0 4.1 4.2 4.6 24 MHz 2.66 2.68 2.74 2.83 2.99 3.0 3.0 3.1 3.3 3.6 16 MHz 1.82 1.84 1.89 1.98 2.14 2.0 2.1 2.2 2.3 2.7 2 MHz 205 228 275 352 501 276.5 302.3 358.4 502.5 816.4 1 MHz 111 126 175 248 397 151.3 180.9 245.3 390.7 703.4 400 kHz 49.2 62.7 108 181 330 73.3 104.0 170.8 321.0 632.4 100 kHz 21.5 33.3 76.6 151 299 36.4 67.7 137.2 287.8 600.8 Unit Electrical characteristics 96/208 Table 28. Current consumption in Run and Low-power run modes, code with data processing running from SRAM1 mA µA 1. Guaranteed by characterization results, unless otherwise specified. STM32L431xx STM32L431xx Electrical characteristics Table 29. Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART enable (Cache ON Prefetch OFF) Conditions - IDD_ALL (Run) Supply current in Run mode fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable Voltage scaling Range 2 fHCLK = 26 MHz Parameter Supply current in fHCLK = fMSI = 2 MHz Low-power all peripherals disable run Unit 25 °C 25 °C Reduced code(1) 2.37 91 Coremark 2.69 103 Dhrystone 2.1 2.74 Fibonacci 2.58 99 2.30 88 Reduced code 8.53 107 Coremark 9.68 121 Dhrystone 2.1 9.76 Fibonacci 9.27 116 8.20 103 Reduced code 211 106 Coremark 251 126 Dhrystone 2.1 269 Fibonacci 230 115 While(1) 286 143 While(1) While(1) (1) IDD_ALL (LPRun) TYP Unit Code (1) Range 1 fHCLK = 80 MHz Symbol TYP mA mA µA 105 122 135 µA/MHz µA/MHz µA/MHz 1. Reduced code used for characterization results provided in Table 26, Table 27, Table 28. DS11453 Rev 3 97/208 176 Electrical characteristics STM32L431xx Table 30. Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART disable Conditions Parameter - IDD_ALL (Run) IDD_ALL (LPRun) Supply current in Run mode fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable Supply current in fHCLK = fMSI = 2 MHz Low-power all peripherals disable run TYP Unit Voltage scaling Range 1 Range 2 fHCLK = 80 MHz fHCLK = 26 MHz Symbol TYP Code Unit 25 °C 25 °C Reduced code(1) 2.66 102 Coremark 2.44 94 Dhrystone 2.1 2.46 Fibonacci 2.27 87 While(1) 2.20 84.6 Reduced code(1) 8.56 107 Coremark 8.00 mA 95 µA/MHz 100 mA Dhrystone 2.1 7.98 100 Fibonacci 7.41 While(1) 7.83 98 Reduced code(1) 310 155 µA/MHz 93 Coremark 342 Dhrystone 2.1 324 171 Fibonacci 324 162 While(1) 384 192 µA 162 µA/MHz 1. Reduced code used for characterization results provided in Table 26, Table 27, Table 28. Table 31. Typical current consumption in Run and Low-power run modes, with different codes running from SRAM1 Conditions Parameter - IDD_ALL (Run) IDD_ALL (LPRun) fHCLK = fHSE up to 48 MHz included, bypass mode Supply current in PLL ON above Run mode 48 MHz all peripherals disable Voltage scaling Range 1 Range 2 fHCLK = 80 MHz fHCLK = 26 MHz Symbol Supply current in fHCLK = fMSI = 2 MHz Low-power all peripherals disable run TYP Unit Code Unit 25 °C 25 °C Reduced code(1) 2.42 93 Coremark 2.18 Dhrystone 2.1 2.40 84 mA 92 Fibonacci 2.40 92 While(1) 2.29 88 Reduced code(1) 8.63 108 Coremark 7.76 8.55 Fibonacci 8.56 107 While(1) 8.12 102 Reduced code(1) 205 103 Coremark 188 107 µA/MHz 94 µA Dhrystone 2.1 222 Fibonacci 204 102 While(1) 211 106 DS11453 Rev 3 µA/MHz 97 mA Dhrystone 2.1 1. Reduced code used for characterization results provided in Table 26, Table 27, Table 28. 98/208 TYP 111 µA/MHz Conditions Symbol Parameter - Voltage scaling Unit fHCLK 26 MHz IDD_ALL (Sleep) DS11453 Rev 3 IDD_ALL (LPSleep) 25 °C 55 °C 85 °C 0.68 0.74 0.69 105 °C 125 °C 25 °C 0.81 0.95 0.8 55 °C 85 °C 0.8 0.9 105 °C 125 °C 1.0 1.3 16 MHz 0.46 0.48 0.52 0.59 0.73 0.5 0.6 0.6 0.8 1.1 8 MHz 0.29 0.30 0.34 0.41 0.55 0.3 0.4 0.4 0.6 0.9 4 MHz 0.20 0.21 0.25 0.32 0.46 0.2 0.3 0.3 0.5 0.8 2 MHz 0.16 0.17 0.21 0.28 0.42 0.2 0.2 0.3 0.4 0.7 1 MHz 0.13 0.15 0.19 0.26 0.40 0.1 0.2 0.3 0.4 0.7 100 kHz 0.11 0.13 0.17 0.24 0.38 0.1 0.2 0.2 0.4 0.7 80 MHz 2.23 2.25 2.30 2.38 2.54 2.5 2.5 2.6 2.8 3.1 72 MHz 2.02 2.04 2.10 2.18 2.34 2.2 2.3 2.4 2.5 2.9 64 MHz 1.82 1.84 1.89 1.98 2.14 2.0 2.1 2.1 2.3 2.6 Range 1 48 MHz 1.34 1.36 1.42 1.50 1.66 1.5 1.6 1.7 1.8 2.2 32 MHz 0.93 0.95 1.01 1.09 1.25 1.1 1.1 1.2 1.4 1.7 24 MHz 0.73 0.75 0.80 0.88 1.04 0.8 0.9 1.0 1.1 1.4 16 MHz 0.53 0.55 0.60 0.68 0.84 0.6 0.6 0.7 0.9 1.2 2 MHz 71.8 80.7 125 200 350 91.1 122.7 191.3 341.5 653.5 1 MHz 45.0 57.3 101 176 325 63.2 95.4 165.4 316.5 628.7 400 kHz 27.0 40.7 84.6 158 308 43.9 75.8 147.2 297.6 609.2 100 kHz 22.8 30.9 63.3 113.2 207.7 35.2 67.9 140.9 290.8 602.4 Range 2 Supply current in sleep mode, MAX(1) TYP fHCLK = fHSE up to 48 MHz included, bypass mode pll ON above 48 MHz all peripherals disable Supply current in =f f low-power HCLK MSI all peripherals disable sleep mode mA µA 99/208 Electrical characteristics 1. Guaranteed by characterization results, unless otherwise specified. STM32L431xx Table 32. Current consumption in Sleep and Low-power sleep modes, Flash ON Conditions Symbol Parameter Voltage scaling - IDD_ALL (LPSleep) Supply current in low-power sleep mode fHCLK = fMSI all peripherals disable MAX(1) TYP Unit fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 2 MHz 58.7 70.7 103.2 153.7 248.5 105 °C 125 °C 80 113 180 330 641 1 MHz 39.4 47.2 79.3 129.6 224.8 53 86 154 304 616 400 kHz 20.8 30.8 62.1 112.5 207.8 35 67 137 286 597 100 kHz 14.3 23.1 55.1 105.7 201.5 27 58 130 279 590 µA Electrical characteristics 100/208 Table 33. Current consumption in Low-power sleep modes, Flash in power-down 1. Guaranteed by characterization results, unless otherwise specified. Table 34. Current consumption in Stop 2 mode DS11453 Rev 3 Symbol Parameter IDD_ALL (Stop 2) Supply current in Stop 2 mode, RTC disabled Conditions - - RTC clocked by LSI IDD_ALL (Stop 2 with RTC) Supply current in RTC clocked by LSE Stop 2 mode, bypassed at 32768 Hz RTC enabled VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C 1.8 V 1 2.54 8.74 19.8 43.4 2.0 5.6 21.1 50.8 116.0 2.4 V 1.02 2.59 8.89 20.2 44.3 2.1 5.8 21.6 52.3 119.6 3V 1.06 2.67 9.11 20.7 45.5 2.1 5.9 22.2 53.7 123.2 3.6 V 1.23 2.88 9.56 21.6 47.3 2.3 6.1 23.0 55.8 127.9 1.8 V 1.3 2.82 9.02 20.1 43.6 2.5 6.2 21.6 51.3 116.3 2.4 V 1.39 2.95 9.24 20.5 44.6 2.8 6.4 22.3 52.8 120.0 3V 1.5 3.11 9.55 21.1 45.8 3.0 6.8 23.0 54.5 123.8 3.6 V 1.76 3.42 10.1 22.1 47.8 3.3 7.2 24.1 56.7 128.7 1.8 V 1.36 2.9 9.1 20.1 43.7 - - - - - 2.4 V 1.48 3.09 9.44 20.8 45 - - - - - 3V 1.83 3.67 10.4 22.3 47.3 - - - - - 3.6 V 3.58 6.17 13.9 26.6 53 - - - - - 1.8 V 1.28 2.81 9.13 20.8 - - - - - - 2.4 V 1.39 2.93 9.34 21.3 - - - - - - 3V 1.59 3.1 9.64 21.8 - - - - - - 3.6 V 1.86 3.45 10.2 22.8 - - - - - - Unit µA µA STM32L431xx RTC clocked by LSE quartz(2) in low drive mode MAX(1) TYP Symbol Parameter Supply current IDD_ALL during wakeup (wakeup from from Stop 2 Stop2) mode Conditions - MAX(1) TYP VDD 25 °C 55 °C Wakeup clock is MSI = 48 MHz, voltage Range 1. See (3). 3V 1.85 - - - - Wakeup clock is MSI = 4 MHz, voltage Range 2. See (3). 3V 1.52 - - - Wakeup clock is HSI16 = 16 MHz, voltage Range 1. See (3). 3V 1.54 - - - 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C - - - - - - - - - - - - - - - - - Unit STM32L431xx Table 34. Current consumption in Stop 2 mode (continued) mA DS11453 Rev 3 1. Guaranteed based on test during characterization, unless otherwise specified. 2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors. 3. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 41: Low-power mode wakeup timings. Electrical characteristics 101/208 Symbol Parameter IDD_ALL (Stop 1) Supply current in Stop 1 mode, RTC disabled Conditions - - RTC clocked by LSI DS11453 Rev 3 Supply IDD_ALL current in stop RTC clocked by LSE (Stop 1 with 1 mode, bypassed, at 32768 Hz RTC) RTC enabled RTC clocked by LSE quartz(2) in low drive mode Wakeup clock MSI = 48 MHz, voltage Range 1. See (3). Supply Wakeup clock MSI = 4 MHz, IDD_ALL current during voltage Range 2. (wakeup wakeup from from Stop1) See (3). Stop 1 Wakeup clock HSI16 = 16 MHz, voltage Range 1. See (3). MAX(1) TYP VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C 1.8 V 4.34 12.4 43.6 96.4 204 9.3 27.4 98.9 198.7 397.5 2.4 V 4.35 12.5 43.8 97 205 9.4 27.6 99.5 199.0 398.0 3V 4.41 12.6 44.1 97.7 207 9.5 27.8 100.3 200.4 400.8 3.6 V 4.56 12.9 44.8 98.9 210 9.7 28.3 101.7 202.1 404.2 1.8 V 4.63 12.7 43.9 96.8 205 9.9 28.0 99.5 198.9 397.8 2.4 V 4.78 12.8 44.2 97.4 206 10.1 28.3 100.3 199.5 399.0 3V 4.93 13 44.6 98.1 207 10.4 28.7 101.2 200.9 401.9 3.6 V 5.05 13.4 45.3 99.5 210 10.8 29.4 102.8 202.5 405.0 1.8 V 4.7 12.8 44 96.9 205 - - - - - 2.4 V 4.95 13 44.4 97.6 206 - - - - - 3V 5.33 13.6 45.4 99.1 209 - - - - - 3.6 V 6.91 16.1 48.8 103 216 - - - - - 1.8 V 4.76 12.3 43.7 99.1 - - - - - - 2.4 V 4.95 12.4 43.8 99.3 - - - - - - 3V 5.1 12.6 44.1 99.6 - - - - - - 3.6 V 5.65 13 44.8 101 - - - - - - 3V 1.14 - - - - - - - - - 3V 1.22 - - - - - - - - - 3V 1.20 - - - - - - - - - 2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors. 3. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 41: Low-power mode wakeup timings. µA µA mA STM32L431xx 1. Guaranteed based on test during characterization, unless otherwise specified. Unit Electrical characteristics 102/208 Table 35. Current consumption in Stop 1 mode Symbol Parameter IDD_ALL (Stop 0) Supply current in Stop 0 mode, RTC disabled Conditions VDD MAX(1) TYP 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C 1.8 V 108 119 158 221 347 133 158 244 395 704 2.4 V 110 121 160 223 349 136 161 248 399 710 3V 111 123 161 224 352 139 164 251 403 716 3.6 V 114 125 163 227 355 142 167 254 408 722(2) Unit STM32L431xx Table 36. Current consumption in Stop 0 µA 1. Guaranteed by characterization results, unless otherwise specified. 2. Guaranteed by test in production. DS11453 Rev 3 Electrical characteristics 103/208 Symbol IDD_ALL (Standby) Parameter Supply current in Standby mode (backup registers retained), RTC disabled Conditions - no independent watchdog with independent watchdog DS11453 Rev 3 RTC clocked by LSI, no independent watchdog IDD_ALL (Standby with RTC) Supply current in Standby mode (backup registers retained), RTC enabled RTC clocked by LSI, with independent watchdog RTC clocked by LSE bypassed at 32768Hz MAX(1) TYP VDD 25 °C 55 °C 1.8 V 27.7 144 758 2 072 5 425 2.4 V 50.9 187 892 2 408 3V 90.2 253 1 090 3.6 V 253 459 1.8 V 216 - 2.4 V 342 3V 416 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C 119 425 2866 7524 20510 6 247 183 564 3383 8778 23768 2 884 7 409 225 681 3912 10071 26976 1 474 3 575 8 836 292 877 4638 11659 30758 - - - - - - - - - - - - - - - - - - - - - - - - - - 3.6 V 551 - - - - - - - - - 1.8 V 287 407 989 2 230 5 396 585 944 3344 7866 20504 2.4 V 386 526 1 201 2 638 6 274 811 1230 4007 9246 23824 3V 513 679 1 478 3 167 7 414 1022 1521 4683 10671 27124 3.6 V 771 978 1 963 3 992 9 039 1284 1924 5577 12383 1.8 V 342 - - - - - - - - - 2.4 V 521 - - - - - - - - - Unit nA Electrical characteristics 104/208 Table 37. Current consumption in Standby mode 30954 (2) 3V 655 - - - - - - - - - 3.6 V 865 - - - - - - - - - 1.8 V 142 126 865 2 220 5 650 - - - - - 2.4 V 249 219 1 090 2 660 6 600 - - - - - 404 364 1 410 3 260 7 850 - - - - - 742 670 2 000 4 230 9 700 - - - - - 1.8 V 281 423 1 046 2 410 5 700 - - - - - 2.4 V RTC clocked by LSE quartz (3) in low drive mode 3 V 388 548 1 268 2 847 6 564 - - - - - 535 715 1 565 3 420 7 694 - - - - - 3.6 V 836 1 048 2 081 4 311 9 338 - - - - - nA STM32L431xx 3V 3.6 V nA Symbol IDD_ALL (SRAM2)(4) IDD_ALL (wakeup from Standby) Conditions Parameter Supply current to be added in Standby mode when SRAM2 is retained Supply current during wakeup from Standby mode - VDD - Wakeup clock is MSI = 4 MHz. See (5). MAX(1) TYP 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C 1.8 V 173 349 1 009 2 158 4 542 249 527 1604 3402 6908 2.4 V 174 345 1 015 2 163 4 535 271 589 1623 3438 6924 3V 178 350 1 019 2 148 4 419 277 594 1628 3467 6935 3.6 V 184 352 1 033 2 208 4 610 293 611 1631 3480 6948 3V 1.23 - - - - - - - - - Unit STM32L431xx Table 37. Current consumption in Standby mode (continued) nA mA 1. Guaranteed by characterization results, unless otherwise specified. 2. Guaranteed by test in production. 3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors. DS11453 Rev 3 4. The supply current in Standby with SRAM2 mode is: IDD_ALL(Standby) + IDD_ALL(SRAM2). The supply current in Standby with RTC with SRAM2 mode is: IDD_ALL(Standby + RTC) + IDD_ALL(SRAM2). 5. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 41: Low-power mode wakeup timings. Table 38. Current consumption in Shutdown mode Symbol IDD_ALL (Shutdown) Parameter - - MAX(1) TYP VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 1.8 V 7.82 190 386 1 286 3 854 2.4 V 23 229 485 1 517 3V 44.3 290 634 3.6 V 212 397 977 105 °C 125 °C 25.0 255 1721 5052 15543 4 431 34.9 270 2085 5878 17639 1 878 5 310 70.1 345 2454 6755 19984 2 516 6 656 119.1 496 2992 7939 22860 Unit nA 105/208 Electrical characteristics Supply current in Shutdown mode (backup registers retained) RTC disabled Conditions Symbol IDD_ALL (Shutdown with RTC) Parameter Supply current in Shutdown mode (backup registers retained) RTC enabled DS11453 Rev 3 Supply current IDD_ALL during wakeup (wakeup from from Shutdown Shutdown) mode Conditions - RTC clocked by LSE bypassed at 32768 Hz RTC clocked by LSE quartz (2) in low drive mode Wakeup clock is MSI = 4 MHz. See (3). MAX(1) TYP VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C 1.8 V 63 133 522 1 490 4 270 - - - - - 2.4 V 165 253 710 1 830 4 980 - - - - - 3V 316 423 990 2 340 6 050 - - - - - 3.6 V 649 787 1 530 3 220 7 710 - - - - - 1.8 V 203 293 700 1 675 - - - - - - 2.4 V 303 411 880 2 001 - - - - - - 3V 448 567 1 136 2 479 - - - - - - 3.6 V 744 887 1 609 3 256 - - - - - - 3V 0.780 - - - - - - - - - Unit nA Electrical characteristics 106/208 Table 38. Current consumption in Shutdown mode (continued) mA 1. Guaranteed by characterization results, unless otherwise specified. 2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors. 3. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 41: Low-power mode wakeup timings. STM32L431xx Symbol Parameter Conditions - RTC disabled IDD_VBAT (VBAT) RTC enabled and Backup domain clocked by LSE supply current bypassed at 32768 Hz DS11453 Rev 3 RTC enabled and clocked by LSE quartz(2) MAX(1) TYP VBAT 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 5 55 °C 85 °C 30 165 105 °C 125 °C 1.8 V 2 12 66 193 540 482 2.4 V 1 12 73 217 600 6 30 182 542 1500 3V 5 16 92 266 731 12.5 40 230 665 1928 3.6 V 6 30 161 459 1 269 15 75 402 1147 3173 1.8 V 154 175 247 430 - - - - - - 2.4 V 228 246 335 542 - - - - - - 3V 316 340 459 714 - - - - - - 3.6 V 419 462 684 1 140 - - - - - - 1.8 V 256 297 385 558 823 - - - - - 2.4 V 345 381 477 673 906 - - - - - 3V 455 495 603 836 1 085 - - - - - 3.6 V 591 642 824 1 207 1 733 - - - - - Unit 1350 STM32L431xx Table 39. Current consumption in VBAT mode nA 1. Guaranteed by characterization results, unless otherwise specified. 2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors. Electrical characteristics 107/208 Electrical characteristics STM32L431xx I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 60: I/O static characteristics. For the output pins, any external pull-down or external load must also be considered to estimate the current consumption. Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs. Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode. I/O dynamic current consumption In addition to the internal peripheral current consumption measured previously (see Table 40: Peripheral current consumption), the I/Os used by an application also contribute to the current consumption. When an I/O pin switches, it uses the current from the I/O supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: I SW = V DDIOx × f SW × C where ISW is the current sunk by a switching I/O to charge/discharge the capacitive load VDDIOx is the I/O supply voltage fSW is the I/O switching frequency C is the total capacitance seen by the I/O pin: C = CINT+ CEXT + CS CS is the PCB board capacitance including the pad pin. The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. 108/208 DS11453 Rev 3 STM32L431xx Electrical characteristics On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 40. The MCU is placed under the following conditions: • All I/O pins are in Analog mode • The given value is calculated by measuring the difference of the current consumptions: – when the peripheral is clocked on – when the peripheral is clocked off • Ambient operating temperature and supply voltage conditions summarized in Table 19: Voltage characteristics • The power consumption of the digital part of the on-chip peripherals is given in Table 40. The power consumption of the analog part of the peripherals (where applicable) is indicated in each related section of the datasheet. Table 40. Peripheral current consumption Range 1 Range 2 Low-power run and sleep Bus Matrix(1) 3.2 2.9 3.1 ADC independent clock domain 0.4 0.1 0.2 ADC clock domain 2.1 1.9 1.9 CRC 0.4 0.2 0.3 DMA1 1.4 1.3 1.4 DMA2 1.5 1.3 1.4 6.2 5.2 5.8 1.7 1.4 1.6 Peripheral FLASH (2) GPIOA GPIOB(2)) AHB APB1 1.6 1.3 1.6 (2) GPIOC 1.7 1.5 1.6 GPIOD(2) 1.8 1.6 1.7 (2) GPIOE 1.7 1.6 1.6 GPIOH(2) 0.6 0.6 0.5 QSPI 7.0 5.8 7.3 RNG independent clock domain 2.2 N/A N/A RNG clock domain 0.5 N/A N/A SRAM1 0.8 0.9 0.7 SRAM2 1.0 0.8 0.8 TSC 1.6 1.3 1.3 All AHB Peripherals 25.2 21.7 23.6 AHB to APB1 bridge(3) 0.9 0.7 0.9 CAN1 4.1 3.2 3.9 DAC1 2.4 1.8 2.2 DS11453 Rev 3 Unit µA/MHz 109/208 176 Electrical characteristics STM32L431xx Table 40. Peripheral current consumption (continued) Range 1 Range 2 Low-power run and sleep RTCA 1.7 1.1 2.1 CRS 0.3 0.3 0.6 I2C1 independent clock domain 3.5 2.8 3.4 I2C1 clock domain 1.1 0.9 1.0 I2C2 independent clock domain 3.5 3.0 3.4 I2C2 clock domain 1.1 0.7 0.9 I2C3 independent clock domain 2.9 2.3 2.5 I2C3 clock domain 0.9 0.4 0.8 LPUART1 independent clock domain 1.9 1.6 1.8 LPUART1 clock domain 0.6 0.6 0.6 LPTIM1 independent clock domain 2.9 2.4 2.8 LPTIM1 clock domain 0.8 0.4 0.7 LPTIM2 independent clock domain 3.1 2.7 3.9 LPTIM2 clock domain 0.8 0.7 0.8 OPAMP 0.4 0.2 0.4 PWR 0.4 0.1 0.4 SPI2 1.8 1.6 1.6 SPI3 1.7 1.3 1.6 SWPMI1 independent clock domain 1.9 1.6 1.9 SWPMI1 clock domain 0.9 0.7 0.8 TIM2 6.2 5.0 5.9 TIM6 1.0 0.6 0.9 TIM7 1.0 0.6 0.6 USART2 independent clock domain 4.1 3.6 3.8 USART2 clock domain 1.3 0.9 1.1 USART3 independent clock domain 4.3 3.5 4.2 USART3 clock domain 1.5 1.1 1.3 WWDG 0.5 0.5 0.5 45.4 35 47.8 1.0 0.9 0.9 Peripheral APB1 All APB1 on APB2 110/208 (4) AHB to APB2 DS11453 Rev 3 Unit µA/MHz STM32L431xx Electrical characteristics Table 40. Peripheral current consumption (continued) Range 1 Range 2 Low-power run and sleep FW 0.2 0.2 0.2 SAI1 independent clock domain 2.3 1.8 1.9 SAI1 clock domain 2.1 1.8 2.0 SDMMC1 independent clock domain 4.7 3.9 3.9 SDMMC1 clock domain 2.5 1.9 1.9 SPI1 1.8 1.6 1.7 SYSCFG/VREFBUF/COMP 0.6 0.5 0.6 TIM1 8.1 6.5 7.6 TIM15 3.7 3.0 3.4 TIM16 2.7 2.1 2.6 USART1 independent clock domain 4.8 4.2 4.6 USART1 clock domain 1.5 1.3 1.7 All APB2 on 24.2 19.9 22.6 94.8 76.5 94.0 Peripheral APB2 ALL Unit µA/MHz 1. The BusMatrix is automatically active when at least one master is ON (CPU, DMA). 2. The GPIOx (x= A…H) dynamic current consumption is approximately divided by a factor two versus this table values when the GPIO port is locked thanks to LCKK and LCKy bits in the GPIOx_LCKR register. In order to save the full GPIOx current consumption, the GPIOx clock should be disabled in the RCC when all port I/Os are used in alternate function or analog mode (clock is only required to read or write into GPIO registers, and is not used in AF or analog modes). 3. The AHB to APB1 Bridge is automatically active when at least one peripheral is ON on the APB1. 4. The AHB to APB2 Bridge is automatically active when at least one peripheral is ON on the APB2. 6.3.6 Wakeup time from low-power modes and voltage scaling transition times The wakeup times given in Table 41 are the latency between the event and the execution of the first user instruction. The device goes in low-power mode after the WFE (Wait For Event) instruction. Table 41. Low-power mode wakeup timings(1) Symbol tWUSLEEP Parameter Conditions Typ Max - 6 6 Wakeup time from Sleep mode to Run mode Wakeup time from LowtWULPSLEEP power sleep mode to Lowpower run mode Wakeup in Flash with Flash in power-down during low-power sleep mode (SLEEP_PD=1 in FLASH_ACR) and with clock MSI = 2 MHz DS11453 Rev 3 6 8.3 Unit Nb of CPU cycles 111/208 176 Electrical characteristics STM32L431xx Table 41. Low-power mode wakeup timings(1) (continued) Symbol Parameter Conditions Range 1 Wake up time from Stop 0 mode to Run mode in Flash Range 2 tWUSTOP0 Range 1 Wake up time from Stop 0 mode to Run mode in SRAM1 Range 2 Range 1 Wake up time from Stop 1 mode to Run in Flash Range 2 Range 1 tWUSTOP1 Wake up time from Stop 1 mode to Run mode in SRAM1 Wake up time from Stop 1 mode to Low-power run mode in Flash Wake up time from Stop 1 mode to Low-power run mode in SRAM1 112/208 Range 2 Regulator in low-power mode (LPR=1 in PWR_CR1) Typ Max Wakeup clock MSI = 48 MHz 3.8 5.7 Wakeup clock HSI16 = 16 MHz 4.1 6.9 Wakeup clock MSI = 24 MHz 4.07 6.2 Wakeup clock HSI16 = 16 MHz 4.1 6.8 Wakeup clock MSI = 4 MHz 8.45 11.8 Wakeup clock MSI = 48 MHz 1.5 2.9 Wakeup clock HSI16 = 16 MHz 2.4 2.76 Wakeup clock MSI = 24 MHz 2.4 3.48 Wakeup clock HSI16 = 16 MHz 2.4 2.76 Wakeup clock MSI = 4 MHz 8.16 10.94 Wakeup clock MSI = 48 MHz 6.34 7.86 Wakeup clock HSI16 = 16 MHz 6.84 8.23 Wakeup clock MSI = 24 MHz 6.74 8.1 Wakeup clock HSI16 = 16 MHz 6.89 8.21 Wakeup clock MSI = 4 MHz 10.47 12.1 Wakeup clock MSI = 48 MHz 4.7 5.97 Wakeup clock HSI16 = 16 MHz 5.9 6.92 Wakeup clock MSI = 24 MHz 5.4 6.51 Wakeup clock HSI16 = 16 MHz 5.9 6.92 Wakeup clock MSI = 4 MHz 11.1 12.2 16.4 17.73 Wakeup clock MSI = 2 MHz DS11453 Rev 3 17.3 18.82 Unit µs µs STM32L431xx Electrical characteristics Table 41. Low-power mode wakeup timings(1) (continued) Symbol Parameter Conditions Typ Max Wakeup clock MSI = 48 MHz 8.02 9.24 Wakeup clock HSI16 = 16 MHz 7.66 8.95 Wakeup clock MSI = 24 MHz 8.5 9.54 Wakeup clock HSI16 = 16 MHz 7.75 8.95 Wakeup clock MSI = 4 MHz 12.06 13.16 Wakeup clock MSI = 48 MHz 5.45 6.79 Wakeup clock HSI16 = 16 MHz 6.9 7.98 Wakeup clock MSI = 24 MHz 6.3 7.36 Wakeup clock HSI16 = 16 MHz 6.9 7.9 Wakeup clock MSI = 4 MHz 13.1 13.31 Wakeup time from Standby Range 1 mode to Run mode Wakeup clock MSI = 8 MHz 12.2 18.35 Wakeup clock MSI = 4 MHz 19.14 25.8 Wakeup time from Standby Range 1 with SRAM2 to Run mode Wakeup clock MSI = 8 MHz 12.1 Wakeup clock MSI = 4 MHz 19.2 25.87 Wakeup clock MSI = 4 MHz 261.5 315.7 Range 1 Wake up time from Stop 2 mode to Run mode in Flash Range 2 tWUSTOP2 Range 1 Wake up time from Stop 2 mode to Run mode in SRAM1 tWUSTBY tWUSTBY SRAM2 tWUSHDN Wakeup time from Shutdown mode to Run mode Range 2 Range 1 18.3 Unit µs µs µs µs 1. Guaranteed by characterization results. Table 42. Regulator modes transition times(1) Symbol tWULPRUN tVOST Parameter Conditions Typ Max Wakeup time from Low-power run mode to Code run with MSI 2 MHz Run mode(2) 5 7 Regulator transition time from Range 2 to Range 1 or Range 1 to Range 2(3) 20 40 Typ Max Stop 0 mode - 1.7 Stop 1 mode and Stop 2 mode - 8.5 Code run with MSI 24 MHz Unit µs 1. Guaranteed by characterization results. 2. Time until REGLPF flag is cleared in PWR_SR2. 3. Time until VOSF flag is cleared in PWR_SR2. Table 43. Wakeup time using USART/LPUART(1) Symbol tWUUSART tWULPUART Parameter Conditions Wakeup time needed to calculate the maximum USART/LPUART baudrate allowing to wakeup up from stop mode when USART/LPUART clock source is HSI16 Unit µs 1. Guaranteed by design. DS11453 Rev 3 113/208 176 Electrical characteristics 6.3.7 STM32L431xx External clock source characteristics High-speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 6.3.14. However, the recommended clock input waveform is shown in Figure 21: High-speed external clock source AC timing diagram. Table 44. High-speed external user clock characteristics(1) Symbol fHSE_ext Parameter User external clock source frequency Conditions Min Typ Max Voltage scaling Range 1 - 8 48 Voltage scaling Range 2 - 8 26 Unit MHz VHSEH OSC_IN input pin high level voltage - 0.7 VDDIOx - VDDIOx VHSEL OSC_IN input pin low level voltage - VSS - 0.3 VDDIOx Voltage scaling Range 1 7 - - Voltage scaling Range 2 18 tw(HSEH) OSC_IN high or low time tw(HSEL) V ns - - 1. Guaranteed by design. Figure 21. High-speed external clock source AC timing diagram tw(HSEH) VHSEH 90% VHSEL 10% tr(HSE) tf(HSE) tw(HSEL) t THSE MS19214V2 114/208 DS11453 Rev 3 STM32L431xx Electrical characteristics Low-speed external user clock generated from an external source In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 6.3.14. However, the recommended clock input waveform is shown in Figure 22. Table 45. Low-speed external user clock characteristics(1) Symbol Parameter Conditions Min Typ Max Unit kHz fLSE_ext User external clock source frequency - - 32.768 1000 VLSEH OSC32_IN input pin high level voltage - 0.7 VDDIOx - VDDIOx VLSEL OSC32_IN input pin low level voltage - VSS - 0.3 VDDIOx - 250 - - tw(LSEH) OSC32_IN high or low time tw(LSEL) V ns 1. Guaranteed by design. Figure 22. Low-speed external clock source AC timing diagram tw(LSEH) VLSEH 90% VLSEL 10% tr(LSE) tf(LSE) t tw(LSEL) TLSE MS19215V2 DS11453 Rev 3 115/208 176 Electrical characteristics STM32L431xx High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 46. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 46. HSE oscillator characteristics(1) Symbol fOSC_IN RF Conditions(2) Min Typ Max Unit Oscillator frequency - 4 8 48 MHz Feedback resistor - - 200 - kΩ - - 5.5 VDD = 3 V, Rm = 30 Ω, CL = 10 pF@8 MHz - 0.44 - VDD = 3 V, Rm = 45 Ω, CL = 10 pF@8 MHz - 0.45 - VDD = 3 V, Rm = 30 Ω, CL = 5 pF@48 MHz - 0.68 - VDD = 3 V, Rm = 30 Ω, CL = 10 pF@48 MHz - 0.94 - VDD = 3 V, Rm = 30 Ω, CL = 20 pF@48 MHz - 1.77 - Startup - - 1.5 mA/V VDD is stabilized - 2 - ms Parameter During startup IDD(HSE) Gm HSE current consumption Maximum critical crystal transconductance tSU(HSE)(4) Startup time (3) mA 1. Guaranteed by design. 2. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time 4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 23). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. 116/208 DS11453 Rev 3 STM32L431xx Note: Electrical characteristics For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Figure 23. Typical application with an 8 MHz crystal Resonator with integrated capacitors CL1 OSC_IN 8 MHz resonator CL2 REXT (1) fHSE RF Bias controlled gain OSC_OUT MS19876V1 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 47. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 47. LSE oscillator characteristics (fLSE = 32.768 kHz)(1) Symbol IDD(LSE) Parameter LSE current consumption Maximum critical crystal Gmcritmax gm tSU(LSE)(3) Startup time Conditions(2) Min Typ Max LSEDRV[1:0] = 00 Low drive capability - 250 - LSEDRV[1:0] = 01 Medium low drive capability - 315 - LSEDRV[1:0] = 10 Medium high drive capability - 500 - LSEDRV[1:0] = 11 High drive capability - 630 - LSEDRV[1:0] = 00 Low drive capability - - 0.5 LSEDRV[1:0] = 01 Medium low drive capability - - 0.75 LSEDRV[1:0] = 10 Medium high drive capability - - 1.7 LSEDRV[1:0] = 11 High drive capability - - 2.7 VDD is stabilized - 2 - DS11453 Rev 3 Unit nA µA/V s 117/208 176 Electrical characteristics STM32L431xx 1. Guaranteed by design. 2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for ST microcontrollers”. 3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Figure 24. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors CL1 OSC32_IN fLSE Drive programmable amplifier 32.768 kHz resonator OSC32_OUT CL2 MS30253V2 Note: 118/208 An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one. DS11453 Rev 3 STM32L431xx 6.3.8 Electrical characteristics Internal clock source characteristics The parameters given in Table 48 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 22: General operating conditions. The provided curves are characterization results, not tested in production. High-speed internal (HSI16) RC oscillator Table 48. HSI16 oscillator characteristics(1) Symbol fHSI16 TRIM Parameter HSI16 Frequency HSI16 user trimming step DuCy(HSI16)(2) Duty Cycle Conditions Min Typ Max Unit 15.88 - 16.08 MHz Trimming code is not a multiple of 64 0.2 0.3 0.4 Trimming code is a multiple of 64 -4 -6 -8 45 - 55 % -1 - 1 % -2 - 1.5 % -0.1 - 0.05 % VDD=3.0 V, TA=30 °C - % ∆Temp(HSI16) HSI16 oscillator frequency TA= 0 to 85 °C drift over temperature TA= -40 to 125 °C ∆VDD(HSI16) HSI16 oscillator frequency VDD=1.62 V to 3.6 V drift over VDD tsu(HSI16)(2) HSI16 oscillator start-up time - - 0.8 1.2 μs tstab(HSI16)(2) HSI16 oscillator stabilization time - - 3 5 μs IDD(HSI16)(2) HSI16 oscillator power consumption - - 155 190 μA 1. Guaranteed by characterization results. 2. Guaranteed by design. DS11453 Rev 3 119/208 176 Electrical characteristics STM32L431xx Figure 25. HSI16 frequency versus temperature MHz 16.4 +2% 16.3 +1.5% 16.2 +1% 16.1 16 15.9 -1% 15.8 -1.5% 15.7 -2% 15.6 -40 -20 0 20 min 40 mean 60 80 100 120 °C max MSv39299V1 120/208 DS11453 Rev 3 STM32L431xx Electrical characteristics Multi-speed internal (MSI) RC oscillator Table 49. MSI oscillator characteristics(1) Symbol Parameter Conditions Min Typ Max Range 0 98.7 100 101.3 Range 1 197.4 200 202.6 Range 2 394.8 400 405.2 Range 3 789.6 800 810.4 Range 4 0.987 1 1.013 Range 5 1.974 2 2.026 Range 6 3.948 4 4.052 Range 7 7.896 8 8.104 Range 8 15.79 16 16.21 Range 9 23.69 24 24.31 Range 10 31.58 32 32.42 Range 11 47.38 48 48.62 Range 0 - 98.304 - Range 1 - 196.608 - Range 2 - 393.216 - Range 3 - 786.432 - Range 4 - 1.016 - PLL mode Range 5 XTAL= 32.768 kHz Range 6 - 1.999 - - 3.998 - Range 7 - 7.995 - Range 8 - 15.991 - Range 9 - 23.986 - Range 10 - 32.014 - Range 11 - 48.005 - -3.5 - 3 -8 - 6 MSI mode fMSI ∆TEMP(MSI)(2) MSI frequency after factory calibration, done at VDD=3 V and TA=30 °C MSI oscillator frequency drift over temperature MSI mode TA= -0 to 85 °C TA= -40 to 125 °C DS11453 Rev 3 Unit kHz MHz kHz MHz % 121/208 176 Electrical characteristics STM32L431xx Table 49. MSI oscillator characteristics(1) (continued) Symbol Parameter Conditions Min Typ VDD=1.62 V to 3.6 V -1.2 - VDD=2.4 V to 3.6 V -0.5 - VDD=1.62 V to 3.6 V -2.5 - VDD=2.4 V to 3.6 V -0.8 - VDD=1.62 V to 3.6 V -5 - VDD=2.4 V to 3.6 V -1.6 - TA= -40 to 85 °C - 1 2 TA= -40 to 125 °C - 2 4 Range 0 to 3 ∆VDD(MSI) (2) MSI oscillator frequency drift MSI mode over VDD (reference is 3 V) Range 4 to 7 Range 8 to 11 ∆FSAMPLING (MSI)(2)(4) CC jitter(MSI)(4) P jitter(MSI)(4) tSU(MSI)(4) tSTAB(MSI)(4) 122/208 Frequency variation in MSI mode sampling mode(3) Max Unit 0.5 0.7 % 1 % RMS cycle-tocycle jitter PLL mode Range 11 - - 60 - ps RMS Period jitter PLL mode Range 11 - - 50 - ps Range 0 - - 10 20 Range 1 - - 5 10 Range 2 - - 4 8 Range 3 - - 3 7 Range 4 to 7 - - 3 6 Range 8 to 11 - - 2.5 6 10 % of final frequency - - 0.25 0.5 5 % of final frequency - - 0.5 1.25 1 % of final frequency - - - 2.5 MSI oscillator start-up time MSI oscillator stabilization time PLL mode Range 11 DS11453 Rev 3 us ms STM32L431xx Electrical characteristics Table 49. MSI oscillator characteristics(1) (continued) Symbol IDD(MSI)(4) Parameter MSI oscillator power consumption Conditions MSI and PLL mode Min Typ Max Range 0 - - 0.6 1 Range 1 - - 0.8 1.2 Range 2 - - 1.2 1.7 Range 3 - - 1.9 2.5 Range 4 - - 4.7 6 Range 5 - - 6.5 9 Range 6 - - 11 15 Range 7 - - 18.5 25 Range 8 - - 62 80 Range 9 - - 85 110 Range 10 - - 110 130 Range 11 - - 155 190 Unit µA 1. Guaranteed by characterization results. 2. This is a deviation for an individual part once the initial frequency has been measured. 3. Sampling mode means Low-power run/Low-power sleep modes with Temperature sensor disable. 4. Guaranteed by design. Figure 26. Typical current consumption versus MSI frequency DS11453 Rev 3 123/208 176 Electrical characteristics STM32L431xx High-speed internal 48 MHz (HSI48) RC oscillator Table 50. HSI48 oscillator characteristics(1) Symbol fHSI48 TRIM USER TRIM COVERAGE Parameter Conditions HSI48 Frequency VDD=3.0V, TA=30°C HSI48 user trimming step - HSI48 user trimming coverage ±32 steps DuCy(HSI48) Duty Cycle - DVDD(HSI48) HSI48 oscillator frequency drift with VDD Typ Max Unit - 48 - MHz - 0.11 (2) 0.18 (2) % ±3(3) ±3.5(3) - % 45(2) - 55(2) % - - ±3(3) VDD = 3.0 V to 3.6 V, TA = –15 to 85 °C Accuracy of the HSI48 oscillator ACCHSI48_REL over temperature (factory calibrated) Min % VDD = 1.65 V to 3.6 V, TA = –40 to 125 °C - - VDD = 3 V to 3.6 V - 0.025(3) 0.05(3) VDD = 1.65 V to 3.6 V - 0.05(3) 0.1(3) (3) ±4.5 % tsu(HSI48) HSI48 oscillator start-up time - - 2.5(2) 6(2) μs IDD(HSI48) HSI48 oscillator power consumption - - 340(2) 380(2) μA NT jitter Next transition jitter Accumulated jitter on 28 cycles(4) - - +/-0.15(2) - ns PT jitter Paired transition jitter Accumulated jitter on 56 cycles(4) - - +/-0.25(2) - ns 1. VDD = 3 V, TA = –40 to 125°C unless otherwise specified. 2. Guaranteed by design. 3. Guaranteed by characterization results. 4. Jitter measurement are performed without clock source activated in parallel. 124/208 DS11453 Rev 3 STM32L431xx Electrical characteristics Figure 27. HSI48 frequency versus temperature % 6 4 2 0 -2 -4 -6 -50 -30 -10 10 Avg 30 50 70 90 min 110 130 °C max MSv40989V1 Low-speed internal (LSI) RC oscillator Table 51. LSI oscillator characteristics(1) Symbol Parameter LSI Frequency fLSI Min Typ Max VDD = 3.0 V, TA = 30 °C 31.04 - 32.96 VDD = 1.62 to 3.6 V, TA = -40 to 125 °C 29.5 - 34 - - 80 130 μs 5% of final frequency - 125 180 μs - - 110 180 nA LSI oscillator startup time tSU(LSI)(2) tSTAB(LSI)(2) IDD(LSI)(2) Conditions LSI oscillator stabilization time LSI oscillator power consumption Unit kHz 1. Guaranteed by characterization results. 2. Guaranteed by design. 6.3.9 PLL characteristics The parameters given in Table 52 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 22: General operating conditions. Table 52. PLL, PLLSAI1 characteristics(1) Symbol fPLL_IN Parameter Conditions Min Typ Max Unit PLL input clock(2) - 4 - 16 MHz PLL input clock duty cycle - 45 - 55 % DS11453 Rev 3 125/208 176 Electrical characteristics STM32L431xx Table 52. PLL, PLLSAI1 characteristics(1) (continued) Symbol Parameter fPLL_P_OUT PLL multiplier output clock P fPLL_Q_OUT PLL multiplier output clock Q fPLL_R_OUT PLL multiplier output clock R fVCO_OUT tLOCK Jitter IDD(PLL) PLL VCO output Conditions Min Typ Max Voltage scaling Range 1 3.0968 - 80 Voltage scaling Range 2 3.0968 - 26 Voltage scaling Range 1 12 - 80 Voltage scaling Range 2 12 - 26 Voltage scaling Range 1 12 - 80 Voltage scaling Range 2 12 - 26 Voltage scaling Range 1 96 - 344 Voltage scaling Range 2 96 - 128 - 15 40 - 40 - - 30 - VCO freq = 96 MHz - 200 260 VCO freq = 192 MHz - 300 380 VCO freq = 344 MHz - 520 650 PLL lock time RMS cycle-to-cycle jitter RMS period jitter PLL power consumption on VDD(1) System clock 80 MHz Unit MHz MHz MHz MHz μs ±ps 1. Guaranteed by design. 2. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared between the 2 PLLs. 126/208 DS11453 Rev 3 μA STM32L431xx 6.3.10 Electrical characteristics Flash memory characteristics Table 53. Flash memory characteristics(1) Symbol Parameter Conditions Typ Max Unit tprog 64-bit programming time - 81.69 90.76 µs tprog_row one row (32 double word) programming time normal programming 2.61 2.90 fast programming 1.91 2.12 tprog_page one page (2 Kbyte) programming time normal programming 20.91 23.24 fast programming 15.29 16.98 22.02 24.47 normal programming 5.35 5.95 fast programming 3.91 4.35 22.13 24.59 Write mode 3.4 - Erase mode 3.4 - Write mode 7 (for 2 μs) - Erase mode 7 (for 41 μs) - tERASE tprog_bank tME IDD Page (2 KB) erase time one bank (512 Kbyte) programming time - Mass erase time (one or two banks) - Average consumption from VDD Maximum current (peak) ms s ms mA 1. Guaranteed by design. Table 54. Flash memory endurance and data retention Symbol NEND tRET Min(1) Unit TA = –40 to +105 °C 10 kcycles 1 kcycle(2) at TA = 85 °C 30 Parameter Endurance Data retention Conditions 1 kcycle (2) 1 kcycle (2) at TA = 105 °C 15 at TA = 125 °C 7 (2) at TA = 55 °C 30 10 kcycles(2) at TA = 85 °C 15 10 kcycles 10 kcycles (2) at TA = 105 °C Years 10 1. Guaranteed by characterization results. 2. Cycling performed over the whole temperature range. DS11453 Rev 3 127/208 176 Electrical characteristics 6.3.11 STM32L431xx EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: • Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. • FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 55. They are based on the EMS levels and classes defined in application note AN1709. Table 55. EMS characteristics Conditions Level/ Class Symbol Parameter VFESD Voltage limits to be applied on any I/O pin to induce a functional disturbance VDD = 3.3 V, TA = +25 °C, fHCLK = 80 MHz, conforming to IEC 61000-4-2 3B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 3.3 V, TA = +25 °C, fHCLK = 80 MHz, conforming to IEC 61000-4-4 5A Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: 128/208 • Corrupted program counter • Unexpected reset • Critical Data corruption (control registers...) DS11453 Rev 3 STM32L431xx Electrical characteristics Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading. Table 56. EMI characteristics Symbol Parameter Max vs. [fHSE/fHCLK] Monitored frequency band Conditions Unit 8 MHz/ 80 MHz SEMI Peak level 0.1 MHz to 30 MHz -8 VDD = 3.6 V, TA = 25 °C, 30 MHz to 130 MHz LQFP100 package 130 MHz to 1 GHz compliant with IEC 61967-2 1 GHz to 2 GHz 2 8 EMI Level 6.3.12 dBµV 5 2.5 - Electrical sensitivity characteristics Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the ANSI/JEDEC standard. Table 57. ESD absolute maximum ratings Symbol VESD(HBM) Ratings Conditions TA = +25 °C, conforming Electrostatic discharge to ANSI/ESDA/JEDEC voltage (human body model) JS-001 Electrostatic discharge VESD(CDM) voltage (charge device model) TA = +25 °C, conforming to ANSI/ESD STM5.3.1 Class Maximum value(1) 2 2000 Unit V C3 250 1. Guaranteed by characterization results. DS11453 Rev 3 129/208 176 Electrical characteristics STM32L431xx Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: • A supply overvoltage is applied to each power supply pin. • A current injection is applied to each input, output and configurable I/O pin. These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 58. Electrical sensitivities Symbol LU 6.3.13 Parameter Static latch-up class Conditions Class TA = +105 °C conforming to JESD78A II I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDDIOx (for standard, 3.3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibility to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of the -5 µA/+0 µA range) or other functional failure (for example reset occurrence or oscillator frequency deviation). The characterization results are given in Table 59. Negative induced leakage current is caused by negative injection and positive induced leakage current is caused by positive injection. Table 59. I/O current injection susceptibility(1) Functional susceptibility Symbol IINJ Description Positive injection Injected current on all pins except PA4, PA5, PE8, PE9, PE10, PE11, PE12 -5 N/A(2) Injected current on PE8, PE9, PE10, PE11, PE12 -0 N/A(2) Injected current on PA4, PA5 pins -5 0 1. Guaranteed by characterization results. 2. Injection is not possible. 130/208 Unit Negative injection DS11453 Rev 3 mA STM32L431xx 6.3.14 Electrical characteristics I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 60 are derived from tests performed under the conditions summarized in Table 22: General operating conditions. All I/Os are designed as CMOS- and TTL-compliant. Table 60. I/O static characteristics Symbol VIL(1) VIH(1) Vhys(3) Parameter Conditions Min Typ Max Unit I/O input low level voltage 1.62 V