STM32L4P5xx
Ultra-low-power Arm®Cortex®-M4 32-bit MCU+FPU, 150 DMIPS,
up to 1-MB Flash memory, 320-KB SRAM, LCD-TFT, ext. SMPS
Datasheet - production data
Features
Includes ST state-of-the-art patented
technology
Ultra-low-power with FlexPowerControl
• 1.71 V to 3.6 V power supply
LQFP48 (7 x 7 mm)
LQFP64 (10 x 10 mm)
LQFP100 (14 x 14 mm)
LQFP144 (20 x 20 mm)
UFQFPN48
(7 x 7 mm)
UFBGA132 (7 x 7 mm)
UFBGA169 (7 x 7 mm) WLCSP100
(pitch 0.4 mm)
• -40 °C to 85/125 °C temperature range
• Batch acquisition mode (BAM)
• 150 nA in VBAT mode: supply for RTC and
32x32-bit backup registers
• 2 x Octo-SPI memory interfaces
• 22 nA Shutdown mode (5 wakeup pins)
General-purpose inputs/outputs
• 42 nA Standby mode (5 wakeup pins)
• Up to 136 fast I/Os, most 5 V-tolerant, up to 14
I/Os with independent supply down to 1.08 V
• 190 nA Standby mode with RTC
• 2.95 μA Stop 2 with RTC
Performance benchmark
• 110 μA/MHz Run mode (LDO mode)
• 1.25 DMIPS/MHz (Drystone 2.1)
• 41 μA/MHz Run mode (@ 3.3 V SMPS mode)
• 409.20 CoreMark® (3.41 CoreMark/MHz @120
MHz)
• 5 µs wakeup from Stop mode
• Brownout reset (BOR) in all modes except
Shutdown
Core
Energy benchmark
• 285 ULPMark™CP score
• Arm® 32-bit Cortex®-M4 CPU with FPU,
adaptive real-time accelerator (ART
Accelerator) allowing 0-wait-state execution
from Flash memory, frequency up to 120 MHz,
MPU, 150 DMIPS/1.25 DMIPS/MHz
(Dhrystone 2.1), and DSP instructions
Up to 24 capacitive sensing channels
Memories
• 32 kHz crystal oscillator for RTC (LSE)
• 1-Mbyte Flash memory, 2 banks read-whilewrite, proprietary code readout protection
• Internal 16 MHz factory-trimmed RC (±1%)
• 320 Kbytes of SRAM including 64 Kbytes with
hardware parity check
• Internal multispeed 100 kHz to 48 MHz
oscillator, auto-trimmed by LSE (better than
±0.25 % accuracy)
• External memory interface for static memories
supporting SRAM, PSRAM, NOR, NAND and
FRAM memories
March 2021
This is information on a product in full production.
• Support touchkey, linear and rotary touch
sensors
Clock management
• 4 to 48 MHz crystal oscillator
• Internal low-power 32 kHz RC (±5%)
• Internal 48 MHz with clock recovery
• 3 PLLs for system clock, USB, audio, ADC
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STM32L4P5xx
Interconnect matrix
Advanced graphics features
• 1 AHB bus matrix
• Chrom-ART Accelerator (DMA2D) for
enhanced graphic content creation
14-channel DMA controller
• LCD-TFT controller
23 communication peripherals
16x timers and watchdog
• USB OTG 2.0 full-speed, LPM and BCD
• 2 x 16-bit advanced motor-control
• 2x SAIs (serial audio interface)
• 2 x 32-bit general purpose timers
• 4x I2C FM+(1 Mbit/s), SMBus/PMBus
• 6x USARTs (ISO 7816, LIN, IrDA, modem)
• 3x SPIs (5x SPIs with the dual Octo-SPI)
• 5 x 16-bit general purpose timers
• 2x 16-bit basic timers
• 2x low-power 16-bit timers (available in Stop
mode)
• CAN (2.0B Active) and 2x SDMMC
• 8- to 14-bit camera interface up to 32 MHz
(black and white) or 10 MHz (color)
• 2x watchdogs
• 8-/16-bit parallel synchronous data
input/output slave interface (PSSI)
• RTC with hardware calendar, alarms and
calibration
• 1x SysTick timer
11 analog peripherals (independent
supply)
True random generator
• 2x 12-bit ADC 5 Msps, up to 16-bit with
hardware oversampling, 200 µA/Msps
CRC calculation unit
• 2x 12-bit DAC, low-power sample and hold
HASH (SHA-256) hardware accelerator
• 2x operational amplifiers with built-in PGA
Debug mode
• 2x ultra-low-power comparators
• Serial wire debug (SWD)
• 2x digital filters for sigma delta modulator
• JTAG
• 1x temperature sensor
• Embedded Trace Macrocell™ (ETM)
96-bit unique ID
Table 1. Device summary
Reference
STM32L4P5xx
2/311
Part numbers
STM32L4P5AE, STM32L4P5AG, STM32L4P5CE, STM32L4P5CG, STM32L4P5QE,
STM32L4P5QG, STM32L4P5RE, STM32L4P5RG, STM32L4P5VE, STM32L4P5VG,
STM32L4P5ZE, STM32L4P5ZG
DS12903 Rev 3
STM32L4P5xx
Contents
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1
Arm® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2
Adaptive real-time memory accelerator (ART Accelerator) . . . . . . . . . . . 19
3.3
Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4.1
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4.2
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.6
Firewall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.7
Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.7.1
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.7.2
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.7.3
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.7.4
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.7.5
Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.7.6
VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.8
Peripheral and interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.9
Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.10
Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.11
General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.12
Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.13
Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.14
DMA request router (DMAMux) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.15
Chrom-ART Accelerator (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.16
Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.17
3.16.1
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 43
3.16.2
Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 44
Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 44
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STM32L4P5xx
3.18
Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . 44
3.19
Octo-SPI interface (OCTOSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.20
Octo-SPI IO manager (OCTOSPIIOM) . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.21
Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.21.1
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.21.2
Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.21.3
VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.22
Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.23
Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.24
Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.25
Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.26
Digital filter for sigma-delta modulators (DFSDM) . . . . . . . . . . . . . . . . . . 50
3.27
Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.28
LCD-TFT controller (LTDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.29
Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.30
Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.31
Parallel synchronous slave interface (PSSI) . . . . . . . . . . . . . . . . . . . . . . 53
3.32
HASH hardware accelerator (HASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.33
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.33.1
Advanced-control timer (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.33.2
General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16,
TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.33.3
Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.33.4
Low-power timer (LPTIM1 and LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . . 55
3.33.5
Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.33.6
Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.33.7
SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.34
Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 57
3.35
Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.36
Universal synchronous/asynchronous receiver transmitter (USART) . . . 59
3.37
Low-power universal asynchronous receiver transmitter (LPUART) . . . . 60
3.38
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.39
Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.40
Secure digital input/output and MultiMediaCards Interface (SDMMC) . . . 61
3.41
Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
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Contents
3.42
Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 63
3.43
Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.43.1
Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.43.2
Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
6
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
6.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
6.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
6.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
6.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
6.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
6.1.6
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
6.1.7
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 136
6.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
6.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
6.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
6.3.2
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 140
6.3.3
Embedded reset and power control block characteristics . . . . . . . . . . 140
6.3.4
Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
6.3.5
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
6.3.6
Wakeup time from low-power modes and voltage scaling
transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
6.3.7
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 184
6.3.8
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 189
6.3.9
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
6.3.10
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
6.3.11
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
6.3.12
Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
6.3.13
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
6.3.14
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
6.3.15
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
6.3.16
Extended interrupt and event controller input (EXTI) characteristics . . 208
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6.3.17
Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
6.3.18
Analog-to-digital converter characteristics . . . . . . . . . . . . . . . . . . . . . . 209
6.3.19
Digital-to-Analog converter characteristics . . . . . . . . . . . . . . . . . . . . . 222
6.3.20
Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 227
6.3.21
Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
6.3.22
Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 230
6.3.23
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
6.3.24
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
6.3.25
DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
6.3.26
Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
6.3.27
Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 239
6.3.28
FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
6.3.29
OCTOSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
6.3.30
Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 269
6.3.31
Parallel slave interface (PSSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
6.3.32
LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 274
6.3.33
SD/SDIO/MMC card host interfaces (SDMMC) . . . . . . . . . . . . . . . . . . 275
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
7.1
LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
7.2
UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
7.3
LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
7.4
LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
7.5
WLCSP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
7.6
UFBGA132 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
7.7
LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
7.8
UFBGA169 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
7.9
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
8
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
STM32L4P5xx features and peripheral counts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Access status versus readout protection level and execution modes. . . . . . . . . . . . . . . . . 21
STM32L4P5xx modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Functionalities depending on the working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
STM32L4P5xx peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
USART/UART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
SAI implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
STM32L4P5xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Alternate function AF0 to AF7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Alternate function AF8 to AF15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 140
Embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Current consumption in Run and Low-power run modes, code with data processing
running from Flash in single Bank, ART enable (Cache ON Prefetch OFF). . . . . . . . . . . 145
Current consumption in Run and Low-power run modes, code with data processing
running from Flash in single Bank, ART enable (Cache ON Prefetch OFF)
and power supplied by external SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Current consumption in Run and Low-power run modes, code with data
processing running from Flash in dual bank, ART enable (Cache ON Prefetch OFF) . . . 147
Consumption in Run and Low-power run modes, code with data processing
running from Flash in dual bank, ART enable (Cache ON Prefetch OFF)
and power supplied by external SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Current consumption in Run and Low-power run modes,
code with data processing running from Flash in single bank, ART disable. . . . . . . . . . . 149
Current consumption in Run and Low-power run modes, code with data processing
running from Flash in single bank, ART disable and power supplied by external SMPS . 150
Current consumption in Run and Low-power run modes,
code with data processing running from Flash in dual bank, ART disable . . . . . . . . . . . . 151
Current consumption in Run and Low-power run modes, code with data processing
running from Flash in dual bank, ART disable and power supplied by external SMPS . . 152
Current consumption in Run and Low-power run modes,
code with data processing running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Current consumption in Run and Low-power run modes, code with data processing
running from SRAM1 and power supplied by external SMPS . . . . . . . . . . . . . . . . . . . . . 154
Typical current consumption in Run and Low-power run modes, with different codes
running from Flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . 155
DS12903 Rev 3
7/311
10
List of tables
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
8/311
STM32L4P5xx
Typical current consumption in Run and Low-power run modes, with
different codes running from Flash, ART enable (Cache ON Prefetch OFF)
and power supplied by external SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Typical current consumption in Run and Low-power run modes,
with different codes running from Flash, ART disable . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Typical current consumption in Run and Low-power run modes with different codes
running from Flash, ART disable and power supplied by external SMPS . . . . . . . . . . . . 159
Typical current consumption in Run and Low-power run modes, with different codes
running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Typical consumption in Run and Low-power run modes, with different codes
running from SRAM1 and power supplied by external SMPS . . . . . . . . . . . . . . . . . . . . . 161
Current consumption in Sleep and Low-power sleep mode, Flash ON . . . . . . . . . . . . . . 162
Current consumption in Sleep mode,
Flash ON and power supplied by external SMPS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Current consumption in Low-power sleep mode, Flash in power-down . . . . . . . . . . . . . . 164
Current consumption in Stop 2 mode, SRAM3 disabled . . . . . . . . . . . . . . . . . . . . . . . . . 164
Current consumption in Stop 2 mode, SRAM3 enabled . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
STM32L4P5xx peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Wakeup time using USART/LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
PLL, PLLSAI1, PLLSAI2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
EXTI input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Analog switches booster characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
ADC accuracy - limited test conditions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
ADC accuracy - limited test conditions 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
DS12903 Rev 3
STM32L4P5xx
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
Table 100.
Table 101.
Table 102.
Table 103.
Table 104.
Table 105.
Table 106.
Table 107.
Table 108.
Table 109.
Table 110.
Table 111.
Table 112.
Table 113.
Table 114.
Table 115.
Table 116.
Table 117.
Table 118.
Table 119.
Table 120.
Table 121.
Table 122.
Table 123.
Table 124.
Table 125.
Table 126.
Table 127.
Table 128.
Table 129.
Table 130.
List of tables
ADC accuracy - limited test conditions 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
ADC accuracy - limited test conditions 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
OPAMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
IWDG min/max timeout period at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
WWDG min/max timeout value at 120 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
USB electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
USB OTG electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
USB BCD DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 249
Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 249
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 250
Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 251
Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 252
Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 254
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 259
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 263
OCTOSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
OCTOSPI characteristics in DTR mode (with DQS)/Octal and HyperBus™ . . . . . . . . . . 265
Dynamics characteristics: Delay Block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
PSSI receive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
PSSI transmit characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Dynamics characteristics:
SD / eMMC characteristics at VDD = 2.7 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Dynamics characteristics:
eMMC characteristics at VDD = 1.71 V to 1.9 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
LQFP48 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
UFQFPN48 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
LQFP 64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
LQPF100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
WLCSP100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
WLCSP100 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . 292
UFBGA132 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
DS12903 Rev 3
9/311
10
List of tables
Table 131.
Table 132.
Table 133.
Table 134.
Table 135.
Table 136.
Table 137.
10/311
STM32L4P5xx
UFBGA132 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 295
LQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
UFBGA169 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
UFBGA169 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 303
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
DS12903 Rev 3
STM32L4P5xx
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
STM32L4P5xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
STM32L4P5xx power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
STM32L4P5xxxP with external SMPS power supply overview . . . . . . . . . . . . . . . . . . . . . 25
Power-up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Voltage reference buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
STM32L4P5Cxxx LQFP48 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
STM32L4P5CxxxP external SMPS LQFP48 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
STM32L4P5Cxxx UFQFPN48 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
STM32L4P5CxxxP external SMPS UFQFPN48 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . 66
STM32L4P5Rxxx LQFP64 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
STM32L4P5RxxxP external SMPS LQFP64 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
STM32L4P5Vxxx LQFP100 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
STM32L4P5VxxxP external SMPS LQFP100 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
STM32L4P5Vxxx WLCSP100 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
STM32L4P5VxxxP external SMPS WLCSP100 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . 70
STM32L4P5Qxxx UFBGA132 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
STM32L4P5QxxxP external SMPS UFBGA132 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . 71
STM32L4P5Zxxx LQFP144 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
STM32L4P5ZxxxP external SMPS LQFP144 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
STM32L4P5Axxx UFBGA169 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
STM32L4P5AxxxP UFBGA169 external SMPS ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . 74
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
STM32L4P5xx power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
VREFINT versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
HSI16 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Typical current consumption versus MSI frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
HSI48 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
I/O AC characteristics definition(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
USB OTG timings – definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . 246
Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 248
DS12903 Rev 3
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13
List of figures
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
Figure 64.
Figure 65.
Figure 66.
Figure 67.
Figure 68.
Figure 69.
Figure 70.
Figure 71.
Figure 72.
Figure 73.
Figure 74.
Figure 75.
Figure 76.
Figure 77.
Figure 78.
Figure 79.
Figure 80.
Figure 81.
Figure 82.
Figure 83.
Figure 84.
Figure 85.
Figure 86.
Figure 87.
Figure 88.
Figure 89.
Figure 90.
Figure 91.
Figure 92.
Figure 93.
Figure 94.
Figure 95.
Figure 96.
Figure 97.
Figure 98.
Figure 99.
Figure 100.
12/311
STM32L4P5xx
Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 250
Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 251
Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 253
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 259
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 262
NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 263
OCTOSPI timing diagram - SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
OCTOSPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
OCTOSPI HyperBus™ clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
OCTOSPI HyperBus™ read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
OCTOSPI HyperBus™ read with double latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
OCTOSPI HyperBus™ write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
PSSI receive timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
PSSI transmit timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
LQFP48 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
LQFP48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
LQFP48 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
LQFP48, external SMPS device marking (package top view) . . . . . . . . . . . . . . . . . . . . . 280
UFQFPN48 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
UFQFPN48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
UFQFPN48 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
UFQFPN48, external SMPS device, marking (package top view) . . . . . . . . . . . . . . . . . . 283
LQFP64 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
LQFP64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
LQFP64 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
LQFP64, external SMPS device, marking (package top view) . . . . . . . . . . . . . . . . . . . . . 286
LQFP100 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
LQFP100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
LQFP100 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
LQFP100, external SMPS device, marking (package top view) . . . . . . . . . . . . . . . . . . . . 289
WLCSP100 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
WLCSP100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
WLCSP100 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
WLCSP100, external SMPS device, marking (package top view) . . . . . . . . . . . . . . . . . . 293
UFBGA132 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
UFBGA132 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
UFBGA132 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
UFBGA132, external SMPS device, marking (package top view) . . . . . . . . . . . . . . . . . . 297
LQFP144 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
LQFP144 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
LQFP144 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
LQFP144, external SMPS device, marking (package top view) . . . . . . . . . . . . . . . . . . . . 301
UFBGA169 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
DS12903 Rev 3
STM32L4P5xx
List of figures
Figure 101. UFBGA169 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Figure 102. UFBGA169 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Figure 103. UFBGA169, external SMPS device, marking (package top view) . . . . . . . . . . . . . . . . . . 305
DS12903 Rev 3
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13
Introduction
1
STM32L4P5xx
Introduction
This document provides the ordering information and mechanical device characteristics of
the STM32L4P5xx microcontrollers.
This document should be read in conjunction with the STM32L4P5xx reference manual
(RM0432). The reference manual is available from the STMicroelectronics website
www.st.com.
For information on the Arm®(a) Cortex®-M4 core, refer to the Cortex®-M4 Technical
Reference Manual, available from the www.arm.com website.
For information on the device errata with respect to the datasheet and reference manual,
refer to the STM32L4P5xx errata sheet (ES0510), available from the STMicroelectronics
website www.st.com.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
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DS12903 Rev 3
STM32L4P5xx
2
Description
Description
STM32L4P5xx designates a family of ultra-low-power microcontroller devices (part of
STM32L4+ Series) based on the high-performance Arm® Cortex®-M4 32-bit RISC core.
They operate at a frequency of up to 120 MHz.
The Cortex-M4 core features a single-precision floating-point unit (FPU), which supports all
the Arm® single-precision data-processing instructions and all the data types. The CortexM4 core also implements a full set of DSP (digital signal processing) instructions and a
memory protection unit (MPU) that enhances the application’s security.
These devices embed high-speed memories (up to 1 Mbyte of Flash memory and
320 Kbytes of SRAM), a flexible external memory controller (FSMC) for static memories (for
devices with packages of 100 pins and more), two OCTOSPI Flash memory interfaces (for
devices with packages of 100 pins or more) and an extensive range of enhanced I/Os and
peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus
matrix.
These devices embed several protection mechanisms for embedded Flash memory and
SRAM: readout protection, write protection, proprietary code readout protection and a
firewall.
These devices offer two fast 12-bit ADCs (5 Msps), two comparators, two operational
amplifiers, two DAC channels, an internal voltage reference buffer, a low-power RTC, two
general-purpose 32-bit timers, two 16-bit PWM timers dedicated to motor control, seven
general-purpose 16-bit timers, and two 16-bit low-power timers. The devices support two
digital filters for external sigma delta modulators (DFSDMs). In addition, up to 24 capacitive
sensing channels are available.
They also feature standard and advanced communication interfaces such as:
- Four I2Cs
- Three SPIs
- Three USARTs, two UARTs and one low-power UART
- Two SAIs
- Two SDMMCs
- One CAN
- One USB OTG full-speed
- Camera interface
- Synchronous parallel data interface (PSSI)
The devices operate in the -40 to +85 °C (+105 °C junction) and -40 to +125 °C (+130 °C
junction) temperature ranges from a 1.71 to 3.6 V power supply. A comprehensive set of
power-saving modes allows the design of low-power applications.
Some independent power supplies are supported such as an analog independent supply
input for ADC, DAC, OPAMPs and comparators, a 3.3 V dedicated supply input for USB and
up to 14 I/Os, which can be supplied independently down to 1.08 V. A VBAT input allows
backup of the RTC and the registers. Dedicated VDD12 power supplies can be used to
bypass the internal LDO regulator when connected to an external SMPS.
DS12903 Rev 3
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18
Description
STM32L4P5xx
The STM32L4P5xx family offers eight packages from 48-pin to 169-pin.
Table 2. STM32L4P5xx features and peripheral counts
Peripheral
STM32L4
STM32L4
STM32L4
STM32L4
STM32L4
STM32L4
P5CG/P5CE P5RG/P5RE P5VG/P5VE P5QG/P5QE P5ZG/P5ZE P5AG/P5AE
(48 pins)
(64 pins)
(100 pins)
(132 pins)
(144 pins)
(169 pins)
Flash memory
SRAM
Up to 1 Mbyte
System
320 (128 + 64 + 128) Kbytes
Backup
128 bytes
External memory controller
for static memories
(FSMC)
2
Advanced
control
2 (16-bit)
General
purpose
5 (16-bit)
2 (32-bit)
Basic
2 (16-bit)
Low-power
2 (16-bit)
SysTick timer
1
Watchdog
timers
(independent,
window)
2
SPI
3
2C
4
I
Comm.
interfaces
Yes
2(2)
OCTOSPI
Timers
Yes(1)
No
USART/UART
UART
LPUART
3
2(3)
1
SAI
2
CAN
1
USB OTG FS
Yes
SDMMC
2(4)
Digital filters for sigmadelta modulators
Number of channels
Yes (2 filters)
Real time clock (RTC)
Yes
4
Tamper pins
3
Camera interface
Yes(5)
PSSI
Yes(6)
Chrom-ART Accelerator
LTDC
16/311
Yes
Yes(7)
Yes
DS12903 Rev 3
STM32L4P5xx
Description
Table 2. STM32L4P5xx features and peripheral counts (continued)
Peripheral
STM32L4
STM32L4
STM32L4
STM32L4
STM32L4
STM32L4
P5CG/P5CE P5RG/P5RE P5VG/P5VE P5QG/P5QE P5ZG/P5ZE P5AG/P5AE
(48 pins)
(64 pins)
(100 pins)
(132 pins)
(144 pins)
(169 pins)
True random number
generator
Yes
HASH (SHA-256)
Yes
(8)
GPIOs
Wakeup pins
Nb of I/Os down to 1.08 V
38
3
0
Capacitive sensing
Number of channels
9
12-bit ADCs
Number of channels
83(9)
5
0
52
4
0
110
5
14
21
136
5
14
24
2
10
16
16
16
12-bit DAC channels
16
16
2
Internal voltage reference
buffer
Yes
Analog comparator
2
Operational amplifiers
2
Max. CPU frequency
120 MHz
Operating voltage (VDD)
1.71 to 3.6 V
Operating voltage (VDD12)
1.00 to 1.32 V
Operating temperature
Packages
115
5
14
Ambient operating temperature: -40 to 85 °C / -40 to 125 °C
UFQFPN48/
LQFP48
LQFP64
LQFP100/
WLCSP100
UFBGA132
LQFP144
UFBGA169
1. For the LQFP100 package, only FMC bank1 and NAND bank are available. Bank1 can only support a multiplexed
NOR/PSRAM memory using the NE1 chip select.
2. When multiplexed mode is enabled two OCTOSPIs are available, otherwise only one OCTOSPI is available, for further
details on multiplexed mode refer to the RM0432 reference manual.
3. For 48-pin and 64-pin packages only 1x UART is available.
4. For 48 pins packages only one SDMMC2 with SDIO 4-bits is available. SDMMC1 and SDMMC2 are available for packages
starting from 64 pins.
5. DCMI is available on devices with packages starting from 64-pin.
6. PSSI is available on devices with packages starting from 64-pin.
7. For 48-pin and 64-pin packages, only RGB222 parallel output is supported.
8. When an SMPS package type is used, two GPIOs are replaced by VDD12 pins to connect the SMPS power supplies hence
the available GPIOs number is reduced by two.
9. 81 GPIOs available for WLCSP100 package.
DS12903 Rev 3
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18
Description
STM32L4P5xx
Figure 1. STM32L4P5xx block diagram
MPU
ETM
NVIC
CLK, NE[4:1], NL, NBL[1:0],
A[25:0], D[15:0], NOE, NWE,
NWAIT, NCE, INT as AF, FRAM
Flexible static memory controller (FSMC):
SRAM, PSRAM, NOR Flash, NAND Flash
OctoSPI1 memory interface
IO[7:0],
CLK, NCLK, NCS. DQS
D-BUS
®
OctoSPI2 memory interface
SDIO2/MMC
FIFO
HSYNC, VSYNC,
PIXCLK, D[13:0]
Camera Interface
PDCK, DE, RDY, D[15:0]
PSSI
SRAM 128 KB
@ VDDUSB
SRAM 64 KB
SRAM 128 KB
AHB2 120 MHz
VDD
DMA2
USB
OTG
PHY
SDIO1/MMC
D[7:0]
CMD, CK as AF
FIFO
CHROM-ART
DMA2D
D[7:0]
CMD, CK as AF
Flash
up to
1 MB
AHB bus-matrix
LCD - TFT
ART
ACCEL/
CACHE
RNG
HASH
FIFO
LCD_R[7:0], LCD_G[7:0], LCD_B[7:0],
LCD_HSYNC, LCD_VSYNC, LCD_DE,
LCD_CLK
I-BUS
S-BUS
FIFO
Arm Cortex -M4
120 MHz
FPU
FIFO
®
FIFO
TRACECLK
TRACED[3:0]
JTAG & SW
FIFO
NJTRST, JTDI,
JTCK/SWCLK
JTDO/SWD, JTDO
DP
DM
ID, VBUS, SOF
Power management
Voltage
regulator
3.3 to 1.2 V
VDD = 1.71 to 3.6 V
VSS
DMA1
@ VDD
@ VDD
8 Groups of 4 channels max as AF
RC HSI
PA[15:0]
Supply
supervision
reset
MSI
Touch sensing controller
VDDIO, VDDUSB
Int
BOR
GPIO PORT A
VDDA, VSSA
RC LSI
GPIO PORT B
PC[15:0]
GPIO PORT C
PD[15:0]
GPIO PORT D
PE[15:0]
GPIO PORT E
PF[15:0]
GPIO PORT F
PG[15:0]
GPIO PORT G
PH[15:0]
GPIO PORT H
PI[11:0]
GPIO PORT I
PVD, PVM
PLL 1&2&3
AHB1 120 MHz
PB[15:0]
VDD, VSS, NRST
@VDD
OSC_IN
OSC_OUT
XTAL OSC
4- 16MHz
IWDG
Standby
interface
Reset & clock
M AN
AGT
control
@VBAT
XTAL 32 kHz
OSC32_IN
OSC32_OUT
PCLKx
FCLK
HCLKx
RTC
RTC_TS
RTC_TAMPx
RTC_OUT
AWU
Backup register
VBAT = 1.55 to 3.6 V
@ VDD
U STemperature
AR T 2 M B
ps
sensor
TIM2
32b
4 channels, ETR as AF
TIM3
16b
4 channels, ETR as AF
TIM4
16b
4 channels, ETR as AF
TIM5
32b
4 channels, ETR as AF
CRC
8 analog inputs common to the ADC
@ VDDA
ADC1
ITF
ADC2
AHB/APB2
@ VDDA
AHB/APB1
USART2
smcard
irDA
RX, TX, CK, CTS, RTS as AF
USART3
smcard
irDA
RX, TX, CK, CTS, RTS as AF
VREF+
VREF Buffer
114 AF
EXT IT. WKUP
3 compl. channels (TIM1_CH[1:3]N),
4 channels (TIM1_CH[1:4]),
ETR, BKIN, BKIN2 as AF
TIM1 / PWM
16b
TIM8 / PWM
16b
2 channels,
1 compl. channel, BKIN as AF
TIM15
16b
1 channel,
1 compl. channel, BKIN as AF
TIM16
16b
1 channel,
1 compl. channel, BKIN as AF
TIM17
RX, TX, CTS, RTS as AF
UART5
RX, TX, CTS, RTS as AF
SPI2
MOSI, MISO, SCK, NSS as AF
SPI3
MOSI, MISO, SCK, NSS as AF
I2C1/SMBUS
3 compl. Channels (TIM1_CH[1:3]N),
4 channels (TIM1_CH[1:4]),
ETR, BKIN, BKIN2 as AF
SCL, SDA, SMBA as AF
USART1
MOSI, MISO,
SCK, NSS as AF
SPI1
MCLK_A, SD_A, FS_A, SCK_A, EXTCLK
MCLK_B, SD_B, FS_B, SCK_B as AF
SAI1
MCLK_A, SD_A, FS_A, SCK_A, EXTCLK
MCLK_B, SD_B, FS_B, SCK_B as AF
TIM6
16b
TIM7
16b
I2C2/SMBUS
SCL, SDA, SMBA as AF
I2C3/SMBUS
SCL, SDA, SMBA as AF
I2C4/SMBUS
SCL, SDA, SMBA as AF
bxCAN1
FIFO
P B 1(max)
3 0 M Hz
APB1 120AMHz
smcard
irDA
16b
APB2 120MHz
WWDG
A
60PM
B Hz
2
RX, TX, CK,CTS,
RTS as AF
UART4
TX, RX as AF
@VDDA
OpAmp1
OUT, INN, INP
OpAmp2
OUT, INN, INP
LPUART1
RX, TX, CTS, RTS as AF
LPTIM1
IN1, IN2, OUT, ETR as AF
LPTIM2
IN1, OUT, ETR as AF
SAI2
SDCKIN[7:0], SDDATIN[7:0],
SDCKOUT,SDTRIG as AF
DFSDM
@ VDDA
INP, INN, OUT
COMP1
@ VDDA
INP, INN, OUT
COMP2
DAC1
ITF
Firewall
DAC1_OUT1
DAC1_OUT2
1. AF: alternate function on I/O pins.
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STM32L4P5xx
Functional overview
3
Functional overview
3.1
Arm® Cortex®-M4 core with FPU
The Arm® Cortex®-M4 with FPU processor is the latest generation of Arm® processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
the MCU implementation, with a reduced pin count and with low-power consumption, while
delivering outstanding computational performance and an advanced response to interrupts.
The Arm® Cortex®-M4 with FPU 32-bit RISC processor features an exceptional codeefficiency, delivering the expected high-performance from an Arm® core in a memory size
usually associated with 8-bit and 16-bit devices.
The processor supports a set of DSP instructions which allows an efficient signal processing
and a complex algorithm execution. Its single precision FPU speeds up the software
development by using metalanguage development tools to avoid saturation.
With its embedded Arm® core, the family is compatible with all Arm® tools and software.
Figure 1 shows the general block diagram of the family devices.
3.2
Adaptive real-time memory accelerator (ART Accelerator)
The ART Accelerator is a memory accelerator that is optimized for the STM32 industrystandard Arm®Cortex®-M4 processors. It balances the inherent performance advantage of
the Arm® Cortex®-M4 over Flash memory technologies, which normally requires the
processor to wait for the Flash memory at higher frequencies.
To release the processor near 150 DMIPS performance at 120 MHz, the accelerator
implements an instruction prefetch queue and a branch cache, which increases the
program’s execution speed from the Flash memory. Based on CoreMark benchmark, the
performance achieved thanks to the ART accelerator is equivalent to 0 wait state program
execution from the Flash memory at a CPU frequency of up to 120 MHz.
3.3
Memory protection unit (MPU)
The memory protection unit (MPU) is used to manage the CPU accesses to the memory
and to prevent one task to accidentally corrupt the memory or the resources used by any
other active task. This memory area is organized into up to eight protected areas, which can
be divided in up into eight subareas each. The protection area sizes range between 32
bytes and the whole 4 gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
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STM32L4P5xx
3.4
Memories
3.4.1
Embedded Flash memory
The devices feature up to 1 Mbyte of embedded Flash memory which is available for storing
programs and data.
The Flash interface features:
–
Single or dual bank operating modes
–
Read-while-write (RWW) in dual bank mode
This feature allows to perform a read operation from one bank while an erase or program
operation is performed to the other bank. The dual-bank boot is also supported. Each bank
contains 128 pages of 4 Kbytes. In Single-bank mode the main Flash memory contains 128
pages of 8 Kbytes.
Flexible protections can be configured thanks to the option bytes:
• Readout protection (RDP) to protect the whole memory. Three levels of protection are
available:
– Level 0: no readout protection
– Level 1: memory readout protection; the Flash memory cannot be read from or written
to if either the debug features are connected or the boot in RAM or bootloader are
selected
– Level 2: chip readout protection; the debug features (Cortex-M4 JTAG and serial
wire), the boot in RAM and the bootloader selection are disabled (JTAG fuse). This
selection is irreversible.
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STM32L4P5xx
Functional overview
Table 3. Access status versus readout protection level and execution modes
Area
Debug, boot from RAM or boot
from system memory (loader)
User execution
Protection
level
Read
Write
Erase
Read
Write
Erase
Main
memory
1
Yes
Yes
Yes
No
No
No
2
Yes
Yes
Yes
N/A
N/A
N/A
System
memory
1
Yes
No
No
Yes
No
No
2
Yes
No
No
N/A
N/A
N/A
Option
bytes
1
Yes
Yes
Yes
Yes
Yes
Yes
2
Yes
No
No
N/A
N/A
N/A
No
No
N/A(1)
Backup
registers
SRAM2
(1)
1
Yes
Yes
N/A
2
Yes
Yes
N/A
N/A
N/A
N/A
No
No
No(1)
N/A
N/A
N/A
1
Yes
Yes
Yes(1)
2
Yes
Yes
Yes
1. Erased when RDP change from Level 1 to Level 0.
•
•
Write protection (WRP): the protected area is protected against erasing and
programming:
–
In single bank mode, four areas can be selected with 8-Kbyte granularity.
–
In dual bank mode, two areas per bank can be selected with 4-Kbyte granularity.
Proprietary code readout protection (PCROP): a part of the Flash memory can be
protected against read and write from third parties. The protected area is execute-only
and it can only be reached by the STM32 CPU as an instruction code, while all other
accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited:
–
In single bank mode, two areas can be selected with 128-bit granularity.
–
In dual bank mode, one area per bank can be selected with 64-bit granularity.
An additional option bit (PCROP_RDP) allows to select if the PCROP area is erased or
not when the RDP protection is changed from Level 1 to Level 0.
The whole non-volatile memory embeds the error correction code (ECC) feature supporting:
3.4.2
•
Single error detection and correction
•
Double error detection
•
The address of the ECC fail can be read in the ECC register.
Embedded SRAM
The devices feature 320 Kbytes of embedded SRAM. This SRAM is split into three blocks:
•
128 Kbytes mapped at address 0x2000 0000 (SRAM1).
•
64 Kbytes located at address 0x1000 0000 with hardware parity check (SRAM2).
This memory is also mapped at address 0x2002 0000 offering a contiguous address
space with the SRAM1.
This block is accessed through the ICode/DCode buses for maximum performance.
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Either 64 Kbytes or 4 Kbytes of SRAM2 can be retained in Standby mode.
The SRAM2 can be write-protected with 1 Kbyte granularity.
•
128 Kbytes mapped at address 0x2003 0000 (SRAM3).
The memory can be accessed in read/write at CPU clock speed with 0 wait states.
3.5
Boot modes
At startup, a BOOT0 pin and an nBOOT1 option bit are used to select one of three boot
options:
•
Boot from user Flash
•
Boot from system memory
•
Boot from embedded SRAM
The BOOT0 value may come from the PH3-BOOT0 pin or from an option bit depending on
the value of a user option bit to free the GPIO pad if needed.
A Flash empty-check mechanism is implemented to force the boot from system Flash if the
first Flash memory location is not programmed and if the boot selection is configured to boot
from main Flash.
The boot loader is located in the system memory. It is used to reprogram the Flash memory
by using USART, I2C, SPI, CAN or USB OTG FS in device mode through the DFU (device
firmware upgrade).
3.6
Firewall
These devices embed a firewall which protects code sensitive and secure data from any
access performed by a code executed outside of the protected areas.
Each illegal access generates a reset which kills immediately the detected intrusion.
The main features of the firewall are the following:
•
•
Three segments can be protected and defined thanks to the firewall registers:
–
Code segment (located in Flash or SRAM1 if defined as executable protected
area)
–
Non-volatile data segment (located in Flash)
–
Volatile data segment (located in SRAM1)
The start address and the length of each segment are configurable:
–
Code segment: up to 1024 Kbytes with granularity of 256 bytes
–
Non-volatile data segment: up to 1024 Kbytes with granularity of 256 bytes
–
Volatile data segment: up to 128 Kbytes of SRAM1 with a granularity of 64 bytes
•
Specific mechanism implemented to open the firewall to get access to the protected
areas (call gate entry sequence)
•
Volatile data segment can be shared or not with the non-protected code
•
Volatile data segment can be executed or not depending on the firewall configuration
The Flash readout protection must be set to level 2 in order to reach the expected level of
protection.
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Functional overview
3.7
Power supply management
3.7.1
Power supply schemes
The STM32L4P5xx devices require a 1.71 V to 3.6 V VDD operating voltage supply. Several
independent supplies can be provided for specific peripherals:
•
VDD = 1.71 V to 3.6 V
VDD is the external power supply for the I/Os, the internal regulator and the system
analog such as reset, power management and internal clocks. It is provided externally
through the VDD pins.
•
VDD12 = 1.00 to 1.32 V
VDD12 is the external power supply bypassing the internal regulator when connected to
an external SMPS. It is provided externally through VDD12 pins and only available on
packages with the external SMPS supply option. VDD12 does not require any external
decoupling capacitance and cannot support any external load.
•
VDDA = 1.62 V (ADCs/COMPs) / 1.8 V (DACs/OPAMPs) to 2.4 V (VREFBUF) to 3.6 V
VDDA is the external analog power supply for A/D converters, D/A converters, voltage
reference buffer, operational amplifiers and comparators. The VDDA voltage level is
independent from the VDD voltage and should preferably be connected to VDD when
these peripherals are not used.
•
VDDUSB = 3.0 V to 3.6 V
VDDUSB is the external independent power supply for USB transceivers. The
VDDUSB voltage level is independent from the VDD voltage and should preferably be
connected to VDD when the USB is not used.
•
VDDIO2 = 1.08 V to 3.6 V
•
VDDIO2 is the external power supply for 14 I/Os (port G[15:2]). The VDDIO2 voltage
level is independent from the VDD voltage and should preferably be connected to VDD
when PG[15:2] are not used.
•
VBAT = 1.55 V to 3.6 V
VBAT is the power supply for RTC, external clock 32 kHz oscillator and backup registers
(through power switch) when VDD is not present.
•
VREF-, VREF+
VREF+ is the input reference voltage for ADCs and DACs. It is also the output of the
internal voltage reference buffer when enabled.
When VDDA < 2 V VREF+ must be equal to VDDA.
When VDDA ≥ 2 V VREF+ must be between 2 V and VDDA.
VREF+ can be grounded when ADC and DAC are not active.
The internal voltage reference buffer supports two output voltages, which are
configured with VRS bit in the VREFBUF_CSR register:
–
VREF+ around 2.048 V. This requires VDDA equal to or higher than 2.4 V.
–
VREF+ around 2.5 V. This requires VDDA equal to or higher than 2.8 V.
VREF- and VREF+ pins are not available on all packages. When not available, they are
bonded to VSSA and VDDA, respectively.
When the VREF+ is double-bonded with VDDA in a package, the internal voltage
reference buffer is not available and must be kept disable (refer to datasheet for
packages pinout description).
VREF- must always be equal to VSSA.
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An embedded linear voltage-regulator is used to supply the internal digital power VCORE.
VCORE is the power supply for digital peripherals, SRAM1, SRAM2 and SRAM3. The Flash
is supplied by VCORE and VDD.
Figure 2. STM32L4P5xx power supply overview
VDDA domain
VDDA
VSSA
VDDUSB
VSS
VDDIO2
VSS
1 x A/D converter
2 x comparators
2 x D/A converters
2 x operational amplifiers
Voltage reference buffer
USB transceivers
VDDIO2 domain
VDDIO2
I/O ring
PG[15:2]
VDD domain
VDDIO1 I/O ring
VCORE domain
Reset block
Temp. sensor
3 x PLL, HSI, MSI
VSS
VDD
Standby circuitry
(Wakeup logic,
IWDG)
VCORE
Core
SRAM1
SRAM2
SRAM3
Digital
peripherals
Voltage regulator
Low voltage detector
Flash memory
Backup domain
VBAT
LSE crystal 32 K osc
BKP registers
RCC BDCR register
RTC
MSv49328V1
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STM32L4P5xx
Functional overview
Figure 3. STM32L4P5xxxP with external SMPS power supply overview
VDDA domain
VDDA
VSSA
1 x A/D converter
2 x comparators
2 x D/A converters
2 x operational amplifiers
Voltage reference buffer
VDDUSB
VSS
VDDIO2
VSS
USB transceivers
VDDIO2 domain
VDDIO2
I/O ring
PG[15:2]
VDD domain
VDDIO1 I/O ring
VCORE domain
Reset block
Temp. sensor
Core
3 x PLL, HSI, MSI
VSS
VDD
Standby circuitry
(Wakeup logic,
IWDG)
Voltage regulator
2x VDD12
SRAM1
SRAM2
SRAM3
VCORE
Digital
peripherals
Flash memory
Low voltage detector
Backup domain
VBAT
LSE crystal 32 K osc
BKP registers
RCC BDCR register
RTC
MSv49333V1
During power-up and power-down phases, the following power sequence requirements
must be respected:
•
When VDD is below 1 V, other power supplies (VDDA, VDDIO2 and VDDUSB) must remain
below VDD +300 mV.
•
When VDD is above 1 V, all power supplies are independent.
•
During the power-down phase, VDD can temporarily become lower than other supplies
only if the energy provided to the MCU remains below 1 mJ; this allows external
decoupling capacitors to be discharged with different time constants during the powerdown transient phase.
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STM32L4P5xx
Figure 4. Power-up/down sequence
V
3.6
VDDX(1)
VDD
VBOR0
1
0.3
Power-on
Invalid supply area
Operating mode
VDDX < VDD + 300 mV
Power-down
time
VDDX independent from VDD
MSv47490V1
1. VDDX refers to any power supply among VDDA, VDDIO2 and VDDUSB.
3.7.2
Power supply supervisor
The STM32L4P5xx devices have an integrated ultra-low-power Brownout reset (BOR)
active in all modes (except for Shutdown mode). The BOR ensures proper operation of the
devices after power-on and during power-down. The devices remain in reset mode when
the monitored supply voltage VDD is below a specified threshold, without the need for an
external reset circuit.
The lowest BOR level is 1.71 V at power on, and other higher thresholds can be selected
through option bytes.The devices feature an embedded programmable voltage detector
(PVD) that monitors the VDD power supply and compares it to the VPVD threshold.
An interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD
is higher than the VPVD threshold. The interrupt service routine can then generate a
warning message and/or put the MCU into a safe state. The PVD is enabled by software.
In addition, the devices embed a peripheral voltage monitor which compares the
independent supply voltages VDDA, VDDUSB, VDDIO2 with a fixed threshold in order to ensure
that the peripheral is in its functional supply range.
3.7.3
Voltage regulator
Two embedded linear voltage regulators supply most of the digital circuitries: the main
regulator (MR) and the low-power regulator (LPR).
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•
The MR is used in the Run and Sleep modes and in the Stop 0 mode.
•
The LPR is used in Low-power run, Low-power sleep, Stop 1 and Stop 2 modes. It is
also used to supply the 64 Kbytes SRAM2 in standby with RAM2 retention.
•
Both regulators are in power-down while they are in standby and Shutdown modes: the
regulator output is in high impedance, and the kernel circuitry is powered down thus
inducing zero consumption.
DS12903 Rev 3
STM32L4P5xx
Functional overview
The ultra-low-power devices support dynamic voltage scaling to optimize its power
consumption in Run mode. The voltage from the main regulator that supplies the logic
(VCORE) can be adjusted according to the system’s maximum operating frequency.
The main regulator operates in the following ranges:
•
Range 1 boost mode with the CPU running at up to 120 MHz.
•
Range 1 normal mode with the CPU running at up to 80 MHz.
•
Range 2 with a maximum CPU frequency of 26 MHz. All peripheral clocks are also
limited to 26 MHz.
The VCORE can be supplied by the low-power regulator, the main regulator being switched
off. The system is then in Low-power run mode.
•
Low-power run mode with the CPU running at up to 2 MHz. Peripherals with
independent clock can be clocked by the HSI16.
When the MR is in use, the device with the external SMPS option allows to force an external
VCORE supply on the VDD12 supply pins.
When VDD12 is forced by an external source and that it is higher than the output of the
internal LDO, the current is taken from this external supply and the overall power efficiency
is significantly improved if using an external step down DC/DC converter.
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Functional overview
3.7.4
STM32L4P5xx
Low-power modes
The ultra-low-power devices support seven low-power modes to achieve the best
compromise between low-power consumption, short startup time, available peripherals and
available wake-up sources. The table below shows the related STM32L4P5xx modes
overview.
Table 4. STM32L4P5xx modes overview
Mode
(1)
Regulator
CPU
Flash
SRAM
Clocks
DMA and peripherals(2)
Wakeup source
Range 1
Run
SMPS range
2 High
Range 2
All
Yes
ON(3)
ON
Any
All except
OTG_FS, RNG, LCD-TFT
SMPS range
2 Low
LPRun
LPR
N/A
Yes
ON(3)
ON
Any
except
PLL
All except
OTG_FS, RNG, LCD-TFT
N/A
Range 1
Sleep
SMPS range
2 High
Range 2
All
No
ON(3)
ON(4)
All except
OTG_FS, RNG, LCD-TFT
SMPS range
2 Low
LPSleep
LPR
No
ON(3)
ON(4)
Any
except
PLL
All except OTG_FS, RNG,
LCD-TFT
Any interrupt or
event
LSE
LSI
BOR, PVD, PVM
RTC, IWDG
COMPx (x=1,2)
DAC1
OPAMPx (x=1,2)
USARTx (x=1...5)(6)
LPUART1(6)
I2Cx (x=1...4)(7)
LPTIMx (x=1,2)
***
All other peripherals are
frozen
Reset pin, all I/Os
BOR, PVD, PVM
RTC, IWDG
COMPx (x=1..2)
USARTx
(x=1...5)(6)
LPUART1(6)
I2Cx (x=1...4)(7)
LPTIMx (x=1,2)
OTG_FS(8)
Range 1
Stop 0(5)
No
Off
ON
Range 2
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Any interrupt or
event
Any
DS12903 Rev 3
STM32L4P5xx
Functional overview
Table 4. STM32L4P5xx modes overview (continued)
Mode
Stop 1
Stop 2
Regulator(1)
LPR
LPR
CPU
No
No
Flash
Off
Off
OFF
Shutdown
OFF
ON
ON
Clocks
DMA and peripherals(2)
Wakeup source
LSE
LSI
BOR, PVD, PVM
RTC, IWDG
COMPx (x=1,2)
DAC1
OPAMPx (x=1,2)
USARTx (x=1...5)(6)
LPUART1(6)
I2Cx (x=1...4)(7)
LPTIMx (x=1,2)
***
All other peripherals are
frozen
Reset pin, all I/Os
BOR, PVD, PVM
RTC, IWDG
COMPx (x=1..2)
USARTx
(x=1...5)(6)
LPUART1(6)
I2Cx (x=1...4)(7)
LPTIMx (x=1,2)
OTG_FS(8)
LSE
LSI
BOR, PVD, PVM
RTC, IWDG
COMPx (x=1..2)
I2C3(7)
LPUART1(6)
LPTIMx (x=1,2)
***
All other peripherals are
frozen
Reset pin, all I/Os
BOR, PVD, PVM
RTC, IWDG
COMPx (x=1..2)
I2C3(7)
LPUART1(6)
LPTIMx (x=1,2)
LSE
LSI
BOR, RTC, IWDG
***
All other peripherals are
powered off
***
I/O configuration can be
floating, pull-up or pulldown
Reset pin
5 I/Os (WKUPx)(9)
BOR, RTC, IWDG
LSE
RTC
***
All other peripherals are
powered off
***
I/O configuration can be
floating, pull-up or pulldown(10)
Reset pin
5 I/Os (WKUPx)(9)
RTC
SRAM2
ON
LPR
Standby
SRAM
Powered
Off
Powered
Off
Off
Off
Powered
Off
Powered
Off
1. LPR means Main regulator is OFF and Low-power regulator is ON.
2. All peripherals can be active or clock gated to save power consumption.
3. The Flash memory can be put in power-down and its clock can be gated off when executing from SRAM.
4. The SRAM1, SRAM2 and SRAM3 clocks can be gated on or off independently.
5. SMPS mode can be used in Stop 0 mode, but no significant power gain can be expected.
6. U(S)ART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or
received frame event.
7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.
8. OTG_FS wakeup by resume from suspend and attach detection protocol event.
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9. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5.
10. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when
exiting the Shutdown mode.
By default, the microcontroller is in Run mode after a system or a power reset. It is up to the
user to select one of the low-power modes described below:
•
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
•
Low-power run mode
This mode is achieved with VCORE supplied by the low-power regulator to minimize
the regulator's operating current. The code can be executed from SRAM or from Flash,
and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can
be clocked by HSI16.
•
Low-power sleep mode
This mode is entered from the Low-power run mode. Only the CPU clock is stopped.
When wakeup is triggered by an event or an interrupt, the system reverts to the Lowpower run mode.
•
Stop 0, Stop 1 and Stop 2 modes
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the VCORE domain are stopped, the PLL, the MSI
RC, the HSI16 RC and the HSE crystal oscillators are disabled. The LSE or LSI is still
running.
The RTC can remain active (Stop mode with RTC, Stop mode without RTC).
Some peripherals with wake-up capability can enable the HSI16 RC during Stop mode
to detect their wake-up condition.
Three Stop modes are available: Stop 0, Stop 1 and Stop 2 modes. In Stop 2 mode,
most of the VCORE domain is put in a lower leakage mode.
Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller
wakeup time but a higher consumption than Stop 2. In Stop 0 mode, the main regulator
remains ON, allowing a very fast wakeup time but with much higher consumption.
The system clock when exiting from Stop 0, Stop 1 or Stop 2 modes can be either MSI
up to 48 MHz or HSI16, depending on software configuration.
•
Standby mode
The Standby mode is used to achieve the lowest power consumption with BOR. The
internal regulator is switched off so that the VCORE domain is powered off. The PLL,
the MSI RC, the HSI16 RC and the HSE crystal oscillators are also switched off.
The RTC can remain active (Standby mode with RTC, Standby mode without RTC).
The Brownout reset (BOR) always remains active in Standby mode.
The state of each I/O during Standby mode can be selected by software: I/O with
internal pull-up, internal pull-down or floating.
After entering Standby mode, SRAM1, SRAM3 and register contents are lost except for
registers in the Backup domain and Standby circuitry. Optionally, the full SRAM2 (or
30/311
DS12903 Rev 3
STM32L4P5xx
Functional overview
only the upper 4 Kbytes) can be retained in Standby mode, supplied by the low-power
regulator (standby with RAM2 retention mode).
The device exits Standby mode when an external reset (NRST pin), an IWDG reset,
WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm,
periodic wakeup, timestamp, tamper) or a failure is detected on LSE (CSS on LSE).
The system clock after wakeup is MSI up to 8 MHz.
•
Shutdown mode
The Shutdown mode allows to achieve the lowest power consumption. The internal
regulator is switched off so that the VCORE domain is powered off. The PLL, the
HSI16, the MSI, the LSI and the HSE oscillators are also switched off.
The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).
The BOR is not available in Shutdown mode. No power voltage monitoring is possible
in this mode, therefore the switch to Backup domain is not supported.
SRAM1, SRAM2, SRAM3 and register contents are lost except for registers in the
Backup domain.
The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin
event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic
wakeup, timestamp, tamper).
The system clock after wakeup is MSI at 4 MHz.
DS12903 Rev 3
31/311
64
Functional overview
STM32L4P5xx
Table 5. Functionalities depending on the working mode(1)
-
-
Y
-
Y
-
-
-
-
-
-
-
-
-
-
O(2)
O(2)
O(2)
O(2)
-
-
-
-
-
-
-
-
-
SRAM1
(128 Kbytes)
Y
Y(3)
Y
Y(3)
Y
-
Y
-
-
-
-
-
-
SRAM2 (64 Kbytes)
Y
Y(3)
Y
Y(3)
Y
-
Y
-
O(4)
-
-
-
-
SRAM3
(128 Kbytes)
Y
Y(3)
Y
Y(3)
Y
-
Y(3)
-
-
-
-
-
-
FSMC
O
O
O
O
-
-
-
-
-
-
-
-
-
OCTOSPIx
(x=1,2)
O
O
O
O
-
-
-
-
-
-
-
-
-
Backup registers
Y
Y
Y
Y
Y
-
Y
-
Y
-
Y
-
Y
Brownout reset
(BOR)
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
-
-
Programmable
voltage detector
(PVD)
O
O
O
O
O
O
O
O
-
-
-
-
-
Peripheral voltage
monitor (PVMx;
x=1,2,3,4)
O
O
O
O
O
O
O
O
-
-
-
-
-
DMA
O
O
O
O
-
-
-
-
-
-
-
-
-
DMA2D
O
O
O
O
-
-
-
-
-
-
-
-
-
High speed internal
(HSI16)
O
O
O
O
(5)
-
(5)
-
-
-
-
-
-
Oscillator HSI48
O
O
-
-
-
-
-
-
-
-
-
-
-
High speed external
(HSE)
O
O
O
O
-
-
-
-
-
-
-
-
-
Low speed internal
(LSI)
O
O
O
O
O
-
O
-
O
-
-
-
-
Low speed external
(LSE)
O
O
O
O
O
-
O
-
O
-
O
-
O
Multi speed internal
(MSI)
O
O
O
O
-
-
-
-
-
-
-
-
-
Clock security
system (CSS)
O
O
O
O
-
-
-
-
-
-
-
-
-
Peripheral
CPU
Flash memory
(2 Mbytes)
32/311
Run
Sleep
Lowpower
run
Lowpower
sleep
-
DS12903 Rev 3
Wakeup capability
-
Wakeup capability
Standby Shutdown
Wakeup capability
Stop 2
Wakeup capability
Stop 0/1
VBAT
STM32L4P5xx
Functional overview
Table 5. Functionalities depending on the working mode(1) (continued)
-
-
Clock security
system on LSE
O
O
O
O
O
O
O
O
O
O
-
-
-
RTC / Auto wakeup
O
O
O
O
O
O
O
O
O
O
O
O
O
Number of RTC
Tamper pins
3
3
3
3
3
O
3
O
3
O
3
O
3
Camera interface
(DCMI)
O
O
O
O
-
-
-
-
-
-
-
-
-
PSSI
O
O
O
O
-
-
-
-
-
-
-
-
-
LCD-TFT
O
O
-
-
-
-
-
-
-
-
-
-
-
O(8)
-
-
-
O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Peripheral
USB OTG FS
Run
O
(8)
Sleep
Lowpower
run
Lowpower
sleep
-
Wakeup capability
-
Wakeup capability
Standby Shutdown
Wakeup capability
Stop 2
Wakeup capability
Stop 0/1
VBAT
USARTx
(x=1,2,3,4,5)
O
O
O
O
O(6) O(6)
Low-power UART
(LPUART)
O
O
O
O
O(6) O(6) O(6) O(6)
-
-
-
-
-
I2Cx (x=1,2,4)
O
O
O
O
O(7) O(7)
(7)
-
-
-
-
-
-
-
O(7)
O(7)
O(7)
-
-
-
-
-
I2C3
O
O
O
O
O
SPIx (x=1,2,3)
O
O
O
O
-
-
-
-
-
-
-
-
-
CAN(x=1,2)
O
O
O
O
-
-
-
-
-
-
-
-
-
SDMMC1
O
O
O
O
-
-
-
-
-
-
-
-
-
SDMMC2
O
O
O
O
-
-
-
-
-
-
-
-
-
SAIx (x=1,2)
O
O
O
O
-
-
-
-
-
-
-
-
-
DFSDM1
O
O
O
O
-
-
-
-
-
-
-
-
-
ADCx
(x=1,2)
O
O
O
O
-
-
-
-
-
-
-
-
-
DAC1
O
O
O
O
O
-
-
-
-
-
-
-
-
VREFBUF
O
O
O
O
O
-
-
-
-
-
-
-
-
OPAMPx (x=1,2)
O
O
O
O
O
-
-
-
-
-
-
-
-
COMPx (x=1,2)
O
O
O
O
O
O
O
O
-
-
-
-
-
Temperature sensor
O
O
O
O
-
-
-
-
-
-
-
-
-
Timers (TIMx)
O
O
O
O
-
-
-
-
-
-
-
-
-
Low-power timer 1
(LPTIM1)
O
O
O
O
O
O
O
O
-
-
-
-
-
DS12903 Rev 3
33/311
64
Functional overview
STM32L4P5xx
Table 5. Functionalities depending on the working mode(1) (continued)
-
-
Low-power timer 2
(LPTIM2)
O
O
O
O
O
O
O
O
-
-
-
-
-
Independent
watchdog (IWDG)
O
O
O
O
O
O
O
O
O
O
-
-
-
Window watchdog
(WWDG)
O
O
O
O
-
-
-
-
-
-
-
-
-
SysTick timer
O
O
O
O
-
-
-
-
-
-
-
-
-
Touch sensing
controller (TSC)
O
O
O
O
-
-
-
-
-
-
-
-
-
Random number
generator (RNG)
O(8)
O(8)
-
-
-
-
-
-
-
-
-
-
-
HASH hardware
accelerator
O
O
O
O
-
-
-
-
-
-
-
-
-
CRC calculation
unit
O
O
O
O
-
-
-
-
-
-
-
-
-
GPIOs
O
O
O
O
O
O
O
O
(9)
5
pins
(11)
5
pins
-
Peripheral
Run
Sleep
Lowpower
run
Lowpower
sleep
-
(10)
Wakeup capability
-
Wakeup capability
Standby Shutdown
Wakeup capability
Stop 2
Wakeup capability
Stop 0/1
VBAT
(10)
1. Legend: Y = yes (enable). O = optional (disable by default, can be enabled by software). - = not available.
Gray cells highlight the wakeup capability in each mode.
2. The Flash can be configured in power-down mode. By default, it is not in power-down mode.
3. The SRAM clock can be gated on or off. In Stop 2 mode, the content of SRAM3 is preserved or not depending on the
RRSTP bit in PWR_CR1 register.
4. The upper 4 Kbytes or the full SRAM2 content is preserved depending on RRS[1:0] bits configuration in PWR_CR3
register.
5. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by
the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not
need it anymore.
6. UART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or
received frame event.
7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.
8. Voltage scaling range 1 only.
9. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.
10. The I/Os with wakeup from standby/shutdown capability are: PA0, PC13, PE6, PA2, PC5.
11. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when
exiting the Shutdown mode.
34/311
DS12903 Rev 3
STM32L4P5xx
3.7.5
Functional overview
Reset mode
In order to improve the consumption under reset, the I/Os state under and after reset is
“analog state” (the I/O schmitt trigger is disable). In addition, the internal reset pull-up is
deactivated when the reset source is internal.
3.7.6
VBAT operation
The VBAT pin allows the device VBAT domain to be powered from an external battery, an
external supercapacitor, or from VDD when there is no external battery and when an external
supercapacitor is present. The VBAT pin supplies the RTC with LSE and the backup
registers. Three anti-tamper detection pins are available in VBAT mode.
The VBAT operation is automatically activated when VDD is not present. An internal VBAT
battery charging circuit is embedded and can be activated when VDD is present.
Note:
When the microcontroller is supplied from VBAT, neither external interrupts nor RTC
alarm/events exit the microcontroller from the VBAT operation.
3.8
Peripheral and interconnect matrix
Several peripherals have direct connections between them, which allow autonomous
communication between them and support the saving of CPU resources (thus power supply
consumption). In addition, these hardware connections allow fast and predictable latency.
Depending on the peripherals, these interconnections can operate in Run, Sleep, Lowpower run, Low-power Sleep, Stop 0, Stop 1 and Stop 2 modes. See Table 6 for more
details.
Stop 0 / Stop 1
Stop 2
ADCx
Low-power sleep
COMPx
Low-power run
TIMx
Sleep
Interconnect source
Run
Table 6. STM32L4P5xx peripherals interconnect matrix
TIMx
Timers synchronization or chaining
Y
Y
Y
Y
-
-
ADCx
DAC1
DFSDM1
Conversion triggers
Y
Y
Y
Y
-
-
DMA
Memory to memory transfer trigger
Y
Y
Y
Y
-
-
COMPx
Comparator output blanking
Y
Y
Y
Y
-
-
TIM1, 8
TIM2, 3
Timer input channel, trigger, break from
analog signals comparison
Y
Y
Y
Y
-
-
LPTIMERx
Low-power timer triggered by analog
signals comparison
Y
Y
Y
Y
Y
Y
TIM1, 8
Timer triggered by analog watchdog
Y
Y
Y
Y
-
-
Interconnect
destination
Interconnect action
DS12903 Rev 3
35/311
64
Functional overview
STM32L4P5xx
Run
Sleep
Low-power run
Low-power sleep
Stop 0 / Stop 1
Stop 2
Table 6. STM32L4P5xx peripherals interconnect matrix (continued)
TIM16
Timer input channel from RTC events
Y
Y
Y
Y
-
-
LPTIMERx
Low-power timer triggered by RTC alarms
or tampers
Y
Y
Y
Y
Y
Y
All clocks sources (internal TIM2
and external)
TIM15, 16, 17
Clock source used as input channel for
RC measurement and trimming
Y
Y
Y
Y
-
-
USB
Timer triggered by USB SOF
Y
Y
-
-
-
-
Timer break
Y
Y
Y
Y
-
-
TIMx
External trigger
Y
Y
Y
Y
-
-
LPTIMERx
External trigger
Y
Y
Y
Y
Y
Y
ADC
DAC1
DFSDM1
Conversion external trigger
Y
Y
Y
Y
-
-
Interconnect source
RTC
Interconnect
destination
TIM2
CSS
CPU (hard fault)
RAM (parity error)
Flash memory (ECC error)
TIM1,8
COMPx
TIM15,16,17
PVD
DFSDM1 (analog
watchdog, short circuit
detection)
GPIO
36/311
Interconnect action
DS12903 Rev 3
STM32L4P5xx
3.9
Functional overview
Reset and clock controller (RCC)
The clock controller (see Figure 5) distributes the clocks coming from the different
oscillators to the core and to the peripherals. It also manages the clock gating for low-power
modes and ensures the clock robustness. It features:
•
Clock prescaler: to get the best trade-off between speed and current consumption,
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler.
•
Safe clock switching: clock sources can be changed safely on the fly in Run mode
through a configuration register.
•
Clock management: to reduce the power consumption, the clock controller can stop
the clock to the core, individual peripherals or memory.
•
System clock source: four different clock sources can be used to drive the master
clock SYSCLK:
–
4 to 48 MHz high-speed external crystal or ceramic resonator (HSE), that can
supply a PLL. The HSE can also be configured in bypass mode for an external
clock.
–
16 MHz high-speed internal RC oscillator (HSI16), trimmable by software, that can
supply a PLL
–
Multispeed internal RC oscillator (MSI), trimmable by software, able to generate
12 frequencies from 100 kHz to 48 MHz. When a 32.768 kHz clock source is
available in the system (LSE), the MSI frequency can be automatically trimmed by
hardware to reach better than ±0.25% accuracy. In this mode the MSI can feed the
USB device, saving the need of an external high-speed crystal (HSE). The MSI
can supply a PLL.
–
System PLL which can be fed by HSE, HSI16 or MSI, with a maximum frequency
at 120 MHz.
•
RC48 with clock recovery system (HSI48): internal 48 MHz clock source (HSI48)can
be used to drive the USB, the SDMMC or the RNG peripherals. This clock can be
output on the MCO.
•
Auxiliary clock source: two ultra-low-power clock sources that can be used to drive
the real-time clock:
–
32.768 kHz low-speed external crystal (LSE), supporting four drive capability
modes. The LSE can also be configured in bypass mode for an external clock.
–
32 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.
The LSI clock accuracy is ±5% accuracy.
•
Peripheral clock sources: several peripherals (USB, SDMMC, RNG, SAI, USARTs,
I2Cs, LPTimers, ADC) have their own independent clock whatever the system clock.
Three PLLs, each having three independent outputs allowing the highest flexibility, can
generate independent clocks for the ADC, the USB/SDMMC/RNG, the two SAIs, and
LCD-TFT.
•
Startup clock: after reset, the microcontroller restarts by default with an internal 4 MHz
clock (MSI). The prescaler ratio and clock source can be changed by the application
program as soon as the code execution starts.
•
Clock security system (CSS): this feature can be enabled by software. If a HSE clock
failure occurs, the master clock is automatically switched to HSI16 and a software
DS12903 Rev 3
37/311
64
Functional overview
STM32L4P5xx
interrupt is generated if enabled. LSE failure can also be detected and generated an
interrupt.
•
Clock-out capability:
–
MCO (microcontroller clock output): it outputs one of the internal clocks for
external use by the application
–
LSCO (low-speed clock output): it outputs LSI or LSE in all low-power modes
(except VBAT).
Several prescalers allow the AHB frequency, the high speed APB (APB2) and the lowspeed APB (APB1) domains to be configured. The maximum frequency of the AHB and the
APB domains is 120 MHz.
38/311
DS12903 Rev 3
STM32L4P5xx
Functional overview
Figure 5. Clock tree
to IWDG
LSI RC 32 kHz
LSCO
to RTC
OSC32_OUT
LSE OSC
32.768 kHz
/32
OSC32_IN
MCO
to PWR
LSE
LSI
MSI
HSI16
HSE
SYSCLK
/ 1→16
to AHB bus, core, memory and DMA
AHB PRESC
/ 1,2,..512
HCLK
PLLCLK
HSI48
to Cortex system timer
/8
Clock
source
control
OSC_OUT
HSE OSC
4-48 MHz
OSC_IN
Clock
detector
FCLK Cortex free running clock
APB1 PRESC
/ 1,2,4,8,16
HSE
PCLK1
to APB1 peripherals
x1 or x2
MSI
SYSCLK
HSI16
LSE
HSI16
SYSCLK
to USARTx
X=2..5
to LPUART1
HSI RC
16 MHz
HSI16
SYSCLK
MSI RC
100 kHz – 48 MHz
PLL
MSI
HSI16
HSE
/M
/P
PLLSAI3CLK
/Q
PLL48M1CLK
/R
PLLCLK
MSI
to OCTOSPIx
x=1,2
CRS clock
APB2 PRESC
/ 1,2,4,8,16
/P
PLLSAI1CLK
/Q
PLL48M2CLK
/R
PLLADC1CLK
HSI16
x1 or x2
LSE
HSI16
SYSCLK
48 MHz clock to USB, RNG
PLLSAI2CLK
DFSDM
audio clock
/Q
PLLLCDCLK
to ADCx
X=1,2
MSI
HSI16
/M
/R
to
USART1
to SDMMCx
x=1,2
MSI
SYSCLK
/P
to APB2 peripherals
to TIMx
x=1,8,15,16,17
HSI16
PLLSAI2
to LPTIMx
x=1,2
PCLK2
/M
PLLSAI1
to I2Cx
x=1,2,3,4
LSI
LSE
HSI16
RC 48 MHz
to TIMx
x=2..7
to SAI1
HSI16
PLLSAI2DIVR
SAI1_EXTCLK
LTDC clock
to SAI2
SAI2_EXTCLK
MSv61129V2
DS12903 Rev 3
39/311
64
Functional overview
3.10
STM32L4P5xx
Clock recovery system (CRS)
The devices embed a special block which allows automatic trimming of the internal 48 MHz
oscillator to guarantee its optimal accuracy over the whole device operational range. This
automatic trimming is based on the external synchronization signal, which can be either
derived from USB SOF signalization, from LSE oscillator, from an external signal on
CRS_SYNC pin or generated by user software. For faster lock-in during startup it is also
possible to combine automatic trimming with manual trimming action.
3.11
General-purpose inputs/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be
achieved thanks to their mapping on the AHB2 bus.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
3.12
Multi-AHB bus matrix
The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, DMA2D,
SDMMC1, SDMMC2 and LCD-TFT) and the slaves (Flash memory, RAM, FSMC,
OCTOSPI, AHB and APB peripherals). It also ensures a seamless and efficient operation
even when several high-speed peripherals work simultaneously.
40/311
DS12903 Rev 3
STM32L4P5xx
Functional overview
Figure 6. Multi-AHB bus matrix
DMA1
DMA2 DMA2D LCD-TFT
SDMMC1
SDMMC2
S-bus
D-bus
I-bus
Cortex®-M4
with FPU
DCode
ACCEL
ICode
FLASH
2 MB
SRAM1
SRAM2
SRAM3
AHB1
peripherals
AHB2
peripherals
FSMC
OCTOSPI1
OCTOSPI2
BusMatrix-S
MSv61127V1
3.13
Direct memory access controller (DMA)
The device embeds 2 DMAs. Refer to Table 7: DMA implementation for the features
implementation.
Direct memory access (DMA) is used in order to provide a high-speed data transfer
between peripherals and memory as well as from memory to memory. Data can be quickly
moved by DMA without any CPU actions. This keeps the CPU resources free for other
operations.
The two DMA controllers have 14 channels in total, each one dedicated to manage memory
access requests from one or more peripherals. Each controller has an arbiter for handling
the priority between DMA requests.
DS12903 Rev 3
41/311
64
Functional overview
STM32L4P5xx
The DMA supports:
•
14 independently configurable channels (requests)
–
Each channel is connected to a dedicated hardware DMA request, a software
trigger is also supported on each channel. This configuration is done by software.
•
Priorities between requests from channels of one DMA are both software
programmable (4 levels: very high, high, medium, low) or hardware programmable in
case of equality (request 1 has priority over request 2, etc.)
•
Independent source and destination transfer size (byte, half word, word), emulating
packing and unpacking. Source/destination addresses must be aligned on the data size
•
Support for circular buffer management
•
3 event flags (DMA half transfer, DMA transfer complete and DMA transfer error)
logically ORed together in a single interrupt request for each channel
•
Memory-to-memory transfer
•
Peripheral-to-memory, memory-to-peripheral, and peripheral-to-peripheral transfers
•
Access to Flash, SRAM, APB and AHB peripherals as source and destination
•
Programmable number of data to be transferred: up to 65536
Table 7. DMA implementation
42/311
DMA features
DMA1
DMA2
Number of regular channels
7
7
DS12903 Rev 3
STM32L4P5xx
3.14
Functional overview
DMA request router (DMAMux)
When a peripheral indicates a request for DMA transfer by setting its DMA request line, the
DMA request is pending until it is served and the corresponding DMA request line is reset.
The DMA request router allows to route the DMA control lines between the peripherals and
the DMA controllers of the product.
An embedded multi-channel DMA request generator can be considered as one of such
peripherals. The routing function is ensured by a multi-channel DMA request line
multiplexer. Each channel selects a unique set of DMA control lines, unconditionally or
synchronously with events on synchronization inputs.
For simplicity, the functional description is limited to DMA request lines. The other DMA
control lines are not shown in figures or described in the text. The DMA request generator
produces DMA requests following events on DMA request trigger inputs.
3.15
Chrom-ART Accelerator (DMA2D)
Chrom-ART Accelerator (DMA2D) is a graphic accelerator that offers an advanced bit
blitting, row data copy and pixel format conversion. It supports the following functions:
•
Rectangle filling with a fixed color
•
Rectangle copy
•
Rectangle copy with pixel format conversion
•
Rectangle composition with blending and pixel format conversion.
Various image format coding are supported, from indirect 4 bpp color mode up to 32 bpp
direct color. It embeds a dedicated memory to store color lookup tables.
An interrupt can be generated when an operation is complete or at a programmed
watermark.
All the operations are fully automatized and are running independently from the CPU or the
DMAs.
3.16
Interrupts and events
3.16.1
Nested vectored interrupt controller (NVIC)
The STM32L4P5xx devices embed a nested vectored interrupt controller which is able to
manage 16 priority levels, and to handle up to 95 maskable interrupt channels plus the 16
interrupt lines of the Cortex®-M4.
The NVIC benefits are the following:
•
Closely coupled NVIC gives low latency interrupt processing
•
Interrupt entry vector table address passed directly to the core
•
Allows early processing of interrupts
•
Processing of late arriving higher priority interrupts
•
Support for tail chaining
•
Processor state automatically saved
•
Interrupt entry restored on interrupt exit with no instruction overhead
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The NVIC hardware block provides flexible interrupt management features with minimal
interrupt latency.
3.16.2
Extended interrupt/event controller (EXTI)
The extended interrupt/event controller consists of 36 edge detector lines used to generate
interrupt/event requests and to wake up the system from the Stop mode. Each external line
can be independently configured to select the trigger event (rising edge, falling edge, both)
and can be masked independently.
A pending register maintains the status of the interrupt requests. The internal lines are
connected to peripherals with wakeup from Stop mode capability. The EXTI can detect an
external line with a pulse width shorter than the internal clock period. Up to 114 GPIOs can
be connected to the 16 external interrupt lines.
3.17
Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator with polynomial value and size.
Among other applications, the CRC-based techniques are used to verify data transmission
or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a mean to verify
the Flash memory integrity.
The CRC calculation unit helps to compute a signature of the software during runtime, which
can be ulteriorly compared with a reference signature generated at link-time and which can
be stored at a given memory location.
3.18
Flexible static memory controller (FSMC)
The flexible static memory controller (FSMC) includes two memory controllers:
•
The NOR/PSRAM memory controller
•
The NAND/memory controller
This memory controller is also named flexible memory controller (FMC).
The main features of the FSMC controller are the following:
•
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Interface with static-memory mapped devices including:
–
Static random access memory (SRAM)
–
NOR Flash memory/OneNAND Flash memory
–
PSRAM (four memory banks)
–
NAND Flash memory with ECC hardware to check up to 8 Kbytes of data
–
Ferroelectric RAM (FRAM)
•
8-,16- bit data bus width
•
Independent chip select control for each memory bank
•
Independent configuration for each memory bank
•
Write FIFO
•
The Maximum FMC_CLK frequency for synchronous accesses is HCLK/2.
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Functional overview
LCD parallel interface
The FMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost
effective graphic applications using LCD modules with embedded controllers or highperformance solutions using external controllers with dedicated acceleration.
3.19
Octo-SPI interface (OCTOSPI)
The OCTOSPI is a specialized communication interface targetting single, dual, quad or octal
SPI memories. It can operate in any of the three following modes:
•
Indirect mode: all the operations are performed using the OCTOSPI registers
•
Status polling mode: the external memory status register is periodically read and an
interrupt can be generated in case of flag setting
•
Memory-mapped mode: the external memory is memory mapped and is seen by the
system as if it were an internal memory supporting read and write operation
The OCTOSPI supports two frame formats:
•
Classical frame format with command, address, alternate byte, dummy cycles and data
phase over 1, 2, 4 or 8 data pins
•
HyperBus™ frame format
The OCTOSPI offers the following features:
•
Three functional modes: indirect, status-polling, and memory-mapped
•
Read and write support in memory-mapped mode
•
Supports for single, dual, quad and octal communication
•
Dual-quad mode, where 8 bits can be sent/received simultaneously by accessing two
quad memories in parallel.
•
SDR and DTR support
•
Data strobe support
•
Fully programmable opcode for both indirect and memory mapped mode
•
Fully programmable frame format for both indirect and memory mapped mode
•
Each of the five following phases can be configured independently (enable, length,
single/dual/quad communication)
–
Instruction phase
–
Address phase
–
Alternate bytes phase
–
Dummy cycles phase
–
Data phase
•
HyperBus™ support
•
Integrated FIFO for reception and transmission
•
8, 16, and 32-bit data accesses are allowed
•
DMA channel for indirect mode operations
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3.20
STM32L4P5xx
•
Timeout management
•
Interrupt generation on FIFO threshold, timeout, status match, operation complete, and
access error
Octo-SPI IO manager (OCTOSPIIOM)
The OCTOSPI IO manager is a low level interface allowing:
•
Efficient OCTOSPI pin assignment with a full IO Matrix (before alternate function map)
•
Multiplexing single/dual/quad/octal SPI interface over the same bus
The OCTOSPI IO manager has the following features:
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•
Support up to two single/dual/quad/octal SPI Interface
•
Support up to eight ports for pin assignment
•
Fully programmable IO matrix for pin assignment by function (data/control/clock)
•
Muxer for Single/Dual/Quad/Octal SPI interface multiplexing over the same bus
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3.21
Functional overview
Analog-to-digital converter (ADC)
The device embeds two successive approximation analog-to-digital converters with the
following features:
•
12-bit native resolution, with built-in calibration
•
5.33 Msps maximum conversion rate with full resolution
Down to 18.75 ns sampling time
–
Increased conversion rate for lower resolution (up to 8.88 Msps for 6-bit
resolution)
•
Up to 16 external channels
•
5 internal channels: internal reference voltage, temperature sensor, VBAT/3,
DAC1_OUT1 and DAC1_OUT2 outputs
•
One external reference pin is available on some package, allowing the input voltage
range to be independent from the power supply
•
Single-ended and differential mode inputs
•
Low-power design
•
3.21.1
–
–
Capable of low-current operation at low conversion rate (consumption decreases
linearly with speed)
–
Dual clock domain architecture: ADC speed independent from CPU frequency
Highly versatile digital interface
–
Single-shot or continuous/discontinuous sequencer-based scan mode: 2 groups
of analog signals conversions can be programmed to differentiate background and
high-priority real-time conversions
–
Each ADC support multiple trigger inputs for synchronization with on-chip timers
and external signals
–
Results stored into a data register or in RAM with DMA controller support
–
Data pre-processing: left/right alignment and per channel offset compensation
–
Built-in oversampling unit for enhanced SNR
–
Channel-wise programmable sampling time
–
Analog watchdog for automatic voltage monitoring, generating interrupts and
trigger for selected timers
–
Hardware assistant to prepare the context of the injected channels to allow fast
context switching
Temperature sensor
The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature.
The temperature sensor is internally connected to the ADC1_IN17 input channels which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.
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Table 8. Temperature sensor calibration values
3.21.2
Calibration value name
Description
Memory address
TS_CAL1
TS ADC raw data acquired at a
temperature of 30 °C (± 5 °C),
VDDA = VREF+ = 3.0 V (± 10 mV)
0x1FFF 75A8 - 0x1FFF 75A9
TS_CAL2
TS ADC raw data acquired at a
temperature of 130 °C (± 5 °C),
VDDA = VREF+ = 3.0 V (± 10 mV)
0x1FFF 75CA - 0x1FFF 75CB
Internal voltage reference (VREFINT)
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for
the ADC and the comparators. The VREFINT is internally connected to the ADC1_IN0 input
channel. The precise voltage of VREFINT is individually measured for each part by ST
during production test and stored in the system memory area. It is accessible in read-only
mode.
Table 9. Internal voltage reference calibration values
3.21.3
Calibration value name
Description
Memory address
VREFINT
Raw data acquired at a
temperature of 30 °C (± 5 °C),
VDDA = VREF+ = 3.0 V (± 10 mV)
0x1FFF 75AA - 0x1FFF 75AB
VBAT battery voltage monitoring
This embedded hardware enables the application to measure the VBAT battery voltage using
the internal ADC channel ADC1_IN18. As the VBAT voltage may be higher than the VDDA,
and thus outside the ADC input range, the VBAT pin is internally connected to a bridge
divider by 3. As a consequence, the converted digital value is one third of the VBAT voltage.
3.22
Digital to analog converter (DAC)
Two 12-bit buffered DAC channels can be used to convert digital signals into analog voltage
signal outputs. The chosen design structure is composed of integrated resistor strings and
an amplifier in inverting configuration.
This digital interface supports the following features:
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•
Up to two DAC output channels
•
8-bit or 12-bit output mode
•
Buffer offset calibration (factory and user trimming)
•
Left or right data alignment in 12-bit mode
•
Synchronized update capability
•
Noise-wave generation
•
Triangular-wave generation
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Functional overview
•
Dual DAC channel independent or simultaneous conversions
•
DMA capability for each channel
•
External triggers for conversion
•
Sample and hold low-power mode, with internal or external capacitor
The DAC channels are triggered through the timer update outputs that are also connected
to different DMA channels.
3.23
Voltage reference buffer (VREFBUF)
The devices embed a voltage reference buffer which can be used as voltage reference for
ADC, DACs and also as voltage reference for external components through the VREF+ pin.
The internal voltage reference buffer supports two voltages:
•
2.042 V
•
2.5 V
An external voltage reference can be provided through the VREF+ pin when the internal
voltage reference buffer is off.
The VREF+ pin is double-bonded with VDDA on some packages. In these packages the
internal voltage reference buffer is not available.
Figure 7. Voltage reference buffer
VREFBUF
VDDA
Bandgap
DAC, ADC
+
VREF+
Low frequency
cut-off capacitor
100 nF
MSv40197V1
3.24
Comparators (COMP)
The devices embed two rail-to-rail comparators with programmable reference voltage
(internal or external), hysteresis and speed (low speed for low-power) and with selectable
output polarity.
The reference voltage can be one of the following:
•
External I/O
•
DAC output channels
•
Internal reference voltage or submultiple (1/4, 1/2, 3/4).
All comparators can wake up from Stop mode, generate interrupts and breaks for the timers
and can also be combined into a window comparator.
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3.25
STM32L4P5xx
Operational amplifier (OPAMP)
The devices embed two operational amplifiers with external or internal follower routing and
PGA capability.
The operational amplifier features:
3.26
•
Low input bias current
•
Low offset voltage
•
Low-power mode
•
Rail-to-rail input
Digital filter for sigma-delta modulators (DFSDM)
The STM32L4P5xx devices embed one DFSDM with two digital filters modules and four
external input serial channels (transceivers) or alternately four internal parallel inputs
support.
The DFSDM peripheral is dedicated to interface the external Σ∆ modulators to the
microcontroller and then to perform digital filtering of the received data streams (which
represent analog value on Σ∆ modulators inputs).
The DFSDM can also interface the PDM (pulse density modulation) microphones and
perform PDM to PCM conversion and filtering in hardware. The DFSDM features optional
parallel data stream inputs from microcontrollers memory (through DMA/CPU transfers into
DFSDM).
The DFSDM transceivers support several serial interface formats (to support various Σ∆
modulators) and the DFSDM digital filter modules perform digital processing according to
the user’s selected filter parameters with up to 24-bit final ADC resolution.
The DFSDM peripheral supports:
•
•
4 multiplexed input digital serial channels:
–
Configurable SPI interface to connect various SD modulator(s)
–
Configurable Manchester coded 1 wire interface support
–
PDM (pulse density modulation) microphone input support
–
Maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding)
–
Clock output for SD modulator(s): 0..20 MHz
Alternative inputs from 8 internal digital parallel channels (up to 16-bit input resolution):
–
•
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Internal sources: device memory data streams (DMA)
2 digital filter modules with adjustable digital signal processing:
–
Sincx filter: filter order/type (1..5), oversampling ratio (up to 1..1024)
–
Integrator: oversampling ratio (1..256)
•
Up to 24-bit output data resolution, signed output data format
•
Automatic data offset correction (offset stored in register by user)
•
Continuous or single conversion
•
Start-of-conversion triggered by:
–
Software trigger
–
Internal timers
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•
•
3.27
Functional overview
–
External events
–
Start-of-conversion synchronously with first digital filter module (DFSDM0)
Analog watchdog feature:
–
Low value and high-value data threshold registers
–
Dedicated configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32)
–
Input from final output data or from selected input digital serial channels
–
Continuous monitoring independently from standard conversion
Short circuit detector to detect saturated analog input values (bottom and top range):
–
Up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on serial data stream
–
Monitoring continuously each input serial channel
•
Break signal generation on analog watchdog event or on short circuit detector event
•
Extremes detector:
–
Storage of minimum and maximum values of final conversion data
–
Refreshed by software
•
DMA capability to read the final conversion data
•
Interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial
channel clock absence
•
“Regular” or “injected” conversions:
–
“Regular” conversions can be requested at any time or even in continuous mode
without having any impact on the timing of “injected” conversions
–
“Injected” conversions for precise timing and with high conversion priority
Digital camera interface (DCMI)
The devices embed a camera interface that can connect with any camera modules and
CMOS sensors through an 8-bit to 14-bit parallel interface in order to receive video data.
The camera interface can sustain a data transfer rate up to 54 Mbytes/s at 54 MHz. It
features:
•
Programmable polarity for the input pixel clock and synchronization signals
•
Parallel data communication of 8-, 10-, 12- or 14-bit
•
Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2
progressive video, RGB 565 progressive video or compressed data (like JPEG)
•
Supports continuous mode or snapshot (a single frame) mode
•
Capability to automatically crop the image.
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3.28
STM32L4P5xx
LCD-TFT controller (LTDC)
The LCD-TFT display controller provides a 24-bit parallel digital RGB (red, green, blue) and
delivers all signals to interface directly to a broad range of LCD and TFT panels with the
following features:
3.29
•
One display layer with dedicated FIFO (64 x 32-bit)
•
Color look-up table (CLUT) up to 256 colors (256 x 24-bit) per layer
•
Up to 8 input color formats selectable per layer
•
Flexible blending between two layers using alpha value (per pixel or constant)
•
Flexible programmable parameters for each layer
•
Color keying (transparency color)
•
Up to four programmable interrupt events
Touch sensing controller (TSC)
The touch sensing controller provides a simple solution to add capacitive sensing
functionality to any application. A capacitive sensing technology is able to detect finger
presence near an electrode that is protected from direct touch by a dielectric (glass, plastic
or other). The capacitive variation introduced by the finger (or any conductive object) is
measured using a proven implementation based on a surface charge transfer acquisition
principle.
The touch sensing controller is fully supported by the STMTouch touch sensing firmware
library which is free to use and allows touch sensing functionality to be implemented reliably
in the end application.
The main features of the touch sensing controller are the following:
Note:
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•
Proven and robust surface charge transfer acquisition principle
•
Supports up to 24 capacitive sensing channels
•
Up to 3 capacitive sensing channels can be acquired in parallel offering a very good
response time
•
Spread spectrum feature to improve system robustness in noisy environments
•
Full hardware management of the charge transfer acquisition sequence
•
Programmable charge transfer frequency
•
Programmable sampling capacitor I/O pin
•
Programmable channel I/O pin
•
Programmable max count value to avoid long acquisition when a channel is faulty
•
Dedicated end of acquisition and max count error flags with interrupt capability
•
One sampling capacitor for up to 3 capacitive sensing channels to reduce the system
components
•
Compatible with proximity, touchkey, linear and rotary touch sensor implementation
•
Designed to operate with STMTouch touch sensing firmware library
The number of capacitive sensing channels is dependent on the size of the packages and
subject to I/O availability.
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3.30
Functional overview
Random number generator (RNG)
All devices embed an RNG that delivers 32-bit random numbers generated by an integrated
analog circuit.
3.31
Parallel synchronous slave interface (PSSI)
The PSSI is a generic synchronous 8-/16-bit parallel data input/output slave interface. It
allows the transmitter to send a data valid signal to indicate when the data is valid, and the
receiver to output a flow control signal to indicate when it is ready to sample the data.
The PSSI main features are:
3.32
•
The PSSI shares most of the circuitry with the digital camera interface (DCMI). It thus
cannot be used simultaneously with the DCMI.
•
Slave mode operation
•
8- or 16-bit parallel data input or output
•
4-word (16-byte) FIFO
•
Data enable (DE) alternate function input and Ready (RDY) alternate function output.
When enabled, these signals can either allow the transmitter to indicate when the data
is valid or the receiver to indicate when it is ready to sample the data, or both.
HASH hardware accelerator (HASH)
The hash processor is a fully compliant implementation of the secure hash algorithm (SHA1, SHA-224, SHA-256), the MD5 (message-digest algorithm 5) hash algorithm and the
HMAC (keyed-hash message authentication code) algorithm suitable for a variety of
applications.
It computes a message digest (160 bits for the SHA-1 algorithm, 256 bits for the SHA-256
algorithm and 224 bits for the SHA-224 algorithm,128 bits for the MD5 algorithm) for
messages of up to (264 - 1) bits, while the HMAC algorithms provide a way of authenticating
messages by means of hash functions. The HMAC algorithms consist in calling the SHA-1,
SHA-224, SHA-256 or MD5 hash function twice.
3.33
Timers and watchdogs
The devices include two advanced control timers, up to nine general-purpose timers, two
basic timers, two low-power timers, two watchdog timers and a SysTick timer.
Table 10 below compares the features of the advanced control, general-purpose and basic
timers.
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Table 10. Timer feature comparison
Timer type
Timer
Counter
resolution
Counter
type
Prescaler
factor
DMA
request
generation
Capture/
compare
channels
Complementary
outputs
Advanced
control
TIM1, TIM8
16-bit
Up, down,
Up/down
Any integer
between 1
and 65536
Yes
4
3
Generalpurpose
TIM2, TIM5
32-bit
Up, down,
Up/down
Any integer
between 1
and 65536
Yes
4
No
Generalpurpose
TIM3, TIM4
16-bit
Up, down,
Up/down
Any integer
between 1
and 65536
Yes
4
No
Generalpurpose
TIM15
16-bit
Up
Any integer
between 1
and 65536
Yes
2
1
Generalpurpose
TIM16, TIM17
16-bit
Up
Any integer
between 1
and 65536
Yes
1
1
Basic
TIM6, TIM7
16-bit
Up
Any integer
between 1
and 65536
Yes
0
No
3.33.1
Advanced-control timer (TIM1, TIM8)
The advanced-control timers can each be seen as a three-phase PWM multiplexed on six
channels. They have complementary PWM outputs with programmable inserted deadtimes. They can also be seen as complete general-purpose timers.
The four independent channels can be used for:
•
Input capture
•
Output compare
•
PWM generation (edge or center-aligned modes) with full modulation capability (0100%)
•
One-pulse mode output
In debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled in order to turn off any power switches driven by these outputs.
Many features are shared with the general-purpose TIMx timers (described in
Section 3.33.2) using the same architecture, so the advanced-control timers can work
together with the TIMx timers via the Timer Link feature for synchronization or event
chaining.
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3.33.2
Functional overview
General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16,
TIM17)
There are up to seven synchronizable general-purpose timers embedded in the devices
(see Table 10 for differences).
Each general-purpose timer can be used to generate PWM outputs, or act as a simple time
base.
•
TIM2, TIM3, TIM4 and TIM5
They are full-featured general-purpose timers:
–
TIM2 and TIM5 have a 32-bit auto-reload up/downcounter and 32-bit prescaler
–
TIM3 and TIM4 have 16-bit auto-reload up/downcounter and 16-bit prescaler.
These timers feature four independent channels for input capture/output compare,
PWM or one-pulse mode output. They can work together, or with the other generalpurpose timers via the Timer Link feature for synchronization or event chaining.
The counters can be frozen in debug mode.
All have independent DMA request generation and support quadrature encoders.
•
TIM15, 16 and 17
They are general-purpose timers with mid-range features:
They have 16-bit auto-reload upcounters and 16-bit prescalers.
–
TIM15 has two channels and one complementary channel
–
TIM16 and TIM17 have one channel and one complementary channel
All channels can be used for input capture/output compare, PWM or one-pulse mode
output.
The timers can work together via the Timer Link feature for synchronization or event
chaining. The timers have independent DMA request generation.
The counters can be frozen in debug mode.
3.33.3
Basic timers (TIM6 and TIM7)
The basic timers are mainly used for DAC trigger generation. They can also be used as
generic 16-bit timebases.
3.33.4
Low-power timer (LPTIM1 and LPTIM2)
The devices embed two low-power timers. These timers have an independent clock and are
running in Stop mode if they are clocked by LSE, LSI or an external clock. They are able to
wakeup the system from Stop mode.
LPTIM1 and LPTIM2 can be active in Stop 0, Stop 1 and Stop 2 modes.
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This low-power timer supports the following features:
3.33.5
•
16-bit up counter with 16-bit autoreload register
•
16-bit compare register
•
Configurable output: pulse, PWM
•
Continuous/ one shot mode
•
Selectable software/hardware input trigger
•
Selectable clock source
–
Internal clock sources: LSE, LSI, HSI16 or APB clock
–
External clock source over LPTIM input (working even with no internal clock
source running, used by pulse counter application).
•
Programmable digital glitch filter
•
Encoder mode (LPTIM1 only)
•
Repetition counter.
Independent watchdog (IWDG)
The independent watchdog is based on a 12-bit downcounter and an 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC (LSI) and as it operates independently
from the main clock, it can operate in Stop and Standby modes. It can be used either as a
watchdog to reset the device when a problem occurs, or as a free running timer for
application timeout management. It is hardware or software configurable through the option
bytes. The counter can be frozen in debug mode.
3.33.6
Window watchdog (WWDG)
The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
3.33.7
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
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•
A 24-bit down counter
•
Autoreload capability
•
Maskable system interrupt generation when the counter reaches 0.
•
Programmable clock source
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3.34
Functional overview
Real-time clock (RTC) and backup registers
The RTC is an independent BCD timer/counter. It supports the following features:
•
Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format
•
Automatic correction for 28, 29 (leap year), 30, and 31 days of the month
•
Two programmable alarms
•
On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock
•
Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision
•
Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy
•
Three anti-tamper detection pins with programmable filter
•
Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
VBAT mode
•
17-bit auto-reload wakeup timer (WUT) for periodic events with programmable
resolution and period
The RTC and the 32 backup registers are supplied through a switch that takes power either
from the VDD supply when present or from the VBAT pin.
The backup registers are 32-bit registers used to store 128 bytes of user application data
when VDD power is not present. They are not reset by a system or power reset, or when the
device wakes up from standby or Shutdown mode.
The RTC clock sources can be:
•
A 32.768 kHz external crystal (LSE)
•
An external resonator or oscillator (LSE)
•
The internal low-power RC oscillator (LSI, with typical frequency of 32 kHz)
•
The high-speed external clock (HSE) divided by 32
The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the
LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in
all low-power modes except Shutdown mode.
All RTC events (alarm, wake-up timer, Timestamp or Tamper) can generate an interrupt and
wakeup the device from the low-power modes.
DS12903 Rev 3
57/311
64
Functional overview
3.35
STM32L4P5xx
Inter-integrated circuit interface (I2C)
The device embeds four I2C. Refer to Table 11: I2C implementation for the features
implementation.
The I2C bus interface handles communications between the microcontroller and the serial
I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
•
•
I2C-bus specification and user manual rev. 5 compatibility:
–
Slave and master modes, multimaster capability
–
Standard-mode (Sm), with a bitrate up to 100 kbit/s
–
Fast-mode (Fm), with a bitrate up to 400 kbit/s
–
Fast-mode plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os
–
7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
–
Programmable setup and hold times
–
Optional clock stretching
System management bus (SMBus) specification rev 2.0 compatibility:
–
Hardware PEC (packet error checking) generation and verification with ACK
control
–
Address resolution protocol (ARP) support
–
SMBus alert
•
Power system management protocol (PMBusTM) specification rev 1.1 compatibility
•
Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming. Refer to
Figure 5: Clock tree
•
Wakeup from Stop mode on address match
•
Programmable analog and digital noise filters
•
1-byte buffer with DMA capability
Table 11. I2C implementation
I2C features(1)
I2C1
I2C2
I2C3
I2C4
Standard-mode (up to 100 kbit/s)
X
X
X
X
Fast-mode (up to 400 kbit/s)
X
X
X
X
Fast-mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s)
X
X
X
X
Programmable analog and digital noise filters
X
X
X
X
SMBus/PMBus hardware support
X
X
X
X
Independent clock
X
X
X
X
Wakeup from Stop 0, Stop 1 mode on address match
X
X
X
X
Wakeup from Stop 2 mode on address match
-
-
X
-
1. X: supported
58/311
DS12903 Rev 3
STM32L4P5xx
3.36
Functional overview
Universal synchronous/asynchronous receiver transmitter
(USART)
The devices have three embedded universal synchronous receiver transmitters (USART1,
USART2 and USART3) and two universal asynchronous receiver transmitters (UART4,
UART5).
These interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN master/slave capability. They provide hardware management of the CTS and RTS
signals, and RS485 driver enable. They are able to communicate at speeds of up to
10 Mbit/s.
The USART1, USART2 and USART3 also provide a Smartcard mode (ISO 7816 compliant)
and an SPI-like communication capability.
All USART have a clock domain independent from the CPU clock, allowing the USARTx
(x=1,2,3,4,5) to wake up the MCU from Stop mode using baudrates up to 200 Kbaud. The
wake up events from Stop mode are programmable and can be:
•
Start bit detection
•
Any received data frame
•
A specific programmed data frame
All USART interfaces can be served by the DMA controller.
Table 12. USART/UART/LPUART features
USART modes/features(1)
USART1 USART2 USART3
UART4
UART5
LPUART1
Hardware flow control for modem
X
X
X
X
X
X
Continuous communication using DMA
X
X
X
X
X
X
Multiprocessor communication
X
X
X
X
X
X
Synchronous mode
X
X
X
-
-
-
Smartcard mode
X
X
X
-
-
-
Single-wire half-duplex communication
X
X
X
X
X
X
IrDA SIR ENDEC block
X
X
X
X
X
-
LIN mode
X
X
X
X
X
-
Dual clock domain
X
X
X
X
X
X
Wakeup from Stop 0 / Stop 1 modes
X
X
X
X
X
X
Wakeup from Stop 2 mode
-
-
-
-
-
X
Receiver timeout interrupt
X
X
X
X
X
-
Modbus communication
X
X
X
X
X
-
Auto baud rate detection
Driver enable
X (4 modes)
X
X
LPUART/USART data length
X
X
X
X
7, 8 and 9 bits
1. X = supported.
DS12903 Rev 3
59/311
64
Functional overview
3.37
STM32L4P5xx
Low-power universal asynchronous receiver transmitter
(LPUART)
The devices embed one low-power UART. The LPUART supports asynchronous serial
communication with minimum power consumption. It supports half-duplex single-wire
communication and modem operations (CTS/RTS). It allows multiprocessor
communication.
The LPUART has a clock domain independent from the CPU clock, and can wakeup the
system from Stop mode using baudrates up to 220 Kbaud. The wake up events from Stop
mode are programmable and can be:
•
Start bit detection
•
Any received data frame
•
A specific programmed data frame
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600
baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while
having an extremely low energy consumption. Higher speed clock can be used to reach
higher baudrates.
The LPUART interface can be served by the DMA controller.
3.38
Serial peripheral interface (SPI)
Three SPI interfaces allow communication up to slave modes, in half-duplex, full-duplex and
simplex modes. The 3-bit prescaler gives eight master mode frequencies and the frame size
is configurable from 4 bits to 16 bits. The SPI interfaces support NSS pulse mode, TI mode
and hardware CRC calculation.
All SPI interfaces can be served by the DMA controller.
3.39
Serial audio interfaces (SAI)
The devices embed two SAI. Refer to Table 13: SAI implementation for the features
implementation. The SAI bus interface handles communications between the
microcontroller and the serial audio protocol.
The SAI peripheral supports:
60/311
•
Two independent audio sub-blocks which can be transmitters or receivers with their
respective FIFO.
•
8-word integrated FIFOs for each audio sub-block.
•
Synchronous or asynchronous mode between the audio sub-blocks.
•
Master or slave configuration independent for both audio sub-blocks.
•
Clock generator for each audio block to target independent audio frequency sampling
when both audio sub-blocks are configured in master mode.
•
Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit.
•
Peripheral with large configurability and flexibility allowing to target as example the
following audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF
out.
DS12903 Rev 3
STM32L4P5xx
Functional overview
•
Up to 16 slots available with configurable size and with the possibility to select which
ones are active in the audio frame.
•
Number of bits by frame may be configurable.
•
Frame synchronization active level configurable (offset, bit length, level).
•
First active bit position in the slot is configurable.
•
LSB first or MSB first for data transfer.
•
Mute mode.
•
Stereo/Mono audio frame capability.
•
Communication clock strobing edge configurable (SCK).
•
Error flags with associated interrupts if enabled respectively.
•
•
–
Overrun and underrun detection.
–
Anticipated frame synchronization signal detection in slave mode.
–
Late frame synchronization signal detection in slave mode.
–
Codec not ready for the AC’97 mode in reception.
Interruption sources when enabled:
–
Errors.
–
FIFO requests.
DMA interface with two dedicated channels to handle access to the dedicated
integrated FIFO of each SAI audio sub-block.
Table 13. SAI implementation
SAI features(1)
SAI1
SAI2
I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97
X
X
Mute mode
X
X
Stereo/Mono audio frame capability.
X
X
16 slots
X
X
Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit
X
X
X (8 Word)
X (8 Word)
SPDIF
X
X
PDM
X
-
FIFO size
1. X: supported
3.40
Secure digital input/output and MultiMediaCards Interface
(SDMMC)
The devices embed two SDMMC host interfaces. Each SDMMC host interface embeds a
dedicated DMA controller allowing high-speed transfers between the interface and the other
AHB slaves.
The SD/SDIO, MultiMediaCard (MMC) host interface (SDMMC) provides an interface
between the AHB bus and SD memory cards, SDIO cards and MMC devices.
DS12903 Rev 3
61/311
64
Functional overview
STM32L4P5xx
The SDMMC features include the following:
3.41
•
Full compliance with MultiMediaCard System Specification Version 4.51. Card support
for three different databus modes: 1-bit (default), 4-bit and 8-bit
•
Full compatibility with previous versions of MultiMediaCards (backward compatibility)
•
Full compliance with SD Memory Card Specifications Version 4.1. (SDR104
SDMMC_CK speed limited to maximum allowed IO speed, SPI mode and UHS-II mode
not supported)
•
Full compliance with SDIO Card Specification Version 4.0: card support for two different
databus modes: 1-bit (default) and 4-bit. (SDR104 SDMMC_CK speed limited to
maximum allowed IO speed, SPI mode and UHS-II mode not supported)
•
Data transfer up to 104 Mbyte/s for the 8-bit mode (depending maximum allowed IO
speed)
•
Data and command output enable signals to control external bidirectional drivers.
Controller area network (CAN)
The CAN is compliant with the 2.0A and B (active) specifications with a bit rate of up to
1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as
extended frames with 29-bit identifiers. The CAN has three transmit mailboxes, two receive
FIFOS with three stages and 28 shared scalable filter banks (all of them can be used even if
one CAN is used). 256 bytes of SRAM are allocated.
The CAN peripheral supports:
•
CAN protocol version 2.0 A, B Active
•
Bit rates of up to 1 Mbit/s
•
Transmission
•
•
•
62/311
–
Three transmit mailboxes
–
Configurable transmit priority
Reception
–
Two receive FIFOs with three stages
–
Scalable filter banks: 28 filter banks
–
Identifier list feature
–
Configurable FIFO overrun
Time-triggered communication option
–
Disable automatic retransmission mode
–
16-bit free running timer
–
Time Stamp sent in last two data bytes
Management
–
Maskable interrupts
–
Software-efficient mailbox mapping at a unique address space
DS12903 Rev 3
STM32L4P5xx
3.42
Functional overview
Universal serial bus on-the-go full-speed (OTG_FS)
The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated
transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and
with the OTG 2.0 specification. It has software-configurable endpoint setting and supports
suspend/resume.
The USB OTG controller requires a dedicated 48 MHz clock that can be provided by the
internal multispeed oscillator (MSI) automatically trimmed by 32.768 kHz external oscillator
(LSE).This allows to use the USB device without external high speed crystal (HSE).
The major features are:
•
Combined Rx and Tx FIFO size of 1.25 Kbytes with dynamic FIFO sizing
•
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
•
One bidirectional control endpoint + 5 IN endpoints + 5 OUT endpoints
•
Eight host channels with periodic OUT support
•
HNP/SNP/IP inside (no need for any external resistor)
•
Software configurable to OTG 1.3 and OTG 2.0 modes of operation
•
OTG 2.0 Supports ADP (Attach detection Protocol)
•
USB 2.0 LPM (Link Power Management) support
•
Battery charging specification revision 1.2 support
•
Internal FS OTG PHY support
For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected.
The synchronization for this oscillator can also be taken from the USB data stream itself
(SOF signalization) which allows crystal less operation.
3.43
Development support
3.43.1
Serial wire JTAG debug port (SWJ-DP)
The Arm® SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using two pins only instead of five required by the JTAG (JTAG pins
could be re-used as GPIO with alternate function): the JTAG TMS and TCK pins are shared
with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.
DS12903 Rev 3
63/311
64
Functional overview
3.43.2
STM32L4P5xx
Embedded Trace Macrocell™
The Arm® Embedded Trace Macrocell provides a greater visibility of the instruction and data
flow inside the CPU core by streaming compressed data at a very high rate from the
devices through a small number of ETM pins to an external hardware trace port analyzer
(TPA) device. Real-time instruction and data flow activity being recorded and then formatted
for display on the host computer that runs the debugger software. TPA hardware is
commercially available from common development tool vendors.
The Embedded Trace Macrocell operates with third party debugger software tools.
64/311
DS12903 Rev 3
STM32L4P5xx
Pinouts and pin description
VDD
VSS
PB9
PB8
PH3-BOOT0
PB7
PB6
PB5
PB4
PB3
PA15
PA14
48
47
46
45
44
43
42
41
40
39
38
37
Figure 8. STM32L4P5Cxxx LQFP48 pinout(1)
VBAT
1
36
VDDUSB
PC13
2
35
VSS
PC14-OSC32_IN
3
34
PA13
PC15-OSC32_OUT
4
33
PA12
PH0-OSC_IN
5
32
PA11
PH1-OSC_OUT
6
31
PA10
NRST
7
30
PA9
VSSA/VREF-
8
29
PA8
VDDA/VREF+
9
28
PB15
PA0
10
27
PB14
PA1
11
26
PB13
PA2
12
25
PB12
13
14
15
16
17
18
19
20
21
22
23
24
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB10
PB11
VSS
VDD
LQFP48
MSv62912V1
1. The above figure shows the package top view.
VDD
VSS
VDD12
PB9
PH3-BOOT0
PB7
PB6
PB5
PB4
PB3
PA15
PA14
48
47
46
45
44
43
42
41
40
39
38
37
Figure 9. STM32L4P5CxxxP external SMPS LQFP48 pinout(1)
VBAT
1
36
VDDUSB
PC13
2
35
VSS
PC14-OSC32_IN
3
34
PA13
PC15-OSC32_OUT
4
33
PA12
PH0-OSC_IN
5
32
PA11
PH1-OSC_OUT
6
31
PA10
NRST
7
30
PA9
VSSA/VREF-
8
29
PA8
VDDA/VREF+
9
28
PB15
PA0
10
27
PB14
PA1
11
26
PB13
PA2
12
25
PB12
13
14
15
16
17
18
19
20
21
22
23
24
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB10
VDD12
VSS
VDD
LQFP48
PA3
4
Pinouts and pin description
MSv62913V1
1. The above figure shows the package top view.
DS12903 Rev 3
65/311
74
Pinouts and pin description
STM32L4P5xx
VDD
VSS
PB9
PB8
PH3-BOOT0
PB7
PB6
PB5
PB4
PB3
PA15
PA14
48
47
46
45
44
43
42
41
40
39
38
37
Figure 10. STM32L4P5Cxxx UFQFPN48 pinout(1)
VBAT
1
36
VDDUSB
PC13
2
35
VSS
PC14-OSC32_IN
3
34
PA13
PC15-OSC32_OUT
4
33
PA12
PH0-OSC_IN
5
32
PA11
PH1-OSC_OUT
6
31
PA10
NRST
7
30
PA9
VSSA/VREF-
8
29
PA8
VDDA/VREF+
9
28
PB15
PA0
10
27
PB14
PA1
11
26
PB13
PA2
12
25
PB12
13
14
15
16
17
18
19
20
21
22
23
24
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB10
PB11
VSS
VDD
UFQFPN48
MSv62914V1
1. The above figure shows the package top view.
VDD
VSS
VDD12
PB9
PH3-BOOT0
PB7
PB6
PB5
PB4
PB3
PA15
PA14
48
47
46
45
44
43
42
41
40
39
38
37
Figure 11. STM32L4P5CxxxP external SMPS UFQFPN48 pinout(1)
VBAT
1
36
VDDUSB
PC13
2
35
VSS
PC14-OSC32_IN
3
34
PA13
PC15-OSC32_OUT
4
33
PA12
PH0-OSC_IN
5
32
PA11
PH1-OSC_OUT
6
31
PA10
NRST
7
30
PA9
VSSA/VREF-
8
29
PA8
VDDA/VREF+
9
28
PB15
PA0
10
27
PB14
PA1
11
26
PB13
PA2
12
25
PB12
13
14
15
16
17
18
19
20
21
22
23
24
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB10
VDD12
VSS
VDD
UFQFPN48
1. The above figure shows the package top view.
66/311
DS12903 Rev 3
MSv62915V1
STM32L4P5xx
Pinouts and pin description
VDD
VSS
PB9
PB8
PH3-BOOT0
PB7
PB6
PB5
PB4
PB3
PD2
PC12
PC11
PC10
PA15
PA14
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
Figure 12. STM32L4P5Rxxx LQFP64 pinout(1)
VBAT
1
48
VDDUSB
PC13
2
47
VSS
PC14-OSC32_IN
3
46
PA13
PC15-OSC32_OUT
4
45
PA12
PH0-OSC_IN
5
44
PA11
PH1-OSC_OUT
6
43
PA10
NRST
7
42
PA9
PC0
8
41
PA8
PC1
9
40
PC9
PC2
10
39
PC8
PC3
11
38
PC7
VSSA/VREF-
12
37
PC6
VDDA/VREF+
13
36
PB15
PA0
14
35
PB14
PA1
15
34
PB13
PA2
16
33
PB12
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PA3
VSS
VDD
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PB10
PB11
VSS
VDD
LQFP64
MSv62910V1
1. The above figure shows the package top view.
VDD
VSS
VDD12
PB9
PB8
PH3-BOOT0
PB7
PB6
PB5
PB4
PB3
PC12
PC11
PC10
PA15
PA14
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
Figure 13. STM32L4P5RxxxP external SMPS LQFP64 pinout(1)
VBAT
1
48
VDDUSB
PC13
2
47
VSS
PC14-OSC32_IN
3
46
PA13
PC15-OSC32_OUT
4
45
PA12
PH0-OSC_IN
5
44
PA11
PH1-OSC_OUT
6
43
PA10
NRST
7
42
PA9
PC0
8
41
PA8
PC1
9
40
PC9
PC2
10
39
PC8
PC3
11
38
PC7
VSSA/VREF-
12
37
PC6
VDDA/VREF+
13
36
PB15
PA0
14
35
PB14
PA1
15
34
PB13
PA2
16
33
PB12
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PA3
VSS
VDD
PA4
PA5
PA6
PA7
PC4
PB0
PB1
PB2
PB10
PB11
VDD12
VSS
VDD
LQFP64
MSv62911V1
1. The above figure shows the package top view.
DS12903 Rev 3
67/311
74
Pinouts and pin description
STM32L4P5xx
VDD
VSS
PE1
PE0
PB9
PB8
PH3-BOOT0
PB7
PB6
PB5
PB4
PB3
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
Figure 14. STM32L4P5Vxxx LQFP100 pinout(1)
PE2
1
75
VDD
PE3
2
74
VSS
PE4
3
73
VDDUSB
PE5
4
72
PA13
PE6
5
71
PA12
VBAT
6
70
PA11
PC13
7
69
PA10
PC14-OSC32_IN
8
68
PA9
PC15-OSC32_OUT
9
67
PA8
VSS
10
66
PC9
VDD
11
65
PC8
PH0-OSC_IN
12
64
PC7
PH1-OSC_OUT
13
63
PC6
NRST
14
62
PD15
PC0
15
61
PD14
PC1
16
60
PD13
PC2
17
59
PD12
PC3
18
58
PD11
VSSA
19
57
PD10
VREF-
20
56
PD9
VREF+
21
55
PD8
VDDA
22
54
PB15
PA0
23
53
PB14
PA1
24
52
PB13
PA2
25
51
PB12
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PA3
VSS
VDD
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VSS
VDD
LQFP100
MSv62908V1
1. The above figure shows the package top view.
68/311
DS12903 Rev 3
STM32L4P5xx
Pinouts and pin description
VDD
VSS
VDD12
PE0
PB9
PB8
PH3-BOOT0
PB7
PB6
PB5
PB4
PB3
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
Figure 15. STM32L4P5VxxxP external SMPS LQFP100 pinout(1)
PE2
1
75
VDD
PE3
2
74
VSS
PE4
3
73
VDDUSB
PE5
4
72
PA13
PE6
5
71
PA12
VBAT
6
70
PA11
PC13
7
69
PA10
PC14-OSC32_IN
8
68
PA9
PC15-OSC32_OUT
9
67
PA8
VSS
10
66
PC9
VDD
11
65
PC8
PH0-OSC_IN
12
64
PC7
PH1-OSC_OUT
13
63
PC6
NRST
14
62
PD15
PC0
15
61
PD14
PC1
16
60
PD13
PC2
17
59
PD12
PC3
18
58
PD11
VSSA
19
57
PD10
VREF-
20
56
PD9
VREF+
21
55
PD8
VDDA
22
54
PB15
PA0
23
53
PB14
PA1
24
52
PB13
PA2
25
51
PB12
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PA3
VSS
VDD
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PB10
VDD12
VSS
VDD
LQFP100
1. The above figure shows the package top view.
Figure 16. STM32L4P5Vxxx WLCSP100 ballout(1)
1
2
3
4
5
6
7
8
9
10
A
VDDUSB
PA15
PD1
VDD
PG10
VDDIO2
PB6
PB9
VSS
VDD
B
VSS
PA14
PD0
PD4
PG9
PG12
PB5
PB8
PE2
PE3
C
PA12
PA13
PC11
PC12
PD7
PB3
PB4
PE4
PC13
VBAT
D
PA11
PA10
PA9
PC10
PD6
PG11
PB7
PE5
VSS
PC14OSC32_IN
E
PC8
PC9
PA8
PD2
PD5
PH3-BOOT0
PE6
NRST
VDD
PC15OSC32_OUT
F
VDD
PC6
PC7
PD15
PB2
PA4
PC3
PC1
PC0
PH0-OSC_IN
G
PD10
PD9
PD14
PE13
PE12
PA5
VREF+
VREF-
PA0
PH1OSC_OUT
H
PB15
PB14
PD8
PE15
PE10
PC4
PA2
PA1
VSSA
PC2
J
PB12
PB13
PB11
PE14
PE9
PB0
PA7
VDD
PA3
VDDA
K
VDD
VSS
PB10
PE11
PE8
PE7
PB1
PC5
PA6
VSS
MSv62906V1
1. The above figure shows the package top view.
DS12903 Rev 3
69/311
74
Pinouts and pin description
STM32L4P5xx
Figure 17. STM32L4P5VxxxP external SMPS WLCSP100 ballout(1)
1
2
3
4
5
6
7
8
9
10
A
VDDUSB
PA15
PD1
VDD
PG10
VDDIO2
PB6
PB9
VDD12
VDD
B
VSS
PA14
PD0
PD5
PD6
PG12
PB7
PB8
VSS
PE3
C
PA12
PA13
PC10
PC12
PD4
PD7
PB5
PE2
PC13
VBAT
D
PA11
PA10
PA9
PC11
PD2
PG9
PH3-BOOT0
PE6
PC15OSC32_OUT
PC14OSC32_IN
E
PC8
PC9
PA8
PC7
PG11
PB4
PE4
PE5
VDD
VSS
PH0-OSC_IN
F
VDD
PD15
PD14
PC6
PB3
PC3
PC1
NRST
PH1OSC_OUT
G
PD10
PD9
PD8
PE14
PE13
PA7
PA1
PA0
PC2
PC0
H
PB14
PB13
PB15
PE15
PE10
PB0
PA4
PA2
VSSA/VREF-
VREF+
J
PB12
VDD
PB11
PE12
PE9
PB2
PA5
VDD
PA3
VDDA
K
VDD12
VSS
PB10
PE11
PE8
PE7
PB1
PC4
PA6
VSS
MSv62907V1
1. The above figure shows the package top view.
Figure 18. STM32L4P5Qxxx UFBGA132 ballout(1)
1
2
3
4
5
6
7
8
9
10
11
12
A
PE3
PE1
PB8
PH3-BOOT0
PD7
PD5
PB4
PB3
PA15
PA14
PA13
PA12
B
PE4
PE2
PB9
PB7
PB6
PD6
PD4
PD3
PD1
PC12
PC10
PA11
C
PC13
PE5
PE0
VDD
PB5
PG14
PG13
PD2
PD0
PC11
VDDUSB
PA10
D
PC14OSC32_IN
PE6
VSS
PF2
PF1
PF0
PG12
PG10
PG9
PA9
PA8
PC9
E
PC15OSC32_OUT
VBAT
VSS
PF3
PG5
PC8
PC7
PC6
F
PH0-OSC_IN
VSS
PF4
PF5
VSS
VSS
PG3
PG4
VSS
VSS
G
PH1OSC_OUT
VDD
PG11
PG6
VDD
VDDIO2
PG1
PG2
VDD
VDD
H
PC0
NRST
VDD
PG7
PG0
PD15
PD14
PD13
J
VSSA/VREF-
PC1
PC2
PA4
PA7
PG8
PF12
PF14
PF15
PD12
PD11
PD10
K
PG15
PC3
PA2
PA5
PC4
PF11
PF13
PD9
PD8
PB15
PB14
PB13
L
VREF+
PA0
PA3
PA6
PC5
PB2
PE8
PE10
PE12
PB10
PB11
PB12
PA1
OPAMP1_VI
NM
OPAMP2_VI
NM
PB0
PB1
PE7
PE9
PE11
PE13
PE14
PE15
M
VDDA
MSv62904V1
1. The above figure shows the package top view.
70/311
DS12903 Rev 3
STM32L4P5xx
Pinouts and pin description
Figure 19. STM32L4P5QxxxP external SMPS UFBGA132 ballout(1)
1
2
3
4
5
6
7
8
9
10
11
12
A
PE3
PE1
PB8
PH3-BOOT0
PD7
PD5
PB4
PB3
PA15
PA14
PA13
PA12
B
PE4
PE2
PB9
PB7
PB6
PD6
PD4
PD3
PD1
PC12
PC10
PA11
C
PC13
PE5
PE0
VDD
PB5
VDD12
PG13
PD2
PD0
PC11
VDDUSB
PA10
D
PC14OSC32_IN
PE6
VSS
PF2
PF1
PF0
PG12
PG10
PG9
PA9
PA8
PC9
E
PC15OSC32_OUT
VBAT
VSS
PF3
PG5
PC8
PC7
PC6
F
PH0-OSC_IN
VSS
PF4
PF5
VSS
VSS
PG3
PG4
VSS
VSS
G
PH1OSC_OUT
VDD
PG11
PG6
VDD
VDDIO2
PG1
PG2
VDD
VDD
H
PC0
NRST
VDD
PG7
PG0
PD15
PD14
PD13
J
VSSA/VREF-
PC1
PC2
PA4
PA7
PG8
PF12
PF14
PF15
PD12
PD11
PD10
K
PG15
PC3
PA2
PA5
PC4
PF11
PF13
PD9
PD8
PB15
PB14
PB13
L
VREF+
PA0
PA3
PA6
PC5
PB2
PE8
PE10
PE12
PB10
VDD12
PB12
M
VDDA
PA1
OPAMP1_VI
NM
OPAMP2_VI
NM
PB0
PB1
PE7
PE9
PE11
PE13
PE14
PE15
MSv62905V1
1. The above figure shows the package top view.
DS12903 Rev 3
71/311
74
Pinouts and pin description
STM32L4P5xx
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
VDD
VSS
PE1
PE0
PB9
PB8
PH3-BOOT0
PB7
PB6
PB5
PB4
PB3
PG15
VDDIO2
VSS
PG14
PG13
PG12
PG11
PG10
PG9
PD7
PD6
VDD
VSS
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
Figure 20. STM32L4P5Zxxx LQFP144 pinout(1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
LQFP144
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
VDD
VSS
VDDUSB
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
VDDIO2
VSS
PG8
PG7
PG6
PG5
PG4
PG3
PG2
PD15
PD14
VDD
VSS
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12
PA3
VSS
VDD
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PF11
PF12
VSS
VDD
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
VSS
VDD
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VSS
VDD
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
PE2
PE3
PE4
PE5
PE6
VBAT
PC13
PC14-OSC32_IN
PC15-OSC32_OUT
PF0
PF1
PF2
PF3
PF4
PF5
VSS
VDD
PF6
PF7
PF8
PF9
PF10
PH0-OSC_IN
PH1-OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA
VREFVREF+
VDDA
PA0
PA1
PA2
MSv62902V1
1. The above figure shows the package top view.
72/311
DS12903 Rev 3
STM32L4P5xx
Pinouts and pin description
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
VDD
VSS
VDD12
PE1
PE0
PB9
PB8
PH3-BOOT0
PB7
PB6
PB5
PB4
PB3
VDDIO2
VSS
PG14
PG13
PG12
PG11
PG10
PG9
PD7
PD6
VDD
VSS
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
Figure 21. STM32L4P5ZxxxP external SMPS LQFP144 pinout(1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
LQFP144
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
VDD
VSS
VDDUSB
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
VDDIO2
VSS
PG8
PG7
PG6
PG5
PG4
PG3
PG2
PD15
PD14
VDD
VSS
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12
PA3
VSS
VDD
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PF11
PF12
VSS
VDD
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
VSS
VDD
PE10
PE11
PE12
PE13
PE14
PE15
PB10
VDD12
VSS
VDD
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
PE2
PE3
PE4
PE5
PE6
VBAT
PC13
PC14-OSC32_IN
PC15-OSC32_OUT
PF0
PF1
PF2
PF3
PF4
PF5
VSS
VDD
PF6
PF7
PF8
PF9
PF10
PH0-OSC_IN
PH1-OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA
VREFVREF+
VDDA
PA0
PA1
PA2
MSv62903V1
1. The above figure shows the package top view.
DS12903 Rev 3
73/311
74
Pinouts and pin description
STM32L4P5xx
Figure 22. STM32L4P5Axxx UFBGA169 ballout(1)
1
2
3
4
5
6
7
8
9
10
11
12
13
A
PI10
PH2
VDD
PE0
PB4
PB3
VSS
VDD
PA15
PA14
PA13
PI0
PH14
B
PI9
PI7
VSS
PE1
PB5
VDDIO2
PG9
PD0
PI6
PI2
PI1
PH15
PH12
C
VDD
VSS
PI11
PB8
PB6
PG15
PD4
PD1
PH13
PI3
PI8
VSS
VDD
D
PE4
PE3
PE2
PB9
PB7
PG10
PD5
PD2
PC10
PI4
PH9
PH7
PA12
E
PC13
VBAT
PE6
PE5
PH3-BOOT0
PG11
PD6
PD3
PC11
PI5
PH6
VDDUSB
PA11
F
PC14OSC32_IN
VSS
PF2
PF1
PF0
PG12
PD7
PC12
PA10
PA9
PC6
VDDIO2
VSS
G
PC15OSC32_OUT
VDD
PF3
PF4
PF5
PG14
PG13
PA8
PC9
PC8
PG6
PC7
VDD
H
PH0-OSC_IN
VSS
NRST
PF10
PC4
PG1
PE10
PB11
PG8
PG7
PD15
VSS
VDD
J
PH1OSC_OUT
PC0
PC1
PC2
PC5
PG0
PE9
PE15
PG5
PG4
PG3
PG2
PD10
K
PC3
VSSA/VREF-
PA0
PA5
PB0
PF15
PE8
PE14
PH4
PD14
PD12
PD11
PD13
L
VREF+
VDDA
PA4
PA7
PB1
PF14
PE7
PE13
PH5
PD9
PD8
VDD
VSS
M
OPAMP1_VI
NM
PA3
VSS
PA6
PF11
PF13
VSS
PE12
PH10
PH11
VSS
PB15
PB14
VDD
OPAMP2_VI
NM
PB2
PF12
VDD
PE11
PB10
PH8
VDD
PB12
N
PA2
PA1
PB13
MSv62900V1
1. The above figure shows the package top view.
Figure 23. STM32L4P5AxxxP UFBGA169 external SMPS ballout(1)
1
2
3
4
5
6
7
8
9
10
11
12
13
A
PI10
PH2
VDD
PE0
PB4
PB3
VSS
VDD
PA15
PA14
PA13
PI0
PH14
B
PI9
PI7
VSS
PE1
PB5
VDDIO2
PG9
PD0
PI6
PI2
PI1
PH15
PH12
C
VDD
VSS
PI11
PB8
PB6
VDD12
PD4
PD1
PH13
PI3
PI8
VSS
VDD
D
PE4
PE3
PE2
PB9
PB7
PG10
PD5
PD2
PC10
PI4
PH9
PH7
PA12
E
PC13
VBAT
PE6
PE5
PH3-BOOT0
PG11
PD6
PD3
PC11
PI5
PH6
VDDUSB
PA11
F
PC14OSC32_IN
VSS
PF2
PF1
PF0
PG12
PD7
PC12
PA10
PA9
PC6
VDDIO2
VSS
G
PC15OSC32_OUT
VDD
PF3
PF4
PF5
PG14
PG13
PA8
PC9
PC8
PG6
PC7
VDD
H
PH0-OSC_IN
VSS
NRST
PF10
PC4
PG1
PE10
PB11
PG8
PG7
PD15
VSS
VDD
J
PH1OSC_OUT
PC0
PC1
PC2
PC5
PG0
PE9
PE15
PG5
PG4
PG3
PG2
PD10
K
PC3
VSSA/VREF-
PA0
PA5
PB0
PF15
PE8
PE14
PH4
PD14
PD12
PD11
PD13
L
VREF+
VDDA
PA4
PA7
PB1
PF14
PE7
PE13
PH5
PD9
PD8
VDD
VSS
M
OPAMP1_VI
NM
PA3
VSS
PA6
PF11
PF13
VSS
PE12
PH10
VDD12
VSS
PB15
PB14
VDD
OPAMP2_VI
NM
PB2
PF12
VDD
PE11
PB10
PH8
VDD
PB12
N
PA2
PA1
PB13
MSv62901V1
1. The above figure shows the package top view.
74/311
DS12903 Rev 3
STM32L4P5xx
Table 14. Legend/abbreviations used in the pinout table
Name
Pin name
Abbreviation
Definition
Unless otherwise specified in brackets below the pin name, the pin function during and after
reset is the same as the actual pin name
S
Supply pin
I
Input only pin
I/O
Input / output pin
FT
5 V tolerant I/O
TT
3.6 V tolerant I/O
B
Dedicated BOOT0 pin
RST
Bidirectional reset pin with embedded weak pull-up resistor
Pin type
I/O structure
Option for TT or FT I/Os
_f
(1)
I/O, Fm+ capable
_u
(2)
I/O, with USB function supplied by VDDUSB
_a (3) (4)
_s
Notes
I/O supplied only by VDDIO2
Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset.
Alternate
functions
Pin
functions Additional
functions
I/O, with Analog switch function supplied by VDDA
(5)
Functions selected through GPIOx_AFR registers
Functions directly selected/enabled through peripheral registers
1. The related I/O structures are: FT_f, FT_fa, FT_fl, FT_fla.
2. The related I/O structures are: FT_u, FT_lu.
3. The related I/O structures are: FT_a, FT_la, FT_fa, FT_fla, TT_a, TT_la.
4. The analog switch for the TSC function is supplied by VDD.
5. The related I/O structures are: FT_s, FT_fs.
DS12903 Rev 3
75/311
132
76/311
Table 15. STM32L4P5xx pin definitions
LQFP48
LQFP64 + Ext SMPS
LQFP64
WLCSP100 + Ext SMPS
WLCSP100
LQFP100 + Ext SMPS
LQFP100
UFBGA132 + Ext SMPS
UFBGA132
LQFP144 + Ext SMSP
LQFP144
Pin type
I/O structure
Notes
-
-
-
-
-
-
-
-
-
-
D3
D3
-
-
M11 M11
VSS
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
C4
C4
-
-
C1
C1
VDD
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
C3
C3
PI11
I/O
FT
-
OCTOSPIM_P2_IO0,
PSSI_D15,
EVENTOUT
-
-
TRACECK,
TIM3_ETR,
SAI1_CK1,
TSC_G7_IO1,
LCD_R7, FMC_A23,
SAI1_MCLK_A,
EVENTOUT
-
-
TRACED0,
TIM3_CH1,
OCTOSPIM_P1_DQS
, TSC_G7_IO2,
LCD_R6, FMC_A19,
SAI1_SD_B,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
C8
B9
B10 B10
1
2
1
2
B2
A1
B2
A1
1
2
1
2
D3
D2
UFBGA169
LQFP48 + Ext SMPS
Alternate functions
UFBGA169 + ext SMPS
UFQFPN48
DS12903 Rev 3
UFQFPN48 + Ext SMPS
Pin Number
D3
D2
Pin name
(function
after
reset)
PE2
PE3
I/O
I/O
FT
_l
FT
_l
Additional
functions
STM32L4P5xx
-
-
-
-
E7
C8
3
3
B1
B1
3
3
D1
D1
PE4
I/O
I/O structure
Pin type
UFBGA169
UFBGA169 + ext SMPS
LQFP144
LQFP144 + Ext SMSP
UFBGA132
UFBGA132 + Ext SMPS
LQFP100
LQFP100 + Ext SMPS
WLCSP100
WLCSP100 + Ext SMPS
LQFP64
LQFP64 + Ext SMPS
LQFP48
LQFP48 + Ext SMPS
-
Pin name
(function
after
reset)
FT
Alternate functions
Additional
functions
-
TRACED1,
TIM3_CH2, SAI1_D2,
DFSDM1_DATIN3,
TSC_G7_IO3,
DCMI_D4/PSSI_D4,
LCD_B7, FMC_A20,
SAI1_FS_A,
EVENTOUT
-
-
TRACED2,
TIM3_CH3,
SAI1_CK2,
DFSDM1_CKIN3,
TSC_G7_IO4,
DCMI_D6/PSSI_D6,
LCD_G7, FMC_A21,
SAI1_SCK_A,
EVENTOUT
-
RTC_TAMP3,WKU
P3
DS12903 Rev 3
Notes
-
UFQFPN48
UFQFPN48 + Ext SMPS
Pin Number
-
-
-
-
-
-
E8
D8
4
4
C2
C2
4
4
E4
E4
PE5
I/O
FT
77/311
5
5
D2
D2
5
5
E3
E3
PE6
I/O
FT
-
TRACED3,
TIM3_CH4, SAI1_D1,
DCMI_D7/PSSI_D7,
LCD_G6, FMC_A22,
SAI1_SD_A,
EVENTOUT
C10 C10
6
6
E2
E2
6
6
E2
E2
VBAT
S
-
-
-
-
C9
7
7
C1
C1
7
7
E1
E1
PC13
I/O
EVENTOUT
RTC_TAMP1/RTC
_TS/RTC_OUT,WK
UP2
-
-
-
-
-
-
D8
1
1
1
1
1
1
2
2
2
2
2
2
E7
C9
(1)
FT (2)
STM32L4P5xx
Table 15. STM32L4P5xx pin definitions (continued)
78/311
Table 15. STM32L4P5xx pin definitions (continued)
-
-
-
-
4
-
-
4
-
-
4
-
-
4
-
-
D9
-
-
E10
-
-
LQFP144
UFBGA169 + ext SMPS
UFBGA169
8
D1
D1
8
8
F1
F1
9
-
-
9
-
-
E1
D6
D5
E1
D6
D5
9
10
11
9
10
11
G1
F5
F4
PC14OSC32_I
N (PC14)
I/O
FT (2)
G1
PC15OSC32_O
I/O
UT
(PC15)
FT (2)
F5
F4
PF0
PF1
Notes
I/O structure
4
8
Pin name
(function
after
reset)
Pin type
DS12903 Rev 3
4
D10 D10
LQFP144 + Ext SMSP
3
UFBGA132
LQFP64
3
UFBGA132 + Ext SMPS
LQFP64 + Ext SMPS
3
LQFP100
LQFP48
3
LQFP100 + Ext SMPS
LQFP48 + Ext SMPS
3
WLCSP100
UFQFPN48
3
WLCSP100 + Ext SMPS
UFQFPN48 + Ext SMPS
Pin Number
Alternate functions
Additional
functions
EVENTOUT
OSC32_IN
EVENTOUT
OSC32_OUT
-
I2C2_SDA,
OCTOSPIM_P2_IO0,
FMC_A0,
EVENTOUT
-
-
I2C2_SCL,
OCTOSPIM_P2_IO1,
FMC_A1,
EVENTOUT
-
-
(1)
(1)
I/O
FT
_f
I/O
FT
_f
-
-
-
-
-
-
-
-
-
D4
D4
12
12
F3
F3
PF2
I/O
FT
-
-
-
-
-
-
-
-
-
-
-
E4
E4
13
13
G3
G3
PF3
I/O
FT
-
OCTOSPIM_P2_IO3,
FMC_A3,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
F3
F3
14
14
G4
G4
PF4
I/O
FT
-
OCTOSPIM_P2_CLK
, FMC_A4,
EVENTOUT
-
STM32L4P5xx
-
I2C2_SMBA,
OCTOSPIM_P2_IO2,
FMC_A2,
EVENTOUT
UFQFPN48
LQFP48 + Ext SMPS
LQFP48
LQFP64 + Ext SMPS
LQFP64
WLCSP100 + Ext SMPS
WLCSP100
LQFP100 + Ext SMPS
LQFP100
UFBGA132 + Ext SMPS
UFBGA132
LQFP144 + Ext SMSP
LQFP144
UFBGA169 + ext SMPS
UFBGA169
Pin type
I/O structure
Notes
DS12903 Rev 3
UFQFPN48 + Ext SMPS
Pin Number
Alternate functions
-
-
-
-
-
-
-
-
-
-
F4
F4
15
15
G5
G5
PF5
I/O
FT
-
OCTOSPIM_P2_NCL
K, FMC_A5,
EVENTOUT
-
-
-
-
-
-
-
E10
D9
10
10
F2
F2
16
16
F2
F2
VSS
S
-
-
-
-
-
-
-
-
-
-
E9
E9
11
11
G2
G2
17
17
G2
G2
VDD
S
-
-
-
-
-
TIM5_ETR,
TIM5_CH1,
OCTOSPIM_P1_IO3,
SAI1_SD_B,
EVENTOUT
-
-
TIM5_CH2,
OCTOSPIM_P1_IO2,
SAI1_MCLK_B,
EVENTOUT
-
-
TIM5_CH3,
OCTOSPIM_P1_IO0,
SAI1_SCK_B,
EVENTOUT
-
-
TIM5_CH4,
OCTOSPIM_P1_IO1,
SAI1_FS_B,
TIM15_CH1,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
18
19
20
21
18
19
20
21
-
-
-
-
-
-
-
-
Pin name
(function
after
reset)
PF6
PF7
PF8
PF9
I/O
I/O
I/O
I/O
FT
FT
FT
FT
Additional
functions
STM32L4P5xx
Table 15. STM32L4P5xx pin definitions (continued)
79/311
80/311
Table 15. STM32L4P5xx pin definitions (continued)
I/O structure
Pin type
UFBGA169
UFBGA169 + ext SMPS
LQFP144 + Ext SMSP
UFBGA132
H4
PF10
I/O
FT
-
F10 F10
12
12
F1
F1
23
23
H1
H1
PH0OSC_IN
(PH0)
I/O
FT
-
EVENTOUT
OSC_IN
6
F9
G10
13
13
G1
G1
24
24
J1
J1
PH1OSC_OU
T (PH1)
I/O
FT
-
EVENTOUT
OSC_OUT
7
F8
E8
14
14
H2
H2
25
25
H3
H3
NRST
I-O
RS
T
-
-
-
-
LPTIM1_IN1,
I2C3_SCL,
SDMMC2_CKIN,
LPUART1_RX,
LCD_DE,
SDMMC1_CMD,
SAI2_FS_A,
LPTIM2_IN1,
EVENTOUT
ADC12_IN1
5
5
5
5
5
6
6
6
6
6
7
7
7
7
7
8
-
G10
-
F9
15
15
H1
H1
26
LQFP144
H4
5
8
UFBGA132 + Ext SMPS
22
-
LQFP100
22
-
-
LQFP100 + Ext SMPS
-
-
-
WLCSP100
-
-
-
WLCSP100 + Ext SMPS
-
-
26
J2
J2
PC0
I/O
FT
_fl
a
Additional
functions
-
STM32L4P5xx
Notes
DS12903 Rev 3
-
OCTOSPIM_P1_CLK
, PSSI_D15,
DFSDM1_CKOUT,
DCMI_D11/PSSI_D11
, SAI1_D3,
TIM15_CH2,
EVENTOUT
-
-
Pin name
(function
after
reset)
Alternate functions
LQFP64
LQFP64 + Ext SMPS
LQFP48
LQFP48 + Ext SMPS
UFQFPN48
UFQFPN48 + Ext SMPS
Pin Number
DS12903 Rev 3
-
-
-
-
-
-
9
10
9
10
F7
G9
F8
H10
16
17
16
17
J2
J3
J2
J3
27
28
27
28
J3
J4
J3
J4
PC1
PC2
I/O
I/O
I/O structure
Pin type
UFBGA169
UFBGA169 + ext SMPS
LQFP144
LQFP144 + Ext SMSP
UFBGA132
UFBGA132 + Ext SMPS
LQFP100
LQFP100 + Ext SMPS
WLCSP100
WLCSP100 + Ext SMPS
LQFP64
LQFP64 + Ext SMPS
LQFP48
LQFP48 + Ext SMPS
-
Pin name
(function
after
reset)
FT
_fl
a
FT
_la
Notes
-
UFQFPN48
UFQFPN48 + Ext SMPS
Pin Number
Alternate functions
Additional
functions
-
TRACED0,
LPTIM1_OUT,
SPI2_MOSI,
I2C3_SDA,
LPUART1_TX,
OCTOSPIM_P1_IO4,
SAI1_SD_A,
EVENTOUT
ADC12_IN2
-
LPTIM1_IN2,
SPI2_MISO,
DFSDM1_CKOUT,
OCTOSPIM_P1_IO5,
LCD_HSYNC,
EVENTOUT
ADC12_IN3
ADC12_IN4
81/311
-
-
-
-
11
11
F6
F7
18
18
K2
K2
29
29
K1
K1
PC3
I/O
FT
_a
-
LPTIM1_ETR,
SAI1_D1,
SPI2_MOSI,
OCTOSPIM_P1_IO6,
SAI1_SD_A,
LPTIM2_ETR,
EVENTOUT
-
-
-
-
-
-
-
H9
19
19
-
-
30
30
-
-
VSSA
S
-
-
-
-
-
-
-
-
-
-
-
G8
20
20
-
-
31
31
-
-
VREF-
S
-
-
-
-
8
8
8
8
12
12
H9
-
-
-
J1
J1
-
-
K2
K2
VSSA/VR
EF-
S
-
-
-
-
-
-
-
-
-
-
H10
G7
21
21
L1
L1
32
32
L1
L1
VREF+
S
-
-
-
VREFBUF_OUT
STM32L4P5xx
Table 15. STM32L4P5xx pin definitions (continued)
82/311
Table 15. STM32L4P5xx pin definitions (continued)
LQFP48 + Ext SMPS
LQFP48
LQFP64 + Ext SMPS
LQFP64
WLCSP100 + Ext SMPS
WLCSP100
LQFP100 + Ext SMPS
LQFP100
UFBGA132 + Ext SMPS
UFBGA132
LQFP144 + Ext SMSP
LQFP144
UFBGA169 + ext SMPS
UFBGA169
Pin type
I/O structure
Notes
Alternate functions
-
-
-
-
-
-
J10
J10
22
22
M1
M1
33
33
L2
L2
VDDA
S
-
-
-
-
9
9
9
9
13
13
-
-
-
-
-
-
-
-
-
-
VDDA/VR
EF+
S
-
-
-
-
-
TIM2_CH1,
TIM5_CH1,
TIM8_ETR,
USART2_CTS_NSS,
UART4_TX,
SAI1_EXTCLK,
TIM2_ETR,
EVENTOUT
OPAMP1_VINP,
ADC12_IN5,
RTC_TAMP2,WKU
P1
-
-
-
-
TIM2_CH2,
TIM5_CH2,
I2C1_SMBA,
SPI1_SCK,
USART2_RTS_DE,
UART4_RX,
OCTOSPIM_P1_DQS
, SDMMC2_CMD,
TIM15_CH1N,
EVENTOUT
OPAMP1_VINM,
ADC12_IN6
Pin name
(function
after
reset)
10
10
10
10
14
14
G8
G9
23
23
L2
L2
34
34
K3
K3
PA0
I/O
FT
_a
-
-
-
-
-
-
-
-
-
-
M3
M3
-
-
M1
M1
OPAMP1
_VINM
I
TT
11
11
11
11
15
15
G7
H8
24
24
M2
M2
35
35
N2
N2
PA1
I/O
FT
_la
Additional
functions
STM32L4P5xx
UFQFPN48
DS12903 Rev 3
UFQFPN48 + Ext SMPS
Pin Number
12
12
16
16
H8
H7
25
25
K3
K3
36
36
N1
N1
PA2
I/O
I/O structure
Pin type
UFBGA169
UFBGA169 + ext SMPS
LQFP144
LQFP144 + Ext SMSP
UFBGA132
UFBGA132 + Ext SMPS
LQFP100
LQFP100 + Ext SMPS
WLCSP100
WLCSP100 + Ext SMPS
LQFP64
LQFP64 + Ext SMPS
LQFP48
LQFP48 + Ext SMPS
12
Pin name
(function
after
reset)
FT
_la
Alternate functions
Additional
functions
-
TIM2_CH3,
TIM5_CH3,
USART2_TX,
LPUART1_TX,
OCTOSPIM_P1_NCS
, SAI2_EXTCLK,
TIM15_CH1,
EVENTOUT
ADC12_IN7,
WKUP4/LSCO
OPAMP1_VOUT,
ADC12_IN8
DS12903 Rev 3
Notes
12
UFQFPN48
UFQFPN48 + Ext SMPS
Pin Number
13
13
13
13
17
17
-
-
-
-
18
18
-
-
-
-
19
19
J9
J9
K10 K10
J8
J8
26
26
L3
L3
37
37
M2
M2
PA3
I/O
TT
_a
-
TIM2_CH4,
TIM5_CH4,
SAI1_CK1,
USART2_RX,
LPUART1_RX,
OCTOSPIM_P1_CLK
, SAI1_MCLK_A,
TIM15_CH2,
EVENTOUT
27
27
E3
E3
38
38
H2
H2
VSS
S
-
-
-
-
28
28
H3
H3
39
39
N3
N3
VDD
S
-
-
-
-
STM32L4P5xx
Table 15. STM32L4P5xx pin definitions (continued)
83/311
84/311
Table 15. STM32L4P5xx pin definitions (continued)
14
14
20
20
H7
F6
29
29
J4
J4
40
40
L3
L3
PA4
I/O
DS12903 Rev 3
15
15
15
15
21
21
J7
G6
30
30
K4
K4
41
41
K4
K4
PA5
I/O
I/O structure
Pin type
UFBGA169
UFBGA169 + ext SMPS
LQFP144
LQFP144 + Ext SMSP
UFBGA132
UFBGA132 + Ext SMPS
LQFP100
LQFP100 + Ext SMPS
WLCSP100
WLCSP100 + Ext SMPS
LQFP64
LQFP64 + Ext SMPS
LQFP48
LQFP48 + Ext SMPS
14
Pin name
(function
after
reset)
TT
_a
TT
_a
Alternate functions
Additional
functions
-
OCTOSPIM_P1_NCS
, SPI1_NSS,
SPI3_NSS,
USART2_CK,
DCMI_HSYNC/PSSI_
DE, LCD_CLK,
SAI1_FS_B,
LPTIM2_OUT,
EVENTOUT
ADC12_IN9,
DAC1_OUT1
-
TIM2_CH1,
TIM2_ETR,
TIM8_CH1N,
PSSI_D14,
SPI1_SCK, LCD_R7,
LPTIM2_ETR,
EVENTOUT
ADC12_IN10,
DAC1_OUT2
OPAMP2_VINP,
ADC12_IN11
-
16
16
16
16
22
22
K9
K9
31
31
L4
L4
42
42
M4
M4
PA6
I/O
FT
_a
-
TIM1_BKIN,
TIM3_CH1,
TIM8_BKIN,
DCMI_PIXCLK/PSSI_
PDCK, SPI1_MISO,
USART3_CTS_NSS,
LPUART1_CTS,
OCTOSPIM_P1_IO3,
TIM16_CH1,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
M4
M4
-
-
N4
N4
OPAMP2
_VINM
I
TT
-
-
STM32L4P5xx
Notes
14
UFQFPN48
UFQFPN48 + Ext SMPS
Pin Number
DS12903 Rev 3
-
-
18
17
-
-
18
-
-
18
17
-
-
18
23
24
NC
25
23
24
25
26
G6
K8
-
H6
J7
H6
K8
J6
32
33
34
35
32
33
34
35
J5
K5
L5
M5
J5
K5
L5
M5
43
44
45
46
43
44
45
46
L4
H5
J5
K5
L4
H5
J5
K5
PA7
PC4
PC5
PB0
I/O structure
Pin type
UFBGA169
UFBGA169 + ext SMPS
LQFP144
LQFP144 + Ext SMSP
UFBGA132
UFBGA132 + Ext SMPS
LQFP100
LQFP100 + Ext SMPS
WLCSP100
WLCSP100 + Ext SMPS
LQFP64
LQFP64 + Ext SMPS
LQFP48
LQFP48 + Ext SMPS
17
Pin name
(function
after
reset)
Notes
17
UFQFPN48
UFQFPN48 + Ext SMPS
Pin Number
Alternate functions
Additional
functions
-
TIM1_CH1N,
TIM3_CH2,
TIM8_CH1N,
I2C3_SCL,
SPI1_MOSI,
OCTOSPIM_P1_IO2,
TIM17_CH1,
EVENTOUT
OPAMP2_VINM,
ADC12_IN12
-
OCTOSPIM_P2_NCS
, USART3_TX,
OCTOSPIM_P1_IO7,
EVENTOUT
COMP1_INM,
ADC12_IN13
I/O
FT
_fl
a
I/O
FT
_a
I/O
FT (3)
_a
SAI1_D3, PSSI_D15,
USART3_RX,
LCD_CLK,
EVENTOUT
COMP1_INP,
ADC12_IN14,
WKUP5
TT
_la
TIM1_CH2N,
TIM3_CH3,
TIM8_CH2N,
SPI1_NSS,
USART3_CK,
OCTOSPIM_P1_IO1,
LCD_B6,
COMP1_OUT,
SAI1_EXTCLK,
EVENTOUT
OPAMP2_VOUT,
ADC12_IN15
I/O
-
STM32L4P5xx
Table 15. STM32L4P5xx pin definitions (continued)
85/311
86/311
Table 15. STM32L4P5xx pin definitions (continued)
20
19
20
20
19
20
26
27
27
28
K7
J6
K7
F5
36
37
36
37
M6
L6
M6
L6
47
48
47
48
L5
N5
L5
N5
PB1
PB2
I/O
I/O
I/O structure
Pin type
UFBGA169
UFBGA169 + ext SMPS
LQFP144
LQFP144 + Ext SMSP
UFBGA132
UFBGA132 + Ext SMPS
LQFP100
LQFP100 + Ext SMPS
WLCSP100
WLCSP100 + Ext SMPS
LQFP64
LQFP64 + Ext SMPS
LQFP48
LQFP48 + Ext SMPS
19
Pin name
(function
after
reset)
FT
_a
FT
_a
Notes
DS12903 Rev 3
19
UFQFPN48
UFQFPN48 + Ext SMPS
Pin Number
Alternate functions
Additional
functions
-
TIM1_CH3N,
TIM3_CH4,
TIM8_CH3N,
DFSDM1_DATIN0,
USART3_RTS_DE,
LPUART1_RTS_DE,
OCTOSPIM_P1_IO0,
LCD_G6,
LPTIM2_IN1,
EVENTOUT
COMP1_INM,
ADC12_IN16
-
RTC_OUT2,
LPTIM1_OUT,
I2C3_SMBA,
DFSDM1_CKIN0,
OCTOSPIM_P1_DQS
, EVENTOUT
COMP1_INP
-
-
-
-
-
-
-
-
-
-
K6
K6
49
49
M5
M5
PF11
I/O
FT
-
-
-
-
-
-
-
-
-
-
-
J7
J7
50
50
N6
N6
PF12
I/O
FT
-
OCTOSPIM_P2_DQS
, LCD_B0, FMC_A6,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
E3
E3
51
51
H2
H2
VSS
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
H3
H3
52
52
N7
N7
VDD
S
-
-
-
-
STM32L4P5xx
-
OCTOSPIM_P1_NCL
K, LCD_DE,
DCMI_D12/PSSI_D1
2, EVENTOUT
LQFP48
LQFP64 + Ext SMPS
LQFP64
WLCSP100 + Ext SMPS
WLCSP100
LQFP100 + Ext SMPS
LQFP100
UFBGA132 + Ext SMPS
UFBGA132
LQFP144 + Ext SMSP
LQFP144
UFBGA169 + ext SMPS
UFBGA169
-
-
-
-
-
-
-
-
K7
K7
53
53
M6
M6
DS12903 Rev 3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
K6
-
-
-
-
K6
-
-
-
-
38
-
-
-
-
38
J8
J9
H9
G9
M7
J8
J9
H9
G9
M7
54
55
56
57
58
54
55
56
57
58
L6
K6
J6
H6
L7
L6
K6
J6
H6
L7
Notes
LQFP48 + Ext SMPS
-
I/O structure
UFQFPN48
-
Alternate functions
Additional
functions
FT
-
I2C4_SMBA,
LCD_B1, FMC_A7,
EVENTOUT
-
-
I2C4_SCL,
TSC_G8_IO1,
LCD_G0, FMC_A8,
EVENTOUT
-
-
I2C4_SDA,
TSC_G8_IO2,
LCD_G1, FMC_A9,
EVENTOUT
-
-
OCTOSPIM_P2_IO4,
TSC_G8_IO3,
FMC_A10,
EVENTOUT
-
-
OCTOSPIM_P2_IO5,
TSC_G8_IO4,
FMC_A11,
EVENTOUT
-
-
TIM1_ETR,
DFSDM1_DATIN2,
LCD_B6, FMC_D4,
SAI1_SD_B,
EVENTOUT
-
Pin name
(function
after
reset)
Pin type
UFQFPN48 + Ext SMPS
Pin Number
PF13
I/O
I/O
FT
_f
I/O
FT
_f
PF14
PF15
PG0
PG1
PE7
I/O
I/O
I/O
FT
FT
FT
STM32L4P5xx
Table 15. STM32L4P5xx pin definitions (continued)
87/311
88/311
Table 15. STM32L4P5xx pin definitions (continued)
-
-
-
-
K5
K5
39
39
L7
L7
59
59
K7
K7
PE8
I/O
I/O structure
Pin type
UFBGA169
UFBGA169 + ext SMPS
LQFP144
LQFP144 + Ext SMSP
UFBGA132
UFBGA132 + Ext SMPS
LQFP100
LQFP100 + Ext SMPS
WLCSP100
WLCSP100 + Ext SMPS
LQFP64
LQFP64 + Ext SMPS
LQFP48
LQFP48 + Ext SMPS
-
Pin name
(function
after
reset)
FT
DS12903 Rev 3
Notes
-
UFQFPN48
UFQFPN48 + Ext SMPS
Pin Number
Alternate functions
Additional
functions
-
TIM1_CH1N,
DFSDM1_CKIN2,
LCD_B7, FMC_D5,
SAI1_SCK_B,
EVENTOUT
-
-
-
-
-
-
-
J5
J5
40
40
M8
M8
60
60
J7
J7
PE9
I/O
FT
-
-
-
-
-
-
-
-
-
-
-
F6
F6
61
61
M7
M7
VSS
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
G6
G6
62
62
N7
N7
VDD
S
-
-
-
-
-
TIM1_CH2N,
TSC_G5_IO1,
OCTOSPIM_P1_CLK
, LCD_G3, FMC_D7,
SAI1_MCLK_B,
EVENTOUT
-
-
TIM1_CH2,
TSC_G5_IO2,
OCTOSPIM_P1_NCS
, LCD_G4, FMC_D8,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
H5
K4
H5
K4
41
42
41
42
L8
M9
L8
M9
63
64
63
64
H7
N8
H7
N8
PE10
PE11
I/O
I/O
FT
FT
STM32L4P5xx
-
TIM1_CH1,
DFSDM1_CKOUT,
OCTOSPIM_P1_NCL
K, LCD_G2,
FMC_D6,
SAI1_FS_B,
EVENTOUT
DS12903 Rev 3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
J4
G5
G4
H4
G5
G4
J4
H4
43
44
45
46
43
44
L9
M1
0
L9
M1
0
45
M11 M11
46
M1
2
M1
2
65
66
67
68
65
66
67
68
M8
L8
K8
J8
M8
L8
K8
J8
PE12
PE13
PE14
PE15
I/O
I/O
I/O
I/O
I/O structure
Pin type
UFBGA169
UFBGA169 + ext SMPS
LQFP144
LQFP144 + Ext SMSP
UFBGA132
UFBGA132 + Ext SMPS
LQFP100
LQFP100 + Ext SMPS
WLCSP100
WLCSP100 + Ext SMPS
LQFP64
LQFP64 + Ext SMPS
LQFP48
LQFP48 + Ext SMPS
-
Pin name
(function
after
reset)
FT
FT
FT
FT
Notes
-
UFQFPN48
UFQFPN48 + Ext SMPS
Pin Number
Alternate functions
Additional
functions
-
TIM1_CH3N,
SPI1_NSS,
TSC_G5_IO3,
OCTOSPIM_P1_IO0,
LCD_G5, FMC_D9,
EVENTOUT
-
-
TIM1_CH3,
SPI1_SCK,
TSC_G5_IO4,
OCTOSPIM_P1_IO1,
LCD_G6, FMC_D10,
EVENTOUT
-
-
TIM1_CH4,
TIM1_BKIN2,
SPI1_MISO,
OCTOSPIM_P1_IO2,
LCD_G7, FMC_D11,
EVENTOUT
-
-
TIM1_BKIN,
SPI1_MOSI,
OCTOSPIM_P1_IO3,
LCD_R2, FMC_D12,
EVENTOUT
-
STM32L4P5xx
Table 15. STM32L4P5xx pin definitions (continued)
89/311
90/311
Table 15. STM32L4P5xx pin definitions (continued)
NC
21
22
NC
21
22
28
29
29
30
K3
J3
K3
J3
47
NC
47
48
L10 L10
NC
L11
69
NC
69
70
N9
H8
N9
H8
PB10
PB11
I/O structure
Pin type
UFBGA169
UFBGA169 + ext SMPS
LQFP144
LQFP144 + Ext SMSP
UFBGA132
UFBGA132 + Ext SMPS
LQFP100
LQFP100 + Ext SMPS
WLCSP100
WLCSP100 + Ext SMPS
LQFP64
LQFP64 + Ext SMPS
LQFP48
LQFP48 + Ext SMPS
21
Pin name
(function
after
reset)
Alternate functions
Additional
functions
I/O
FT
_fl
-
TIM2_CH3,
I2C4_SCL,
I2C2_SCL,
SPI2_SCK,
OCTOSPIM_P1_IO3,
USART3_TX,
LPUART1_RX,
TSC_SYNC,
OCTOSPIM_P1_CLK
, COMP1_OUT,
SAI1_SCK_A,
EVENTOUT
-
I/O
TIM2_CH4,
I2C4_SDA,
I2C2_SDA,
USART3_RX,
FT (3)
LPUART1_TX,
_fl
OCTOSPIM_P1_NCS
, LCD_VSYNC,
COMP2_OUT,
EVENTOUT
-
-
I2C2_SCL,
OCTOSPIM_P2_DQS
, PSSI_D14,
EVENTOUT
-
-
I2C2_SDA,
DCMI_PIXCLK/PSSI_
PDCK, EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
K9
K9
PH4
I/O
FT
_f
-
-
-
-
-
-
-
-
-
-
-
-
-
-
L9
L9
PH5
I/O
FT
_f
STM32L4P5xx
Notes
DS12903 Rev 3
21
UFQFPN48
UFQFPN48 + Ext SMPS
Pin Number
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
UFBGA169
UFBGA169 + ext SMPS
LQFP144
LQFP144 + Ext SMSP
UFBGA132
UFBGA132 + Ext SMPS
LQFP100
LQFP100 + Ext SMPS
WLCSP100
WLCSP100 + Ext SMPS
LQFP64
-
N10 N10
PH8
PH10
I/O structure
-
LQFP64 + Ext SMPS
LQFP48
LQFP48 + Ext SMPS
-
I/O
FT
_f
I/O
Notes
DS12903 Rev 3
-
-
Pin name
(function
after
reset)
Pin type
-
UFQFPN48
UFQFPN48 + Ext SMPS
Pin Number
Alternate functions
Additional
functions
-
I2C3_SDA,
OCTOSPIM_P2_IO3,
DCMI_HSYNC/PSSI_
DE, EVENTOUT
-
FT
-
TIM5_CH1,
OCTOSPIM_P2_IO5,
DCMI_D1/PSSI_D1,
EVENTOUT
-
TIM5_CH2,
OCTOSPIM_P2_IO6,
DCMI_D2/PSSI_D2,
EVENTOUT
-
M9
M9
PH11
I/O
FT
(3)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
NC
M1
0
-
-
-
-
-
-
-
-
-
-
F6
F6
-
-
C2
C2
VSS
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
G6
G6
-
-
L12 L12
VDD
S
-
-
-
-
22
-
22
-
30
-
K1
-
48
-
L11
-
70
-
M1
0
-
VDD12
S
-
-
-
-
23
23
23
23
31
31
K2
K2
49
49
F12 F12
71
71
A7
A7
VSS
S
-
-
-
-
24
24
24
24
32
32
J2
K1
50
50
G12 G12
72
72
N11 N11
VDD
S
-
-
-
-
STM32L4P5xx
Table 15. STM32L4P5xx pin definitions (continued)
91/311
92/311
Table 15. STM32L4P5xx pin definitions (continued)
26
25
26
26
25
26
33
34
33
34
J1
H2
J1
J2
51
52
51
52
L12 L12
K12 K12
73
74
73
74
N12 N12
N13 N13
PB12
PB13
I/O
I/O
I/O structure
Pin type
UFBGA169
UFBGA169 + ext SMPS
LQFP144
LQFP144 + Ext SMSP
UFBGA132
UFBGA132 + Ext SMPS
LQFP100
LQFP100 + Ext SMPS
WLCSP100
WLCSP100 + Ext SMPS
LQFP64
LQFP64 + Ext SMPS
LQFP48
LQFP48 + Ext SMPS
25
Pin name
(function
after
reset)
FT
FT
_fl
Notes
DS12903 Rev 3
25
UFQFPN48
UFQFPN48 + Ext SMPS
Pin Number
Alternate functions
Additional
functions
-
TIM1_BKIN,
I2C2_SMBA,
SPI2_NSS,
DFSDM1_DATIN1,
USART3_CK,
LPUART1_RTS_DE,
TSC_G1_IO1,
OCTOSPIM_P1_NCL
K, SDMMC2_CK,
SAI2_FS_A,
TIM15_BKIN,
EVENTOUT
-
-
TIM1_CH1N,
I2C2_SCL,
SPI2_SCK,
DFSDM1_CKIN1,
USART3_CTS_NSS,
LPUART1_CTS,
TSC_G1_IO2,
OCTOSPIM_P1_IO1,
SAI2_SCK_A,
TIM15_CH1N,
EVENTOUT
-
STM32L4P5xx
28
-
27
28
-
28
-
27
28
-
35
36
-
35
36
-
H1
H3
G3
H2
H1
H3
53
54
55
53
54
55
K11 K11
K10 K10
K9
K9
75
76
77
75
76
77
M1
3
M1
2
L11
M1
3
M1
2
L11
PB14
PB15
PD8
I/O
I/O
I/O
I/O structure
Pin type
UFBGA169
UFBGA169 + ext SMPS
LQFP144
LQFP144 + Ext SMSP
UFBGA132
UFBGA132 + Ext SMPS
LQFP100
LQFP100 + Ext SMPS
WLCSP100
WLCSP100 + Ext SMPS
LQFP64
LQFP64 + Ext SMPS
LQFP48
LQFP48 + Ext SMPS
27
Pin name
(function
after
reset)
FT
_fl
FT
FT
93/311
Notes
DS12903 Rev 3
27
UFQFPN48
UFQFPN48 + Ext SMPS
Pin Number
Alternate functions
Additional
functions
-
TIM1_CH2N,
TIM8_CH2N,
I2C2_SDA,
SPI2_MISO,
DFSDM1_DATIN2,
USART3_RTS_DE,
TSC_G1_IO3,
OCTOSPIM_P1_IO6,
SDMMC2_D0,
SAI2_MCLK_A,
TIM15_CH1,
EVENTOUT
-
-
RTC_REFIN,
TIM1_CH3N,
TIM8_CH3N,
SPI2_MOSI,
DFSDM1_CKIN2,
TSC_G1_IO4,
OCTOSPIM_P1_IO7,
SDMMC2_D1,
SAI2_SD_A,
TIM15_CH2,
EVENTOUT
-
-
USART3_TX,
DCMI_HSYNC/PSSI_
DE, LCD_R3,
FMC_D13,
EVENTOUT
-
STM32L4P5xx
Table 15. STM32L4P5xx pin definitions (continued)
94/311
Table 15. STM32L4P5xx pin definitions (continued)
-
-
-
-
G2
G2
56
56
K8
K8
78
78
DS12903 Rev 3
-
-
-
-
-
H13 H13
VDD
S
-
-
-
-
-
I2C4_SMBA,
USART3_CTS_NSS,
TSC_G6_IO2,
LCD_R6, FMC_A16,
SAI2_SD_A,
LPTIM2_ETR,
EVENTOUT
-
J12
J12
79
79
-
-
-
-
-
-
-
-
-
-
F11
F11
-
-
-
-
-
-
-
-
-
-
-
H3
H3
-
J11
J11
80
I/O structure
S
57
58
Pin type
VSS
57
58
UFBGA169
L13 L13
G1
-
-
-
G1
-
-
-
-
-
-
FT
-
-
FT
I/O
-
-
I/O
USART3_RX,
DCMI_PIXCLK/PSSI_
PDCK, LCD_R4,
FMC_D14,
SAI2_MCLK_A,
EVENTOUT
PD10
-
-
PD9
Additional
functions
J13
-
-
L10 L10
Alternate functions
USART3_CK,
TSC_G6_IO1,
LCD_R5, FMC_D15,
SAI2_SCK_A,
EVENTOUT
-
-
UFBGA169 + ext SMPS
LQFP144
LQFP144 + Ext SMSP
UFBGA132
UFBGA132 + Ext SMPS
LQFP100
LQFP100 + Ext SMPS
WLCSP100
WLCSP100 + Ext SMPS
LQFP64
LQFP64 + Ext SMPS
LQFP48
LQFP48 + Ext SMPS
-
Pin name
(function
after
reset)
Notes
-
UFQFPN48
UFQFPN48 + Ext SMPS
Pin Number
80
J13
K12 K12
PD11
I/O
FT
STM32L4P5xx
-
-
-
-
-
-
59
59
J10
J10
81
81
K11 K11
PD12
I/O
I/O structure
Pin type
UFBGA169
UFBGA169 + ext SMPS
LQFP144
LQFP144 + Ext SMSP
UFBGA132
UFBGA132 + Ext SMPS
LQFP100
LQFP100 + Ext SMPS
WLCSP100
WLCSP100 + Ext SMPS
LQFP64
LQFP64 + Ext SMPS
LQFP48
LQFP48 + Ext SMPS
-
Pin name
(function
after
reset)
FT
_fl
DS12903 Rev 3
Notes
-
UFQFPN48
UFQFPN48 + Ext SMPS
Pin Number
Alternate functions
Additional
functions
-
TIM4_CH1,
I2C4_SCL,
USART3_RTS_DE,
TSC_G6_IO3,
LCD_R7, FMC_A17,
SAI2_FS_A,
LPTIM2_IN1,
EVENTOUT
-
-
H12 H12
82
82
K13 K13
PD13
I/O
FT
_fl
-
TIM4_CH2,
I2C4_SDA,
TSC_G6_IO4,
FMC_A18,
LPTIM2_OUT,
EVENTOUT
-
F11
F11
83
83
H12 H12
VSS
S
-
-
-
-
-
-
H3
H3
84
84
G13 G13
VDD
S
-
-
-
-
G3
61
61
H11 H11
85
85
K10 K10
PD14
I/O
FT
-
TIM4_CH3, LCD_B2,
FMC_D0,
EVENTOUT
-
F4
62
62
H10 H10
86
86
H11 H11
PD15
I/O
FT
-
TIM4_CH4, LCD_B3,
FMC_D1,
EVENTOUT
-
-
-
-
-
-
-
-
-
60
60
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
F1
F1
-
-
-
-
-
-
F3
-
-
-
-
-
-
F2
STM32L4P5xx
Table 15. STM32L4P5xx pin definitions (continued)
95/311
96/311
Table 15. STM32L4P5xx pin definitions (continued)
DS12903 Rev 3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
G10 G10
F9
F9
F10 F10
E9
G4
E9
G4
87
88
89
90
91
87
88
89
90
91
J12
J11
J10
J9
J12
J11
J10
J9
G11 G11
PG2
PG3
PG4
PG5
PG6
I/O
I/O
I/O
I/O structure
Pin type
UFBGA169
UFBGA169 + ext SMPS
LQFP144
LQFP144 + Ext SMSP
UFBGA132
UFBGA132 + Ext SMPS
LQFP100
LQFP100 + Ext SMPS
WLCSP100
WLCSP100 + Ext SMPS
LQFP64
LQFP64 + Ext SMPS
LQFP48
LQFP48 + Ext SMPS
-
FT
_s
FT
_s
FT
_s
I/O
FT
_s
I/O
FT
_s
Alternate functions
Additional
functions
-
SPI1_SCK,
SDMMC2_D4,
FMC_A12,
SAI2_SCK_B,
EVENTOUT
-
-
SPI1_MISO,
SDMMC2_D5,
FMC_A13,
SAI2_FS_B,
EVENTOUT
-
-
SPI1_MOSI,
SDMMC2_D6,
FMC_A14,
SAI2_MCLK_B,
EVENTOUT
-
-
SPI1_NSS,
LPUART1_CTS,
SDMMC2_D7,
FMC_A15,
SAI2_SD_B,
EVENTOUT
-
-
OCTOSPIM_P1_DQS
, I2C3_SMBA,
LPUART1_RTS_DE,
LCD_R1, EVENTOUT
-
STM32L4P5xx
-
-
Pin name
(function
after
reset)
Notes
-
UFQFPN48
UFQFPN48 + Ext SMPS
Pin Number
DS12903 Rev 3
-
-
-
-
-
-
-
-
H4
H4
92
92
H10 H10
PG7
I/O
FT
_fs
-
-
-
-
-
-
-
-
-
-
-
J6
J6
93
93
H9
H9
PG8
I/O
FT
_fs
-
I2C3_SDA,
LPUART1_RX,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
F7
F7
94
94
F13 F13
VSS
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
G7
G7
95
95
F12 F12
VDDIO2
S
-
-
-
-
-
TIM3_CH1,
TIM8_CH1,
DFSDM1_CKIN3,
SDMMC2_D6,
SDMMC1_D0DIR,
TSC_G4_IO1,
DCMI_D0/PSSI_D0,
LCD_G7,
SDMMC1_D6,
SAI2_MCLK_A,
EVENTOUT
-
-
-
-
-
37
37
F4
F2
63
63
E12 E12
96
LQFP144
-
LQFP100
-
SAI1_CK1,
I2C3_SCL,
OCTOSPIM_P2_DQS
, DFSDM1_CKOUT,
LPUART1_TX,
FMC_INT,
SAI1_MCLK_A,
EVENTOUT
LQFP64
Alternate functions
LQFP48
Notes
I/O structure
Pin name
(function
after
reset)
Pin type
UFBGA169
UFBGA169 + ext SMPS
LQFP144 + Ext SMSP
UFBGA132
UFBGA132 + Ext SMPS
LQFP100 + Ext SMPS
WLCSP100
WLCSP100 + Ext SMPS
LQFP64 + Ext SMPS
LQFP48 + Ext SMPS
UFQFPN48
UFQFPN48 + Ext SMPS
Pin Number
96
F11
F11
PC6
I/O
FT
Additional
functions
-
STM32L4P5xx
Table 15. STM32L4P5xx pin definitions (continued)
97/311
98/311
Table 15. STM32L4P5xx pin definitions (continued)
-
-
-
-
-
-
-
-
38
39
40
38
39
40
E4
E1
E2
F3
E1
E2
64
65
66
64
65
66
E11 E11
E10 E10
D12 D12
97
98
99
97
98
99
G12 G12
G10 G10
G9
G9
PC7
PC8
PC9
I/O
I/O
I/O
I/O structure
Pin type
UFBGA169
UFBGA169 + ext SMPS
LQFP144
LQFP144 + Ext SMSP
UFBGA132
UFBGA132 + Ext SMPS
LQFP100
LQFP100 + Ext SMPS
WLCSP100
WLCSP100 + Ext SMPS
LQFP64
LQFP64 + Ext SMPS
LQFP48
LQFP48 + Ext SMPS
-
FT
FT
FT
_fl
Alternate functions
Additional
functions
-
TIM3_CH2,
TIM8_CH2,
DFSDM1_DATIN3,
SDMMC2_D7,
SDMMC1_D123DIR,
TSC_G4_IO2,
DCMI_D1/PSSI_D1,
LCD_B6,
SDMMC1_D7,
SAI2_MCLK_B,
EVENTOUT
-
-
TIM3_CH3,
TIM8_CH3,
TSC_G4_IO3,
DCMI_D2/PSSI_D2,
SDMMC1_D0,
EVENTOUT
-
-
TRACED0,
TIM8_BKIN2,
TIM3_CH4,
TIM8_CH4,
DCMI_D3/PSSI_D3,
I2C3_SDA,
TSC_G4_IO4,
OTG_FS_NOE,
SDMMC1_D1,
SAI2_EXTCLK,
EVENTOUT
-
STM32L4P5xx
-
-
Pin name
(function
after
reset)
Notes
DS12903 Rev 3
-
UFQFPN48
UFQFPN48 + Ext SMPS
Pin Number
29
29
41
41
E3
E3
67
67
D11 D11 100 100
G8
G8
PA8
I/O
DS12903 Rev 3
30
31
30
31
30
31
30
31
42
43
42
43
D3
D2
D3
D2
68
69
68
69
D10 D10 101 101 F10 F10
C12 C12 102 102
F9
F9
PA9
PA10
I/O
I/O
I/O structure
Pin type
UFBGA169
UFBGA169 + ext SMPS
LQFP144
LQFP144 + Ext SMSP
UFBGA132
UFBGA132 + Ext SMPS
LQFP100
LQFP100 + Ext SMPS
WLCSP100
WLCSP100 + Ext SMPS
LQFP64
LQFP64 + Ext SMPS
LQFP48
LQFP48 + Ext SMPS
29
Pin name
(function
after
reset)
FT
_f
FT
_fl
u
FT
_fl
u
Notes
29
UFQFPN48
UFQFPN48 + Ext SMPS
Pin Number
Alternate functions
Additional
functions
-
MCO, TIM1_CH1,
SAI1_CK2,
USART1_CK,
OTG_FS_SOF,
LCD_B7,
SAI1_SCK_A,
LPTIM2_OUT,
EVENTOUT
-
-
TIM1_CH2,
SPI2_SCK,
DCMI_D0/PSSI_D0,
USART1_TX,
LCD_G7,
SAI1_FS_A,
TIM15_BKIN,
EVENTOUT
OTG_FS_VBUS
-
TIM1_CH3, SAI1_D1,
DCMI_D1/PSSI_D1,
USART1_RX,
OTG_FS_ID,
LCD_G6,
SAI1_SD_A,
TIM17_BKIN,
EVENTOUT
-
STM32L4P5xx
Table 15. STM32L4P5xx pin definitions (continued)
99/311
100/311
Table 15. STM32L4P5xx pin definitions (continued)
32
32
44
44
D1
D1
70
70
B12 B12 103 103 E13 E13
PA11
I/O
I/O structure
Pin type
UFBGA169
UFBGA169 + ext SMPS
LQFP144
LQFP144 + Ext SMSP
UFBGA132
UFBGA132 + Ext SMPS
LQFP100
LQFP100 + Ext SMPS
WLCSP100
WLCSP100 + Ext SMPS
LQFP64
LQFP64 + Ext SMPS
LQFP48
LQFP48 + Ext SMPS
32
Pin name
(function
after
reset)
FT
_u
Alternate functions
Additional
functions
-
TIM1_CH4,
TIM1_BKIN2,
SPI1_MISO,
USART1_CTS_NSS,
CAN1_RX,
OTG_FS_DM,
LCD_DE,
EVENTOUT
-
-
TIM1_ETR,
SPI1_MOSI,
OCTOSPIM_P2_NCS
, USART1_RTS_DE,
CAN1_TX,
OTG_FS_DP,
LCD_VSYNC,
EVENTOUT
-
JTMS/SWDIO,
IR_OUT,
OTG_FS_NOE,
SAI1_SD_B,
EVENTOUT
-
DS12903 Rev 3
Notes
32
UFQFPN48
UFQFPN48 + Ext SMPS
Pin Number
33
33
33
33
45
45
C1
C1
71
71
I/O
FT
_u
PA12
A11 A11 105 105 A11 A11
PA13
(JTMS/S
WDIO)
I/O
VSS
S
-
-
-
-
VDDUSB
S
-
-
-
-
FT (4)
34
34
34
34
46
46
C2
C2
72
72
35
35
35
35
47
47
B1
B1
-
-
36
36
36
36
48
48
A1
A1
73
73
C11 C11 106 106 E12 E12
-
-
-
-
-
-
B1
B1
74
74
F11
F11 107 107 C12 C12
VSS
S
-
-
-
-
-
-
-
-
-
-
F1
F1
75
75
G11 G11 108 108 C13 C13
VDD
S
-
-
-
-
F11
F11
-
-
C12 C12
STM32L4P5xx
A12 A12 104 104 D13 D13
DS12903 Rev 3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
E11 E11
D12 D12
D11 D11
PH6
PH7
PH9
I/O
I/O
I/O
I/O structure
Pin type
UFBGA169
UFBGA169 + ext SMPS
LQFP144
LQFP144 + Ext SMSP
UFBGA132
UFBGA132 + Ext SMPS
LQFP100
LQFP100 + Ext SMPS
WLCSP100
WLCSP100 + Ext SMPS
LQFP64
LQFP64 + Ext SMPS
LQFP48
LQFP48 + Ext SMPS
-
Pin name
(function
after
reset)
FT
FT
_f
FT
Notes
-
UFQFPN48
UFQFPN48 + Ext SMPS
Pin Number
Alternate functions
Additional
functions
-
I2C2_SMBA,
OCTOSPIM_P2_CLK
, DCMI_D8/PSSI_D8,
EVENTOUT
-
-
I2C3_SCL,
OCTOSPIM_P2_NCL
K,
DCMI_D9/PSSI_D9,
EVENTOUT
-
-
I2C3_SMBA,
OCTOSPIM_P2_IO4,
DCMI_D0/PSSI_D0,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
B13 B13
PH12
I/O
FT
-
TIM5_CH3,
OCTOSPIM_P2_IO7,
DCMI_D3/PSSI_D3,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
A13 A13
PH14
I/O
FT
-
TIM8_CH2N,
DCMI_D4/PSSI_D4,
EVENTOUT
-
-
TIM8_CH3N,
OCTOSPIM_P2_IO6,
DCMI_D11/PSSI_D11
, EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
B12 B12
PH15
I/O
FT
STM32L4P5xx
Table 15. STM32L4P5xx pin definitions (continued)
101/311
102/311
Table 15. STM32L4P5xx pin definitions (continued)
-
-
-
-
-
-
-
-
-
-
-
-
A12 A12
PI0
I/O
I/O structure
Pin type
UFBGA169
UFBGA169 + ext SMPS
LQFP144
LQFP144 + Ext SMSP
UFBGA132
UFBGA132 + Ext SMPS
LQFP100
LQFP100 + Ext SMPS
WLCSP100
WLCSP100 + Ext SMPS
LQFP64
LQFP64 + Ext SMPS
LQFP48
LQFP48 + Ext SMPS
-
Pin name
(function
after
reset)
FT
DS12903 Rev 3
Notes
-
UFQFPN48
UFQFPN48 + Ext SMPS
Pin Number
Alternate functions
Additional
functions
-
TIM5_CH4,
OCTOSPIM_P1_IO5,
SPI2_NSS,
DCMI_D13/PSSI_D1
3, EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
C11 C11
PI8
I/O
FT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
B11 B11
PI1
I/O
FT
-
SPI2_SCK,
DCMI_D8/PSSI_D8,
EVENTOUT
-
-
TIM8_CH4,
SPI2_MISO,
DCMI_D9/PSSI_D9,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
B10 B10
PI2
I/O
FT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
C10 C10
PI3
I/O
FT
-
TIM8_ETR,
SPI2_MOSI,
DCMI_D10/PSSI_D1
0, EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
D10 D10
PI4
I/O
FT
-
TIM8_BKIN,
DCMI_D5/PSSI_D5,
EVENTOUT
STM32L4P5xx
-
OCTOSPIM_P2_NCS
,
DCMI_D12/PSSI_D1
2, EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
E10 E10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
C9
-
37
-
37
-
37
-
37
-
49
-
49
-
B2
-
B2
-
76
-
76
-
-
-
-
B9
C9
B9
A10 A10 109 109 A10 A10
I/O structure
Notes
DS12903 Rev 3
-
Pin name
(function
after
reset)
Pin type
UFBGA169
UFBGA169 + ext SMPS
LQFP144
LQFP144 + Ext SMSP
UFBGA132
UFBGA132 + Ext SMPS
LQFP100
LQFP100 + Ext SMPS
WLCSP100
WLCSP100 + Ext SMPS
LQFP64
LQFP64 + Ext SMPS
LQFP48
LQFP48 + Ext SMPS
UFQFPN48
UFQFPN48 + Ext SMPS
Pin Number
Alternate functions
PI5
I/O
FT
-
TIM8_CH1,
OCTOSPIM_P2_NCS
,
DCMI_VSYNC/PSSI_
RDY, EVENTOUT
PH13
I/O
FT
-
TIM8_CH1N,
CAN1_TX,
EVENTOUT
-
-
TIM8_CH2,
OCTOSPIM_P2_CLK
, DCMI_D6/PSSI_D6,
EVENTOUT
-
JTCK/SWCLK,
LPTIM1_OUT,
I2C1_SMBA,
I2C4_SMBA,
OTG_FS_SOF,
SAI1_FS_B,
EVENTOUT
-
PI6
PA14
(JTCK/S
WCLK)
I/O
I/O
FT
FT (4)
Additional
functions
-
STM32L4P5xx
Table 15. STM32L4P5xx pin definitions (continued)
103/311
104/311
Table 15. STM32L4P5xx pin definitions (continued)
-
38
-
-
38
-
50
51
50
51
A2
C3
A2
D4
77
78
77
78
A9
A9
B11 B11
110
111
110
111
A9
D9
A9
D9
PA15
(JTDI)
PC10
I/O
I/O
I/O structure
Pin type
UFBGA169
UFBGA169 + ext SMPS
LQFP144
LQFP144 + Ext SMSP
UFBGA132
UFBGA132 + Ext SMPS
LQFP100
LQFP100 + Ext SMPS
WLCSP100
WLCSP100 + Ext SMPS
LQFP64
LQFP64 + Ext SMPS
LQFP48
LQFP48 + Ext SMPS
38
Pin name
(function
after
reset)
Notes
DS12903 Rev 3
38
UFQFPN48
UFQFPN48 + Ext SMPS
Pin Number
Alternate functions
Additional
functions
FT (4)
JTDI, TIM2_CH1,
TIM2_ETR,
USART2_RX,
SPI1_NSS,
SPI3_NSS,
USART3_RTS_DE,
UART4_RTS_DE,
TSC_G3_IO1,
LCD_HSYNC,
SAI2_FS_B,
EVENTOUT
-
TRACED1,
DCMI_VSYNC/PSSI_
RDY, SPI3_SCK,
USART3_TX,
UART4_TX,
TSC_G3_IO2,
DCMI_D8/PSSI_D8,
SDMMC1_D2,
SAI2_SCK_B,
EVENTOUT
-
FT
-
STM32L4P5xx
-
-
105/311
-
-
-
-
-
-
-
-
-
-
-
-
52
53
-
-
52
53
-
-
D4
C4
B3
A3
C3
C4
B3
A3
79
80
81
82
79
80
81
82
C10 C10 112
B10 B10 113
C9
B9
C9
B9
114
115
112
113
114
115
E9
F8
B8
C8
E9
F8
B8
C8
PC11
PC12
PD0
PD1
I/O
I/O
I/O
I/O
I/O structure
Pin type
UFBGA169
UFBGA169 + ext SMPS
LQFP144
LQFP144 + Ext SMSP
UFBGA132
UFBGA132 + Ext SMPS
LQFP100
LQFP100 + Ext SMPS
WLCSP100
WLCSP100 + Ext SMPS
LQFP64
LQFP64 + Ext SMPS
LQFP48
LQFP48 + Ext SMPS
-
Pin name
(function
after
reset)
FT
FT
FT
FT
Notes
DS12903 Rev 3
-
UFQFPN48
UFQFPN48 + Ext SMPS
Pin Number
Alternate functions
Additional
functions
-
DCMI_D2/PSSI_D2,
OCTOSPIM_P1_NCS
, SPI3_MISO,
USART3_RX,
UART4_RX,
TSC_G3_IO3,
DCMI_D4/PSSI_D4,
SDMMC1_D3,
SAI2_MCLK_B,
EVENTOUT
-
-
TRACED3,
SPI3_MOSI,
USART3_CK,
UART5_TX,
TSC_G3_IO4,
DCMI_D9/PSSI_D9,
LCD_R6,
SDMMC1_CK,
SAI2_SD_B,
EVENTOUT
-
-
SPI2_NSS,
CAN1_RX, LCD_B4,
FMC_D2,
EVENTOUT
-
-
SPI2_SCK,
CAN1_TX, LCD_B5,
FMC_D3,
EVENTOUT
-
STM32L4P5xx
Table 15. STM32L4P5xx pin definitions (continued)
106/311
Table 15. STM32L4P5xx pin definitions (continued)
-
NC
54
D5
E4
83
83
C8
C8
116
116
D8
D8
PD2
-
I/O
-
SPI2_SCK,
DCMI_D5/PSSI_D5,
SPI2_MISO,
DFSDM1_DATIN0,
USART2_CTS_NSS,
OCTOSPIM_P2_NCS
, LCD_CLK,
FMC_CLK,
EVENTOUT
-
-
SPI2_MOSI,
DFSDM1_CKIN0,
USART2_RTS_DE,
SDMMC2_CKIN,
OCTOSPIM_P1_IO4,
FMC_NOE,
EVENTOUT
-
-
USART2_TX,
OCTOSPIM_P1_IO5,
FMC_NWE,
EVENTOUT
-
DS12903 Rev 3
I/O
TRACED2,
TIM3_ETR,
USART3_RTS_DE,
UART5_RX,
(3)
FT
TSC_SYNC,
DCMI_D11/PSSI_D11
, SDMMC1_CMD,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
C5
B4
-
B4
E5
84
85
86
84
85
86
B8
B7
A6
B8
B7
A6
117
118
119
117
118
119
E8
C7
D7
E8
C7
D7
PD3
PD4
PD5
I/O
I/O
FT
FT
FT
Alternate functions
Additional
functions
STM32L4P5xx
-
-
Notes
UFBGA169
UFBGA169 + ext SMPS
LQFP144
LQFP144 + Ext SMSP
UFBGA132
UFBGA132 + Ext SMPS
LQFP100
LQFP100 + Ext SMPS
WLCSP100
WLCSP100 + Ext SMPS
LQFP64
LQFP64 + Ext SMPS
LQFP48
LQFP48 + Ext SMPS
-
I/O structure
-
Pin name
(function
after
reset)
Pin type
-
UFQFPN48
UFQFPN48 + Ext SMPS
Pin Number
LQFP48
LQFP64 + Ext SMPS
LQFP64
WLCSP100 + Ext SMPS
WLCSP100
LQFP100 + Ext SMPS
LQFP100
UFBGA132 + Ext SMPS
UFBGA132
UFBGA169 + ext SMPS
UFBGA169
Pin type
I/O structure
Notes
-
-
-
-
-
-
-
-
-
-
F11
F11 120 120
M3
M3
VSS
S
-
-
-
-
-
-
-
-
-
-
A4
A4
-
-
G11 G11 121 121
A8
A8
VDD
S
-
-
-
-
-
SAI1_D1,
DCMI_D10/PSSI_D1
0, SPI3_MOSI,
DFSDM1_DATIN1,
USART2_RX,
SDMMC2_CK,
OCTOSPIM_P1_IO6,
LCD_DE,
FMC_NWAIT,
SAI1_SD_A,
EVENTOUT
-
-
DFSDM1_CKIN1,
USART2_CK,
SDMMC2_CMD,
OCTOSPIM_P1_IO7,
FMC_NCE/FMC_NE1
, EVENTOUT
-
-
OCTOSPIM_P2_IO6,
SPI3_SCK,
USART1_TX,
SDMMC2_D0,
FMC_NCE/FMC_NE2
, SAI2_SCK_A,
TIM15_CH1N,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
B5
C6
D6
D5
C5
B5
87
88
-
87
88
-
B6
A5
D9
B6
A5
D9
LQFP144
LQFP48 + Ext SMPS
Alternate functions
LQFP144 + Ext SMSP
UFQFPN48
DS12903 Rev 3
UFQFPN48 + Ext SMPS
Pin Number
122 122
123 123
124 124
E7
F7
B7
E7
F7
B7
Pin name
(function
after
reset)
PD6
PD7
PG9
I/O
I/O
I/O
FT
FT
FT
_s
Additional
functions
STM32L4P5xx
Table 15. STM32L4P5xx pin definitions (continued)
107/311
108/311
Table 15. STM32L4P5xx pin definitions (continued)
-
-
-
-
A5
A5
-
-
D8
D8
125 125
D6
D6
PG10
I/O
DS12903 Rev 3
-
-
-
-
-
-
-
-
-
-
-
-
E5
B6
D6
B6
-
-
-
-
G3
D7
G3
D7
126 126
127 127
E6
F6
E6
F6
PG11
PG12
I/O
I/O
I/O structure
Pin type
UFBGA169
UFBGA169 + ext SMPS
LQFP144
LQFP144 + Ext SMSP
UFBGA132
UFBGA132 + Ext SMPS
LQFP100
LQFP100 + Ext SMPS
WLCSP100
WLCSP100 + Ext SMPS
LQFP64
LQFP64 + Ext SMPS
LQFP48
LQFP48 + Ext SMPS
-
Pin name
(function
after
reset)
FT
_s
FT
_s
FT
_s
Alternate functions
Additional
functions
-
LPTIM1_IN1,
OCTOSPIM_P2_IO7,
SPI3_MISO,
USART1_RX,
SDMMC2_D1,
FMC_NE3,
SAI2_FS_A,
TIM15_CH1,
EVENTOUT
-
-
LPTIM1_IN2,
OCTOSPIM_P1_IO5,
SPI3_MOSI,
USART1_CTS_NSS,
SDMMC2_D2,
SAI2_MCLK_A,
TIM15_CH2,
EVENTOUT
-
-
LPTIM1_ETR,
OCTOSPIM_P2_NCS
, SPI3_NSS,
USART1_RTS_DE,
SDMMC2_D3,
FMC_NE4,
SAI2_SD_A,
EVENTOUT
-
STM32L4P5xx
Notes
-
UFQFPN48
UFQFPN48 + Ext SMPS
Pin Number
DS12903 Rev 3
Notes
I/O structure
Pin name
(function
after
reset)
Pin type
UFBGA169
UFBGA169 + ext SMPS
LQFP144
LQFP144 + Ext SMSP
UFBGA132
UFBGA132 + Ext SMPS
LQFP100
LQFP100 + Ext SMPS
WLCSP100
WLCSP100 + Ext SMPS
LQFP64
LQFP64 + Ext SMPS
LQFP48
LQFP48 + Ext SMPS
UFQFPN48
UFQFPN48 + Ext SMPS
Pin Number
Alternate functions
Additional
functions
-
I2C1_SDA,
USART1_CK,
LCD_R0, FMC_A24,
EVENTOUT
-
I2C1_SCL, LCD_R1,
FMC_A25,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
C7
C7
128 128
G7
G7
PG13
FT
I/O
_fs
-
-
-
-
-
-
-
-
-
-
NC
C6
129 129
G6
G6
PG14
I/O
-
-
-
-
-
-
-
-
-
-
F7
F7
130 130
A7
A7
VSS
S
-
-
-
-
-
-
-
-
-
-
A6
A6
-
-
G7
G7
131 131
B6
B6
VDDIO2
S
-
-
-
-
-
39
-
39
-
39
-
39
-
54
-
55
-
F5
-
C6
-
89
-
89
K1
A8
K1
A8
NC
132
132 133
NC
A6
C6
A6
PG15
I/O
FT (3)
_fs
LPTIM1_OUT,
I2C1_SMBA,
FT (3) OCTOSPIM_P2_DQS
,
_s
DCMI_D13/PSSI_D1
3, EVENTOUT
PB3
(JTDO/TR
FT
I/O
ACESWO
_la
)
-
109/311
JTDO/TRACESWO,
TIM2_CH2,
OCTOSPIM_P1_IO4,
SPI1_SCK,
SPI3_SCK,
USART1_RTS_DE,
OTG_FS_CRS_SYN
C, SDMMC2_D2,
SAI1_SCK_B,
EVENTOUT
-
COMP2_INM
STM32L4P5xx
Table 15. STM32L4P5xx pin definitions (continued)
110/311
Table 15. STM32L4P5xx pin definitions (continued)
DS12903 Rev 3
40
41
40
41
40
41
40
41
55
56
56
57
E6
C7
C7
B7
90
91
90
91
A7
C5
A7
C5
133 134
134 135
A5
B5
Notes
I/O structure
Pin name
(function
after
reset)
Pin type
UFBGA169
UFBGA169 + ext SMPS
LQFP144
LQFP144 + Ext SMSP
UFBGA132
UFBGA132 + Ext SMPS
LQFP100
LQFP100 + Ext SMPS
WLCSP100
WLCSP100 + Ext SMPS
LQFP64
LQFP64 + Ext SMPS
LQFP48
LQFP48 + Ext SMPS
UFQFPN48
UFQFPN48 + Ext SMPS
Pin Number
Alternate functions
B5
LPTIM1_IN1,
TIM3_CH2,
OCTOSPIM_P1_IO0,
I2C1_SMBA,
SPI1_MOSI,
SPI3_MOSI,
USART1_CK,
UART5_CTS,
TSC_G2_IO2,
DCMI_D10/PSSI_D1
0, COMP2_OUT,
SAI1_SD_B,
TIM16_BKIN,
EVENTOUT
PB5
I/O
FT
_la
-
COMP2_INP
-
STM32L4P5xx
A5
NJTRST, TIM3_CH1,
OCTOSPIM_P1_IO5,
I2C3_SDA,
SPI1_MISO,
SPI3_MISO,
USART1_CTS_NSS,
PB4
FT (4)
UART5_RTS_DE,
I/O
(NJTRST)
_fa
TSC_G2_IO1,
DCMI_D12/PSSI_D1
2, SDMMC2_D3,
SAI1_MCLK_B,
TIM17_BKIN,
EVENTOUT
Additional
functions
42
42
57
58
A7
A7
92
92
B5
B5
135 136
C5
C5
PB6
I/O
I/O structure
Pin type
UFBGA169
UFBGA169 + ext SMPS
LQFP144
LQFP144 + Ext SMSP
UFBGA132
UFBGA132 + Ext SMPS
LQFP100
LQFP100 + Ext SMPS
WLCSP100
WLCSP100 + Ext SMPS
LQFP64
LQFP64 + Ext SMPS
LQFP48
LQFP48 + Ext SMPS
42
Pin name
(function
after
reset)
FT
_fa
111/311
Notes
DS12903 Rev 3
42
UFQFPN48
UFQFPN48 + Ext SMPS
Pin Number
Alternate functions
Additional
functions
-
LPTIM1_ETR,
TIM4_CH1,
TIM8_BKIN2,
I2C1_SCL,
I2C4_SCL,
USART1_TX,
TSC_G2_IO3,
DCMI_D5/PSSI_D5,
LCD_R6,
SAI1_FS_B,
TIM16_CH1N,
EVENTOUT
COMP2_INP
COMP2_INM,
PVD_IN
-
43
43
43
43
58
59
B7
D7
93
93
B4
B4
136 137
D5
D5
PB7
I/O
FT
_fl
a
-
LPTIM1_IN2,
TIM4_CH2,
TIM8_BKIN,
I2C1_SDA,
I2C4_SDA,
USART1_RX,
UART4_CTS,
TSC_G2_IO4,
DCMI_VSYNC/PSSI_
RDY, LCD_VSYNC,
FMC_NL,
TIM17_CH1N,
EVENTOUT
44
44
44
44
59
60
D7
E6
94
94
A4
A4
137 138
E5
E5
PH3BOOT0
I/O
FT
-
EVENTOUT
STM32L4P5xx
Table 15. STM32L4P5xx pin definitions (continued)
112/311
Table 15. STM32L4P5xx pin definitions (continued)
45
45
46
45
45
46
60
61
61
62
B8
A8
B8
A8
95
96
95
96
A3
B3
A3
B3
138 139
139 140
C4
D4
C4
D4
PB8
PB9
I/O
I/O
I/O structure
Pin type
UFBGA169
UFBGA169 + ext SMPS
LQFP144
LQFP144 + Ext SMSP
UFBGA132
UFBGA132 + Ext SMPS
LQFP100
LQFP100 + Ext SMPS
WLCSP100
WLCSP100 + Ext SMPS
LQFP64
LQFP64 + Ext SMPS
LQFP48
LQFP48 + Ext SMPS
NC
Pin name
(function
after
reset)
Alternate functions
Additional
functions
FT (3)
_fl
TIM4_CH3,
SAI1_CK1,
I2C1_SCL,
DFSDM1_CKOUT,
SDMMC2_D4,
SDMMC1_CKIN,
CAN1_RX,
DCMI_D6/PSSI_D6,
LCD_DE,
SDMMC1_D4,
SAI1_MCLK_A,
TIM16_CH1,
EVENTOUT
-
FT
_fl
IR_OUT, TIM4_CH4,
SAI1_D2, I2C1_SDA,
SPI2_NSS,
SDMMC2_D5,
SDMMC1_CDIR,
CAN1_TX,
DCMI_D7/PSSI_D7,
SDMMC1_D5,
SAI1_FS_A,
TIM17_CH1,
EVENTOUT
-
-
STM32L4P5xx
Notes
DS12903 Rev 3
NC
UFQFPN48
UFQFPN48 + Ext SMPS
Pin Number
-
-
-
-
-
-
97
97
C3
C3
140 141
DS12903 Rev 3
-
-
-
-
-
-
-
-
NC
98
A2
A2
46
-
46
-
62
-
A9
-
98
-
C6
-
47
47
47
47
63
63
B9
A9
99
99
D3
D3
48
48
48
48
64
64
A10 A10 100 100
C4
C4
-
-
-
-
-
-
-
-
-
-
C4
C4
-
-
-
-
-
-
-
-
-
-
-
D3
D3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
A4
A4
PE0
I/O
I/O structure
Pin type
UFBGA169
UFBGA169 + ext SMPS
LQFP144
LQFP144 + Ext SMSP
UFBGA132
UFBGA132 + Ext SMPS
LQFP100
LQFP100 + Ext SMPS
WLCSP100
WLCSP100 + Ext SMPS
LQFP64
LQFP64 + Ext SMPS
LQFP48
LQFP48 + Ext SMPS
-
Pin name
(function
after
reset)
FT
Notes
-
UFQFPN48
UFQFPN48 + Ext SMPS
Pin Number
Alternate functions
Additional
functions
-
TIM4_ETR,
DCMI_D2/PSSI_D2,
LCD_HSYNC,
FMC_NBL0,
TIM16_CH1,
EVENTOUT
-
DCMI_D3/PSSI_D3,
LCD_VSYNC,
FMC_NBL1,
TIM17_CH1,
EVENTOUT
-
FT (3)
113/311
141 142
B4
B4
PE1
I/O
142
C6
-
VDD12
-
-
-
-
-
143 143
B3
B3
VSS
S
-
-
-
-
144 144
A3
A3
VDD
S
-
-
-
-
-
A3
A3
VDD
S
-
-
-
-
-
-
B3
B3
VSS
S
-
-
-
-
-
-
A2
A2
PH2
I/O
FT
-
OCTOSPIM_P1_IO4,
EVENTOUT
-
-
TIM8_CH3,
OCTOSPIM_P2_NCL
K,
DCMI_D7/PSSI_D7,
EVENTOUT
-
-
-
-
B2
B2
PI7
I/O
FT
STM32L4P5xx
Table 15. STM32L4P5xx pin definitions (continued)
114/311
Table 15. STM32L4P5xx pin definitions (continued)
UFQFPN48
LQFP48 + Ext SMPS
LQFP48
LQFP64 + Ext SMPS
LQFP64
WLCSP100 + Ext SMPS
WLCSP100
LQFP100 + Ext SMPS
LQFP100
UFBGA132 + Ext SMPS
UFBGA132
LQFP144 + Ext SMSP
LQFP144
UFBGA169 + ext SMPS
UFBGA169
Pin type
I/O structure
Notes
DS12903 Rev 3
UFQFPN48 + Ext SMPS
Pin Number
Alternate functions
-
-
-
-
-
-
-
-
-
-
-
-
-
-
B1
B1
PI9
I/O
FT
-
OCTOSPIM_P2_IO2,
CAN1_RX,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
A1
A1
PI10
I/O
FT
-
OCTOSPIM_P2_IO1,
PSSI_D14,
EVENTOUT
-
Pin name
(function
after
reset)
Additional
functions
1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output
mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF
- These GPIOs must not be used as current sources (for example to drive a LED).
2. After a Backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers which are not reset by the
system reset. For details on how to manage these GPIOs, refer to the Backup domain and RTC register descriptions in the RM0432 reference manual.
3. NC (not-connected) balls must be left unconnected. However, PF8 and PF9 NC' IOs are not bonded. They must be configured by software to output push-pull and forced to
0 in the output data register to avoid extra current consumption in low-power modes.
4. After reset, these pins are configured as JTAG/SW debug alternate functions, and the internal pull-up on PA15, PA13, PB4 pins and the internal pull-down on PA14 pin are
activated.
STM32L4P5xx
AF0
Port
DS12903 Rev 3
Port A
AF1
OTG_FS/SYS_A TIM1/2/5/8/LPTI
F
M1
AF2
TIM1/2/3/4/5
AF3
AF4
AF5
AF6
AF7
SPI2/SAI1/I2C4/
SPI1/2/3/I2C4/D SPI3/I2C3/DFSD
USART2/CAN2/
FSDM1/DCMI/O M1/COMP1/OCT USART1/2/3/SD
OTG_FS/TIM1/8 I2C1/2/3/4/DCMI
MMC2
CTOSPIM_P1/2/ OSPIM_P1/2/QU
/OCTOSPIM_P1/
ADSPI
QUADSPI
QUADSPI
115/311
PA0
-
TIM2_CH1
TIM5_CH1
TIM8_ETR
-
-
-
USART2_CTS_
NSS
PA1
-
TIM2_CH2
TIM5_CH2
-
I2C1_SMBA
SPI1_SCK
-
USART2_RTS_
DE
PA2
-
TIM2_CH3
TIM5_CH3
-
-
-
-
USART2_TX
PA3
-
TIM2_CH4
TIM5_CH4
SAI1_CK1
-
-
-
USART2_RX
PA4
-
-
-
OCTOSPIM_P1_
NCS
-
SPI1_NSS
SPI3_NSS
USART2_CK
PA5
-
TIM2_CH1
TIM2_ETR
TIM8_CH1N
PSSI_D14
SPI1_SCK
-
-
PA6
-
TIM1_BKIN
TIM3_CH1
TIM8_BKIN
DCMI_PIXCLK/P
SSI_PDCK
SPI1_MISO
-
USART3_CTS_
NSS
PA7
-
TIM1_CH1N
TIM3_CH2
TIM8_CH1N
I2C3_SCL
SPI1_MOSI
-
-
PA8
MCO
TIM1_CH1
-
SAI1_CK2
-
-
-
USART1_CK
PA9
-
TIM1_CH2
-
SPI2_SCK
-
DCMI_D0/PSSI_
D0
-
USART1_TX
PA10
-
TIM1_CH3
-
SAI1_D1
-
DCMI_D1/PSSI_
D1
-
USART1_RX
PA11
-
TIM1_CH4
TIM1_BKIN2
-
-
SPI1_MISO
-
USART1_CTS_
NSS
PA12
-
TIM1_ETR
-
-
-
SPI1_MOSI
OCTOSPIM_P2_
NCS
USART1_RTS_
DE
PA13
JTMS/SWDIO
IR_OUT
-
-
-
-
-
-
PA14
JTCK/SWCLK
LPTIM1_OUT
-
-
I2C1_SMBA
I2C4_SMBA
-
-
PA15
JTDI
TIM2_CH1
TIM2_ETR
USART2_RX
-
SPI1_NSS
SPI3_NSS
USART3_RTS_
DE
STM32L4P5xx
Table 16. Alternate function AF0 to AF7(1)
116/311
Table 16. Alternate function AF0 to AF7(1) (continued)
AF0
Port
DS12903 Rev 3
Port B
AF1
OTG_FS/SYS_A TIM1/2/5/8/LPTI
F
M1
AF2
TIM1/2/3/4/5
AF3
AF4
AF5
AF6
AF7
SPI2/SAI1/I2C4/
SPI1/2/3/I2C4/D SPI3/I2C3/DFSD
USART2/CAN2/
FSDM1/DCMI/O M1/COMP1/OCT USART1/2/3/SD
OTG_FS/TIM1/8 I2C1/2/3/4/DCMI
MMC2
CTOSPIM_P1/2/ OSPIM_P1/2/QU
/OCTOSPIM_P1/
ADSPI
QUADSPI
QUADSPI
-
TIM1_CH2N
TIM3_CH3
TIM8_CH2N
-
SPI1_NSS
-
USART3_CK
PB1
-
TIM1_CH3N
TIM3_CH4
TIM8_CH3N
-
-
DFSDM1_DATIN
0
USART3_RTS_
DE
PB2
RTC_OUT2
LPTIM1_OUT
-
-
I2C3_SMBA
-
DFSDM1_CKIN0
-
PB3
JTDO/TRACES
WO
TIM2_CH2
-
OCTOSPIM_P1_
IO4
-
SPI1_SCK
SPI3_SCK
USART1_RTS_
DE
PB4
NJTRST
-
TIM3_CH1
OCTOSPIM_P1_
IO5
I2C3_SDA
SPI1_MISO
SPI3_MISO
USART1_CTS_
NSS
PB5
-
LPTIM1_IN1
TIM3_CH2
OCTOSPIM_P1_
IO0
I2C1_SMBA
SPI1_MOSI
SPI3_MOSI
USART1_CK
PB6
-
LPTIM1_ETR
TIM4_CH1
TIM8_BKIN2
I2C1_SCL
I2C4_SCL
-
USART1_TX
PB7
-
LPTIM1_IN2
TIM4_CH2
TIM8_BKIN
I2C1_SDA
I2C4_SDA
-
USART1_RX
PB8
-
-
TIM4_CH3
SAI1_CK1
I2C1_SCL
DFSDM1_CKOU
T
-
SDMMC2_D4
PB9
-
IR_OUT
TIM4_CH4
SAI1_D2
I2C1_SDA
SPI2_NSS
-
SDMMC2_D5
PB10
-
TIM2_CH3
-
I2C4_SCL
I2C2_SCL
SPI2_SCK
OCTOSPIM_P1_
IO3
USART3_TX
PB11
-
TIM2_CH4
-
I2C4_SDA
I2C2_SDA
-
-
USART3_RX
PB12
-
TIM1_BKIN
-
TIM1_BKIN
I2C2_SMBA
SPI2_NSS
DFSDM1_DATIN
1
USART3_CK
PB13
-
TIM1_CH1N
-
-
I2C2_SCL
SPI2_SCK
DFSDM1_CKIN1
USART3_CTS_
NSS
PB14
-
TIM1_CH2N
-
TIM8_CH2N
I2C2_SDA
SPI2_MISO
DFSDM1_DATIN
2
USART3_RTS_
DE
PB15
RTC_REFIN
TIM1_CH3N
-
TIM8_CH3N
-
SPI2_MOSI
DFSDM1_CKIN2
-
STM32L4P5xx
PB0
AF0
Port
DS12903 Rev 3
Port C
AF1
OTG_FS/SYS_A TIM1/2/5/8/LPTI
F
M1
AF2
TIM1/2/3/4/5
AF3
AF4
AF5
AF6
AF7
SPI2/SAI1/I2C4/
SPI1/2/3/I2C4/D SPI3/I2C3/DFSD
USART2/CAN2/
FSDM1/DCMI/O M1/COMP1/OCT USART1/2/3/SD
OTG_FS/TIM1/8 I2C1/2/3/4/DCMI
MMC2
CTOSPIM_P1/2/ OSPIM_P1/2/QU
/OCTOSPIM_P1/
ADSPI
QUADSPI
QUADSPI
PC0
-
LPTIM1_IN1
-
-
I2C3_SCL
-
-
SDMMC2_CKIN
PC1
TRACED0
LPTIM1_OUT
-
SPI2_MOSI
I2C3_SDA
-
-
-
PC2
-
LPTIM1_IN2
-
-
-
SPI2_MISO
DFSDM1_CKOU
T
-
PC3
-
LPTIM1_ETR
-
SAI1_D1
-
SPI2_MOSI
-
-
PC4
-
-
-
-
-
OCTOSPIM_P2_
NCS
-
USART3_TX
PC5
-
-
-
SAI1_D3
PSSI_D15
-
-
USART3_RX
PC6
-
-
TIM3_CH1
TIM8_CH1
-
-
DFSDM1_CKIN3
SDMMC2_D6
PC7
-
-
TIM3_CH2
TIM8_CH2
-
-
DFSDM1_DATIN
3
SDMMC2_D7
PC8
-
-
TIM3_CH3
TIM8_CH3
-
-
-
-
PC9
TRACED0
TIM8_BKIN2
TIM3_CH4
TIM8_CH4
DCMI_D3/PSSI_
D3
-
I2C3_SDA
-
PC10
TRACED1
-
-
-
DCMI_VSYNC/P
SSI_RDY
-
SPI3_SCK
USART3_TX
PC11
-
-
-
-
DCMI_D2/PSSI_ OCTOSPIM_P1_
D2
NCS
SPI3_MISO
USART3_RX
PC12
TRACED3
-
-
-
-
-
SPI3_MOSI
USART3_CK
PC13
-
-
-
-
-
-
-
-
PC14
-
-
-
-
-
-
-
-
PC15
-
-
-
-
-
-
-
-
STM32L4P5xx
Table 16. Alternate function AF0 to AF7(1) (continued)
117/311
118/311
Table 16. Alternate function AF0 to AF7(1) (continued)
AF0
Port
DS12903 Rev 3
Port D
AF1
OTG_FS/SYS_A TIM1/2/5/8/LPTI
F
M1
AF2
TIM1/2/3/4/5
AF3
AF4
AF5
AF6
AF7
SPI2/SAI1/I2C4/
SPI1/2/3/I2C4/D SPI3/I2C3/DFSD
USART2/CAN2/
FSDM1/DCMI/O M1/COMP1/OCT USART1/2/3/SD
OTG_FS/TIM1/8 I2C1/2/3/4/DCMI
MMC2
CTOSPIM_P1/2/ OSPIM_P1/2/QU
/OCTOSPIM_P1/
ADSPI
QUADSPI
QUADSPI
-
-
-
-
-
SPI2_NSS
-
-
PD1
-
-
-
-
-
SPI2_SCK
-
-
PD2
TRACED2
-
TIM3_ETR
-
-
-
-
USART3_RTS_
DE
PD3
-
-
-
SPI2_SCK
DCMI_D5/PSSI_
D5
SPI2_MISO
DFSDM1_DATIN
0
USART2_CTS_
NSS
PD4
-
-
-
-
-
SPI2_MOSI
DFSDM1_CKIN0
USART2_RTS_
DE
PD5
-
-
-
-
-
-
-
USART2_TX
PD6
-
-
-
SAI1_D1
DCMI_D10/PSSI
_D10
SPI3_MOSI
DFSDM1_DATIN
1
USART2_RX
PD7
-
-
-
-
-
-
DFSDM1_CKIN1
USART2_CK
PD8
-
-
-
-
-
-
-
USART3_TX
PD9
-
-
-
-
-
-
-
USART3_RX
PD10
-
-
-
-
-
-
-
USART3_CK
PD11
-
-
-
-
I2C4_SMBA
-
-
USART3_CTS_
NSS
PD12
-
-
TIM4_CH1
-
I2C4_SCL
-
-
USART3_RTS_
DE
PD13
-
-
TIM4_CH2
-
I2C4_SDA
-
-
-
PD14
-
-
TIM4_CH3
-
-
-
-
-
PD15
-
-
TIM4_CH4
-
-
-
-
-
STM32L4P5xx
PD0
AF0
Port
DS12903 Rev 3
Port E
AF1
OTG_FS/SYS_A TIM1/2/5/8/LPTI
F
M1
AF2
TIM1/2/3/4/5
AF3
AF4
AF5
AF6
AF7
SPI2/SAI1/I2C4/
SPI1/2/3/I2C4/D SPI3/I2C3/DFSD
USART2/CAN2/
FSDM1/DCMI/O M1/COMP1/OCT USART1/2/3/SD
OTG_FS/TIM1/8 I2C1/2/3/4/DCMI
MMC2
CTOSPIM_P1/2/ OSPIM_P1/2/QU
/OCTOSPIM_P1/
ADSPI
QUADSPI
QUADSPI
PE0
-
-
TIM4_ETR
-
-
-
-
-
PE1
-
-
-
-
-
-
-
-
PE2
TRACECK
-
TIM3_ETR
SAI1_CK1
-
-
-
-
PE3
TRACED0
-
TIM3_CH1
OCTOSPIM_P1_
DQS
-
-
-
-
PE4
TRACED1
-
TIM3_CH2
SAI1_D2
-
-
DFSDM1_DATIN
3
-
PE5
TRACED2
-
TIM3_CH3
SAI1_CK2
-
-
DFSDM1_CKIN3
-
PE6
TRACED3
-
TIM3_CH4
SAI1_D1
-
-
-
-
PE7
-
TIM1_ETR
-
-
-
-
DFSDM1_DATIN
2
-
PE8
-
TIM1_CH1N
-
-
-
-
DFSDM1_CKIN2
-
PE9
-
TIM1_CH1
-
-
-
-
DFSDM1_CKOU
T
-
PE10
-
TIM1_CH2N
-
-
-
-
-
-
PE11
-
TIM1_CH2
-
-
-
-
-
-
PE12
-
TIM1_CH3N
-
-
-
SPI1_NSS
-
-
PE13
-
TIM1_CH3
-
-
-
SPI1_SCK
-
-
PE14
-
TIM1_CH4
TIM1_BKIN2
TIM1_BKIN2
-
SPI1_MISO
-
-
PE15
-
TIM1_BKIN
-
TIM1_BKIN
-
SPI1_MOSI
-
-
STM32L4P5xx
Table 16. Alternate function AF0 to AF7(1) (continued)
119/311
120/311
Table 16. Alternate function AF0 to AF7(1) (continued)
AF0
Port
DS12903 Rev 3
Port F
AF1
OTG_FS/SYS_A TIM1/2/5/8/LPTI
F
M1
AF2
TIM1/2/3/4/5
AF3
AF4
AF5
AF6
AF7
SPI2/SAI1/I2C4/
SPI1/2/3/I2C4/D SPI3/I2C3/DFSD
USART2/CAN2/
FSDM1/DCMI/O M1/COMP1/OCT USART1/2/3/SD
OTG_FS/TIM1/8 I2C1/2/3/4/DCMI
MMC2
CTOSPIM_P1/2/ OSPIM_P1/2/QU
/OCTOSPIM_P1/
ADSPI
QUADSPI
QUADSPI
-
-
-
-
I2C2_SDA
OCTOSPIM_P2_
IO0
-
-
PF1
-
-
-
-
I2C2_SCL
OCTOSPIM_P2_
IO1
-
-
PF2
-
-
-
-
I2C2_SMBA
OCTOSPIM_P2_
IO2
-
-
PF3
-
-
-
-
-
OCTOSPIM_P2_
IO3
-
-
PF4
-
-
-
-
-
OCTOSPIM_P2_
CLK
-
-
PF5
-
-
-
-
-
OCTOSPIM_P2_
NCLK
-
-
PF6
-
TIM5_ETR
TIM5_CH1
-
-
-
-
-
PF7
-
-
TIM5_CH2
-
-
-
-
-
PF8
-
-
TIM5_CH3
-
-
-
-
-
PF9
-
-
TIM5_CH4
-
-
-
-
-
PF10
-
-
-
OCTOSPIM_P1_
CLK
PSSI_D15
-
DFSDM1_CKOU
T
-
PF11
-
-
-
OCTOSPIM_P1_
NCLK
-
-
-
-
PF12
-
-
-
-
-
OCTOSPIM_P2_
DQS
-
-
PF13
-
-
-
-
I2C4_SMBA
-
-
-
PF14
-
-
-
-
I2C4_SCL
-
-
-
PF15
-
-
-
-
I2C4_SDA
-
-
-
STM32L4P5xx
PF0
AF0
Port
DS12903 Rev 3
Port G
AF1
OTG_FS/SYS_A TIM1/2/5/8/LPTI
F
M1
AF2
TIM1/2/3/4/5
AF3
AF4
AF5
AF6
AF7
SPI2/SAI1/I2C4/
SPI1/2/3/I2C4/D SPI3/I2C3/DFSD
USART2/CAN2/
FSDM1/DCMI/O M1/COMP1/OCT USART1/2/3/SD
OTG_FS/TIM1/8 I2C1/2/3/4/DCMI
MMC2
CTOSPIM_P1/2/ OSPIM_P1/2/QU
/OCTOSPIM_P1/
ADSPI
QUADSPI
QUADSPI
121/311
PG0
-
-
-
-
-
OCTOSPIM_P2_
IO4
-
-
PG1
-
-
-
-
-
OCTOSPIM_P2_
IO5
-
-
PG2
-
-
-
-
-
SPI1_SCK
-
-
PG3
-
-
-
-
-
SPI1_MISO
-
-
PG4
-
-
-
-
-
SPI1_MOSI
-
-
PG5
-
-
-
-
-
SPI1_NSS
-
-
PG6
-
-
-
OCTOSPIM_P1_
DQS
I2C3_SMBA
-
-
-
PG7
-
-
-
SAI1_CK1
I2C3_SCL
PG8
-
-
-
-
I2C3_SDA
-
-
-
PG9
-
-
-
-
-
OCTOSPIM_P2_
IO6
SPI3_SCK
USART1_TX
PG10
-
LPTIM1_IN1
-
-
-
OCTOSPIM_P2_
IO7
SPI3_MISO
USART1_RX
PG11
-
LPTIM1_IN2
-
OCTOSPIM_P1_
IO5
-
-
SPI3_MOSI
USART1_CTS_
NSS
PG12
-
LPTIM1_ETR
-
-
-
OCTOSPIM_P2_
NCS
SPI3_NSS
USART1_RTS_
DE
PG13
-
-
-
-
I2C1_SDA
-
-
USART1_CK
PG14
-
-
-
-
I2C1_SCL
-
-
-
PG15
-
LPTIM1_OUT
-
-
I2C1_SMBA
OCTOSPIM_P2_
DQS
-
-
OCTOSPIM_P2_ DFSDM1_CKOU
DQS
T
-
STM32L4P5xx
Table 16. Alternate function AF0 to AF7(1) (continued)
122/311
Table 16. Alternate function AF0 to AF7(1) (continued)
AF0
Port
DS12903 Rev 3
Port H
AF1
OTG_FS/SYS_A TIM1/2/5/8/LPTI
F
M1
AF2
TIM1/2/3/4/5
AF3
AF4
AF5
AF6
AF7
SPI2/SAI1/I2C4/
SPI1/2/3/I2C4/D SPI3/I2C3/DFSD
USART2/CAN2/
FSDM1/DCMI/O M1/COMP1/OCT USART1/2/3/SD
OTG_FS/TIM1/8 I2C1/2/3/4/DCMI
MMC2
CTOSPIM_P1/2/ OSPIM_P1/2/QU
/OCTOSPIM_P1/
ADSPI
QUADSPI
QUADSPI
-
-
-
-
-
-
-
-
PH1
-
-
-
-
-
-
-
-
PH2
-
-
-
OCTOSPIM_P1_
IO4
-
-
-
-
PH3
-
-
-
-
-
-
-
-
PH4
-
-
-
-
I2C2_SCL
OCTOSPIM_P2_
DQS
-
-
PH5
-
-
-
-
I2C2_SDA
-
-
-
PH6
-
-
-
-
I2C2_SMBA
OCTOSPIM_P2_
CLK
-
-
PH7
-
-
-
-
I2C3_SCL
OCTOSPIM_P2_
NCLK
-
-
PH8
-
-
-
-
I2C3_SDA
OCTOSPIM_P2_
IO3
-
-
PH9
-
-
-
-
I2C3_SMBA
OCTOSPIM_P2_
IO4
-
-
PH10
-
-
TIM5_CH1
-
-
OCTOSPIM_P2_
IO5
-
-
PH11
-
-
TIM5_CH2
-
-
OCTOSPIM_P2_
IO6
-
-
PH12
-
-
TIM5_CH3
-
-
OCTOSPIM_P2_
IO7
-
-
PH13
-
-
-
TIM8_CH1N
-
-
-
-
PH14
-
-
-
TIM8_CH2N
-
-
-
-
PH15
-
-
-
TIM8_CH3N
-
OCTOSPIM_P2_
IO6
-
-
STM32L4P5xx
PH0
AF0
Port
DS12903 Rev 3
Port I
AF1
OTG_FS/SYS_A TIM1/2/5/8/LPTI
F
M1
AF2
TIM1/2/3/4/5
AF3
AF4
AF5
AF6
AF7
SPI2/SAI1/I2C4/
SPI1/2/3/I2C4/D SPI3/I2C3/DFSD
USART2/CAN2/
FSDM1/DCMI/O M1/COMP1/OCT USART1/2/3/SD
OTG_FS/TIM1/8 I2C1/2/3/4/DCMI
MMC2
CTOSPIM_P1/2/ OSPIM_P1/2/QU
/OCTOSPIM_P1/
ADSPI
QUADSPI
QUADSPI
PI0
-
-
TIM5_CH4
OCTOSPIM_P1_
IO5
-
SPI2_NSS
-
-
PI1
-
-
-
-
-
SPI2_SCK
-
-
PI2
-
-
-
TIM8_CH4
-
SPI2_MISO
-
-
PI3
-
-
-
TIM8_ETR
-
SPI2_MOSI
-
-
PI4
-
-
-
TIM8_BKIN
-
-
-
-
PI5
-
-
-
TIM8_CH1
-
OCTOSPIM_P2_
NCS
-
-
PI6
-
-
-
TIM8_CH2
-
OCTOSPIM_P2_
CLK
-
-
PI7
-
-
-
TIM8_CH3
-
OCTOSPIM_P2_
NCLK
-
-
PI8
-
-
-
-
-
OCTOSPIM_P2_
NCS
-
-
PI9
-
-
-
-
-
OCTOSPIM_P2_
IO2
-
-
PI10
-
-
-
-
-
OCTOSPIM_P2_
IO1
-
-
PI11
-
-
-
-
-
OCTOSPIM_P2_
IO0
-
-
1. Refer to next table for AF8 to AF15.
STM32L4P5xx
Table 16. Alternate function AF0 to AF7(1) (continued)
123/311
124/311
Table 17. Alternate function AF8 to AF15(1)
AF8
AF9
AF13
AF14
AF15
UART4/5/LPUA
RT1/CAN2/SDM
MC1/2
CAN1/TSC/LCD
SAI1/2/TIM8
TIM2/8/15/16/1
7/LPTIM2
EVENOUT
PA0
UART4_TX
-
-
-
-
SAI1_EXTCLK
TIM2_ETR
EVENTOUT
PA1
UART4_RX
-
OCTOSPIM_P1_DQS
-
SDMMC2_CMD
-
TIM15_CH1N
EVENTOUT
PA2
LPUART1_TX
-
OCTOSPIM_P1_NCS
-
-
SAI2_EXTCLK
TIM15_CH1
EVENTOUT
PA3
LPUART1_RX
-
OCTOSPIM_P1_CLK
-
-
SAI1_MCLK_A
TIM15_CH2
EVENTOUT
PA4
-
-
DCMI_HSYNC/PSSI_
DE
LCD_CLK
-
SAI1_FS_B
LPTIM2_OUT
EVENTOUT
PA5
-
-
-
LCD_R7
-
-
LPTIM2_ETR
EVENTOUT
PA6
LPUART1_CTS
-
OCTOSPIM_P1_IO3
-
TIM1_BKIN
TIM8_BKIN
TIM16_CH1
EVENTOUT
PA7
-
-
OCTOSPIM_P1_IO2
-
-
-
TIM17_CH1
EVENTOUT
PA8
-
-
OTG_FS_SOF
LCD_B7
-
SAI1_SCK_A
LPTIM2_OUT
EVENTOUT
PA9
-
-
-
LCD_G7
-
SAI1_FS_A
TIM15_BKIN
EVENTOUT
PA10
-
-
OTG_FS_ID
LCD_G6
-
SAI1_SD_A
TIM17_BKIN
EVENTOUT
PA11
-
CAN1_RX
OTG_FS_DM
LCD_DE
TIM1_BKIN2
-
-
EVENTOUT
PA12
-
CAN1_TX
OTG_FS_DP
LCD_VSYNC
-
-
-
EVENTOUT
PA13
-
-
OTG_FS_NOE
-
-
SAI1_SD_B
-
EVENTOUT
PA14
-
-
OTG_FS_SOF
-
-
SAI1_FS_B
-
EVENTOUT
TSC_G3_IO1
-
LCD_HSYNC
-
SAI2_FS_B
-
EVENTOUT
Port
DS12903 Rev 3
Port
A
PA15 UART4_RTS_DE
AF10
AF11
AF12
SDMMC1/2/COM
CAN2/OTG_FS/DCMI/
SDMMC2/LCD/D
P1/2/TIM1/8/FM
OCTOSPIM_P1/2/QU
SI/LCD
C/SWPMI1
ADSPI
STM32L4P5xx
AF8
AF9
AF13
AF14
AF15
UART4/5/LPUA
RT1/CAN2/SDM
MC1/2
CAN1/TSC/LCD
SAI1/2/TIM8
TIM2/8/15/16/1
7/LPTIM2
EVENOUT
PB0
-
-
OCTOSPIM_P1_IO1
LCD_B6
COMP1_OUT
SAI1_EXTCLK
-
EVENTOUT
PB1
LPUART1_RTS_
DE
-
OCTOSPIM_P1_IO0
LCD_G6
-
-
LPTIM2_IN1
EVENTOUT
PB2
-
-
OCTOSPIM_P1_DQS
-
-
-
-
EVENTOUT
PB3
-
-
OTG_FS_CRS_SYNC
-
SDMMC2_D2
SAI1_SCK_B
-
EVENTOUT
PB4
UART5_RTS_DE
TSC_G2_IO1
DCMI_D12/PSSI_D12
-
SDMMC2_D3
SAI1_MCLK_B
TIM17_BKIN
EVENTOUT
PB5
UART5_CTS
TSC_G2_IO2
DCMI_D10/PSSI_D10
-
COMP2_OUT
SAI1_SD_B
TIM16_BKIN
EVENTOUT
PB6
-
TSC_G2_IO3
DCMI_D5/PSSI_D5
LCD_R6
TIM8_BKIN2
SAI1_FS_B
TIM16_CH1N
EVENTOUT
PB7
UART4_CTS
TSC_G2_IO4
DCMI_VSYNC/PSSI_
RDY
LCD_VSYNC
FMC_NL
TIM8_BKIN
TIM17_CH1N
EVENTOUT
PB8
SDMMC1_CKIN
CAN1_RX
DCMI_D6/PSSI_D6
LCD_DE
SDMMC1_D4
SAI1_MCLK_A
TIM16_CH1
EVENTOUT
PB9
SDMMC1_CDIR
CAN1_TX
DCMI_D7/PSSI_D7
-
SDMMC1_D5
SAI1_FS_A
TIM17_CH1
EVENTOUT
PB10
LPUART1_RX
TSC_SYNC
OCTOSPIM_P1_CLK
-
COMP1_OUT
SAI1_SCK_A
-
EVENTOUT
PB11
LPUART1_TX
-
OCTOSPIM_P1_NCS
LCD_VSYNC
COMP2_OUT
-
-
EVENTOUT
PB12
LPUART1_RTS_
DE
TSC_G1_IO1
OCTOSPIM_P1_NCL
K
-
SDMMC2_CK
SAI2_FS_A
TIM15_BKIN
EVENTOUT
PB13
LPUART1_CTS
TSC_G1_IO2
OCTOSPIM_P1_IO1
-
-
SAI2_SCK_A
TIM15_CH1N
EVENTOUT
PB14
-
TSC_G1_IO3
OCTOSPIM_P1_IO6
SDMMC2_D0
-
SAI2_MCLK_A
TIM15_CH1
EVENTOUT
PB15
-
TSC_G1_IO4
OCTOSPIM_P1_IO7
SDMMC2_D1
-
SAI2_SD_A
TIM15_CH2
EVENTOUT
Port
DS12903 Rev 3
Port
B
AF10
AF11
AF12
SDMMC1/2/COM
CAN2/OTG_FS/DCMI/
SDMMC2/LCD/D
P1/2/TIM1/8/FM
OCTOSPIM_P1/2/QU
SI/LCD
C/SWPMI1
ADSPI
STM32L4P5xx
Table 17. Alternate function AF8 to AF15(1) (continued)
125/311
126/311
Table 17. Alternate function AF8 to AF15(1) (continued)
AF8
AF9
AF13
AF14
AF15
UART4/5/LPUA
RT1/CAN2/SDM
MC1/2
CAN1/TSC/LCD
SAI1/2/TIM8
TIM2/8/15/16/1
7/LPTIM2
EVENOUT
PC0
LPUART1_RX
-
-
LCD_DE
SDMMC1_CMD
SAI2_FS_A
LPTIM2_IN1
EVENTOUT
PC1
LPUART1_TX
-
OCTOSPIM_P1_IO4
-
-
SAI1_SD_A
-
EVENTOUT
PC2
-
-
OCTOSPIM_P1_IO5
LCD_HSYNC
-
-
-
EVENTOUT
PC3
-
-
OCTOSPIM_P1_IO6
-
-
SAI1_SD_A
LPTIM2_ETR
EVENTOUT
PC4
-
-
OCTOSPIM_P1_IO7
-
-
-
-
EVENTOUT
PC5
-
-
-
LCD_CLK
-
-
-
EVENTOUT
PC6
SDMMC1_D0DI
R
TSC_G4_IO1
DCMI_D0/PSSI_D0
LCD_G7
SDMMC1_D6
SAI2_MCLK_A
-
EVENTOUT
PC7
SDMMC1_D123
DIR
TSC_G4_IO2
DCMI_D1/PSSI_D1
LCD_B6
SDMMC1_D7
SAI2_MCLK_B
-
EVENTOUT
PC8
-
TSC_G4_IO3
DCMI_D2/PSSI_D2
-
SDMMC1_D0
-
-
EVENTOUT
PC9
-
TSC_G4_IO4
OTG_FS_NOE
-
SDMMC1_D1
SAI2_EXTCLK
TIM8_BKIN2
EVENTOUT
PC10
UART4_TX
TSC_G3_IO2
DCMI_D8/PSSI_D8
-
SDMMC1_D2
SAI2_SCK_B
-
EVENTOUT
PC11
UART4_RX
TSC_G3_IO3
DCMI_D4/PSSI_D4
-
SDMMC1_D3
SAI2_MCLK_B
-
EVENTOUT
PC12
UART5_TX
TSC_G3_IO4
DCMI_D9/PSSI_D9
LCD_R6
SDMMC1_CK
SAI2_SD_B
-
EVENTOUT
PC13
-
-
-
-
-
-
-
EVENTOUT
PC14
-
-
-
-
-
-
-
EVENTOUT
PC15
-
-
-
-
-
-
-
EVENTOUT
Port
DS12903 Rev 3
Port
C
AF10
AF11
AF12
SDMMC1/2/COM
CAN2/OTG_FS/DCMI/
SDMMC2/LCD/D
P1/2/TIM1/8/FM
OCTOSPIM_P1/2/QU
SI/LCD
C/SWPMI1
ADSPI
STM32L4P5xx
AF8
AF9
AF13
AF14
AF15
UART4/5/LPUA
RT1/CAN2/SDM
MC1/2
CAN1/TSC/LCD
SAI1/2/TIM8
TIM2/8/15/16/1
7/LPTIM2
EVENOUT
PD0
-
CAN1_RX
-
LCD_B4
FMC_D2
-
-
EVENTOUT
PD1
-
CAN1_TX
-
LCD_B5
FMC_D3
-
-
EVENTOUT
PD2
UART5_RX
TSC_SYNC
DCMI_D11/PSSI_D11
-
SDMMC1_CMD
-
-
EVENTOUT
PD3
-
-
OCTOSPIM_P2_NCS
LCD_CLK
FMC_CLK
-
-
EVENTOUT
PD4
SDMMC2_CKIN
-
OCTOSPIM_P1_IO4
-
FMC_NOE
-
-
EVENTOUT
PD5
-
-
OCTOSPIM_P1_IO5
-
FMC_NWE
-
-
EVENTOUT
PD6
SDMMC2_CK
-
OCTOSPIM_P1_IO6
LCD_DE
FMC_NWAIT
SAI1_SD_A
-
EVENTOUT
PD7
SDMMC2_CMD
-
OCTOSPIM_P1_IO7
-
FMC_NCE/FMC
_NE1
-
-
EVENTOUT
PD8
-
-
DCMI_HSYNC/PSSI_
DE
LCD_R3
FMC_D13
-
-
EVENTOUT
PD9
-
-
DCMI_PIXCLK/PSSI_
PDCK
LCD_R4
FMC_D14
SAI2_MCLK_A
-
EVENTOUT
PD10
-
TSC_G6_IO1
-
LCD_R5
FMC_D15
SAI2_SCK_A
-
EVENTOUT
PD11
-
TSC_G6_IO2
-
LCD_R6
FMC_A16
SAI2_SD_A
LPTIM2_ETR
EVENTOUT
PD12
-
TSC_G6_IO3
-
LCD_R7
FMC_A17
SAI2_FS_A
LPTIM2_IN1
EVENTOUT
PD13
-
TSC_G6_IO4
-
-
FMC_A18
-
LPTIM2_OUT
EVENTOUT
PD14
-
-
-
LCD_B2
FMC_D0
-
-
EVENTOUT
PD15
-
-
-
LCD_B3
FMC_D1
-
-
EVENTOUT
Port
DS12903 Rev 3
Port
D
AF10
AF11
AF12
SDMMC1/2/COM
CAN2/OTG_FS/DCMI/
SDMMC2/LCD/D
P1/2/TIM1/8/FM
OCTOSPIM_P1/2/QU
SI/LCD
C/SWPMI1
ADSPI
STM32L4P5xx
Table 17. Alternate function AF8 to AF15(1) (continued)
127/311
128/311
Table 17. Alternate function AF8 to AF15(1) (continued)
AF8
AF9
AF13
AF14
AF15
UART4/5/LPUA
RT1/CAN2/SDM
MC1/2
CAN1/TSC/LCD
SAI1/2/TIM8
TIM2/8/15/16/1
7/LPTIM2
EVENOUT
PE0
-
-
DCMI_D2/PSSI_D2
LCD_HSYNC
FMC_NBL0
-
TIM16_CH1
EVENTOUT
PE1
-
-
DCMI_D3/PSSI_D3
LCD_VSYNC
FMC_NBL1
-
TIM17_CH1
EVENTOUT
PE2
-
TSC_G7_IO1
-
LCD_R7
FMC_A23
SAI1_MCLK_A
-
EVENTOUT
PE3
-
TSC_G7_IO2
-
LCD_R6
FMC_A19
SAI1_SD_B
-
EVENTOUT
PE4
-
TSC_G7_IO3
DCMI_D4/PSSI_D4
LCD_B7
FMC_A20
SAI1_FS_A
-
EVENTOUT
PE5
-
TSC_G7_IO4
DCMI_D6/PSSI_D6
LCD_G7
FMC_A21
SAI1_SCK_A
-
EVENTOUT
PE6
-
-
DCMI_D7/PSSI_D7
LCD_G6
FMC_A22
SAI1_SD_A
-
EVENTOUT
PE7
-
-
-
LCD_B6
FMC_D4
SAI1_SD_B
-
EVENTOUT
PE8
-
-
-
LCD_B7
FMC_D5
SAI1_SCK_B
-
EVENTOUT
PE9
-
-
OCTOSPIM_P1_NCL
K
LCD_G2
FMC_D6
SAI1_FS_B
-
EVENTOUT
PE10
-
TSC_G5_IO1
OCTOSPIM_P1_CLK
LCD_G3
FMC_D7
SAI1_MCLK_B
-
EVENTOUT
PE11
-
TSC_G5_IO2
OCTOSPIM_P1_NCS
LCD_G4
FMC_D8
-
-
EVENTOUT
PE12
-
TSC_G5_IO3
OCTOSPIM_P1_IO0
LCD_G5
FMC_D9
-
-
EVENTOUT
PE13
-
TSC_G5_IO4
OCTOSPIM_P1_IO1
LCD_G6
FMC_D10
-
-
EVENTOUT
PE14
-
-
OCTOSPIM_P1_IO2
LCD_G7
FMC_D11
-
-
EVENTOUT
PE15
-
-
OCTOSPIM_P1_IO3
LCD_R2
FMC_D12
-
-
EVENTOUT
Port
DS12903 Rev 3
Port
E
AF10
AF11
AF12
SDMMC1/2/COM
CAN2/OTG_FS/DCMI/
SDMMC2/LCD/D
P1/2/TIM1/8/FM
OCTOSPIM_P1/2/QU
SI/LCD
C/SWPMI1
ADSPI
STM32L4P5xx
AF8
AF9
AF13
AF14
AF15
UART4/5/LPUA
RT1/CAN2/SDM
MC1/2
CAN1/TSC/LCD
SAI1/2/TIM8
TIM2/8/15/16/1
7/LPTIM2
EVENOUT
PF0
-
-
-
-
FMC_A0
-
-
EVENTOUT
PF1
-
-
-
-
FMC_A1
-
-
EVENTOUT
PF2
-
-
-
-
FMC_A2
-
-
EVENTOUT
PF3
-
-
-
-
FMC_A3
-
-
EVENTOUT
PF4
-
-
-
-
FMC_A4
-
-
EVENTOUT
PF5
-
-
-
-
FMC_A5
-
-
EVENTOUT
PF6
-
-
OCTOSPIM_P1_IO3
-
-
SAI1_SD_B
-
EVENTOUT
PF7
-
-
OCTOSPIM_P1_IO2
-
-
SAI1_MCLK_B
-
EVENTOUT
PF8
-
-
OCTOSPIM_P1_IO0
-
-
SAI1_SCK_B
-
EVENTOUT
PF9
-
-
OCTOSPIM_P1_IO1
-
-
SAI1_FS_B
TIM15_CH1
EVENTOUT
PF10
-
-
DCMI_D11/PSSI_D11
-
-
SAI1_D3
TIM15_CH2
EVENTOUT
PF11
-
LCD_DE
DCMI_D12/PSSI_D12
-
-
-
-
EVENTOUT
PF12
-
-
-
LCD_B0
FMC_A6
-
-
EVENTOUT
PF13
-
-
-
LCD_B1
FMC_A7
-
-
EVENTOUT
PF14
-
TSC_G8_IO1
-
LCD_G0
FMC_A8
-
-
EVENTOUT
PF15
-
TSC_G8_IO2
-
LCD_G1
FMC_A9
-
-
EVENTOUT
Port
DS12903 Rev 3
Port
F
AF10
AF11
AF12
SDMMC1/2/COM
CAN2/OTG_FS/DCMI/
SDMMC2/LCD/D
P1/2/TIM1/8/FM
OCTOSPIM_P1/2/QU
SI/LCD
C/SWPMI1
ADSPI
STM32L4P5xx
Table 17. Alternate function AF8 to AF15(1) (continued)
129/311
130/311
Table 17. Alternate function AF8 to AF15(1) (continued)
AF8
AF9
AF13
AF14
AF15
UART4/5/LPUA
RT1/CAN2/SDM
MC1/2
CAN1/TSC/LCD
SAI1/2/TIM8
TIM2/8/15/16/1
7/LPTIM2
EVENOUT
PG0
-
TSC_G8_IO3
-
-
FMC_A10
-
-
EVENTOUT
PG1
-
TSC_G8_IO4
-
-
FMC_A11
-
-
EVENTOUT
PG2
-
-
-
SDMMC2_D4
FMC_A12
SAI2_SCK_B
-
EVENTOUT
PG3
-
-
-
SDMMC2_D5
FMC_A13
SAI2_FS_B
-
EVENTOUT
PG4
-
-
-
SDMMC2_D6
FMC_A14
SAI2_MCLK_B
-
EVENTOUT
PG5
LPUART1_CTS
-
-
SDMMC2_D7
FMC_A15
SAI2_SD_B
-
EVENTOUT
PG6
LPUART1_RTS_
DE
LCD_R1
-
-
-
-
-
EVENTOUT
PG7
LPUART1_TX
-
-
-
FMC_INT
SAI1_MCLK_A
-
EVENTOUT
PG8
LPUART1_RX
-
-
-
-
-
-
EVENTOUT
PG9
-
-
-
SDMMC2_D0
FMC_NCE/FMC
_NE2
SAI2_SCK_A
TIM15_CH1N
EVENTOUT
PG10
-
-
-
SDMMC2_D1
FMC_NE3
SAI2_FS_A
TIM15_CH1
EVENTOUT
PG11
-
-
-
SDMMC2_D2
-
SAI2_MCLK_A
TIM15_CH2
EVENTOUT
PG12
-
-
-
SDMMC2_D3
FMC_NE4
SAI2_SD_A
-
EVENTOUT
PG13
-
-
-
LCD_R0
FMC_A24
-
-
EVENTOUT
PG14
-
-
-
LCD_R1
FMC_A25
-
-
EVENTOUT
PG15
-
-
DCMI_D13/PSSI_D13
-
-
-
-
EVENTOUT
Port
DS12903 Rev 3
Port
G
AF10
AF11
AF12
SDMMC1/2/COM
CAN2/OTG_FS/DCMI/
SDMMC2/LCD/D
P1/2/TIM1/8/FM
OCTOSPIM_P1/2/QU
SI/LCD
C/SWPMI1
ADSPI
STM32L4P5xx
AF8
AF9
AF13
AF14
AF15
UART4/5/LPUA
RT1/CAN2/SDM
MC1/2
CAN1/TSC/LCD
SAI1/2/TIM8
TIM2/8/15/16/1
7/LPTIM2
EVENOUT
PH0
-
-
-
-
-
-
-
EVENTOUT
PH1
-
-
-
-
-
-
-
EVENTOUT
PH2
-
-
-
-
-
-
-
EVENTOUT
PH3
-
-
-
-
-
-
-
EVENTOUT
PH4
-
-
PSSI_D14
-
-
-
-
EVENTOUT
PH5
-
-
DCMI_PIXCLK/PSSI_
PDCK
-
-
-
-
EVENTOUT
PH6
-
-
DCMI_D8/PSSI_D8
-
-
-
-
EVENTOUT
PH7
-
-
DCMI_D9/PSSI_D9
-
-
-
-
EVENTOUT
PH8
-
-
DCMI_HSYNC/PSSI_
DE
-
-
-
-
EVENTOUT
PH9
-
-
DCMI_D0/PSSI_D0
-
-
-
-
EVENTOUT
PH10
-
-
DCMI_D1/PSSI_D1
-
-
-
-
EVENTOUT
PH11
-
-
DCMI_D2/PSSI_D2
-
-
-
-
EVENTOUT
PH12
-
-
DCMI_D3/PSSI_D3
-
-
-
-
EVENTOUT
PH13
-
CAN1_TX
-
-
-
-
-
EVENTOUT
PH14
-
-
DCMI_D4/PSSI_D4
-
-
-
-
EVENTOUT
PH15
-
-
DCMI_D11/PSSI_D11
-
-
-
-
EVENTOUT
Port
DS12903 Rev 3
Port
H
AF10
AF11
AF12
SDMMC1/2/COM
CAN2/OTG_FS/DCMI/
SDMMC2/LCD/D
P1/2/TIM1/8/FM
OCTOSPIM_P1/2/QU
SI/LCD
C/SWPMI1
ADSPI
STM32L4P5xx
Table 17. Alternate function AF8 to AF15(1) (continued)
131/311
132/311
Table 17. Alternate function AF8 to AF15(1) (continued)
AF8
AF9
AF13
AF14
AF15
UART4/5/LPUA
RT1/CAN2/SDM
MC1/2
CAN1/TSC/LCD
SAI1/2/TIM8
TIM2/8/15/16/1
7/LPTIM2
EVENOUT
PI0
-
-
DCMI_D13/PSSI_D13
-
-
-
-
EVENTOUT
PI1
-
-
DCMI_D8/PSSI_D8
-
-
-
-
EVENTOUT
PI2
-
-
DCMI_D9/PSSI_D9
-
-
-
-
EVENTOUT
PI3
-
-
DCMI_D10/PSSI_D10
-
-
-
-
EVENTOUT
PI4
-
-
DCMI_D5/PSSI_D5
-
-
-
-
EVENTOUT
PI5
-
-
DCMI_VSYNC/PSSI_
RDY
-
-
-
-
EVENTOUT
PI6
-
-
DCMI_D6/PSSI_D6
-
-
-
-
EVENTOUT
PI7
-
-
DCMI_D7/PSSI_D7
-
-
-
-
EVENTOUT
PI8
-
-
DCMI_D12/PSSI_D12
-
-
-
-
EVENTOUT
PI9
-
CAN1_RX
-
-
-
-
-
EVENTOUT
PI10
-
-
PSSI_D14
-
-
-
-
EVENTOUT
PI11
-
-
PSSI_D15
-
-
-
-
EVENTOUT
Port
Port
I
AF10
AF11
AF12
SDMMC1/2/COM
CAN2/OTG_FS/DCMI/
SDMMC2/LCD/D
P1/2/TIM1/8/FM
OCTOSPIM_P1/2/QU
SI/LCD
C/SWPMI1
ADSPI
DS12903 Rev 3
1. Refer to previous table for AF0 to AF7.
STM32L4P5xx
STM32L4P5xx
5
Memory mapping
Memory mapping
For memory map and peripheral register boundary addresses refer to the corresponding
section of reference manual RM0432.
DS12903 Rev 3
133/311
133
Electrical characteristics
STM32L4P5xx
6
Electrical characteristics
6.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
6.1.1
Minimum and maximum values
Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3σ).
6.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3 V. They
are given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ±2σ).
6.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 24.
6.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 25.
Figure 24. Pin loading conditions
Figure 25. Pin input voltage
MCU pin
MCU pin
C = 50 pF
VIN
MS19210V1
134/311
DS12903 Rev 3
MS19211V1
STM32L4P5xx
6.1.6
Electrical characteristics
Power supply scheme
Figure 26. STM32L4P5xx power supply scheme
VBAT
Backup circuitry
(LSE, RTC,
Backup registers)
1.55 – 3.6 V
Power switch
2 x VDD12
1.00 – 1.32 V
VDD
VCORE
n x VDD
Regulator
n x 100 nF
GPIOs
IN
+1 x 4.7 μF
Level shifter
OUT
IO
logic
Level shifter
VDDIO1
IO
logic
Kernel logic
(CPU, Digital
& Memories)
n x VSS
VDDIO2
m x VDDIO2
VDDIO2
OUT
m x100 nF
+4.7 μF
GPIOs
IN
m x VSS
VDDA
VDDA
VREF
10 nF
+1 μF
VREF+
VREF-
100 nF +1 μF
ADCs/
DACs/
OPAMPs/
COMPs/
VREFBUF
VSSA
MSv45701V2
Caution:
Each power supply pair (VDD/VSS, VDDA/VSSA etc.) must be decoupled with filtering ceramic
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure the good functionality of
the device.
DS12903 Rev 3
135/311
277
Electrical characteristics
6.1.7
STM32L4P5xx
Current consumption measurement
The IDD_ALL parameters given in Table 25 to Table 39 represent the total MCU consumption
including the current supplying VDD, VDDIO2, VDDA, VDDUSB and VBAT.
Figure 27. Current consumption measurement
IDD_USB
IDD_USB
VDDUSB
VDDUSB
IDD_VBAT
IDD_VBAT
VBAT
VBAT
IDD
SMPS
IDD
IDDA
VDD12
VDD
VDD
VDDIO2
VDDIO2
IDDA
VDDA
VDDA
MSv45730V1
6.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 18: Voltage characteristics,
Table 19: Current characteristics and Table 20: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability. Device mission profile (application conditions)
is compliant with JEDEC JESD47 qualification standard, extended mission profiles are
available on demand.
Table 18. Voltage characteristics(1)
Symbol
Ratings
Min
Max
Unit
VDDX - VSS
External main supply voltage (including VDD,
VDDA, VDDIO2, VDDUSB, VBAT, VREF+)
-0.3
4.0
V
VDD12 - VSS
External SMPS supply voltage
Range 1
-0.3
Range 2
-0.3
1.4
V
VIN(2)
136/311
Input voltage on FT_xxx pins
VSS-0.3
min (VDD, VDDA,
VDDIO2, VDDUSB)
+ 4.0(3)(4)
Input voltage on TT_xx pins
VSS-0.3
4.0
Input voltage on any other pins
VSS-0.3
4.0
DS12903 Rev 3
V
STM32L4P5xx
Electrical characteristics
Table 18. Voltage characteristics(1) (continued)
Symbol
Ratings
Min
Max
|∆VDDx|
Variations between different VDDX power pins
of the same domain
-
50
Variations between all the different ground
pins(5)
-
50
Allowed voltage difference for VREF+ > VDDA
-
0.4
|VSSx-VSS|
VREF+ - VDDA
Unit
mV
V
1. All main power (VDD, VDDA, VDDIO2, VDDUSB, VBAT) and ground (VSS, VSSA) pins must always be
connected to the external power supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 19: Current characteristics for the maximum
allowed injected current values.
3. This formula has to be applied only on the power supplies related to the IO structure described in the pin
definition table.
4. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.
5. Include VREF- pin.
Table 19. Current characteristics
Symbol
Ratings
Max
∑IVDD
Total current into sum of all VDD power lines (source)(1) (2)
200
∑IVSS
Total current out of sum of all VSS ground lines (sink)(1) (2)
200
IVDD(PIN)
Maximum current into each VDD power pin (source)(1)
100
IVSS(PIN)
(sink)(1)
100
IIO(PIN)
∑IIO(PIN)
IINJ(PIN)(4)
∑|IINJ(PIN)|
Maximum current out of each VSS ground pin
Output current sunk by any I/O and control pin except FT_f
20
Output current sunk by any FT_f pin
20
Output current sourced by any I/O and control pin
20
Total output current sunk by sum of all I/Os and control pins(3)
Unit
mA
100
(3)
Total output current sourced by sum of all I/Os and control pins
100
Injected current on FT_xxx, TT_xx, RST and B pins, except PA4, PA5 -5/+0(5)
Injected current on PA4, PA5
-5/0
(6)
Total injected current (sum of all I/Os and control pins)
25
1. All main power (VDD, VDDA, VDDIO2, VDDUSB, VBAT) and ground (VSS, VSSA) pins must always be
connected to the external power supplies, in the permitted range.
2. Valid also for VDD12 on SMPS package.
3. This current consumption must be correctly distributed over all I/Os and control pins. The total output
current must not be sunk/sourced between two consecutive power supply pins referring to high pin count
QFP packages.
4. Positive injection (when VIN > VDDIOx) is not possible on these I/Os and does not occur for input voltages
lower than the specified maximum value.
5. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 18:
Voltage characteristics for the minimum allowed input voltage values.
6. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of
the negative injected currents (instantaneous values).
DS12903 Rev 3
137/311
277
Electrical characteristics
STM32L4P5xx
Table 20. Thermal characteristics
Symbol
TSTG
TJ
Ratings
Storage temperature range
Maximum junction temperature
6.3
Operating conditions
6.3.1
General operating conditions
Value
Unit
–65 to +150
°C
150
°C
Table 21. General operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
fHCLK
Internal AHB clock frequency
-
0
120
fPCLK1
Internal APB1 clock frequency
-
0
120
fPCLK2
Internal APB2 clock frequency
-
0
120
Standard operating voltage
-
1.71(1)
3.6
V
Up to 120 MHz
1.14
Up to 80 MHz
1.08
1.32
V
Up to 26 MHz
1.00(2)
At least one I/O in PG[15:2] used
1.08
3.6
0
3.6
VDD
VDD12
VDDIO2
VDDA
Standard operating voltage
PG[15:2] I/Os supply voltage
Analog supply voltage
PG[15:2] not used
ADC or COMP used
1.62
DAC or OPAMP used
1.8
VREFBUF used
2.4
ADC, DAC, OPAMP, COMP,
VREFBUF not used
VBAT
VDDUSB
Backup operating voltage
USB supply voltage
USB used
USB not used
TT_xx I/O
VIN
138/311
I/O input voltage
All I/O except TT_xx
DS12903 Rev 3
3.6
MHz
V
0
1.55
3.6
3.0
3.6
0
3.6
-0.3
VDDIOx+0.3
-0.3
MIN(MIN(VDD, VDDA,
VDDIO2,
VDDUSB)+3.6 V,
5.5 V)(3)(4)
V
V
STM32L4P5xx
Electrical characteristics
Table 21. General operating conditions (continued)
Symbol
Parameter
Conditions
LQFP144
LQFP100
UFBGA169
PD
Power dissipation at
TA = 85 °C for suffix 6(5)
UFBGA132
WLCSP100
LQFP48
LQFP64
UFQFPN48
LQFP144
LQFP100
UFBGA169
PD
Power dissipation at
TA = 125 °C for suffix 3(5)
UFBGA132
WLCSP100
LQFP48
LGFP64
UFQFPN48
Ambient temperature for the
suffix 6 version
TA
Ambient temperature for the
suffix 3 version
TJ
Junction temperature range
Min
Max
Unit
See Section 7.9: Thermal
characteristics for application
appropriate thermal
resistance and package.
Power dissipation is then
calculated according ambient
temperature (TA) and
maximum junction
temperature (TJ) and
selected thermal resistance.
mW
See Section 7.9: Thermal
characteristics for application
appropriate thermal
resistance and package.
Power dissipation is then
calculated according ambient
temperature (TA) and
maximum junction
temperature (TJ) and
selected thermal resistance.
mW
Maximum power dissipation
–40
85
Low-power dissipation(6)
–40
105
Maximum power dissipation
–40
125
Low-power dissipation(6)
–40
130
Suffix 6 version
–40
105
Suffix 3 version
–40
130
°C
°C
1. When RESET is released functionality is guaranteed down to VBOR0 Min.
2. For Flash erase and program operation, VDD12 min must be 1.08 V.
3. This formula has to be applied only on the power supplies related to the IO structure described by the pin definition table.
Maximum I/O input voltage is the smallest value between MIN(VDD, VDDA, VDDIO2, VDDUSB)+3.6 V and 5.5V.
4. For operation with voltage higher than Min (VDD, VDDA, VDDIO2, VDDUSB) +0.3 V, the internal Pull-up and Pull-Down
resistors must be disabled.
5. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Section 7.9: Thermal characteristics).
6. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 7.9:
Thermal characteristics).
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Electrical characteristics
6.3.2
STM32L4P5xx
Operating conditions at power-up / power-down
The parameters given in Table 22 are derived from tests performed under the ambient
temperature condition summarized in Table 21.
Table 22. Operating conditions at power-up / power-down(1)
Symbol
Parameter
Conditions
Min
Max
-
0
∞
ENULP=0
10
∞
ENULP=1
100
∞
0
∞
10
∞
0
∞
10
∞
0
∞
10
∞
VDD rise time rate
tVDD
VDD fall time rate
VDDA rise time rate
tVDDA
-
VDDA fall time rate
VDDUSB rise time rate
tVDDUSB
-
VDDUSB fall time rate
VDDIO2 rise time rate
tVDDIO2
-
VDDIO2 fall time rate
Unit
µs/V
ms/V
µs/V
µs/V
µs/V
1. At power-up, the VDD12 voltage should not be forced externally.
6.3.3
Embedded reset and power control block characteristics
The parameters given in Table 23 are derived from tests performed under the ambient
temperature conditions summarized in Table 21: General operating conditions.
Table 23. Embedded reset and power control block characteristics
Symbol
tRSTTEMPO(2)
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Parameter
Reset temporization after
BOR0 is detected
VBOR0(2)
Brown-out reset threshold 0
VBOR1
Brown-out reset threshold 1
VBOR2
Brown-out reset threshold 2
VBOR3
Brown-out reset threshold 3
VBOR4
Brown-out reset threshold 4
VPVD0
Programmable voltage
detector threshold 0
Conditions(1)
Min
Typ
Max
Unit
-
250
400
μs
Rising edge
1.62
1.66
1.7
Falling edge
1.6
1.64
1.69
Rising edge
2.06
2.1
2.14
Falling edge
1.96
2
2.04
Rising edge
2.26
2.31
2.35
Falling edge
2.16
2.20
2.24
Rising edge
2.56
2.61
2.66
Falling edge
2.47
2.52
2.57
Rising edge
2.85
2.90
2.95
Falling edge
2.76
2.81
2.86
Rising edge
2.1
2.15
2.19
Falling edge
2
2.05
2.1
VDD rising
DS12903 Rev 3
V
V
V
V
V
V
STM32L4P5xx
Electrical characteristics
Table 23. Embedded reset and power control block characteristics (continued)
Symbol
Parameter
VPVD1
PVD threshold 1
VPVD2
PVD threshold 2
VPVD3
PVD threshold 3
VPVD4
PVD threshold 4
VPVD5
PVD threshold 5
VPVD6
PVD threshold 6
Vhyst_BORH0
Hysteresis voltage of
BORH0
Conditions(1)
Min
Typ
Max
Rising edge
2.26
2.31
2.36
Falling edge
2.15
2.20
2.25
Rising edge
2.41
2.46
2.51
Falling edge
2.31
2.36
2.41
Rising edge
2.56
2.61
2.66
Falling edge
2.47
2.52
2.57
Rising edge
2.69
2.74
2.79
Falling edge
2.59
2.64
2.69
Rising edge
2.85
2.91
2.96
Falling edge
2.75
2.81
2.86
Rising edge
2.92
2.98
3.04
Falling edge
2.84
2.90
2.96
Hysteresis in
continuous mode
-
20
-
Hysteresis in
other mode
-
30
-
Unit
V
V
V
V
V
V
mV
Hysteresis voltage of BORH
(except BORH0) and PVD
-
-
100
-
mV
BOR(3) (except BOR0) and
PVD consumption from VDD
with ENULP=0
-
-
1.1
1.6
µA
BOR(3) (except BOR0) and
PVD consumption from VDD
with ENULP=1
-
-
55
1000
nA
VPVM1
VDDUSB peripheral voltage
monitoring
-
1.18
1.22
1.26
V
VPVM3
VDDA peripheral voltage
monitoring
Rising edge
1.61
1.65
1.69
Falling edge
1.6
1.64
1.68
VPVM4
VDDA peripheral voltage
monitoring
Rising edge
1.78
1.82
1.86
Falling edge
1.77
1.81
1.85
Vhyst_BOR_PVD
IDD
(BOR_PVD)(2)
V
V
Vhyst_PVM3
PVM3 hysteresis
-
-
10
-
mV
Vhyst_PVM4
PVM4 hysteresis
-
-
10
-
mV
PVM1 and PVM2
IDD
(PVM1/PVM2)(2) consumption from VDD
-
-
0.2
-
µA
IDD
PVM3 and PVM4
(PVM3/PVM4)(2) consumption from VDD
-
-
2
-
µA
1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power
sleep modes.
2. Guaranteed by design.
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Electrical characteristics
STM32L4P5xx
3. BOR0 is enabled in all modes (except shutdown) and its consumption is therefore included in the supply
current characteristics tables.
6.3.4
Embedded voltage reference
The parameters given in Table 24 are derived from tests performed under the ambient
temperature and supply voltage conditions summarized in Table 21: General operating
conditions.
Table 24. Embedded internal voltage reference
Symbol
Parameter
VREFINT
Internal reference
voltage
Conditions
Min
Typ
–40 °C < TJ < +130 °C 1.182 1.212
Unit
1.232
V
ADC sampling time
when reading the
internal reference
voltage
-
4(2)
-
-
µs
Start time of reference
voltage buffer when
ADC is enable
-
-
8
12(2)
µs
VREFINT buffer
consumption from VDD
IDD(VREFINTBUF) when converted by
ADC
-
-
12.5
20(2)
µA
tS_vrefint
(1)
tstart_vrefint
∆VREFINT
Internal reference
voltage spread over
the temperature range
VDD = 3 V
-
5
7.5(2)
mV
TCoeff
Average temperature
coefficient
–40°C < TJ < +130°C
-
30
50(2)
ppm/°C
ACoeff
Long term stability
1000 hours, T = 25°C
-
300
1000(2)
ppm
Average voltage
coefficient
3.0 V < VDD < 3.6 V
-
250
1200(2)
ppm/V
24
25
26
49
50
51
74
75
76
VDDCoeff
VREFINT_DIV1
1/4 reference voltage
VREFINT_DIV2
1/2 reference voltage
VREFINT_DIV3
3/4 reference voltage
-
1. The shortest sampling time can be determined in the application by multiple iterations.
2. Guaranteed by design.
142/311
Max
DS12903 Rev 3
%
VREFINT
STM32L4P5xx
Electrical characteristics
Figure 28. VREFINT versus temperature
V
1.235
1.23
1.225
1.22
1.215
1.21
1.205
1.2
1.195
1.19
1.185
-40
-20
0
20
40
Mean
60
Min
80
100
120
°C
Max
MSv40169V2
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277
Electrical characteristics
6.3.5
STM32L4P5xx
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code
The current consumption is measured as described in .
Typical and maximum current consumption
The MCU is placed under the following conditions:
•
All I/O pins are in analog input mode
•
All peripherals are disabled except when explicitly mentioned
•
The Flash memory access time is adjusted with the minimum wait states number,
depending on the fHCLK frequency (refer to the table “Number of wait states according
to CPU clock (HCLK) frequency” available in the RM0432 reference manual).
•
When the peripherals are enabled fPCLK = fHCLK
•
The voltage scaling Range 1 is adjusted to fHCLK frequency as follows:
–
Voltage Range 1 Boost mode for 80 MHz < fHCLK