STP04CM05B1R

STP04CM05 4-bit constant current power-LED sink driver Datasheet - production data Description The STP04CM05 is a high-power LED driver and 4-bit shift register designed for Power-LED applications. The STP04CM05 contains a 4-bit serial IN, parallel OUT shift register that feeds a 4-bit Dtype storage register. In the output stage, four regulated current sources were designed to provide 80-400 mA constant current to drive high power LEDs. Features             4 constant current output channels Adjustable output current through one external resistor Can be driven by a 3.3 V microcontroller Serial data IN/parallel data OUT Output current: 80-400 mA 20 V of output driving capability 30 MHz clock frequency UVLO (under voltage lockout) and POR (power ON reset) TSD, thermal shutdown, output off when junction temperature exceeds limit Operating free-air temperature range -40° to 125 °C ESD protection 2.5 kV HBM, 200 V MM Available in high thermal TSSOP exposed pad The STP04CM05 guarantees 20 V output driving capability, allowing users to connect more LEDs in series. The high clock frequency, 30 MHz, also satisfies the system requirements which include high volume data transmission. The STP04CM05 is well suited for very high brightness displays and special lighting applications. The STP04CM05 is offered in TSSOP16 exposed pad packages. Table 1: Device summary Order code Package Packing STP04CM05XTTR TSSOP16 exposed pad (tape and reel) 2500 parts per reel January 2016 DocID14191 Rev 6 This is information on a product in full production. 1/22 www.st.com Contents STP04CM05 Contents 1 Internal schematic ........................................................................... 3 2 Pin settings ...................................................................................... 4 3 2.1 Pin connection................................................................................... 4 2.2 Pin description................................................................................... 4 Maximum rating ............................................................................... 5 3.1 Thermal data ..................................................................................... 5 3.2 Recommended operating conditions ................................................. 6 4 Electrical characteristics ................................................................ 7 5 Equivalent circuit and outputs ....................................................... 9 6 Timing diagrams ............................................................................ 11 7 Test circuit ..................................................................................... 14 8 9 Typical characteristics .................................................................. 15 Package information ..................................................................... 17 10 2/22 9.1 TSSOP16 exposed pad package information ................................. 18 9.2 TSSOP16 exposed pad packing information .................................. 20 Revision history ............................................................................ 21 DocID14191 Rev 6 STP04CM05 1 Internal schematic Internal schematic Figure 1: Block diagram DocID14191 Rev 6 3/22 Pin settings STP04CM05 2 Pin settings 2.1 Pin connection Figure 2: Pin connection The exposed pad should be attached to a metal land electrically isolated or connected to ground. 2.2 Pin description Table 2: Pin description 4/22 TSSOP16 exposed pad pin N° Symbol Name and function 1, 2 GND Ground terminal 3 SDI Serial data input terminal 4 CLK Clock input terminal 5 LE Latch input terminal 6 OUT 0 Output terminal 7 OUT 1 Output terminal 8, 9, 12 N.C. Not connected 10 OUT 2 Output terminal 11 OUT 3 Output terminal 13 OE Output enable input terminal (active low) 14 SDO Serial data out terminal 15 R-EXT 16 VDD Constant current programming 5 V supply voltage terminal DocID14191 Rev 6 STP04CM05 3 Maximum rating Maximum rating Stressing the device above the rating listed in the “absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 3: Absolute maximum ratings Symbol 3.1 Parameter Value Unit VDD Supply voltage 0 to 7 V VO Output voltage -0.5 to 20 V IO Output current 500 mA VI Input voltage -0.4 to VDD+0.4 V 2000 mA 50 MHz IGND GND terminal current fCLK Clock frequency TOPR Operating temperature range -40 to +125 °C TSTG Storage temperature range -55 to +150 °C Thermal data Table 4: Thermal data Symbol RthJA Parameter Thermal resistance junction-ambient TSSOP16 exposed pad 37.5 (1) Unit °C/W Notes: (1) Using the PCB multi-layer JEDEC Standard test boards. DocID14191 Rev 6 5/22 Maximum rating 3.2 STP04CM05 Recommended operating conditions Table 5: Recommended operating conditions Symbol Parameter Test condition Min. Typ. Max. Unit 3.3 5.0 5.5 V 19 V 400 mA VDD Supply voltage VO Output voltage IO Output current OUTn VDD = 5 V IOH Output current Serial-OUT +1 mA IOL Output current Serial-OUT -1 mA VIH Input voltage 0.7 VDD VDD+0.3 V VIL Input voltage -0.3 0.3 VDD V twEN OE pulse width twLAT LE pulse width twCLK CLK pulse width tSETUP(D) Setup time for DATA tHOLD(D) Hold time for DATA tSETUP(L) Setup time for LATCH tHOLD(E) Hold time for ENABLE 80 VDD = 5 V, IO = 350 mA 80 50 VDD = 3.3 V, IO = 350 mA 250 150 8 4 ns 8.5 7.5 ns 8.5 7.5 ns 8.5 7.5 ns 8.5 7.0 ns 8.5 7.0 ns VDD = 3.0 to 3.6 V Cascade operation fCLK Clock frequency TOPR Operating temperature range (1) -40 ns 30 MHz +125 °C Notes: (1) If multiple devices are cascaded, it may not be possible achieve the maximum data transfer. Please consider the timing conditions carefully. 6/22 DocID14191 Rev 6 STP04CM05 4 Electrical characteristics Electrical characteristics TA = 25 °C, unless otherwise specified. Table 6: Current accuracy Current accuracy Output voltage Output current ≥ 1.4 V Between bits Between ICs Typ. ± 1% ± 6% 80 to 400 mA Table 7: Electrical characteristics (VDD = 3.3 to 5 V) Symbol Parameter Test conditions Min. Typ. Max. Unit VIH Input voltage high level 0.7 VDD VDD V VIL Input voltage low level GND 0.3 VDD V IOH Output leakage current VOH = 19 V 10 μA VOL Output voltage (serial-OUT) IOL = 1 mA 0.4 V VOH Output voltage (serial-OUT) IOH = -1 mA VDD0.4 V VO = 0.3 VREXT = 980 Ω 75.2 80 84.8 mA VO = 1.2 VREXT = 190 kΩ 376 400 424 mA VO = 0.3 VREXT = 980 Ω IO = 80 mA 1 1.5 % VO = 1.2 VREXT = 190 Ω IO = 400 mA 1 1.5 % IOL1 Output current IOL2 ΔIOL1 ΔIOL2 RSIN(up) RSIN(down) Output current error between bit (all output ON) Pull-up resistor 150 300 600 kΩ Pull-down resistor 100 200 400 kΩ REXT = OPEN OUT 0 to 3 = OFF 1 1.5 REXT = 980 Ω OUT 0 to 3 = OFF 3.8 6 REXT = 190 Ω OUT 0 to 3 = OFF 14 18.5 REXT = 980 Ω OUT 0 to 3 = ON 4.0 6.0 REXT = 190 Ω OUT 0 to 3 = ON 14.5 19 IDD(OFF1) IDD(OFF2) Supply current (OFF) IDD(OFF3) IDD(ON1) IDD(ON2) V Supply current (ON) DocID14191 Rev 6 mA 7/22 Electrical characteristics STP04CM05 Table 8: Switching characteristics (VDD = 3.3 to 5 V) Symbol Parameter Test conditions Min. Typ. Max. VDD = 3.3 V - 290 377 VDD = 5 V - 200 260 Propagation delay time, VDD = 3.3 V - 200 260 LE- OUTn , / OE = L VDD = 5 V - 140 180 ns Propagation delay time, VDD = 3.3 V - 240 310 ns / OE - OUTn , LE = H VDD = 5 V - 170 220 Propagation delay time, CLK-SDO VDD = 3.3 V - 25 35 VDD = 5 V - 15 20 VDD = 3.3 V - 49 64 VDD = 5 V - 36 47 VDD = 3.3 V - 39 51 VDD = 5 V - 26 34 VDD = 3.3 V - 48 62 VDD = 5 V - 32 42 Propagation delay time, CLK-SDO VDD = 3.3 V - 30 39 VDD = 5 V - 19 25 Output rise time 10~90% of voltage waveform VDD = 3.3 V - 880 1150 VDD = 5 V - 616 800 Output fall time 90~10% of voltage waveform VDD = 3.3 V - 18 24 VDD = 5 V - 14 18 ns - 5000 ns - 5000 ns Propagation delay time, tPLH1 CLK- OUTn LE = H, / OE = L tPLH2 tPLH3 tPLH Propagation delay time, tPHL1 CLK- OUTn LE = H, / OE = L Propagation delay time, tPHL2 RL = 5.0 Ω CL = 10 pF IO = 350 mA REXT = 224 Ω VL = 3.0 V LE - OUTn , / OE = L Propagation delay time, tPHL3 tPHL tON tOFF / OE - OUTn (1) tr CLK rise time tf CLK fall time (1) 8/22 ns ns ns ns ns LE = H VO = 5.0 V REXT = 224 Ω Notes: (1) Unit In order to achieve high cascade data transfer, please consider tr/tf timings carefully. DocID14191 Rev 6 ns ns STP04CM05 5 Equivalent circuit and outputs Equivalent circuit and outputs Figure 3: OE terminal Figure 4: LE terminal DocID14191 Rev 6 9/22 Equivalent circuit and outputs STP04CM05 Figure 5: CLK, SDI terminal Figure 6: SDO terminal 10/22 DocID14191 Rev 6 STP04CM05 6 Timing diagrams Timing diagrams Figure 7: Timing diagram 1 Latch and output enable are level sensitive and are not synchronized with risingor-falling edge of CLK signal. 2 When LE terminal is low level, the latch circuit hold previous set of data. 3 When LE terminal is high level, the latch circuit refresh new set of data from SDI chain. 4 When OE terminal is at low level, the output terminal - Out 0 to Out 03 respond to data in the latch circuits, either ‘1’ for ON or ‘0’ for OFF. 5 When OE terminal is at high level, all output terminals will be switched OFF. DocID14191 Rev 6 11/22 Timing diagrams STP04CM05 Figure 8: Clock, serial-in, serial-out 12/22 DocID14191 Rev 6 STP04CM05 Timing diagrams Figure 9: Clock, serial-in, latch, enable, outputs Figure 10: Outputs DocID14191 Rev 6 13/22 Test circuit 7 STP04CM05 Test circuit Figure 11: DC characteristic Figure 12: AC characteristic 14/22 DocID14191 Rev 6 STP04CM05 8 Typical characteristics Typical characteristics Figure 13: Output current-REXT resistor Figure 14: Output current vs dropout voltage Figure 15: Output current vs ± ΔIOL(%) Figure 16: Four power-LED typ. application circuit VL will be determined by the VF of the LEDs. Condition: TA = 25 °C, Vdd = 5 V,VL = 3 V, Rext = 227 Ω. DocID14191 Rev 6 15/22 Typical characteristics STP04CM05 Figure 17: tON 16/22 Figure 18: tOFF DocID14191 Rev 6 STP04CM05 9 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DocID14191 Rev 6 17/22 Package information 9.1 STP04CM05 TSSOP16 exposed pad package information Figure 19: TSSOP16 exposed pad package outline 18/22 DocID14191 Rev 6 STP04CM05 Package information Table 9: TSSOP16 exposed pad package mechanical data mm Dim. Min. Typ. A Max. 1.10 A1 0.05 0.15 A2 0.85 b 0.19 0.30 c 0.09 0.20 0.90 D 5.00 D1 ACCORDING TO PAD SIZE E E1 6.40 4.30 E2 4.40 4.50 ACCORDING TO PAD SIZE e L 0.95 0.65 0.50 L1 0.60 0.70 1.00 k 8 aaa 0.076 DocID14191 Rev 6 19/22 Package information 9.2 STP04CM05 TSSOP16 exposed pad packing information Figure 20: TSSOP16 exposed pad tape and reel outline Table 10: TSSOP16 exposed pad packing mechanical data mm inch Dim. Min. A Max. Min. 330 12.8 D 20.2 0.795 N 60 2.362 13.2 Typ. Max. 12.992 C T 20/22 Typ. 0.504 22.4 0.519 0.882 Ao 6.7 6.9 0.264 0.272 Bo 5.3 5.5 0.209 0.217 Ko 1.6 1.8 0.063 0.071 Po 3.9 4.1 0.153 0.161 P 7.9 8.1 0.311 0.319 DocID14191 Rev 6 STP04CM05 10 Revision history Revision history Table 11: Document revision history Date Revision 26-Nov-2007 1 Initial release 16-Jan-2008 2 Added: Figure 15 on page 15 and Figure 19 on page 17, Updated: Table 8 on page 8. 12-Mar-2008 3 Updated: Figure 8 on page 12. 23-Jun-2008 4 Updated: Table 1 on page 1, Figure 21 on page 20. 07-Jun-2010 5 Updated: Note: on page 4, Table 10 on page 19. 6 Removed SO-14 package. Updated Figure 5: "CLK, SDI terminal". Minor text changes. 07-Jan-2016 Changes DocID14191 Rev 6 21/22 STP04CM05 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved 22/22 DocID14191 Rev 6