STP16CP05TTR

STP16CP05 Low voltage 16-bit constant current LED sink driver Datasheet - production data Description The STP16CP05 is a monolithic, low voltage, low current power 16-bit shift register designed for LED panel displays. The STP16CP05 contains a 16-bit serial-in, parallel-out shift register that feeds a 16-bit, D-type storage register. In the output stage, sixteen regulated current sources provide from 5 mA to 100 mA constant current to drive the LEDs. The output current setup time is 40 ns (typ.), thus improving the system performance. The LEDs' brightness can be controlled by using an external resistor to adjust the STP16CP05 output current. Features         Low voltage power supply down to 3 V 16 constant current output channels Adjustable output current through external resistor Serial data IN/parallel data OUT Can be driven by a 3.3 V microcontroller Output current: 5 to 100 mA Max clock frequency 30 MHz ESD protection: 2 kV HBM, 200 V MM The STP16CP05 guarantees a 20 V output driving capability, allowing users to connect more LEDs in series. The high clock frequency, 30 MHz, makes the device suitable for high data rate transmission. The 3.3 V voltage supply is useful in applications that interface with a 3.3 V micro controller. Table 1: Device summary Order code Package Packing STP16CP05MTR SO-24 1000 parts per reel STP16CP05TTR TSSOP24 2500 parts per reel STP16CP05XTTR TSSOP24 exposed pad 2500 parts per reel STP16CP05PTR QSOP-24 2500 parts per reel March 2017 DocID12568 Rev 13 This is information on a product in full production. 1/30 www.st.com Contents STP16CP05 Contents 1 Summary description ...................................................................... 3 1.1 2 Pin connection and description ......................................................... 3 Electrical ratings ............................................................................. 4 2.1 Absolute maximum ratings ................................................................ 4 2.2 Thermal data ..................................................................................... 4 2.3 Recommended operating conditions ................................................. 5 3 Electrical characteristics ................................................................ 6 4 Equivalent circuit and outputs ....................................................... 8 5 Timing diagrams ............................................................................ 11 6 Typical characteristics .................................................................. 14 7 Test circuit ..................................................................................... 17 8 Package information ..................................................................... 19 8.1 QSOP-24 package information ....................................................... 20 8.2 SO-24 package information ............................................................ 22 8.3 TSSOP24 package information ....................................................... 23 8.4 TSSOP24 exposed pad package information ................................. 25 8.5 TSSOP24, TSSOP24 exposed pad and ............................................ SO-24 packing information .............................................................. 27 9 2/30 Revision history ............................................................................ 29 DocID12568 Rev 13 STP16CP05 1 Summary description Summary description Table 2: Typical current accuracy Current accuracy Output voltage Between bits Between ICs ± 1.5 % ±5% ≥ 1.3 V 1.1 Output current VDD Temperature 20 to 100 mA 3.3 V to 5 V 25 °C Pin connection and description Figure 1: Pin connection The exposed pad should be electrically connected to a metal land electrically isolated or connected to ground. Table 3: Pin description Pin n° Symbol Name and function 1 GND Ground terminal 2 SDI Serial data input terminal 3 CLK Clock input terminal 4 LE/DM1 Latch input terminal 5-20 OUT 0-15 Output terminal 21 OE/DM2 Input terminal of output enable (active low) 22 SDO 23 R-EXT 24 VDD Serial data out terminal Input terminal for an external resistor for constant current programming Supply voltage terminal DocID12568 Rev 13 3/30 Electrical ratings STP16CP05 2 Electrical ratings 2.1 Absolute maximum ratings Stressing the device above the ratings listed in the “absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other condition above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 4: Absolute maximum ratings Symbol Value Unit VDD Supply voltage 0 to 7 V VO Output voltage -0.5 to 20 V IO Output current 100 mA VI Input voltage IGND GND terminal current fCLK Clock frequency TJ 2.2 Parameter Junction temperature range -0.4 to VDD V 1600 mA 50 MHz -40 to +170 °C Value Unit Thermal data Table 5: Thermal data Symbol Parameter TOPR Operating temperature range -40 to +125 °C TSTG Storage temperature range -55 to +150 °C 42.7 °C/W 55 °C/W TSSOP24 exposed pad 37.5 °C/W QSOP-24 55 °C/W SO-24 TSSOP24 RthJA Thermal resistance junction-ambient (1) (2) Notes: 4/30 (1) According with JEDEC standard 51-7. (2) The exposed pad should be soldered directly to the PCB to realize the thermal benefits. DocID12568 Rev 13 STP16CP05 2.3 Electrical ratings Recommended operating conditions @ TA = 25 °C Table 6: Recommended operating conditions Symbol Parameter Test conditions Min. Typ. Max. Unit 3.0 - 5.5 V - 20 V - 100 mA VDD Supply voltage VO Output voltage IO Output current OUTn IOH Output current SERIAL-OUT - +1 mA IOL Output current SERIAL-OUT - -1 mA VIH Input voltage 0.7 VDD - VDD V VIL Input voltage -0.3 - 0.3 VDD V 3 twLAT LE/DM1 pulse width 6 - ns twCLK CLK pulse width 8 - ns 100 - ns twEN OE/DM2 pulse VDD = 3.0 V to 5.0 V width tSETUP(D) Setup time for DATA 5 - ns tHOLD(D) Hold time for DATA 3 - ns tSETUP(L) Setup time for LATCH 18 - ns fCLK Clock frequency Cascade operation VDD = 5 V (1) - 30 MHz Notes: (1) If the device is connected in cascade, it may not be possible achieve the maximum data transfer. Please consider the timings carefully. DocID12568 Rev 13 5/30 Electrical characteristics 3 STP16CP05 Electrical characteristics VDD = 3.3 V to 5 V, TA = 25 °C, unless otherwise specified. Table 7: Electrical characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit VIH Input voltage high level 0.7 VDD VDD V VIL Input voltage low level GND 0.3 VDD V IOH Output leakage current VOH = 20 V 1 μA VOL Output voltage (serial-OUT) IOL = 1 mA 0.4 V VOH Output voltage (serial-OUT) IOH = -1 mA VO = 0.3 V, Rext = 4.2 kΩ IOL1 IOL2 Output current IOL3 Output current error between bit (all output ON) ΔIOL3 RSIN(up) RSIN(down) IDD(OFF1) IDD(OFF2) IDD(ON1) 6/30 5 5.75 VO = 0.3 V, Rext = 1 kΩ 19 20 21 VO = 1.3 V, Rext = 200 Ω 96 100 104 ±5 ±8 VO = 0.3 V, Rext = 1 kΩ ± 1.5 ±3 VO = 1.3 V, Rext = 200 Ω ± 1.2 ±3 mA % Pull-up resistor 150 300 600 kΩ Pull-down resistor 100 200 400 kΩ Supply current (OFF) Supply current (ON) IDD(ON2) Thermal V 4.25 VO = 0.3 V, Rext = 4.2 kΩ ΔIOL1 ΔIOL2 VDD-0.4V Rext = 1 kΩ, OUT 0 to 15 = OFF 4 Rext = 250 Ω, OUT 0 to 15 = OFF 11.2 Rext = 1 kΩ, OUT 0 to 15 = ON 4.5 Rext = 250 Ω, OUT 0 to 15 = ON 11.7 Thermal protection 170 DocID12568 Rev 13 mA °C STP16CP05 Electrical characteristics VDD = 5 V, TA = 25 °C, unless otherwise specified. Table 8: Switching characteristics Symbol Parameter Test conditions Propagation delay time, tPLH1 =L Propagation delay time, =L Propagation delay time, Propagation delay time, CLK-SDO Propagation delay time, tPHL1 CLK- OUTn , LE/DM1 = H, OE/DM2 =L Propagation delay time, tPHL2 - 45 74 VDD = 5 V - 24 38 VDD = 3.3 V - 48 77 VDD = 5 V - 27 46 VDD = 3.3 V - 75 128 VDD = 5 V - 43 64 VDD = 3.3 V - 19 28 VDD = 5 V - 11 16.5 VDD = 3.3 V - 15 23 VDD = 5 V - 10 14 VDD = 3.3 V - 13 18.5 VDD = 5 V - 9 12 VDD = 3.3 V - 17 24.5 VDD = 5 V - 14 19.5 ns ns VIH = VDD VIL = GND CL = 10 pF IO = 20 mA VL = 3.0 V Rext = 1 KΩ RL = 60 Ω ns ns ns LE/DM1 -OUTn , OE/DM2 =L Propagation delay time, tPHL3 VDD = 3.3 V Unit OE/DM2 - OUTn , LE/DM1 = H tPLH Max. LE/DM1- OUTn , OE/DM2 tPLH3 Typ. CLK- OUTn , LE/DM1 = H, OE/DM2 tPLH2 Min. ns OE/DM2 - OUTn , LE/DM1 = H ns tPHL Propagation delay time, CLK-SDO VDD = 3.3 V - 23 35 VDD = 5 V - 14 21 Output rise time 10~90% of voltage waveform VDD = 3.3 V - 35 68 tON VDD = 5 V - 21 31.5 Output fall time 90~10% of voltage waveform VDD = 3.3 V - 10.5 15 VDD = 5 V - 11 15.5 ns - 5000 ns - 5000 ns tOFF tr tf CLK rise time (1) CLK fall time (1) ns ns Notes: (1) In order to achieve high cascade data transfer, please consider tr/tf timings carefully. DocID12568 Rev 13 7/30 Equivalent circuit and outputs 4 STP16CP05 Equivalent circuit and outputs Figure 2: OE/DM2 terminal Figure 3: LE/DM1 terminal 8/30 DocID12568 Rev 13 STP16CP05 Equivalent circuit and outputs Figure 4: CLK, SDI terminal Figure 5: SDO terminal DocID12568 Rev 13 9/30 Equivalent circuit and outputs STP16CP05 Figure 6: Block diagram 10/30 DocID12568 Rev 13 STP16CP05 5 Timing diagrams Timing diagrams Table 9: Truth table CLOCK LE/DM1 OE/DM2 SERIAL-IN OUT0 ......... OUT7 ......... OUT15 SDO _|¯ H L Dn Dn ..... Dn - 7 ..... Dn -15 Dn - 15 _|¯ L L Dn + 1 No change Dn - 14 _|¯ H L Dn + 2 Dn + 2 ..... Dn - 5 ..... Dn -13 Dn - 13 ¯|_ X L Dn + 3 Dn + 2 ..... Dn - 5 ..... Dn -13 Dn - 13 ¯|_ X H Dn + 3 OFF Dn - 13 OUTn = ON when Dn = H OUTn = OFF when Dn = L. Figure 7: Timing diagram 1 Latch and output enable terminals are level-sensitive and are not synchronized with rising or falling edge of CLK signal. 2 When LE/DM1 terminal is low level, the latch circuit holds previous set of data. 3 When LE/DM1 terminal is high level, the latch circuit refreshes new set of data from SDI chain. 4 When OE/DM2 terminal is at low level, the output terminals Out 0 to Out 15 respond to data in the latch circuits, either ‘1’ for ON or ‘0’ for OFF. 5 When OE/DM2 terminal is at high level, all output terminals are switched OFF. DocID12568 Rev 13 11/30 Timing diagrams STP16CP05 Figure 8: Clock, serial-in, serial-out 12/30 DocID12568 Rev 13 STP16CP05 Timing diagrams Figure 9: Clock, serial-in, latch, enable, outputs Figure 10: Outputs DocID12568 Rev 13 13/30 Typical characteristics 6 STP16CP05 Typical characteristics Figure 11: Output current-R-EXT resistor Table 10: Output current-R-EXT resistor 14/30 R-EXT (Ω) Output current (mA) 7370 3 4270 5 2056 10 1006 20 382 50 251 80 200 100 DocID12568 Rev 13 STP16CP05 Typical characteristics Figure 12: Output current vs ± ΔIOL(%) TA = 25 °C Figure 13: ISET vs drop out voltage (Vdrop) TA = 25 °C Table 11: ISET vs dropout voltage (Vdrop) Iout (mA) Avg (mV) @ 3.3 V Avg (mV) @ 5.0 V 3 20 22 5 37 40 10 79 79 20 160 158 50 422 415 80 700 690 100 880 870 DocID12568 Rev 13 15/30 Typical characteristics STP16CP05 Figure 14: IDD ON/OFF, TA = 25 °C 16/30 DocID12568 Rev 13 STP16CP05 7 Test circuit Test circuit Figure 15: DC characteristic Figure 16: AC characteristic DocID12568 Rev 13 17/30 Test circuit STP16CP05 Figure 17: Typical application schematic VL will be determined by the VF of the LEDs. Test condition: temp. = 25 °C, VDD = 3.0 V, VIN = VDD, CL = 10 pF, freq. = 1 MHz, Ch1 = OE/DM2 , Ch2 = SDI, Ch3 = VOUT, Ch4 = IOUT Figure 18: Turn ON output current setup Figure 19: Turn OFF output current setup 18/30 DocID12568 Rev 13 STP16CP05 8 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DocID12568 Rev 13 19/30 Package information 8.1 STP16CP05 QSOP-24 package information Figure 20: QSOP-24 package outline 20/30 DocID12568 Rev 13 STP16CP05 Package information Table 12: QSOP-24 mechanical data mm Dim. Min. Typ. Max. A 1.54 1.62 1.73 A1 0.10 0.15 0.25 A2 1.47 b 0.20 0.31 c 0.17 0.254 D 8.56 8.66 8.76 E 5.80 6.00 6.20 E1 3.80 3.91 4.01 e 0.635 L 0.40 0.635 0.89 h 0.25 0.33 0.41 < 0° DocID12568 Rev 13 8° 21/30 Package information 8.2 STP16CP05 SO-24 package information Figure 21: SO-24 package outline 22/30 DocID12568 Rev 13 STP16CP05 Package information Table 13: SO-24 mechanical data mm Dim. Min. Typ. A 2.35 2.65 A1 0.10 0.30 B 0.33 0.51 C 0.23 0.32 D 15.20 15.60 E 7.40 e 7.60 1.27 H 10.00 10.65 h 0.25 0.75 L 0.40 1.27 k 0 8 ddd 8.3 Max. 0.10 TSSOP24 package information Figure 22: TSSOP24 package outline DocID12568 Rev 13 23/30 Package information STP16CP05 Table 14: TSSOP24 mechanical data mm Dim. Min. Typ. A A1 1.1 0.05 A2 0.15 0.9 b 0.19 0.30 c 0.09 0.20 D 7.7 7.9 E 4.3 4.5 e 24/30 Max. 0.65 BSC H 6.25 6.5 K 0° 8° L 0.50 0.70 DocID12568 Rev 13 STP16CP05 8.4 Package information TSSOP24 exposed pad package information Figure 23: TSSOP24 exposed pad package outline DocID12568 Rev 13 25/30 Package information STP16CP05 Table 15: TSSOP24 exposed pad mechanical data mm Dim. Min. Max. A 1.20 A1 0.15 A2 0.80 b 0.19 0.30 c 0.09 0.20 1.00 1.05 D 7.70 7.80 7.90 D1 4.80 5.00 5.2 E 6.20 6.40 6.60 E1 4.30 4.40 4.50 E2 3.00 3.20 3.40 e L 0.65 0.45 L1 k 060 075 1.00 0° aaa 26/30 Typ. 8° 0.10 DocID12568 Rev 13 STP16CP05 8.5 Package information TSSOP24, TSSOP24 exposed pad and SO-24 packing information Figure 24: TSSOP24, TSSOP24 exposed pad and SO-24 reel outline Table 16: TSSOP24 and TSSOP24 exposed pad tape and reel mechanical data mm Dim. Min. A Typ. Max. - 330 13.2 C 12.8 - D 20.2 - N 60 - T - 22.4 Ao 6.8 - 7 Bo 8.2 - 8.4 Ko 1.7 - 1.9 Po 3.9 - 4.1 P 11.9 - 12.1 DocID12568 Rev 13 27/30 Package information STP16CP05 Table 17: SO-24 tape and reel mechanical data mm Dim. Min. A Max. - 330 13.2 C 12.8 - D 20.2 - N 60 - T 28/30 Typ. - 30.4 Ao 10.8 - 11.0 Bo 15.7 - 15.9 Ko 2.9 - 3.1 Po 3.9 - 4.1 P 11.9 - 12.1 DocID12568 Rev 13 STP16CP05 9 Revision history Revision history Table 18: Document revision history Date Revision Changes 28-Jul-2006 1 First release 21-Dec-2006 2 Final datasheet 17-May-2007 3 Updated Table 7 on page 6 10-Jul-2007 4 Updated Table 9: Truth table on page 10 12-Mar-2008 5 Updated Table 15: TSSOP24 exposed-pad on page 23, added QSOP-24Table 12 and Figure 2 on page 19 07-May-2008 6 Updated Section 5 on page 10 03-Dec-2008 7 Updated cover page, Table 6 on page 5, Table 7 on page 6, Table 8 on page 7, Figure 2 on page 13, Table 10 on page 13, Figure 2, 2, and Figure 2 on page 15 12-May-2009 8 Updated cover page, Table 6 on page 5, Table 7 on page 6, Table 8 on page 7 22-Oct-2009 9 Updated Note: on page 3 20-Jan-2010 10 Updated Table 5 on page 4 18-Jun-2014 11 Updated Section 8: Package mechanical data and Section 9: Packaging mechanical data. 01-Apr-2016 12 Updated Table 12: "QSOP-24 mechanical data". Minor text changes. 08-Mar-2017 13 Updated Figure 5: "SDO terminal", Figure 8: "Clock, serial-in, serial-out" and Figure 9: "Clock, serial-in, latch, enable, outputs". Minor text changes. DocID12568 Rev 13 29/30 STP16CP05 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2017 STMicroelectronics – All rights reserved 30/30 DocID12568 Rev 13