STP16DPP05
Low voltage 16-bit constant current LED sink driver with output
error detection
Datasheet - production data
feeds a 16- bit D-type storage register. In the
output stage, sixteen regulated current sources
are designed to provide 3 to 40 mA of constant
current to drive the LEDs. The STP16DPP05
features open and short LED detection on the
outputs. The detection circuit checks for 3
different conditions that can occur on the output
line: short to GND, short to VO or open line. The
data detection results are loaded in the shift
registers and shifted out via the serial line output.
The detection functionality is implemented
without increasing the pin count, through a
secondary function of the output enable and latch
pin (DM1 and DM2 respectively). A dedicated
logic sequence allows the device to enter or exit
from detection mode. The STP16DPP05 output
current can be adjusted through an external
resistor to control the light intensity of the LEDs.
LED brightness is adjustable from 0% to 100%
Features
Low voltage power supply down to 3 V
16 constant current output channels
Adjustable output current through external
resistor
Short and open output error detection
Serial data IN/parallel data OUT
3.3 V MCU-driving capability
Output current: 3 to 40 mA
30 MHz clock frequency
Available in high thermal efficiency TSSOP
exposed pad
ESD protection: 2 kV HBM, 200 V MM
via the OE/DM2 pin. The STP16DPP05
guarantees a 20 V output driving capability,
allowing users to connect more LEDs in series.
The high 30 MHz clock frequency makes the
device suitable for high data rate transmission.
The 3.3 V supply is well suited for applications
which interface a 3.3 V MCU. Compared to a
standard TSSOP package, the TSSOP with
exposed pad increases heat dissipation capability
by a factor of 2.5.
Description
The STP16DPP05 is a monolithic, low voltage,
low current power 16-bit shift register designed
for LED panel displays. The device features a
16-bit serial-in, parallel-out shift register that
Table 1: Device summary
Order code
Package
Packing
STP16DPP05MTR
SO-24 (tape and reel)
1000 parts per reel
STP16DPP05TTR
TSSOP24 (tape and reel)
2500 parts per reel
STP16DPP05XTTR
TSSOP24 exposed pad (tape and reel)
2500 parts per reel
STP16DPP05PTR
QSOP-24
2500 parts per reel
April 2017
DocID16518 Rev 4
This is information on a product in full production.
1/34
www.st.com
Contents
STP16DPP05
Contents
1
Summary description ...................................................................... 3
1.1
2
Pin connection and description ......................................................... 3
Electrical ratings ............................................................................. 4
2.1
Absolute maximum ratings ................................................................ 4
2.2
Thermal data ..................................................................................... 4
2.3
Recommended operating conditions ................................................. 5
3
Electrical characteristics ................................................................ 6
4
Equivalent circuit and outputs ....................................................... 8
5
Timing diagrams ............................................................................ 11
6
Typical characteristics .................................................................. 14
7
Error detection mode functionality .............................................. 18
8
7.1
Phase one: entering error detection mode ...................................... 18
7.2
Phase two: error detection .............................................................. 19
7.3
Phase three: resuming normal mode .............................................. 21
7.4
Error detection conditions ............................................................... 21
Package information ..................................................................... 23
8.1
QSOP-24 package information ....................................................... 24
8.2
SO-24 package information ............................................................ 26
8.3
TSSOP24 package information ....................................................... 27
8.4
TSSOP exposed pad package information ..................................... 29
8.5
TSSOP24, TSSOP24 exposed pad and .............................................
SO-24 packing information .............................................................. 31
9
2/34
Revision history ............................................................................ 33
DocID16518 Rev 4
STP16DPP05
1
Summary description
Summary description
Table 2: Typical current accuracy
Current accuracy
Output voltage
Between bits
Between ICs
± 1%
± 2%
≥ 1.3 V
1.1
Output current
VDD
Temperature
5 to 40 mA
3.3 V to 5 V
25 °C
Pin connection and description
Figure 1: Pin connection
The exposed pad should be electrically connected to a metal land electrically
isolated or connected to ground.
Table 3: Pin description
Pin n°
Symbol
1
GND
Ground terminal
2
SDI
Serial data input terminal
3
CLK
Clock input terminal
4
LE/DM1
5-20
OUT 0-15
Output terminal
21
OE/DM2
Input terminal of output enable (active low) - detect mode 1
(see operation principle)
22
SDO
23
R-EXT
24
VDD
Name and function
Latch input terminal - detect mode 1 (see operation principle)
Serial data out terminal
Input terminal for an external resistor for constant current programming
Supply voltage terminal
DocID16518 Rev 4
3/34
Electrical ratings
STP16DPP05
2
Electrical ratings
2.1
Absolute maximum ratings
Stressing the device above the ratings listed in the “absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other condition above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 4: Absolute maximum ratings
Symbol
Parameter
Value
Unit
VDD
Supply voltage
0 to 7
V
VO
Output voltage
-0.5 to 20
V
IO
Output current
50
mA
VI
Input voltage
-0.4 to VDD
V
800
mA
50
MHz
-40 to +170
°C
Value
Unit
Operating free-air temperature range
-40 to +125
°C
Operating thermal junction temperature range
-40 to +150
°C
Storage temperature range
-55 to +150
°C
42.7
°C/W
55
°C/W
TSSOP24
exposed pad
37.5
°C/W
QSOP-24
55
°C/W
IGND
GND terminal current
fCLK
Clock frequency
TJ
Junction temperature range
(1)
Notes:
(1)
2.2
Such absolute value is based on the thermal shutdown protection.
Thermal data
Table 5: Thermal data
Symbol
TA
TJ-OPR
TSTG
Parameter
SO-24
TSSOP24
RthJA
Thermal resistance junction-ambient (1)
(2)
Notes:
4/34
(1)
According with JEDEC standard 51-7.
(2)
The exposed pad should be soldered directly to the PCB to obtain the thermal benefits.
DocID16518 Rev 4
STP16DPP05
2.3
Electrical ratings
Recommended operating conditions
Table 6: Recommended operating conditions
Symbol
Parameter
Test conditions
Min.
3
Typ.
Max.
Unit
5.5
V
20
V
40
mA
VDD
Supply voltage
VO
Output voltage
IO
Output current
OUTn
IOH
Output current
SERIAL-OUT
1
mA
IOL
Output current
SERIAL-OUT
-1
mA
VIH
Input voltage
0.7 VDD
VDD
V
VIL
Input voltage
-0.3
0.3 VDD
V
3
twLAT
LE/DM1 pulse width
20
ns
twCLK
CLK pulse width
10
ns
100
ns
twEN
OE/DM2
pulse width
tSETUP(D)
Setup time for DATA
tHOLD(D)
Hold time for DATA
tSETUP(L)
Setup time for LATCH
fCLK
Clock frequency
VDD = 3.0 V to 5.0 V
ns
Cascade operation
(1)
5
ns
8
ns
30
MHz
Notes:
(1)
If the device is connected in cascade, it may not be possible achieve the maximum data transfer. Please
consider the timings carefully.
DocID16518 Rev 4
5/34
Electrical characteristics
3
STP16DPP05
Electrical characteristics
VDD = 3.3 V to 5 V, TA = 25 °C, unless otherwise specified.
Table 7: Electrical characteristics
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VIH
Input voltage high level
0.7 VDD
VDD
V
VIL
Input voltage low level
GND
0.3 VDD
V
IOH
Output leakage current
VOH = 20 V
1
μA
VOL
Output voltage (serial-OUT)
IOL = 1 mA
0.4
V
VOH
Output voltage (serial-OUT)
IOH = -1 mA
IOL1
IOL2
Output current
IOL3
ΔIOL1
ΔIOL2
Output current error between
bit (all output ON)
ΔIOL3
VDD-0.4V
V
VO = 0.3 V, Rext = 4 kΩ
4.75
5
5.25
VO = 0.3 V, Rext = 1 kΩ
19
20
21
VO = 1.3 V, Rext = 497 Ω
38
40
42
VO = 0.3 V, IO = 5 mA
Rext = 4 kΩ
±1
±5
VO = 0.3 V, IO = 20 mA
Rext = 980 Ω
± 0.5
±3
VO = 1.3 V, IO = 40 mA
Rext = 490 Ω
± 0.5
±3
mA
%
Pull-up resistor
150
300
600
kΩ
Pull-down resistor
100
200
400
kΩ
Rext = 1 kΩ, IOUT = 20 mA,
OUT 0 to 15 = OFF
5.4
7.5
mA
IDD(OFF2)
Rext = 497 Ω, IOUT = 40 mA
OUT 0 to 15 = OFF
8
9.5
IDD(ON1)
Rext = 1 kΩ, IOUT = 20 mA,
OUT 0 to 15 = ON
5.5
7.5
Rext = 497 Ω, IOUT = 40 mA
OUT 0 to 15 = ON
8.1
9.5
RSIN(up)
RSIN(down)
IDD(OFF1)
Supply current (OFF)
Supply current (ON)
IDD(ON2)
Thermal
6/34
Thermal protection
170
DocID16518 Rev 4
°C
STP16DPP05
VDD = 3.3 V to 5 V, TA = 25 °C, unless otherwise specified.
Electrical characteristics
Table 8: Switching characteristics
Symbol
Parameter
Test conditions
Propagation delay time,
tPLH1
=L
Propagation delay time,
=L
Propagation delay time,
Propagation delay time,
CLK-SDO
Propagation delay time,
tPHL1
CLK- OUTn , LE/DM1 = H,
OE/DM2
=L
VIH = VDD
VIL = GND CL = 10 pF
IO = 20 mA VL = 3.0 V
Rext = 1 KΩ RL = 60 Ω
Propagation delay time,
tPHL2
35.5
44.5
VDD = 5 V
18.5
24
VDD = 3.3 V
41.5
50
VDD = 5 V
23
29
VDD = 3.3 V
45
54
VDD = 5 V
25
31
ns
ns
VDD = 3.3 V
15
21
31
VDD = 5 V
11
15
21
VDD = 3.3 V
13.7
18
VDD = 5 V
8.8
12.5
VDD = 3.3 V
17
22
VDD = 5 V
13
17
VDD = 3.3 V
12.7
17
VDD = 5 V
9.5
13
ns
ns
ns
LE/DM1 - OUTn
OE/DM2
=L
Propagation delay time,
tPHL3
VDD = 3.3 V
Unit
OE/DM2 - OUTn ,
LE = H
tPLH
Max.
LE/DM1 - OUTn ,
OE/DM2
tPLH3
Typ.
CLK- OUTn , LE/DM1 = H,
OE/DM2
tPLH2
Min.
OE/DM2 - OUTn ,
LE/DM1 = H
ns
ns
tPHL
Propagation delay time,
CLK-SDO
VDD = 3.3 V
17.5
24
36
VDD = 5 V
12.5
17
25
tON
Output rise time 10~90% of
voltage waveform
VDD = 3.3 V
28
39
VDD = 5 V
17
23
tOFF
Output fall time 90~10% of
voltage waveform
VDD = 3.3 V
4.5
6
VDD = 5 V
3.5
5
ns
5000
ns
5000
ns
tr
tf
CLK rise time
CLK fall time
(1)
(1)
ns
ns
Notes:
(1)
In order to achieve high cascade data transfer, please consider tr/tf timings carefully.
DocID16518 Rev 4
7/34
Equivalent circuit and outputs
4
STP16DPP05
Equivalent circuit and outputs
Figure 2: OE/DM2 terminal
Figure 3: LE/DM1 terminal
8/34
DocID16518 Rev 4
STP16DPP05
Equivalent circuit and outputs
Figure 4: CLK, SDI terminal
Figure 5: SDO terminal
DocID16518 Rev 4
9/34
Equivalent circuit and outputs
STP16DPP05
Figure 6: Block diagram
10/34
DocID16518 Rev 4
STP16DPP05
5
Timing diagrams
Timing diagrams
Table 9: Truth table
CLOCK
LE/DM1
OE/DM2
SERIAL-IN
OUT0 ............. OUT7 ................ OUT15
SDO
_|¯
H
L
Dn
Dn ..... Dn - 7 ..... Dn -15
Dn - 15
_|¯
L
L
Dn + 1
No change
Dn - 14
_|¯
H
L
Dn + 2
Dn + 2 ..... Dn - 5 ..... Dn -13
Dn - 13
¯|_
X
L
Dn + 3
Dn + 2 ..... Dn - 5 ..... Dn -13
Dn - 13
¯|_
X
H
Dn + 3
OFF
Dn - 13
OUTn = ON when Dn = H OUTn = OFF when Dn = L.
Figure 7: Timing diagram
1 Latch and output enable terminals are level-sensitive and are not synchronized
with rising or falling edge of CLK signal.
2 When LE/DM1 terminal is low level, the latch circuit holds previous set of data.
3 When LE/DM1 terminal is high level, the latch circuit refreshes new set of data
from SDI chain.
4 When OE/DM2 terminal is at low level, the output terminals Out 0 to Out 15
respond to data in the latch circuits, either ‘1’ for ON or ‘0’ for OFF.
5 When OE/DM2 terminal is at high level, all output terminals are switched
OFF.
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Timing diagrams
STP16DPP05
Table 10: Enable IO: shutdown truth table
CLOCK
LE/DM1
SDI0 ...........SDI7............ SDI15
SH
Not active
(1)
OUTn
_|¯
H
All = L
Active
_|¯
L
No change
No change
No change
No change
_|¯
H
One or more = H
Not active
Active
X (2)
Notes:
(1)
At power-up, the device starts in shutdown mode.
(2)
Undefined.
Figure 8: Clock, serial-in, serial-out
12/34
Auto power-up
DocID16518 Rev 4
OFF
STP16DPP05
Timing diagrams
Figure 9: Clock, serial-in, latch, enable, outputs
Figure 10: Outputs
DocID16518 Rev 4
13/34
Typical characteristics
6
STP16DPP05
Typical characteristics
Figure 11: Output current vs. R-EXT resistor
Table 11: Output current vs. R-EXT resistor
14/34
R-EXT (Ω)
Output current (mA)
23700
1
11730
2
6930
3
4090
5
2025
10
1000
20
667
30
497
40
331
60
DocID16518 Rev 4
STP16DPP05
Typical characteristics
Conditions: temperature = 25 °C, VDD = 3.3 V; 5.0 V, ISET = 3 mA; 5 mA; 10 mA; 20 mA;
50 mA; 60 mA.
Figure 12: ISET vs. dropout voltage (Vdrop)
Table 12: ISET vs. dropout voltage (Vdrop)
Iout (mA)
Avg (mV) @ 3.3 V
Avg (mV) @ 5.0 V
3
36
37
5
71
72
10
163
163
20
346
347
40
724
726
60
1080
1110
DocID16518 Rev 4
15/34
Typical characteristics
TA = 25 °C, Vdd = 3.3 V; 5 V
STP16DPP05
Figure 13: Output current vs. ± ΔIOL(%)
Figure 14: Idd ON/OFF
16/34
DocID16518 Rev 4
STP16DPP05
Typical characteristics
Figure 15: Power dissipation vs package temperature
The exposed pad should be soldered to the PCB to obtain the thermal benefits.
Figure 16: Turn ON output current
characteristics(1)
Figure 17: Turn OFF output current
characteristics(2)
Notes:
(1)
The reference level for the TON characteristics is 50% of OE/DM2
(2)
The reference level for the TOFF characteristics is 50% of OE/DM2
signal and 90 % of output current.
signal and 10 % of output current.
Electrical conditions: Vdd = 3.3 V, Vin = Vdd, Vled = 3.0 V, RL = 60 Ω, CL = 10 pF Ch1
(Yellow) = OE/DM2 , Ch2 (Blue) = SDI, Ch3 (Purple) = VOUT, Ch4 (Green) = OUT
DocID16518 Rev 4
17/34
Error detection mode functionality
STP16DPP05
7
Error detection mode functionality
7.1
Phase one: entering error detection mode
From the “normal mode” condition the device can switch to “error mode” by a logic
sequence on the OE/DM2 and LE/DM1 pins, as shown in the following table and
diagram:
Table 13: Entering error detection mode - truth table
CLK
1°
2°
3°
4°
5°
OE/DM2
H
L
H
H
H
LE/DM1
L
L
L
H
L
Figure 18: Entering error detection mode - timing diagram
After these five CLK cycles, the device goes into “error detection mode” and at the rising
edge of the 6th CLK cycle, the SDI data are ready for sampling.
18/34
DocID16518 Rev 4
STP16DPP05
7.2
Error detection mode functionality
Phase two: error detection
The 16 data bits must be set to “1” in order for all the outputs to be ON during error
detection. The data are latched by LE/DM1, after which the outputs are ready for the
detection process. When the microcontroller switches the OE/DM2 to LOW, the device
drives the LEDs to analyze if an OPEN or SHORT condition has occurred.
Figure 19: Detection diagram
The status of the LEDs is detected in at least 1 microsecond, and after this period the
microcontroller sets OE/DM2 to HIGH state and the output data detection result is sent
to the microcontroller via SDO. Error detection mode and normal mode both use the same
data format. As soon as all the detection data bits are available on the serial line, the
device may return to normal mode of operation. To re-detect the status, the device must
first return to normal mode and reenter error detection mode.
DocID16518 Rev 4
19/34
Error detection mode functionality
STP16DPP05
Figure 20: Timing example for open and/or short-circuit detection
20/34
DocID16518 Rev 4
STP16DPP05
7.3
Error detection mode functionality
Phase three: resuming normal mode
The sequence for reentering normal mode is shown in the following table:
Table 14: Resuming normal mode - timing diagram
CLK
1°
2°
3°
4°
5°
OE/DM2
H
L
H
H
H
LE/DM1
L
L
L
L
L
For proper device operation, the “entering error detection” sequence must be
followed by a “resume mode” sequence, it is not possible to insert consecutive
equal sequences.
7.4
Error detection conditions
Table 15: Detection conditions (VDD = 3.3 to 5 V, temperature range -40 to 125 °C)
Configuration
Detect mode
Detection results
SW-1 or SW-3b
Open line or output
short to GND detected
==> IODEC ≤ 0.5 x IO
No error
detected
==> IODEC ≥ 0.5 x IO
SW-2 or SW-3a
Short on LED or short
to V-LED detected
==> VO ≥ 2.6 V
No error
detected
==> VO ≤ 2.3 V
Where: IO = the output current programmed by the R-EXT, IODEC = the detected
output current in detection mode
Figure 21: Detection circuit
DocID16518 Rev 4
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Error detection mode functionality
STP16DPP05
Figure 22: Error detection sequence
22/34
DocID16518 Rev 4
STP16DPP05
8
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
DocID16518 Rev 4
23/34
Package information
8.1
STP16DPP05
QSOP-24 package information
Figure 23: QSOP-24 package outline
24/34
DocID16518 Rev 4
STP16DPP05
Package information
Table 16: QSOP-24 mechanical data
mm
Dim.
Min.
Typ.
Max.
A
1.54
1.62
1.73
A1
0.10
0.15
0.25
A2
1.47
b
0.20
0.31
c
0.17
0.254
D
8.56
8.66
8.76
E
5.80
6.00
6.20
E1
3.80
3.91
4.01
e
0.635
L
0.40
0.635
0.89
h
0.25
0.33
0.41
<
0°
DocID16518 Rev 4
8°
25/34
Package information
8.2
STP16DPP05
SO-24 package information
Figure 24: SO-24 package outline
26/34
DocID16518 Rev 4
STP16DPP05
Package information
Table 17: SO-24 mechanical data
mm
Dim.
Min.
Typ.
A
2.35
2.65
A1
0.10
0.30
B
0.33
0.51
C
0.23
0.32
D
15.20
15.60
E
7.40
e
7.60
1.27
H
10.00
10.65
h
0.25
0.75
L
0.40
1.27
k
0
8
ddd
8.3
Max.
0.10
TSSOP24 package information
Figure 25: TSSOP24 package outline
DocID16518 Rev 4
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Package information
STP16DPP05
Table 18: TSSOP24 mechanical data
mm
Dim.
Min.
Typ.
A
A1
1.1
0.05
A2
0.15
0.9
b
0.19
0.30
c
0.09
0.20
D
7.7
7.9
E
4.3
4.5
e
28/34
Max.
0.65 BSC
H
6.25
6.5
K
0°
8°
L
0.50
0.70
DocID16518 Rev 4
STP16DPP05
8.4
Package information
TSSOP exposed pad package information
Figure 26: TSSOP24 exposed pad package outline
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Package information
STP16DPP05
Table 19: TSSOP24 exposed pad mechanical data
mm
Dim.
Min.
Max.
A
1.20
A1
0.15
A2
0.80
b
0.19
0.30
c
0.09
0.20
1.00
1.05
D
7.70
7.80
7.90
D1
4.80
5.00
5.2
E
6.20
6.40
6.60
E1
4.30
4.40
4.50
E2
3.00
3.20
3.40
e
L
0.65
0.45
L1
k
060
075
1.00
0°
aaa
30/34
Typ.
8°
0.10
DocID16518 Rev 4
STP16DPP05
8.5
Package information
TSSOP24, TSSOP24 exposed pad and SO-24 packing
information
Figure 27: TSSOP24, TSSOP24 exposed pad and SO-24 reel outline
Table 20: TSSOP24 and TSSOP24 exposed pad tape and reel mechanical data
mm
Dim.
Min.
A
Typ.
Max.
-
330
13.2
C
12.8
-
D
20.2
-
N
60
-
T
-
22.4
Ao
6.8
-
7
Bo
8.2
-
8.4
Ko
1.7
-
1.9
Po
3.9
-
4.1
P
11.9
-
12.1
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Package information
STP16DPP05
Table 21: SO-24 tape and reel mechanical data
mm
Dim.
Min.
A
Max.
-
330
13.2
C
12.8
-
D
20.2
-
N
60
-
T
32/34
Typ.
-
30.4
Ao
10.8
-
11.0
Bo
15.7
-
15.9
Ko
2.9
-
3.1
Po
3.9
-
4.1
P
11.9
-
12.1
DocID16518 Rev 4
STP16DPP05
9
Revision history
Revision history
Table 22: Document revision history
Date
Revision
Changes
22-Oct-2009
1
First release.
19-Jun-2014
2
Updated Section 8: Package mechanical data.
Added Section 9: Packaging mechanical data.
Minor text changes.
04-Apr-2016
3
Updated Table 16: "QSOP-24 mechanical data".
Minor text changes.
04-Apr-2017
4
Updated Figure 5: "SDO terminal", Figure 8: "Clock, serial-in,
serial-out" and Figure 9: "Clock, serial-in, latch, enable, outputs".
Minor text changes.
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STP16DPP05
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