STP16DP05
Low voltage 16-bit constant current LED sink driver with outputs
error detection
Datasheet - production data
Features
Low voltage power supply down to 3 V
16 constant current output channels
Adjustable output current through external
resistor
Short and open output error detection
Serial data IN/Parallel data OUT
3.3 V micro driver-able
Output current: 5-100 mA
30 MHz clock frequency
Available in high thermal efficiency TSSOP
exposed pad
ESD protection 2.5 kV HBM, 200 V MM
Description
The STP16DP05 is a monolithic, low voltage, low
current power 16-bit shift register designed for
LED panel displays. The device contains a 16-bit
serial-in, parallel-out shift register that feeds a
16-bit D-type storage register. In the output
stage, sixteen regulated current sources were
designed to provide 5-100 mA constant current to
drive the LEDs. The STP16DP05 features open
and short LED detections on the outputs. The
STP16DP05 is backward compatible with
STP16C/L596. The detection circuit checks
3 different conditions that can occur on the output
line: short to GND, short to VO or open line. The
data detection results are loaded in the shift
register and shifted out via the serial line output.
The detection functionality is implemented
without increasing the pin count number, through
a secondary function of the output enable and
latch pin (DM1 and DM2 respectively), a
dedicated logic sequence allows the device to
enter or leave from detection mode. Through an
external resistor, users can adjust the
STP16DP05 output current, controlling in this
way the light intensity of LEDs, in addition, user
can adjust LED’s brightness intensity from 0 % to
100 % via OE/DM2 pin. The STP16DP05
guarantees a 20 V output driving capability,
allowing users to connect more LEDs in series.
The high clock frequency, 30 MHz, makes the
device suitable for high data rate transmission.
The 3.3 V voltage supply is well useful for
applications that interface any 3.3 V micro.
Compared with a standard TSSOP package, the
TSSOP exposed pad increases heat dissipation
capability by a 2.5 factor.
Table 1: Device summary
Order code
Package
Packing
STP16DP05MTR
SO-24 (tape and reel)
1000 parts per reel
STP16DP05TTR
TSSOP24 (tape and reel)
2500 parts per reel
STP16DP05XTTR
TSSOP24 exposed pad (tape and reel)
2500 parts per reel
STP16DP05PTR
QSOP-24
2500 parts per reel
November 2017
DocID13093 Rev 8
This is information on a product in full production.
1/34
www.st.com
Contents
STP16DP05
Contents
1
Summary description ...................................................................... 3
1.1
2
Pin connection and description ......................................................... 3
Electrical ratings ............................................................................. 4
2.1
Absolute maximum ratings ................................................................ 4
2.2
Thermal data ..................................................................................... 4
2.3
Recommended operating conditions ................................................. 5
3
Electrical characteristics ................................................................ 6
4
Equivalent circuit and outputs ....................................................... 8
5
Timing diagrams ............................................................................ 11
6
Typical characteristics .................................................................. 14
7
Detection mode functionality ....................................................... 17
8
9
2/34
7.1
Phase one: “entering in detection mode“ ........................................ 17
7.2
Phase two: “error detection” ............................................................ 18
7.3
Phase three: “resuming to normal mode” ........................................ 20
7.4
Error detection conditions ............................................................... 20
Package information ..................................................................... 23
8.1
QSOP-24 package information ....................................................... 24
8.2
SO-24 package information ............................................................ 26
8.3
TSSOP24 package information ....................................................... 27
8.4
TSSOP24 exposed pad package information ................................. 29
8.5
TSSOP24, TSSOP24 exposed pad and SO-24 packing information31
Revision history ............................................................................ 33
DocID13093 Rev 8
STP16DP05
1
Summary description
Summary description
Table 2: Typical current accuracy
Current accuracy
Output voltage
≥ 1.3 V
1.1
Between bits
Between ICs
±1.5 %
±5 %
Output current
VDD
Temperature
20 to 100 mA
3.3 V to 5 V
25 °C
Pin connection and description
Figure 1: Pin connection
The exposed pad should be electrically connected to a metal land electrically
isolated or connected to ground
Table 3: Pin description
Pin n°
Symbol
Name and function
1
GND
Ground terminal
2
SDI
Serial data input terminal
3
CLK
Clock input terminal
4
LE-DM1
5-20
OUT 0-15
Output terminal
21
OE-DM2
Input terminal of output enable (active low) - detect mode 1 (see operation principle)
22
SDO
23
R-EXT
24
VDD
Latch input terminal - detect mode 1 (see operation principle)
Serial data out terminal
Input terminal of an external resistor for constant current programing
Supply voltage terminal
DocID13093 Rev 8
3/34
Electrical ratings
STP16DP05
2
Electrical ratings
2.1
Absolute maximum ratings
Stressing the device above the rating listed in the “absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 4: Absolute maximum ratings
Symbol
2.2
Parameter
Value
Unit
VDD
Supply voltage
0 to 7
V
VO
Output voltage
-0.5 to 20
V
IO
Output current
100
mA
VI
Input voltage
IGND
GND terminal current
fCLK
Clock frequency
-0.4 to VDD
V
1600
mA
50
MHz
Value
Unit
Thermal data
Table 5: Thermal data
Symbol
Parameter
TOPR
Operating temperature range
-40 to +125
°C
TSTG
Storage temperature range
-55 to +150
°C
RthJA
Thermal resistance junctionambient
SO-24
42.7
°C/W
TSSOP24
55
°C/W
TSSOP24 exposed pad (1)
37.5
°C/W
QSOP-24
55
°C/W
Notes:
(1)The
4/34
exposed pad should be soldered directly to the PCB to realize the thermal benefits.
DocID13093 Rev 8
STP16DP05
2.4
Electrical ratings
Recommended operating conditions
Table 6: Recommended operating conditions
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
3.0
-
5.5
V
-
20
V
-
100
mA
VDD
Supply voltage
VO
Output voltage
IO
Output current
OUTn
IOH
Output current
SERIAL-OUT
-
+1
mA
IOL
Output current
SERIAL-OUT
-
-1
mA
VIH
Input voltage
0.7 VDD
-
VDD+0.3
V
VIL
Input voltage
-0.3
-
0.3 VDD
V
5
twLAT
LE\DM1 pulse width
6
-
ns
twCLK
CLK pulse width
8
-
ns
100
-
ns
twEN
OE/DM2 pulse width
VDD = 3.0 V to 5.0 V
tSETUP(D)
Setup time for DATA
10
-
ns
tHOLD(D)
Hold time for DATA
5
-
ns
tSETUP(L)
Setup time for LATCH
10
-
ns
fCLK
Clock frequency
Cascade operation
(1)
-
30
MHz
Notes:
(1)If
the device is connected in cascade, it may not be possible achieve the maximum data transfer. Please
consider the timings carefully.
DocID13093 Rev 8
5/34
Electrical characteristics
3
STP16DP05
Electrical characteristics
VDD = 3.3 V to 5 V, T = 25 °C, unless otherwise specified
Table 7: Electrical characteristics
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VIH
Input voltage high level
0.7 VDD
VDD
V
VIL
Input voltage low level
GND
0.3 VDD
V
IOH
Output leakage current
1
µA
VOL
Output voltage (serial-OUT) IOL = 1 mA
0.4
V
VOH
Output voltage (serial-OUT) IOH = -1 mA
VOH = 20 V
VOH -VDD = -0.4 V
V
VO = 0.3 V
REXT = 3.9 kΩ
4.25
5
5.75
VO = 0.3 V
REXT = 970 Ω
19
20
21
IOL3
VO = 1.3 V
REXT = 190 Ω
96
100
104
∆IOL1
VO = 0.3 V
REXT = 3.9 kΩ
±5
±8
VO = 0.3 V
REXT = 970 Ω
± 1.5
±3
VO = 1.3 V
REXT =190 Ω
± 1.2
±3
150
300
600
KΩ
100
200
400
KΩ
REXT = 970 OUT 0 to 15 = OFF
5
6
REXT = 240 OUT 0 to 15 = OFF
13
14
REXT = 970 OUT 0 to 15 = ON
6
7
REXT = 240 OUT 0 to 15 = ON
13.5
14.5
IOL1
IOL2
∆IOL2
Output current
Output current error
between bit (all output ON)
∆IOL3
RSIN(up)
Pull-up resistor
RSIN(down) Pull-down resistor
IDD(OFF1)
IDD(OFF2)
IDD(ON1)
IDD(ON2)
Supply current (OFF)
Supply current (ON)
Thermal Thermal protection
(1)
170
Notes:
(1)Guaranteed
6/34
by design (not tested). The thermal protection switches OFF only the outputs current.
DocID13093 Rev 8
mA
%
mA
°C
STP16DP05
Electrical characteristics
VDD = 5 V, T = 25 °C, unless otherwise specified.
Table 8: Switching characteristics
Symbol
Parameter
Test conditions
Propagation delay time,
tPLH1
=L
Propagation delay time,
LE/DM1 - OUTn , OE/DM2
=L
Propagation delay time,
tPLH3
OE/DM2
Propagation delay time,
CLK-SDO
Propagation delay time,
tPHL1
CLK - OUTn , LE/DM1 = H,
OE/DM2
=L
Propagation delay time,
tPHL2
VDD = 3.3 V
-
40
65
VDD = 5 V
-
20
30
VDD = 3.3 V
-
51
77
VDD = 5 V
-
32
47
VDD = 3.3 V
-
49
77
VDD = 5 V
-
27
41
VDD = 3.3 V
-
21.5
32
VDD = 5 V
-
14.5
21.5
VIH = VDD
VIL = GND
CL = 10 pF IO = 20 mA
VL = 3.0 V REXT = 1 KΩ
RL = 60 Ω
VDD = 3.3 V
-
15
25
VDD = 5 V
-
11
14.5
VDD = 3.3 V
-
13
20
VDD = 5 V
-
9
12.5
VDD = 3.3 V
-
11.5
18
VDD = 5 V
-
8.5
12
LE/DM1 - OUTn ,
OE/DM2
OE/DM2
Unit
ns
ns
ns
ns
ns
ns
=L
Propagation delay time,
tPHL3
Max.
- OUTn ,
LE/DM1 = H
tPLH
Typ.
CLK - OUTn , LE/DM1 = H,
OE/DM2
tPLH2
Min.
- OUTn ,
LE/DM1 = H
tPHL
Propagation delay time,
CLK-SDO
VDD = 3.3 V
-
25.5
38
VDD = 5 V
-
17.5
25
tON
Output fall time 10~90 % of
voltage waveform
VDD = 3.3 V
-
34
53.5
VDD = 5 V
-
12.5
18.5
tOFF
Output rise time 90~10 % of
voltage waveform
VDD = 3.3 V
-
5.5
8.5
VDD = 5 V
-
4.5
6.5
ns
ns
ns
ns
tr
CLK rise time(1)
-
5000
ns
tf
CLK fall time(1)
-
5000
ns
Notes:
(1)In
order to achieve high cascade data transfer, please consider tr/tf timings carefully.
DocID13093 Rev 8
7/34
Equivalent circuit and outputs
4
STP16DP05
Equivalent circuit and outputs
Figure 2: OE\DM2 terminal
Figure 3: LE\DM1 terminal
8/34
DocID13093 Rev 8
STP16DP05
Equivalent circuit and outputs
Figure 4: CLK, SDI terminal
Figure 5: SDO terminal
DocID13093 Rev 8
9/34
Equivalent circuit and outputs
STP16DP05
Figure 6: Block diagram
10/34
DocID13093 Rev 8
STP16DP05
5
Timing diagrams
Timing diagrams
Table 9: Truth table
CLOCK
LE\DM1
OE/DM2
SERIAL-IN
OUT0 .....OUT7.....OUT15
SDO
_|¯
H
L
Dn
Dn ..... Dn - 7 ..... Dn -15
Dn - 15
_|¯
L
L
Dn + 1
No change
Dn - 14
_|¯
H
L
Dn + 2
Dn + 2 ..... Dn - 5 ..... Dn -13
Dn - 13
¯|_
X
L
Dn + 3
Dn + 2 ..... Dn - 5 ..... Dn -13
Dn - 13
¯|_
X
H
Dn + 3
OFF
Dn - 13
OUTn = ON when Dn = H OUTn = OFF when Dn = L
Figure 7: Timing diagram
1 - Latch and output enable are level sensitive and ARE NOT synchronized with
rising-or-falling edge of CLK signal.
2 - When LE terminal is low level, the latch circuits hold previous set of data.
3 - When LE terminal is at high level, the latch circuits refresh new set of data
from SDI chain.
4 - When OE terminal is at low level, the output terminals - Out0 to Out15
respond to data in the latch circuits, either '1' for ON or '0' for OFF.
5 - When OE terminal is at high level, all output terminals will be switched OFF.
DocID13093 Rev 8
11/34
Timing diagrams
STP16DP05
Figure 8: Clock, serial-in, serial-out
12/34
DocID13093 Rev 8
STP16DP05
Timing diagrams
Figure 9: Clock, serial-in, latch, enable, outputs
Figure 10: Outputs
DocID13093 Rev 8
13/34
Typical characteristics
6
STP16DP05
Typical characteristics
Figure 11: Output current-Rext resistor
Table 10: Output current-Rext resistor
Rext (Ω)
Output current (mA)
976
20
780
25
652
30
560
35
488
40
433
45
389
50
354
55
325
60
300
65
278
70
259
75
241
80
229
85
215
90
Conditions:
Temperature = 25 °C, VDD = 3.3 V; 5.0 V, ISET = 3 mA; 5 mA; 10 mA; 20 mA; 50 mA;
80 mA.
14/34
DocID13093 Rev 8
STP16DP05
Typical characteristics
Figure 12: ISET vs drop out voltage (Vdrop)
Table 11: ISET vs drop out voltage (Vdrop)
Iout (mA)
Avg @ 3.0 V
Avg @ 5.0 V
3
19.33
22.66
5
36.67
40.33
10
77.33
80
20
158.67
157.33
50
406
406
80
692
668
Figure 13: IDD ON/OFF
DocID13093 Rev 8
15/34
Typical characteristics
STP16DP05
Figure 14: Power dissipation vs temperature package
The exposed pad should be soldered to the PBC to realize the thermal benefits.
16/34
DocID13093 Rev 8
STP16DP05
Detection mode functionality
7
Detection mode functionality
7.1
Phase one: “entering in detection mode“
From the “normal mode” condition the device can switch to the “error mode” by a logic
sequence on the OE/DM2 and LE/DM1 pins as showed in the following table and
diagram:
Table 12: Entering in detection truth table
CLK
1°
2°
3°
4°
5°
OE/DM2
H
L
H
H
H
LE/DM1
L
L
L
H
L
Figure 15: Entering in detection timing diagram
After these five CLK cycles the device goes into the “error detection mode” and at the 6th
rise front of CLK the SDI data are ready for the sampling.
DocID13093 Rev 8
17/34
Detection mode functionality
7.2
STP16DP05
Phase two: “error detection”
The 16 data bits must be set “1” in order to set ON all the outputs during the detection. The
data are latched by LE/DM1 and after that the outputs are ready for the detection process.
When the micro controller switches the OE/DM2 to LOW, the device drives the LEDs in
order to analyze if an OPEN or SHORT condition has occurred.
Figure 16: Detection diagram
The LEDs status will be detected at least in 1 microsecond and after this time the
microcontroller sets OE/DM2 in HIGH state and the output data detection result will go to
the microprocessor via SDO.
Detection mode and normal mode use both the same format data. As soon as all the
detection data bits are available on the serial line, the device may go back to normal mode
of operation. To re-detect the status the device must go back in normal mode and reentering in error detection mode.
18/34
DocID13093 Rev 8
STP16DP05
Detection mode functionality
Figure 17: Timing example for open and/or short detection
DocID13093 Rev 8
19/34
Detection mode functionality
7.3
STP16DP05
Phase three: “resuming to normal mode”
The sequence for re-entering in normal mode is showed in the following table and diagram:
Table 13: Resuming to normal mode timing diagram
CLK
1°
2°
3°
4°
5°
OE/DM2
H
L
H
H
H
LE/DM1
L
L
L
L
L
For proper device operation the “Entering in detection” sequence must be follow
by a “resume mode” sequence, it is not possible to insert consecutive equal
sequence.
7.4
Error detection conditions
VDD = 3.3 to 5 V temperature range -40 to 125 °C
Table 14: Detection conditions
SW-1
or
SW-3b
SW-2
or
SW-3a
Open line or output short to GND
detected
==> IODEC ≤ 0.5 x IO
No error
==> IODEC ≥ 0.5 x IO
detected
Short on LED or short to V-LED
detected
==> VO ≥ 2.4 V
No error
==> VO ≤ 2.2 V
detected
Where: IO = the output current programmed by the REXT, IODEC = the detected
output current in detection mode.
20/34
DocID13093 Rev 8
STP16DP05
Detection mode functionality
Figure 18: Detection circuit
DocID13093 Rev 8
21/34
Detection mode functionality
STP16DP05
Figure 19: Error detection sequence
22/34
DocID13093 Rev 8
STP16DP05
8
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
DocID13093 Rev 8
23/34
Package information
8.1
STP16DP05
QSOP-24 package information
Figure 20: QSOP-24 package outline
24/34
DocID13093 Rev 8
STP16DP05
Package information
Table 15: QSOP-24 mechanical data
mm
Dim.
Min.
Typ.
Max.
A
1.54
1.62
1.73
A1
0.10
0.15
0.25
A2
1.47
b
0.20
0.31
c
0.17
0.254
D
8.56
8.66
8.76
E
5.80
6.00
6.20
E1
3.80
3.91
4.01
e
0.635
L
0.40
0.635
0.89
h
0.25
0.33
0.41
<
0°
DocID13093 Rev 8
8°
25/34
Package information
8.2
STP16DP05
SO-24 package information
Figure 21: SO-24 package outline
26/34
DocID13093 Rev 8
STP16DP05
Package information
Table 16: SO-24 mechanical data
mm
Dim.
Min.
Typ.
A
2.35
2.65
A1
0.10
0.30
B
0.33
0.51
C
0.23
0.32
D
15.20
15.60
E
7.40
e
7.60
1.27
H
10.00
10.65
h
0.25
0.75
L
0.40
1.27
k
0
8
ddd
8.3
Max.
0.10
TSSOP24 package information
Figure 22: TSSOP24 package outline
DocID13093 Rev 8
27/34
Package information
STP16DP05
Table 17: TSSOP24 mechanical data
mm
Dim.
Min.
Typ.
A
A1
1.1
0.05
A2
0.15
0.9
b
0.19
0.30
c
0.09
0.20
D
7.7
7.9
E
4.3
4.5
e
28/34
Max.
0.65 BSC
H
6.25
6.5
K
0°
8°
L
0.50
0.70
DocID13093 Rev 8
STP16DP05
8.4
Package information
TSSOP24 exposed pad package information
Figure 23: TSSOP24 exposed pad package outline
DocID13093 Rev 8
29/34
Package information
STP16DP05
Table 18: TSSOP24 exposed pad mechanical data
mm
Dim.
Min.
Max.
A
1.20
A1
0.15
A2
0.80
b
0.19
0.30
c
0.09
0.20
1.00
1.05
D
7.70
7.80
7.90
D1
4.80
5.00
5.2
E
6.20
6.40
6.60
E1
4.30
4.40
4.50
E2
3.00
3.20
3.40
e
L
0.65
0.45
L1
k
060
0.75
1.00
0°
aaa
30/34
Typ.
8°
0.10
DocID13093 Rev 8
STP16DP05
8.5
Package information
TSSOP24, TSSOP24 exposed pad and SO-24 packing
information
Figure 24: TSSOP24, TSSOP24 exposed pad and SO-24 reel outline
Table 19: TSSOP24 and TSSOP24 exposed pad tape and reel mechanical data
mm
Dim.
Min.
A
Typ.
Max.
-
330
13.2
C
12.8
-
D
20.2
-
N
60
-
T
-
22.4
Ao
6.8
-
7
Bo
8.2
-
8.4
Ko
1.7
-
1.9
Po
3.9
-
4.1
P
11.9
-
12.1
DocID13093 Rev 8
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Package information
STP16DP05
Table 20: SO-24 tape and reel mechanical data
mm
Dim.
Min.
A
Max.
-
330
13.2
C
12.8
-
D
20.2
-
N
60
-
T
32/34
Typ.
-
30.4
Ao
10.8
-
11.0
Bo
15.7
-
15.9
Ko
2.9
-
3.1
Po
3.9
-
4.1
P
11.9
-
12.1
DocID13093 Rev 8
STP16DP05
9
Revision history
Revision history
Table 21: Document revision history
Date
Revision
Changes
9-Jan-2007
1
First release
21-May-2007
2
Updated Table 7 on page 7
10-Jul-2007
3
Updated Table 9: Truth table on page 11
28-Feb-2008
4
Updated Table 15: TSSOP24 exposed-pad on page 23
Added QSOP-24 package information Table 14 and Figure 21 on
page 24
23-Oct-2009
5
Updated Figure 7 on page 11, Chapter 3 on page 7
20-Jan-2010
6
Updated Table 5 on page 5
17-Jun-2014
7
Updated Section 8: Package mechanical data.
Added Section 9: Packaging mechanical data.
Minor text changes.
8
Updated Figure 5: "SDO terminal", Figure 8: "Clock, serial-in, serial-out",
Figure 9: "Clock, serial-in, latch, enable, outputs" and Section 8:
"Package information".
Minor text changes.
07-Nov-2017
DocID13093 Rev 8
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STP16DP05
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DocID13093 Rev 8
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