STP16CPP05PTR

STP16CPP05 Low voltage 16-bit constant current LED sink driver Datasheet - production data Description The STP16CPP05 is a monolithic, low voltage, low current power 16-bit shift register designed for LED panel displays. The STP16CPP05 contains a 16-bit serial-in, parallel-out shift register that feeds a 16-bit, D-type storage register. In the output stage, sixteen regulated current sources provide from 3 mA to 40 mA constant current to drive the LEDs. The output current setup time is 40 ns (typ), thus improving the system performance. The LEDs' brightness can be controlled by using an external resistor to adjust the STP16CPP05 output current. The STP16CPP05 guarantees a 20 V output driving capability, allowing users to connect more LEDs in series. The high clock frequency, 30 MHz, makes the device suitable for high data rate transmission. The 3.3 V voltage supply is useful in applications that interface with a 3.3 V micro controller. Features          16 constant current output channels Adjustable output current through external resistor Output current: 3-40 mA Serial data in/parallel data ouT 3.3 V or 5 V supply voltage Max clock frequency 30 MHz Schmitt-trigger input ESD protection 2 kV HBM Thermal shutdown Table 1: Device summary Order code Package Packing STP16CPP05MTR SO-24 1000 parts per reel STP16CPP05TTR TSSOP24 2500 parts per reel STP16CPP05XTTR TSSOP24 exposed pad 2500 parts per reel STP16CPP05PTR QSOP-24 2500 parts per reel March 2017 DocID15379 Rev 5 This is information on a product in full production. 1/31 www.st.com Contents STP16CPP05 Contents 1 Summary description ...................................................................... 3 1.1 2 Pin connection and description ......................................................... 3 Electrical ratings ............................................................................. 4 2.1 Absolute maximum ratings ................................................................ 4 2.2 Thermal data ..................................................................................... 4 2.3 Recommended operating conditions ................................................. 5 3 Electrical characteristics ................................................................ 6 4 Equivalent circuit and outputs ....................................................... 8 5 Timing diagrams ............................................................................ 11 6 Typical characteristics .................................................................. 14 7 Tast circuits ................................................................................... 17 8 Package information ..................................................................... 20 8.1 QSOP-24 package information ....................................................... 21 8.2 SO-24 package information ............................................................ 23 8.3 TSSOP24 package information ....................................................... 24 8.4 TSSOP24 exposed pad package information ................................ 26 8.5 TSSOP24, TSSOP24 exposed pad and ............................................ SO-24 packing information .............................................................. 28 9 2/31 Revision history ............................................................................ 30 DocID15379 Rev 5 STP16CPP05 1 Summary description Summary description Table 2: Typical current accuracy Current accuracy Output voltage Between bits Between ICs ± 1.5% ± 5% ≥ 1.3 V 1.1 Output current VDD Temperature ≥ 5 to 40 mA 3.3 V to 5 V 25 °C Pin connection and description Figure 1: Pin connection The exposed pad should be electrically connected to a metal land electrically isolated or connected to ground. Table 3: Pin description Pin n° Symbol Name and function 1 GND Ground terminal 2 SDI Serial data input terminal 3 CLK Clock input terminal 4 LE Latch input terminal 5-20 OUT 0-15 21 OE Input terminal of output enable (active low) 22 SDO Serial data out terminal 23 R-EXT 24 VDD Output terminal Input terminal for an external resistor for constant current programming Supply voltage terminal DocID15379 Rev 5 3/31 Electrical ratings STP16CPP05 2 Electrical ratings 2.1 Absolute maximum ratings Stressing the device above the rating listed in the “absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 4: Absolute maximum ratings Symbol 2.2 Parameter Value Unit VDD Supply voltage 0 to 7 V VO Output voltage -0.5 to 20 V IO Output current 50 mA VI Input voltage -0.4 to VDD + 0.4 V IGND GND terminal current 800 mA fCLK Clock frequency 50 MHz Value Unit Thermal data Table 5: Thermal data Symbol Parameter TOPR Operating temperature range -40 to +125 °C TSTG Storage temperature range -55 to +150 °C RthJA Thermal resistance junction-ambient SO-24 60 °C/W TSSOP24 85 °C/W TSSOP24 (1) exposed pad 37.5 °C/W QSOP-24 72 °C/W Notes: (1) 4/31 The exposed pad should be soldered directly to the PCB to realize the thermal benefits. DocID15379 Rev 5 STP16CPP05 2.3 Electrical ratings Recommended operating conditions Table 6: Recommended operating conditions at 25 °C Symbol Parameter Test conditions Min. 3.0 Typ. Max. Unit 5.5 V 20 V 40 mA VDD Supply voltage VO Output voltage IO Output current OUTn IOH Output current SERIAL-OUT +1 mA IOL Output current SERIAL-OUT -1 mA VIH Input voltage 0.7 VDD VDD + 0.3 V VIL Input voltage -0.3 0.3 VDD V 3 twLAT LE/DM1 pulse width 20 ns twCLK CLK pulse width 16 ns 70 ns twEN OE pulse width VDD = 3.3 V to 5.0 V tSETUP(D) Setup time for DATA 5 ns tHOLD(D) Hold time for DATA 5 ns tSETUP(L) Setup time for LATCH 15 ns fCLK Clock frequency Cascade operation (1) 30 MHz Notes: (1) If the device is connected in cascade, it may not be possible achieve the maximum data transfer. Please consider the timings carefully. DocID15379 Rev 5 5/31 Electrical characteristics 3 STP16CPP05 Electrical characteristics VDD = 3.3 V to 5 V, TA = 25 °C, unless otherwise specified. Table 7: Electrical characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit VIH Input voltage high level 0.7 VDD VDD V VIL Input voltage low level GND 0.3 VDD V IOH Output leakage current VOH = 20 V 1 μA VOL Output voltage (serial-OUT) IOL = 1 mA 0.4 V VOH Output voltage (serial-OUT) IOH = -1 mA VO = 0.3 V, Rext = 4 kΩ IOL1 IOL2 Output current IOL3 ΔIOL1 ΔIOL2 Output current error between bit (all output ON) ΔIOL3 RSIN(up) RSIN(down) IDD(OFF1) IDD(OFF2) IDD(ON1) 6/31 VDD-0.4V V 4.75 5 5.25 VO = 0.3 V, Rext = 980 Ω 19 20 21 VO = 1.3 V, Rext = 490 Ω 38 40 42 VO = 0.3 V, IO = 5 mA, Rext = 4 kΩ ± 1.2 ±5 VO = 0.3 V, IO = 20 mA, Rext = 980 Ω ± 0.5 ±3 VO = 1.3 V, IO = 40 mA, Rext = 490 Ω ± 1.0 ±3 mA % Pull-up resistor 150 300 600 kΩ Pull-down resistor 100 200 400 kΩ Rext = 980 OUT 0 to 15 = OFF 5.4 7.5 Rext = 490 OUT 0 to 15 = OFF 8.0 9.5 Rext = 980, OUT 0 to 15 = ON 5.5 7.5 Rext = 490, OUT 0 to 15 = ON 8.1 9.5 Supply current (OFF) Supply current (ON) IDD(ON2) Thermal 0.15 Thermal protection 170 DocID15379 Rev 5 mA °C STP16CPP05 VDD = 5 V, TA = 25 °C, unless otherwise specified. Electrical characteristics Table 8: Switching characteristics Symbol Parameter Test conditions Min. Typ. Max. VDD = 3.3 V - 44 58 VDD = 5 V - 24 32 Propagation delay time, VDD = 3.3 V - 43 56 LE- OUTn , OE = L VDD = 5 V - 24 32 Propagation delay time, VDD = 3.3 V - 63 82 VDD = 5 V - 37 48 VDD = 3.3 V - 17 22 VDD = 5 V - 11 14 VDD = 3.3 V - 22 28 VDD = 5 V - 16 21 Propagation delay time, VDD = 3.3 V - 19 25 LE- OUTn , OE = L VDD = 5 V - 15 20 Propagation delay time, VDD = 3.3 V - 16 21 VDD = 5 V - 13 17 Propagation delay time, tPLH1 CLK- OUTn , LE = H, OE = L tPLH2 tPLH3 tPLH OE - OUTn , LE = H Propagation delay time, CLK-SDO Propagation delay time, tPHL1 CLK- OUTn , LE = H, OE = L tPHL2 tPHL3 VIH = VDD VIL = GND CL = 10 pF IO = 20 mA VL = 3.0 V Rext = 1 KΩ RL = 60 Ω OE - OUTn , LE = H tPHL Propagation delay time, CLK-SDO VDD = 3.3 V - 21 27 VDD = 5 V - 13 17 tON Output rise time 10~90% of voltage waveform VDD = 3.3 V - 26 35 VDD = 5 V - 12 16 tOFF Output fall time 90~10% of voltage waveform VDD = 3.3 V - 4 6 VDD = 5 V - 3 5 Unit ns ns ns ns ns ns ns ns ns ns tr CLK rise time (1) - 5000 ns tf CLK fall time (1) - 5000 ns Notes: (1) In order to achieve high cascade data transfer, please consider tr/tf timings carefully. DocID15379 Rev 5 7/31 Equivalent circuit and outputs 4 STP16CPP05 Equivalent circuit and outputs Figure 2: OE terminal Figure 3: LE terminal 8/31 DocID15379 Rev 5 STP16CPP05 Equivalent circuit and outputs Figure 4: CLK, SDI terminal Figure 5: SDO terminal DocID15379 Rev 5 9/31 Equivalent circuit and outputs STP16CPP05 Figure 6: Block diagram 10/31 DocID15379 Rev 5 STP16CPP05 5 Timing diagrams Timing diagrams Table 9: Truth table CLOCK LE OE SERIAL-IN OUT0 ............. OUT7 ................ OUT15 SDO _|¯ H L Dn Dn ..... Dn - 7 ..... Dn -15 Dn - 15 _|¯ L L Dn + 1 No change Dn - 14 _|¯ H L Dn + 2 Dn + 2 ..... Dn - 5 ..... Dn -13 Dn - 13 ¯|_ X L Dn + 3 Dn + 2 ..... Dn - 5 ..... Dn -13 Dn - 13 ¯|_ X H Dn + 3 OFF Dn - 13 OUTn = ON when Dn = H OUTn = OFF when Dn = L. Figure 7: Timing diagram The latches circuit holds data when the LE terminal is Low. 1 When LE terminal is at high level, latch circuit does not hold the data it passes from the input to the output. 2 When OE terminal is at low level, output terminals OUT0 to OUT15 respond to the data, either ON or OFF. 3 When OE terminal is at high level, it switches off all the data on the output terminal. DocID15379 Rev 5 11/31 Timing diagrams STP16CPP05 Figure 8: Clock, serial-in, serial-out 12/31 DocID15379 Rev 5 STP16CPP05 Timing diagrams Figure 9: Clock, serial-in, latch, enable, outputs Figure 10: Outputs DocID15379 Rev 5 13/31 Typical characteristics 6 STP16CPP05 Typical characteristics Figure 11: Output current vs Rext resistor Table 10: Output current vs Rext resistor 14/31 Rext (Ω) Output current (mA) 23700 1 11730 2 6930 3 4090 5 2025 10 1000 20 667 30 497 40 331 60 DocID15379 Rev 5 STP16CPP05 Typical characteristics Figure 12: Output current vs ± ΔIOL(%) (temp. = 25 °C, Vdd = 5 V, pin = all outputs) Figure 13: ISET vs drop out voltage (Vdrop) DocID15379 Rev 5 15/31 Typical characteristics STP16CPP05 Table 11: ISET vs drop out voltage (Vdrop) Vdd (V) 3.3 16/31 Iset (mA) Min (mV) Max (mV) Avg (mV) 3 35 37 36 Vdd (V) Iset (mA) Min (mV) Max (mV) Avg (mV) 3 37 37 37 5 71 72 71 5 72 73 72 10 162 165 163 10 162 164 163 20 347 348 347 20 345 347 346 40 724 724 724 40 725 728 726 60 1080 1090 1080 60 1090 1140 1110 5.0 DocID15379 Rev 5 STP16CPP05 7 Tast circuits Tast circuits Figure 14: DC characteristic Figure 15: AC characteristic DocID15379 Rev 5 17/31 Tast circuits STP16CPP05 Figure 16: Typical application schematic VL will be determined by the VF of the LEDs. Test condition: Temp. = 25 °C, VDD = 3.3 V, VIN = VDD, CL = 10 pF, Freq. = 1 MHz, Ch1 = CLK, Ch2 = SDI, Ch3 = OUTn, Ch4 = VOUT Figure 17: Turn ON output current setup 18/31 DocID15379 Rev 5 STP16CPP05 Tast circuits Figure 18: Turn OFF output current setup DocID15379 Rev 5 19/31 Package information 8 STP16CPP05 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 20/31 DocID15379 Rev 5 STP16CPP05 8.1 Package information QSOP-24 package information Figure 19: QSOP-24 package outline DocID15379 Rev 5 21/31 Package information STP16CPP05 Table 12: QSOP-24 mechanical data mm Dim. Min. Typ. Max. A 1.54 1.62 1.73 A1 0.10 0.15 0.25 A2 1.47 b 0.20 0.31 c 0.17 0.254 D 8.56 8.66 8.76 E 5.80 6.00 6.20 E1 3.80 3.91 4.01 e 22/31 0.635 L 0.40 0.635 0.89 h 0.25 0.33 0.41 < 0° DocID15379 Rev 5 8° STP16CPP05 8.2 Package information SO-24 package information Figure 20: SO-24 package outline DocID15379 Rev 5 23/31 Package information STP16CPP05 Table 13: SO-24 mechanical data mm Dim. Min. Typ. A 2.35 2.65 A1 0.10 0.30 B 0.33 0.51 C 0.23 0.32 D 15.20 15.60 E 7.40 e 7.60 1.27 H 10.00 10.65 h 0.25 0.75 L 0.40 1.27 k 0 8 ddd 8.3 0.10 TSSOP24 package information Figure 21: TSSOP24 package outline 24/31 Max. DocID15379 Rev 5 STP16CPP05 Package information Table 14: TSSOP24 mechanical data mm Dim. Min. Typ. A A1 Max. 1.1 0.05 A2 0.15 0.9 b 0.19 0.30 c 0.09 0.20 D 7.7 7.9 E 4.3 4.5 e 0.65 BSC H 6.25 6.5 K 0° 8° L 0.50 0.70 DocID15379 Rev 5 25/31 Package information 8.4 STP16CPP05 TSSOP24 exposed pad package information Figure 22: TSSOP24 exposed pad package outline 26/31 DocID15379 Rev 5 STP16CPP05 Package information Table 15: TSSOP24 exposed pad mechanical data mm Dim. Min. Typ. Max. A 1.20 A1 0.15 A2 0.80 1.00 1.05 b 0.19 0.30 c 0.09 0.20 D 7.70 7.80 7.90 D1 4.80 5.00 5.2 E 6.20 6.40 6.60 E1 4.30 4.40 4.50 E2 3.00 3.20 3.40 e L 0.65 0.45 L1 k 060 075 1.00 0° aaa 8° 0.10 DocID15379 Rev 5 27/31 Package information 8.5 STP16CPP05 TSSOP24, TSSOP24 exposed pad and SO-24 packing information Figure 23: TSSOP24, TSSOP24 exposed pad and SO-24 reel outline Table 16: TSSOP24 and TSSOP24 exposed pad tape and reel mechanical data mm Dim. Min. A Max. - 330 13.2 C 12.8 - D 20.2 - N 60 - T 28/31 Typ. - 22.4 Ao 6.8 - 7 Bo 8.2 - 8.4 Ko 1.7 - 1.9 Po 3.9 - 4.1 P 11.9 - 12.1 DocID15379 Rev 5 STP16CPP05 Package information Table 17: SO-24 tape and reel mechanical data mm Dim. Min. A Typ. Max. - 330 13.2 C 12.8 - D 20.2 - N 60 - T - 30.4 Ao 10.8 - 11.0 Bo 15.7 - 15.9 Ko 2.9 - 3.1 Po 3.9 - 4.1 P 11.9 - 12.1 DocID15379 Rev 5 29/31 Revision history 9 STP16CPP05 Revision history Table 18: Document revision history Date Revision 11-Feb-2009 1 First release 22-Oct-2009 2 Updated Figure 11 on page 14 and Figure 10 on page 14. 10-Jun-2014 3 Updated Section 8: Package mechanical data. Added Section 9: Packaging mechanical data. Minor text changes. 08-Apr-2016 4 Updated Section 8.1: "QSOP-24 package information". Minor text changes. 5 Updated Figure 5: "SDO terminal", Figure 8: "Clock, serial-in, serial-out" and Figure 9: "Clock, serial-in, latch, enable, outputs". Minor text changes. 09-Mar-2017 30/31 Changes DocID15379 Rev 5 STP16CPP05 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2017 STMicroelectronics – All rights reserved DocID15379 Rev 5 31/31