STP16CPPS05PTR

STP16CPPS05 Low voltage 16-bit constant current LED sink driver with auto power-saving Datasheet - production data Description The STP16CPPS05 is a monolithic, low voltage, low current power 16-bit shift register designed for LED panel displays. The device features a 16bit serial-in, parallel-out shift register that feeds a 16-bit D-type storage register. In the output stage, sixteen regulated current sources are designed to provide 3 to 40 mA of constant current to drive the LEDs. The STP16CPPS05 output current can be adjusted through an external resistor to control the light intensity of the LEDs. LED brightness is Features adjustable from 0% to 100% via the OE pin.    The auto power-shutdown and auto power-ON feature allows the device to save power with no external intervention.        Low voltage power supply down to 3 V 16 constant current output channels Adjustable output current through external resistor Serial data IN/parallel data OUT Auto power-saving 3.3 V MCU-driving capability Output current: 3 to 40 mA 30 MHz clock frequency Available in high thermal efficiency TSSOP exposed pad ESD protection: 2 kV HBM, 200 V MM The STP16CPPS05 guarantees a 20 V output driving capability, allowing users to connect more LEDs in series. The high 30 MHz clock frequency makes the device suitable for high data rate transmission. The 3.3 V supply is well suited for applications which interface a 3.3 V MCU. Compared to a standard TSSOP package, the TSSOP with exposed pad increases heat dissipation capability by a factor of 2.5. Table 1: Device summary Order code Package Packing STP16CPPS05MTR SO-24 1000 parts per reel STP16CPPS05TTR TSSOP24 2500 parts per reel STP16CPPS05XTTR TSSOP24 exposed pad 2500 parts per reel STP16CPPS05PTR QSOP-24 2500 parts per reel March 2017 DocID16536 Rev 4 This is information on a product in full production. 1/31 www.st.com Contents STP16CPPS05 Contents 1 Summary description ...................................................................... 3 1.1 2 Pin connection and description ......................................................... 3 Electrical ratings ............................................................................. 4 2.1 Absolute maximum ratings ................................................................ 4 2.2 Thermal data ..................................................................................... 4 2.3 Recommended operating conditions ................................................. 5 3 Electrical characteristics ................................................................ 6 4 Equivalent circuit and outputs ....................................................... 8 5 Timing diagrams ............................................................................ 11 6 Typical characteristics .................................................................. 14 7 Auto power-saving ........................................................................ 18 8 Package information ..................................................................... 20 8.1 QSOP-24 package information ....................................................... 21 8.2 SO-24 package information ............................................................ 23 8.3 TSSOP24 package information ....................................................... 24 8.4 TSSOP24 exposed pad package information ................................. 26 8.5 TSSOP24, TSSOP24 exposed pad and ............................................ SO-24 packing information .............................................................. 28 9 2/31 Revision history ............................................................................ 30 DocID16536 Rev 4 STP16CPPS05 1 Summary description Summary description Table 2: Typical current accuracy Current accuracy Output voltage Between bits Between ICs ± 1% ± 2% ≥ 1.3 V 1.1 Output current VDD Temperature 5 to 40 mA 3.3 V to 5 V 25 °C Pin connection and description Figure 1: Pin connection The exposed pad should be electrically connected to a metal land electrically isolated or connected to ground. Table 3: Pin description Pin n° Symbol Name and function 1 GND Ground terminal 2 SDI Serial data input terminal 3 CLK Clock input terminal 4 LE 5-20 OUT 0-15 21 OE Input terminal of output enable (active low) - detect mode 1 (see operation principle) 22 SDO Serial data out terminal 23 R-EXT 24 VDD Latch input terminal - detect mode 1 (see operation principle) Output terminal Input terminal for an external resistor for constant current programming Supply voltage terminal DocID16536 Rev 4 3/31 Electrical ratings STP16CPPS05 2 Electrical ratings 2.1 Absolute maximum ratings Stressing the device above the ratings listed in the “absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other condition above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 4: Absolute maximum ratings Symbol Parameter Value Unit VDD Supply voltage 0 to 7 V VO Output voltage -0.5 to 20 V IO Output current 50 mA VI Input voltage -0.4 to VDD V 800 mA 50 MHz -40 to +170 °C Value Unit Operating free-air temperature range -40 to +125 °C Operating thermal junction temperature range -40 to +150 °C Storage temperature range -55 to +150 °C IGND GND terminal current fCLK Clock frequency TJ Junction temperature range (1) Notes: (1) 2.2 Such absolute value is based on the thermal shutdown protection. Thermal data Table 5: Thermal data Symbol TA TJ-OPR TSTG RthJA Parameter Thermal resistance junction-ambient (1) SO-24 42.7 °C/W TSSOP24 55 °C/W TSSOP24 (2) exposed pad 37.5 °C/W QSOP-24 55 °C/W Notes: 4/31 (1) According with JEDEC standard 51-7B. (2) The exposed pad should be soldered directly to the PCB to realize the thermal benefits. DocID16536 Rev 4 STP16CPPS05 2.3 Electrical ratings Recommended operating conditions Table 6: Recommended operating conditions Symbol Parameter Test conditions Min. 3.0 Typ. Max. Unit 5.5 V 20 V 40 mA VDD Supply voltage VO Output voltage IO Output current OUTn IOH Output current SERIAL-OUT +1 mA IOL Output current SERIAL-OUT -1 mA VIH Input voltage 0.7 VDD VDD V VIL Input voltage -0.3 0.3 VDD V 3 twLAT LE pulse width 20 ns twCLK CLK pulse width 10 ns 100 ns twEN OE pulse width VDD = 3.0 V to 5.0 V tSETUP(D) Setup time for DATA 8 ns tHOLD(D) Hold time for DATA 5 ns tSETUP(L) Setup time for LATCH 8 ns fCLK Clock frequency Cascade operation (1) 30 MHz Notes: (1) If the device is connected in cascade, it may not be possible achieve the maximum data transfer. Please consider the timings carefully. DocID16536 Rev 4 5/31 Electrical characteristics 3 STP16CPPS05 Electrical characteristics VDD = 3.3 V to 5 V, TA = 25 °C, unless otherwise specified. Table 7: Electrical characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit VIH Input voltage high level 0.7 VDD VDD V VIL Input voltage low level GND 0.3 VDD V IOH Output leakage current VOH = 20 V 1 μA VOL Output voltage (serial-OUT) IOL = 1 mA 0.4 V VOH Output voltage (serial-OUT) IOH = -1 mA IOL1 IOL2 Output current IOL3 ΔIOL1 ΔIOL2 Output current error between bit (all output ON) ΔIOL3 VDD-0.4V V VO = 0.3 V, Rext = 4 kΩ 4.75 5 5.25 VO = 0.3 V, Rext = 1 kΩ 19 20 20 VO = 1.3 V, Rext = 497 Ω 38 40 42 VO = 0.3 V, IO = 5 mA, Rext = 4 kΩ ±1 ±5 VO = 0.3 V, IO = 20 mA, Rext = 980 Ω ± 0.5 ±3 VO = 1.3 V, IO = 40 mA, Rext = 490 Ω ± 0.5 ±3 mA % Pull-up resistor 150 300 600 kΩ Pull-down resistor 100 200 400 kΩ REXT = 1 kΩ, IOUT = 20 mA, OUT 0 to 15 = OFF 5.4 7.5 IDD(OFF2) REXT = 497 Ω, IOUT = 40 mA OUT 0 to 15 = OFF 8.0 9.5 IDD(ON1) REXT = 1 kΩ, IOUT = 20 mA, OUT 0 to 15 = ON 5.5 7.5 REXT = 497 Ω, IOUT = 40 mA OUT 0 to 15 = ON 8.1 9.5 VDD = 3.3 V 160 200 VDD = 5 V 190 240 RSIN(up) RSIN(down) IDD(OFF1) Supply current (OFF) Supply current (ON) IDD(ON2) IDD(SH) Thermal 6/31 Shut-down current all latched data = L Thermal protection mA 170 DocID16536 Rev 4 μA °C STP16CPPS05 VDD = 3.3 V to 5 V, TA = 25 °C, unless otherwise specified. Electrical characteristics Table 8: Switching characteristics Symbol Parameter Test conditions Min. Typ. Max. VDD = 3.3 V - 53.5 86.5 VDD = 5 V - 32 46.5 VDD = 3.3 V - 48 75.5 VDD = 5 V - 30 43 VDD = 3.3 V - 71.5 118 VDD = 5 V - 43 62 VDD = 3.3 V 15 21 31 VDD = 5 V 11 15 21 VDD = 3.3 V - 27.5 39 VDD = 5 V - 22 30.5 Propagation delay time, VDD = 3.3 V - 11.5 17.5 LE- OUTn , OE = L VDD = 5 V - 8 11.5 Propagation delay time, VDD = 3.3 V - 24 33.5 VDD = 5 V - 21 28.5 Propagation delay time, tPLH1 CLK- OUTn , LE = H, OE = L Propagation delay time, tPLH2 LE- OUTn , Unit ns ns OE = L Propagation delay time, tPLH3 tPLH OE - OUTn , LE = H Propagation delay time, CLK-SDO Propagation delay time, tPHL1 CLK- OUTn , LE = H, OE = L tPHL2 tPHL3 VIH = VDD VIL = GND CL = 10 pF IO = 20 mA VL = 3.0 V Rext = 1 KΩ RL = 60 Ω ns ns ns ns ns OE - OUTn , LE = H tPHL Propagation delay time, CLK-SDO VDD = 3.3 V 17.5 24 36 VDD = 5 V 12.5 17 25 Output rise time 10~90% of voltage waveform VDD = 3.3 V - 29 54 tON VDD = 5 V - 10 17 Output fall time 90~10% of voltage waveform VDD = 3.3 V - 4.5 6 tOFF VDD = 5 V - 3.5 5 ns ns ns tr CLK rise time (1) - 5000 ns tf CLK fall time (1) - 5000 ns Notes: (1) In order to achieve high cascade data transfer, please consider tr/tf timings carefully. DocID16536 Rev 4 7/31 Equivalent circuit and outputs 4 STP16CPPS05 Equivalent circuit and outputs Figure 2: OE terminal Figure 3: LE terminal 8/31 DocID16536 Rev 4 STP16CPPS05 Equivalent circuit and outputs Figure 4: CLK, SDI terminal Figure 5: SDO terminal DocID16536 Rev 4 9/31 Equivalent circuit and outputs STP16CPPS05 Figure 6: Block diagram 10/31 DocID16536 Rev 4 STP16CPPS05 5 Timing diagrams Timing diagrams Table 9: Truth table CLOCK LE OE SERIAL-IN OUT0 ............. OUT7 ................ OUT15 SDO _|¯ H L Dn Dn ..... Dn - 7 ..... Dn -15 Dn - 15 _|¯ L L Dn + 1 No change Dn - 14 _|¯ H L Dn + 2 Dn + 2 ..... Dn - 5 ..... Dn -13 Dn - 13 ¯|_ X L Dn + 3 Dn + 2 ..... Dn - 5 ..... Dn -13 Dn - 13 ¯|_ X H Dn + 3 OFF Dn - 13 OUTn = ON when Dn = H OUTn = OFF when Dn = L. Figure 7: Timing diagram 1 Latch and output enable terminals are level-sensitive and are not synchronized with rising or falling edge of CLK signal. 2 When LE terminal is low level, the latch circuit holds previous set of data. 3 When LE terminal is high level, the latch circuit refreshes new set of data from SDI chain. 4 When OE terminal is at low level, the output terminals Out 0 to Out 15 respond to data in the latch circuits, either ‘1’ for ON or ‘0’ for OFF. 5 When OE terminal is at high level, all output terminals are switched OFF. DocID16536 Rev 4 11/31 Timing diagrams STP16CPPS05 Table 10: Enable IO: shutdown truth table CLOCK LE SDI0 ........... SDI7 ............ SDI15 SH Not active (1) OUTn _|¯ H All = L Active _|¯ L No change No change No change No change _|¯ H One or more = H Not active Active X (2) Notes: (1) At power-up, the device starts in shutdown mode. (2) Undefined. Figure 8: Clock, serial-in, serial-out 12/31 Auto power-up DocID16536 Rev 4 OFF STP16CPPS05 Timing diagrams Figure 9: Clock, serial-in, latch, enable, outputs Figure 10: Outputs DocID16536 Rev 4 13/31 Typical characteristics 6 STP16CPPS05 Typical characteristics Figure 11: Output current vs. R-EXT resistor Table 11: Output current vs. R-EXT resistor 14/31 R-EXT (Ω) Output current (mA) 23700 1 11730 2 6930 3 4090 5 2025 10 1000 20 667 30 497 40 331 60 DocID16536 Rev 4 STP16CPPS05 Conditions: Typical characteristics Temperature = 25 °C, VDD = 3.3 V; 5.0 V, ISET = 3 mA; 5 mA; 10 mA; 20 mA; 50 mA; 60 mA. Figure 12: ISET vs drop out voltage (Vdrop) Table 12: ISET vs drop out voltage (Vdrop) Iout (mA) Avg (mV) @ 3.3 V Avg (mV) @ 5.0 V 3 36 37 5 71 72 10 163 163 20 346 347 40 724 724 60 1080 1110 DocID16536 Rev 4 15/31 Typical characteristics TA = 25 °C, Vdd = 3.3 V; 5 V STP16CPPS05 Figure 13: Output current vs. ± ΔIOL(%) Figure 14: Idd ON/OFF 16/31 DocID16536 Rev 4 STP16CPPS05 Typical characteristics Figure 15: Power dissipation vs. package temperature The exposed pad should be soldered to the PCB to obtain the thermal benefits. Figure 16: Turn ON output current characteristics(1) Figure 17: Turn OFF output current characteristics(2) Notes: (1) The reference level for the TON characteristics is 50% of OE (2)The reference level for the TOFF characteristics is 50% of OE signal and 90% of output current. signal and 10% of output current. Electrical conditions: Vdd = 3.3 V, Vin = Vdd, Vled = 3.0 V, RL = 60 Ω, CL = 10 pF Ch1 (Yellow) = OE , Ch2 (Blue) = CLK, Ch3 (Purple) = VOUT, Ch4 (Green) = OUT DocID16536 Rev 4 17/31 Auto power-saving 7 STP16CPPS05 Auto power-saving The auto power-saving feature minimizes the quiescent current if no active data is detected on the latches and auto powers-up the device as the first active data is latched. Figure 18: Auto power-saving feature Electrical conditions: Temp. = 25 °C, Vdd = 3.3 V, Vin = Vdd, Vled = 3.0 V, RL = 60 Ω, CL = 10 pF Ch1 (Yellow) = OE , Ch2 (Blue) = CLK, Ch3 (Purple) = LE, Ch4 (Green) = idd Idd consumption: Idd (normal operation) = 4.2 mA Idd (shut down condition) = 190 μA 18/31 DocID16536 Rev 4 STP16CPPS05 Auto power-saving Figure 19: First output ON after switching from auto power saving to normal operating condition Electrical conditions: temp. = 25 °C, Vdd = 3.3 V, Vin = Vdd, Vled = 3.0 V, Iset = 20 mA Ch1 (Yellow) = SDI, Ch2 (Blue) = CLK, Ch3 (Purple) = LE, Ch4 (Green) = first output ON When the device goes from AUTO power saving to normal operative condition, the first output that switch ON shows TON condition as seen in the plot above. DocID16536 Rev 4 19/31 Package information 8 STP16CPPS05 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 20/31 DocID16536 Rev 4 STP16CPPS05 8.1 Package information QSOP-24 package information Figure 20: QSOP-24 package outline DocID16536 Rev 4 21/31 Package information STP16CPPS05 Table 13: QSOP-24 mechanical data mm Dim. Min. Typ. Max. A 1.54 1.62 1.73 A1 0.10 0.15 0.25 A2 1.47 b 0.20 0.31 c 0.17 0.254 D 8.56 8.66 8.76 E 5.80 6.00 6.20 E1 3.80 3.91 4.01 e 22/31 0.635 L 0.40 0.635 0.89 h 0.25 0.33 0.41 < 0° DocID16536 Rev 4 8° STP16CPPS05 8.2 Package information SO-24 package information Figure 21: SO-24 package outline DocID16536 Rev 4 23/31 Package information STP16CPPS05 Table 14: SO-24 mechanical data mm Dim. Min. Typ. A 2.35 2.65 A1 0.10 0.30 B 0.33 0.51 C 0.23 0.32 D 15.20 15.60 E 7.40 e 7.60 1.27 H 10.00 10.65 h 0.25 0.75 L 0.40 1.27 k 0 8 ddd 8.3 0.10 TSSOP24 package information Figure 22: TSSOP24 package outline 24/31 Max. DocID16536 Rev 4 STP16CPPS05 Package information Table 15: TSSOP24 mechanical data mm Dim. Min. Typ. A A1 Max. 1.1 0.05 A2 0.15 0.9 b 0.19 0.30 c 0.09 0.20 D 7.7 7.9 E 4.3 4.5 e 0.65 BSC H 6.25 6.5 K 0° 8° L 0.50 0.70 DocID16536 Rev 4 25/31 Package information 8.4 STP16CPPS05 TSSOP24 exposed pad package information Figure 23: TSSOP24 exposed pad package outline 26/31 DocID16536 Rev 4 STP16CPPS05 Package information Table 16: TSSOP24 exposed pad mechanical data mm Dim. Min. Typ. Max. A 1.20 A1 0.15 A2 0.80 1.00 1.05 b 0.19 0.30 c 0.09 0.20 D 7.70 7.80 7.90 D1 4.80 5.00 5.2 E 6.20 6.40 6.60 E1 4.30 4.40 4.50 E2 3.00 3.20 3.40 e L 0.65 0.45 L1 k 060 075 1.00 0° aaa 8° 0.10 DocID16536 Rev 4 27/31 Package information 8.5 STP16CPPS05 TSSOP24, TSSOP24 exposed pad and SO-24 packing information Figure 24: TSSOP24, TSSOP24 exposed pad and SO-24 reel outline Table 17: TSSOP24 and TSSOP24 exposed pad tape and reel mechanical data mm Dim. Min. A Max. - 330 13.2 C 12.8 - D 20.2 - N 60 - T 28/31 Typ. - 22.4 Ao 6.8 - 7 Bo 8.2 - 8.4 Ko 1.7 - 1.9 Po 3.9 - 4.1 P 11.9 - 12.1 DocID16536 Rev 4 STP16CPPS05 Package information Table 18: SO-24 tape and reel mechanical data mm Dim. Min. A Typ. Max. - 330 13.2 C 12.8 - D 20.2 - N 60 - T - 30.4 Ao 10.8 - 11.0 Bo 15.7 - 15.9 Ko 2.9 - 3.1 Po 3.9 - 4.1 P 11.9 - 12.1 DocID16536 Rev 4 29/31 Revision history 9 STP16CPPS05 Revision history Table 19: Document revision history 30/31 Date Revision Changes 23-Oct-2009 1 First release. 16-Jun-2014 2 Updated Section 7: Package mechanical data. Added Section 8: Packaging mechanical data. Minor text changes. 08-Apr-2016 3 Updated Section 8.1: "QSOP-24 package information". Minor text changes. 09-Mar-2017 4 Updated Figure 5: "SDO terminal", Figure 8: "Clock, serial-in, serial-out" and Figure 9: "Clock, serial-in, latch, enable, outputs". Minor text changes. DocID16536 Rev 4 STP16CPPS05 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2017 STMicroelectronics – All rights reserved DocID16536 Rev 4 31/31