STS15N4LLF5
N-channel 40 V, 0.00625 Ω, 15 A, SO-8
STripFET™ Power MOSFET
Features
Type
VDSS
RDS(on) max.
ID
STS15N4LLF5
40 V
< 0.0076 Ω
15 A
■
Optimal RDS(on)x Qg trade-off @ 4.5 V
■
Conduction losses reduced
■
Switching losses reduced
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SO-8
Applications
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Switching application
Description
This STripFET™V Power MOSFET technology is
among the latest improvements, which have been
especially tailored to achieve very low on-state
resistance providing also one of the best-in-class
figure of merit (FOM).
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Figure 1.
Internal schematic diagram
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Table 1.
Device summary
Order code
Marking
Package
Packaging
STS15N4LLF5
15C4L
SO-8
Tape and reel
April 2010
Doc ID 17339 Rev 1
1/12
www.st.com
12
Contents
STS15N4LLF5
Contents
1
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
............................. 6
3
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
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Doc ID 17339 Rev 1
STS15N4LLF5
1
Electrical ratings
Electrical ratings
Table 2.
Absolute maximim ratings
Symbol
Parameter
Unit
40
V
VDS
Drain-source voltage (VGS = 0)
VGS
Gate-source voltage
± 16
V
Gate- source voltage
±18
V
ID
Drain current (continuous) at TC = 25 °C
15
A
ID
Drain current (continuous) at TC = 100 °C
10
(1)
VGS
IDM
(2)
Drain current (pulsed)
PTOT
Total dissipation at TC = 25 °C
3
EAS (3)
Single pulse avalanche energy
1090
P
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Thermal resistance
Symbol
Rthj-pcb(1)
Tl
Tstg
Parameter
A
W
mJ
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3. Starting Tj = 25 °C, ID = 7.5 A, VDD = 25 V
Table 3.
ct
du
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2. Pulse width limited by Tjmax
(s)
A
63.6
1. Guaranteed for test time < 15ms
1.
Value
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Value
Unit
47
°C/W
Maximum lead temperature for soldering
-55 to 150
°C
Storage temperature
-55 to 150
°C
)-
Thermal resistance junction-pcb max
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When mounted of FR-4 board with 1 inch pad, 2oz of Cu and t < 10 sec
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Electrical characteristics
2
STS15N4LLF5
Electrical characteristics
(TJ = 25 °C unless otherwise specified)
Table 4.
On/off states
Symbol
Parameter
Drain-source breakdown
voltage
ID = 250 µA, VGS= 0
IDSS
Zero gate voltage drain
current (VGS = 0)
VDS = max rating,
VDS =max rating @125°C
IGSS
Gate body leakage
Current (VDS = 0)
VGS = ±16 V
VGS(th)
Gate threshold voltage
VDS= VGS, ID = 250 µA
RDS(on)
Static drain-source on
resistance
VGS= 10 V, ID= 7.5 A
VGS= 4.5 V, ID= 7.5 A
V(BR)DSS
Table 5.
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Test conditions
Typ.
Max.
40
Unit
V
10
100
µA
µA
±200
nA
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Pr
V
0.00625 0.0067
0.0076 0.0083
Ω
Ω
Min.
Typ.
Max.
Unit
VDS = 25 V, f=1 MHz,
VGS= 0
-
1570
257
32
-
pF
pF
pF
Input capacitance
Output capacitance
Reverse transfer
capacitance
Qg
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain charge
VDD = 15 V, ID = 18 A
VGS = 4.5 V
(see Figure 14)
-
12.9
3.9
5.3
-
nC
nC
nC
Gate input resistance
f=1 MHz Gate DC Bias = 0
Test signal level = 20 mV
open drain
-
1.5
-
Ω
Test conditions
Min.
Typ.
Max.
Unit
-
14
42
-
ns
ns
-
37
5.2
-
ns
ns
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4/12
Parameter
Min.
Ciss
Coss
Crss
RG
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Dynamic
Symbol
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Test conditions
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Table 6.
Symbol
Switching times
Parameter
td(on)
tr
Turn-on delay time
Rise time
td(off)
tf
Turn-off delay time
Fall time
VDD = 15 V, ID = 9 A,
RG = 4.7 Ω, VGS = 10 V
(see Figure 16)
Doc ID 17339 Rev 1
STS15N4LLF5
Electrical characteristics
Table 7.
Source drain diode
Symbol
Parameter
ISD
ISDM(1)
Source-drain current
Source-drain current (pulsed)
VSD (2)
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
trr
Qrr
IRRM
Test conditions
Min. Typ.
Max.
Unit
-
18
72
A
A
ISD = 18 A, VGS = 0
-
1.2
V
ISD = 18 A, VDD = 25 V,
di/dt = 100 A/µs,
Tj = 150 °C
(see Figure 15)
-
27.2
24.5
1.8
ns
nC
A
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ct
1. Pulse width limited by safe operating area
2. Pulsed: pulse duration = 300µs, duty cycle 1.5%
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Electrical characteristics
STS15N4LLF5
2.1
Electrical characteristics (curves)
Figure 2.
Safe operating area
Thermal impedance
!-V
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Figure 3.
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Figure 4.
Output characterisics
Figure 5.
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Normalized BVDSS vs temperature
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Figure 6.
!-V
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Transfer characteristics
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Figure 7.
6'36
Static drain-source on resistance
!-V
2$3ON
M/HM
6'3 6
6/12
4* #
Doc ID 17339 Rev 1
)$!
STS15N4LLF5
Figure 8.
Electrical characteristics
Gate charge vs gate-source voltage Figure 9.
Capacitance variations
v
!-V
6'3
6
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Figure 10. Normalized gate threshold voltage
vs temperature
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Figure 11. Normalized on resistance vs
temperature
!-V
6'3TH
NORM
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2$3ON
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Figure 12. Source-drain diode forward
characteristics
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4* #
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Doc ID 17339 Rev 1
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Test circuits
3
STS15N4LLF5
Test circuits
Figure 13. Switching times test circuit for
resistive load
Figure 14. Gate charge test circuit
VDD
12V
47kΩ
1kΩ
100nF
3.3
µF
2200
RL
µF
IG=CONST
VDD
VGS
100Ω
Vi=20V=VGMAX
VD
RG
2200
µF
D.U.T.
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2.7kΩ
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47kΩ
1kΩ
PW
D.U.T.
AM01468v1
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AM01469v1
Figure 15. Test circuit for inductive load
Figure 16. Unclamped inductive load test
switching and diode recovery times
circuit
A
A
D.U.T.
FAST
DIODE
B
B
A
D
G
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3.3
µF
B
25 Ω
D
1000
µF
RG
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2200
µF
3.3
µF
VDD
ID
Vi
D.U.T.
Pw
let
AM01470v1
Figure 17. Unclamped inductive waveform
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VD
VDD
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so
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L=100µH
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AM01471v1
Figure 18. Switching time waveform
ton
V(BR)DSS
tdon
VD
toff
tr
tdoff
tf
90%
90%
IDM
10%
ID
VDD
10%
0
VDD
VDS
90%
VGS
AM01472v1
8/12
0
Doc ID 17339 Rev 1
10%
AM01473v1
STS15N4LLF5
4
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com. ECOPACK
is an ST trademark.
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Package mechanical data
STS15N4LLF5
Table 1. SO-8 mechanical data
mm.
Dim.
Min
Typ
inch
Max
Min
Typ
Max
A
1.35
1.75
0.053
0.069
A1
0.10
0.25
0.004
0.010
A2
1.10
1.65
0.043
0.065
B
0.33
0.51
0.013
0.020
C
0.19
0.25
0.007
0.010
D (1)
4.80
5.00
0.189
E
3.80
4.00
0.15
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1.27
0.050
H
5.80
6.20
0.228
h
0.25
0.50
0.010
L
0.40
1.27
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0.197
0.157
0.244
0.020
0.050
0° (min.), 8° (max.)
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0.10
0.004
1. Dimensions D does not include mold flash, protru-sions or gate burrs. Mold flash, potrusions or gate burrs
shall not exceed 0.15mm (.006inch) in total (both side).
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Figure 19. Package dimensions
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5
Revision history
Revision history
Table 8.
Revision history
Date
Revision
07-Apr-2010
1
Changes
First release
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STS15N4LLF5
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Please Read Carefully:
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