TDA7438
THREE BANDS
DIGITALLY CONTROLLED AUDIO PROCESSOR
1
■
FEATURES
Figure 1. Package
INPUT MULTIPLEXER
– 3 STEREO INPUTS
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2 DESCRIPTION
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– SELECTABLE INPUT GAIN FOR OPTIMAL
ADAPTATION TO DIFFERENT SOURCES
■
ONE STEREO OUTPUT
■
TREBLE, MIDDLE AND BASS CONTROL IN
2.0dB STEPS
■
■
SO28
Table 1. Order Codes
Package
TDA7438
DIP28
TDA7438D
SO28
TDA7438D013TR
Tape & Reel
TWO SPEAKER ATTENUATORS:
– TWO INDEPENDENT SPEAKER CONTROL
IN 1.0dB STEPS FOR BALANCE FACILITY
■
Part Number
VOLUME CONTROL IN 1.0dB STEPS
– -INDEPENDENT MUTE FUNCTION
ALL FUNCTION ARE PROGRAMMABLE VIA
SERIAL BUS
The TDA7438 is a volume tone (bass, middle and
treble) balance (Left/Right) processor for quality
audio applications in car-radio and Hi-Fi systems.
DIP28
Selectable input gain is provided. Control of all the
functions is accomplished by serial bus.
The AC signal setting is obtained by resistor networks and switches combined with operational
amplifiers.
Thanks to the used BIPOLAR/CMOS Technology,
Low Distortion, Low Noise and DC stepping are
obtained.
Figure 2. Block Diagram
MUXOUTL
L-IN1
3
TREBLE(L)
INL
6
7
18
17
100K
L-IN2
MIN(L) MOUT(L) BIN(L)
16
BOUT(L)
14
RM
15
RB
4
100K
L-IN3
VOLUME
G
5
TREBLE
MIDDLE
SPKR ATT
LEFT
BASS
27
LOUT
100K
R-IN1
21
0/30dB
2dB STEP
2
I2CBUS DECODER + LATCHES
22
20
100K
R-IN2
SDA
DIG_GND
1
100K
R-IN3
SCL
VOLUME
G
TREBLE
MIDDLE
SPKR ATT
RIGHT
BASS
26
ROUT
28
VREF
100K
24
SUPPLY
INPUT MULTIPLEXER
+ GAIN
RM
8
MUXOUTR
June 2004
9
INR
19
TREBLE(R)
10
RB
11
12
MIN(R) MOUT(R) BIN(R)
13
25
VS
AGND
23
BOUT(R) CREF
D96AU488A
REV. 7
1/19
TDA7438
Table 2. Absolute Maximum Ratings
Symbol
VS
Tamb
Tstg
Parameter
Value
Unit
10.5
V
0 to 70
°C
-55 to 150
°C
Operating Supply Voltage
Operating Ambient Temperature
Storage Temperature Range
Figure 3. Pin Connection
R_IN2
1
28
R_IN3
R_IN1
2
27
LOUT
L_IN1
3
26
ROUT
L_IN2
4
25
AGND
L_IN3
5
24
VS
MUXOUTL
6
23
CREF
INL
7
22
SDA
MUXOUTR
8
21
SCL
INR
9
20
DIG-GND
MIN(R)
10
19
TREBLE(R)
MOUT(R)
11
18
TREBLE(L)
BIN(R)
12
17
MIN(L)
BOUT(R)
13
16
MOUT(L)
BIN(L)
14
15
BOUT(L)
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D96AU489A
Table 3. Thermal Data
Symbol
Rth j-pins
Parameter
Thermal Resistance Junction-pins
Value
Unit
85
°C/W
Max.
Table 4. Quick Reference Data
Symbol
Parameter
Min.
Typ.
Max.
9
10.2
Unit
VS
Supply Voltage
6
VCL
Max. input signal handling
2
THD
Total Harmonic Distortion V = 1Vrms f = 1KHz
0.01
S/N
Signal to Noise Ratio Vout = 1Vrms (mode = OFF)
106
dB
SC
Channel Separation f = 1KHz
90
dB
Input Gain in (2db step)
0.1
%
0
30
dB
Volume Control (1db step)
-47
0
dB
Treble Control (2db step)
-14
+14
dB
Middle Control (2db step)
-14
+14
dB
Bass Control (2dB step)
-14
+14
dB
Balance Control 1dB step
-79
0
dB
Mute Attenuation (*)
80
100
(*) Even applied to Speaker Attenuator Left, Speaker Attenuator Right, Volume Control stand alone or to the combination, if any.
2/19
V
Vrms
dB
TDA7438
Table 5. Electrical Characteristcs: (refer to the test circuit Tamb = 25°C, VS = 9V, RL= 10KΩ,
RG = 600Ω, all controls flat (G = 0dB), unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
6
9
10.2
V
SUPPLY
VS
Supply Voltage
IS
Supply Current
SVR
Ripple Rejection
60
7
mA
90
dB
100
KΩ
INPUT STAGE
RIN
Input Resistance
VCL
Clipping Level
THD = 0.3%
2
2.5
SIN
Input Separation
The selected input is grounded
through a 2.2µ capacitor
80
100
-1
0
Ginmin
Minimum Input Gain
Ginman
Maximum Input Gain
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Gstep
Step Resolution
2
VOLUME CONTROL
Input Resistance
20
33
Control Range
45
AVMAX
Max. Attenuation
ASTEP
Step Resolution
Ri
CRANGE
EA
ET
VDC
A
mute
Attenuation Set Error
Tracking Error
DC Step
dB
dB
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t(
dB
dB
50
KΩ
47
49
dB
45
47
49
dB
0.5
1
1.5
dB
AV = 0 to -24dB
-1.0
0
1.0
dB
AV = -24 to -47dB
-1.5
0
1.5
dB
AV = 0 to -24dB
0
1
dB
AV = -24 to -47dB
0
2
dB
0
0.5
3
mV
mV
adjacent attenuation steps from
0dB to AV max
Mute Attenuation
80
100
dB
BASS CONTROL (The center frequency and the response quality can be chosen by the ext. circuitry)
Gb
Control Range
BSTEP
RB
Max. Boost/cut
+12.0
+14.0
+16.0
dB
Step Resolution
1
2
3
dB
Internal Feedback Resistance
33
44
55
KΩ
TREBLE CONTROL (The center frequency and the response quality can be chosen by the ext. circuitry)
Gt
Control Range
TSTEP
Step Resolution
Max. Boost/cut
+13.0
+14.0
+15.0
dB
1
2
3
dB
MIDDLE CONTROL (The center frequency and the response quality can be chosen by the ext. circuitry)
Gm
Control Range
MSTEP
Step Resolution
RM
Internal Feedback Resistance
Max. Boost/cut
+12.0
+14.0
+16.0
dB
1
2
3
dB
18.75
25
31.25
KΩ
3/19
TDA7438
Table 5 (continued)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
SPEAKER ATTENUATORS
CRANGE Control Range
SSTEP
EA
76
Step Resolution
Attenuation Set Error
AV = 0 to -20dB
AV = -20 to -56dB
ET
Tracking Error
dB
0.5
1
1.5
dB
-1.5
0
1.5
dB
-2
0
2
dB
0
1
dB
AV = 0 to -24dB
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VDC
Amute
DC Step
AV = -24 to -47dB
0
2
dB
adjacent attenuation steps
0
3
mV
Mute Attenuation
80
100
dB
2.1
2.6
VRMS
AUDIO OUTPUTS
VCLIP
Clipping Level
d = 0.3%
RL
Output Load Resistance
2
RO
Output Impedance
10
VDC
DC Voltage Level
KΩ
40
70
3.8
W
V
GENERAL (Gain, Bass, Treble, Middle Controls Flat)
ENO
Et
Output Noise
All gains = 0dB;
BW = 20Hz to 20KHz flat
5
15
µV
Total Tracking Error
(Volume + Speaker Attenuator)
AV = 0 to -24dB
0
1
dB
AV= -24 to -47dB
0
2
dB
AV = -47 to -79dB
0
3
dB
S/N
Signal to Noise Ratio
SC
Channel Separation Left/Right
d
Distortion
All gains 0dB; VO = 1VRMS ;
90
106
dB
80
100
dB
AV = 0; VI = 1VRMS ;
0.01
0.08
%
1
V
BUS INPUT
VIL
Input Low Voltage
VIH
Input High Voltage
IIN
Input Current
4/19
3
VIN = 0.4V
-5
V
5
µA
TDA7438
Figure 4. Test Circuit
2.7K
5.6nF
MUXOUTL
3
MOUT(L)
18
17
16
100nF
BIN(L)
BOUT(L)
14
15
RM
RB
4
0.47µF
L-IN3
TREBLE(L)
7
22nF 100nF
100K
0.47µF
L-IN2
INL
6
MIN(L)
2.2µF
L-IN1
5.6K
18nF
100K
G
5
0.47µF
VOLUME
TREBLE
MIDDLE
SPKR ATT
LEFT
BASS
27
LOUT
100K
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3 APPLICATION SUGGESTIONS
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R-IN1
0.47µF
22
20
SCL
SDA
DIGGND
1
100K
0.47µF
R-IN3
2
I CBUS DECODER + LATCHES
100K
0.47µF
R-IN2
21
0/30dB
2dB STEP
2
VOLUME
G
TREBLE
MIDDLE
SPKR ATT
RIGHT
BASS
26
ROUT
28
VREF
100K
24
INPUT MULTIPLEXER
+ GAIN
RM
SUPPLY
RB
25
VS
AGND
MUXOUTR
9
INR
19
TREBLE(R)
10
2.2µF
11
MOUT(R)
MIN(R)
8
18nF
5.6nF
12
13
BIN(R)
BOUT(R)
22nF 100nF
2.7K
5.6K
100nF
23
CREF
10µF
D96AU490A
The first and the last stages are volume control blocks. The control range is 0 to -47dB (mute) for the first
one, 0 to -79dB (mute) for the last one.
Both of them have 1dB step resolution. The very high resolution allows the implementation of systems free
from any noisy acoustical effect. The TDA7438 audioprocessor provides 3 bands tones control.
3.1 Bass, Middle Stages
The Bass and the middle cells have the same structure.
The Bass cell has an internal resistor Ri = 44KΩ typical.
The Middle cell has an internal resistor Ri = 25KΩ typical.
Several filter types can be implemented, connecting external components to the Bass/Middle IN and OUT
pins.
Figure 5.
Ri internal
IN
OUT
C1
C2
R2
D95AU313
5/19
TDA7438
The fig.5 refers to basic T Type Bandpass Filter starting from the filter component values (R1 internal and
R2,C1,C2 external) the centre frequency Fc, the gain Av at max. boost and the filter Q factor are computed
as follows:
1
F c = ----------------------------------------------------------2 ⋅ π ⋅ Ri, R2, C1, C2
R2C2 + R2C1 + RiC1
A V = -----------------------------------------------------------R1C1 + R2C2
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Ri, R2, C1, C2
Q = ------------------------------------------R2C1 + R2C2
Viceversa, once Fc, Av, and Ri internal value are fixed, the external components values will be:
AV – 1
C1 = -----------------------------2 ⋅ π ⋅ Ri ⋅ Q
2
Q ⋅ C1
C2 = -----------------------2
A V – 1Q
2
AV – 1 – Q
R2 = --------------------------------------------------------------------2 ⋅ π ⋅ C1 ⋅ F c ⋅ ( A V – 1 ) ⋅ Q
3.2 Treble Stage
The treble stage is a high pass filter whose time constant is fixed by an internal resistor (25KΩ typical) and
an external capacitor connected between treble pins and ground Typical responses are reported in Figg.
14 to 17.
3.3 CREF
The suggested 10mF reference capacitor (CREF) value can be reduced to 4.7mF if the application requires faster power ON.
Figure 6. THD vs. frequency
6/19
Figure 7. THD vs. RLOAD
TDA7438
Figure 8. Channel separation vs. frequency
Figure 11. Middle response
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Figure 9. Bass response
Figure 12. Typical tone response
Figure 10. Treble response
7/19
TDA7438
4
I2C BUS INTERFACE
Data transmission from microprocessor to the TDA7438 and vice versa takes place through the 2 wires
I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage
must be connected).
4.1 Data Validity
As shown in fig. 12, the data on the SDA line must be stable during the high period of the clock. The HIGH
and LOW state of the data line can only change when the clock signal on the SCL line is LOW.
4.2 Start and Stop Conditions
As shown in fig.13 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The
stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
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4.3 Byte Format
Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge
bit. The MSB is transferred first.
4.4 Acknowledge
The master (mP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig.
14). The peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during this
clock pulse.
The audio processor which has been addressed has to generate an acknowledge after the reception of
each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case
the master transmitter can generate the STOP information in order to abort the transfer.
4.5 Transmission without Acknowledge
Avoiding to detect the acknowledge of the audio processor, the mP can use a simpler transmission: simply
it waits one clock without checking the slave acknowledging, and sends the new data.
This approach of course is less protected from misworking.
Figure 13. Data Validity on the I2CBUS
SDA
SCL
DATA LINE
STABLE, DATA
VALID
CHANGE
DATA
ALLOWED
D99AU1031
Figure 14. Timing Diagram of I2CBUS
SCL
I2CBUS
SDA
START
8/19
D99AU1032
STOP
TDA7438
Figure 15. Acknowledge on the I2CBUS
SCL
1
2
3
7
8
9
SDA
MSB
START
5
ACKNOWLEDGMENT
FROM RECEIVER
D99AU1033
SOFTWARE SPECIFICATION
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Interface Protocol
The interface protocol comprises:
■
A start condition (S)
■
A chip address byte, containing the TDA7438 address
■
A subaddress bytes
■
A sequence of data (N byte + acknowledge)
Figure 16.
SUBADDRESS
CHIP ADDRESS
MSB
S
1
LSB
0
0
0
1
0
0
0
MSB
ACK
X
DATA 1 to DATA n
LSB
X
X
B
DATA
MSB
ACK
LSB
DATA
ACK
P
D96AU420
ACK = Acknowledge
S = Start
P = Stop
A = Address
B = Auto Increment
5.1 EXAMPLES
5.1.1 No Incremental Bus
The TDA7438 receives a start condition, the correct chip address, a subaddress with the B = 0 (no incremental bus), N-data (all these data concern the subaddress selected), a stop condition.
Figure 17.
SUBADDRESS
CHIP ADDRESS
MSB
S
1
LSB
0
0
0
1
0
0
0
MSB
ACK
X
DATA
LSB
X
X
0 D3 D2 D1 D0 ACK
MSB
LSB
DATA
ACK
P
D96AU421
5.1.2 Incremental Bus
The TDA7438 receive a start conditions, the correct chip address, a subaddress with the B = 1 (incremental bus): now it is in a loop condition with an autoincrease of the subaddress whereas SUBADDRESS from
"XXX1000" to "XXX1111" of DATA are ignored.The DATA 1 concern the subaddress sent, and the DATA
2 concern the subaddress sent plus one in the loop etc, and at the end it receivers the stop condition
9/19
TDA7438
Figure 18. .
CHIP ADDRESS
SUBADDRESS
MSB
S
1
LSB
0
0
0
1
0
0
0
MSB
ACK
DATA 1 to DATA n
LSB
X
X
X
MSB
LSB
1 D3 D2 D1 D0 ACK
DATA
ACK
P
D96AU422
Table 6. POWER ON RESET CONDITION
INPUT SELECTION
IN2
INPUT GAIN
28dB
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6 DATA BYTES
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VOLUME
MUTE
BASS
0dB
MIDDLE
2dB
TREBLE
2dB
SPEAKER
MUTE
Address = 88 HEX (ADDR:OPEN).
Table 7. FUNCTION SELECTION: First byte (subaddress)
MSB
LSB
SUBADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
B
0
0
0
0
INPUT SELECT
X
X
X
B
0
0
0
1
INPUT GAIN
X
X
X
B
0
0
1
0
VOLUME
X
X
X
B
0
0
1
1
BASS
X
X
X
B
0
1
0
0
MIDDLE
X
X
X
B
0
1
0
1
TREBLE
X
X
X
B
0
1
1
0
SPEAKER ATTENUATE "R"
X
X
X
B
0
1
1
1
SPEAKER ATTENUATE "L"
B = 1: INCREMENTAL BUS ACTIVE
B = 0: NO INCREMENTAL BUS
X = DON’T CARE
Figure 19. INPUT SELECTION
MSB
LSB
INPUT MULTIPLEXER
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
0
0
IN3
X
X
X
X
X
X
0
1
NOT ALLOWED
X
X
X
X
X
X
1
0
IN2
X
X
X
X
X
X
1
1
IN1
10/19
TDA7438
Table 8. INPUT GAIN SELECTION
MSB
D7
D6
D5
D4
LSB
INPUT GAIN
D3
D2
D1
D0
2dB STEPS
0
0
0
0
0dB
0
0
0
1
2dB
0
0
1
0
4dB
0
0
1
1
6dB
0
1
0
0
8dB
0
1
0
1
10dB
)
s
(
t
c
u
d
o
)
r
s
(
P
t
c
e
t
u
e
d
l
o
o
r
s
P
b
e
O
t
e
l
)
o
s
(
s
t
b
c
u
O
d
o
)
r
s
P
(
t
c
e
t
u
e
l
d
o
o
r
s
P
b
O
e
t
e
l
o
s
b
O
0
1
1
0
12dB
0
1
1
1
14dB
1
0
0
0
16dB
1
0
0
1
18dB
1
0
1
0
20dB
1
0
1
1
22dB
1
1
0
0
24dB
1
1
0
1
26dB
1
1
1
0
28dB
1
1
1
1
30dB
LSB
VOLUME
D3
D2
D1
D0
1dB STEPS
0
0
0
0dB
0
0
1
-1dB
0
1
0
-2dB
0
1
1
-3dB
1
0
0
-4dB
1
0
1
-5dB
1
1
0
-6dB
1
1
1
-7dB
GAIN = 0 to 30dB
Table 9. VOLUME SELECTION
MSB
D7
D6
D5
D4
0
0
0
0
0dB
0
0
0
1
-8dB
0
0
1
0
-16dB
0
0
1
1
-24dB
0
1
0
0
-32dB
0
1
0
1
-40dB
X
1
1
1
X
X
X
MUTE
VOLUME = 0 to 47dB/MUTE
11/19
TDA7438
Table 10. BASS SELECTION
MSB
D7
D6
D5
D4
LSB
BASS
D3
D2
D1
D0
2dB STEPS
0
0
0
0
-14dB
0
0
0
1
-12dB
0
0
1
0
-10dB
0
0
1
1
-8dB
0
1
0
0
-6dB
0
1
0
1
-4dB
)
s
(
t
c
u
d
o
)
r
s
(
P
t
c
e
t
u
e
d
l
o
o
r
s
P
b
e
O
t
e
l
)
o
s
(
s
t
b
c
u
O
d
o
)
r
s
P
(
t
c
e
t
u
e
l
d
o
o
r
s
P
b
O
e
t
e
l
o
s
b
O
0
1
1
0
-2dB
0
1
1
1
0dB
1
1
1
1
0dB
1
1
1
0
2dB
1
1
0
1
4dB
1
1
0
0
6dB
1
0
1
1
8dB
1
0
1
0
10dB
1
0
0
1
12dB
1
0
0
0
14dB
LSB
MIDDLE
Table 11. MIDDLE SELECTION
MSB
D7
12/19
D6
D5
D4
D3
D2
D1
D0
2dB STEPS
0
0
0
0
-14dB
0
0
0
1
-12dB
0
0
1
0
-10dB
0
0
1
1
-8dB
0
1
0
0
-6dB
0
1
0
1
-4dB
0
1
1
0
-2dB
0
1
1
1
0dB
1
1
1
1
0dB
1
1
1
0
2dB
1
1
0
1
4dB
1
1
0
0
6dB
1
0
1
1
8dB
1
0
1
0
10dB
1
0
0
1
12dB
1
0
0
0
14dB
TDA7438
Table 12. TREBLE SELECTION
MSB
D7
D6
D5
D4
LSB
TREBLE
D3
D2
D1
D0
2dB STEPS
0
0
0
0
-14dB
0
0
0
1
-12dB
0
0
1
0
-10dB
0
0
1
1
-8dB
0
1
0
0
-6dB
0
1
0
1
-4dB
0
1
1
0
-2dB
)
s
(
t
c
u
d
o
)
r
s
(
P
t
c
e
t
u
e
d
l
o
o
r
s
P
b
e
O
t
e
l
)
o
s
(
s
t
b
c
u
O
d
o
)
r
s
P
(
t
c
e
t
u
e
l
d
o
o
r
s
P
b
O
e
t
e
l
o
s
b
O
0
1
1
1
0dB
1
1
1
1
0dB
1
1
1
0
2dB
1
1
0
1
4dB
1
1
0
0
6dB
1
0
1
1
8dB
1
0
1
0
10dB
1
0
0
1
12dB
1
0
0
0
14dB
Table 13. SPEAKER ATTENUATE SELECTION
MSB
D7
D6
D5
D4
D3
LSB
SPEAKER ATTENUATION
D2
D1
D0
1dB
0
0
0
0dB
0
0
1
-1dB
0
1
0
-2dB
0
1
1
-3dB
1
0
0
-4dB
1
0
1
-5dB
1
1
0
-6dB
1
1
1
-7dB
0
0
0
0
0dB
0
0
0
1
-8dB
0
0
1
0
-16dB
0
0
1
1
-24dB
0
1
0
0
-32dB
0
1
0
1
-40dB
0
1
1
0
-48dB
0
1
1
1
-56dB
1
0
0
0
-64dB
1
0
0
1
-72dB
1
1
1
1
X
X
X
MUTE
SPEAKER ATTENUATION = 0 to -79dB/MUTE
13/19
TDA7438
Figure 23. PINS: 6, 8
Figure 20. PINS: 23
VS
VS
VS
VS
20µA
20K
CREF
MUXOUT
20K
GND
)
s
(
t
c
u
d
o
)
r
s
(
P
t
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t
u
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d
l
o
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r
s
P
b
e
O
t
e
l
)
o
s
(
s
t
b
c
u
O
d
o
)
r
s
P
(
t
c
e
t
u
e
l
d
o
o
r
s
P
b
O
e
t
e
l
o
s
b
O
D96AU491
D96AU430
Figure 21. PINS: 26, 27
Figure 24. PINS: 7, 9
VS
VS
20µA
24
ROUT
LOUT
INL
INR
33K
20µA
D96AU427
VREF
D96AU434
Figure 25. PINS: 10, 11
Figure 22. PINS: 1, 2, 3, 4, 5, 28
VS
VS
20µA
20µA
IN
100K
VREF
25K
D96AU425
MOUT(L)
MOUT(R)
14/19
D96AU431
TDA7438
Figure 26. PINS: 10, 17
Figure 29. PINS: 18, 19
VS
VS
20µA
20µA
25K
44K
)
s
(
t
c
u
d
o
)
r
s
(
P
t
c
e
t
u
e
d
l
o
o
r
s
P
b
e
O
t
e
l
)
o
s
(
s
t
b
c
u
O
d
o
)
r
s
P
(
t
c
e
t
u
e
l
d
o
o
r
s
P
b
O
e
t
e
l
o
s
b
O
MOUT(L)
BIN(L)
MOUT(R)
D96AU431
Figure 27. PINS: 12, 14
BIN(R)
D96AU428
Figure 30. PIN: 20
VS
20µA
20µA
SCL
44K
BIN(L)
D96AU424
BIN(R)
D96AU428
Figure 28. PINS: 13, 15
Figure 31. PINS: 21
VS
20µA
20µA
SDA
44K
BOUT(L)
BOUT(R)
D96AU423
D96AU429
15/19
TDA7438
Figure 32. DIP28 Mechanical Data & Package Dimensions
mm
inch
DIM.
MIN.
TYP.
MAX.
MIN.
TYP.
a1
0.63
0.025
b
0.45
0.018
b1
0.23
0.31
0.009
MAX.
OUTLINE AND
MECHANICAL DATA
0.012
)
s
(
t
c
u
d
o
)
r
s
(
P
t
c
e
t
u
e
d
l
o
o
r
s
P
b
DIP28
e
O
t
e
l
)
o
s
(
s
t
b
c
u
O
d
o
)
r
s
P
(
t
c
e
t
u
e
l
d
o
o
r
s
P
b
O
e
t
e
l
o
s
b
O
b2
1.27
D
E
37.34
15.2
16.68
1.470
0.598
0.657
e
2.54
0.100
e3
33.02
1.300
F
16/19
0.050
14.1
0.555
I
4.445
0.175
L
3.3
0.130
TDA7438
Figure 33. SO28 Mechanical Data & Package Dimensions
mm
DIM.
MIN.
TYP.
A
inch
MAX.
MIN.
TYP.
2.65
MAX.
OUTLINE AND
MECHANICAL DATA
0.104
a1
0.1
0.3
0.004
0.012
b
0.35
0.49
0.014
0.019
b1
0.23
0.32
0.009
0.013
)
s
(
t
c
u
d
o
)
r
s
(
P
t
c
e
t
u
e
d
l
o
o
r
s
P
b
SO-28
e
O
t
e
l
)
o
s
(
s
t
b
c
u
O
d
o
)
r
s
P
(
t
c
e
t
u
e
l
d
o
o
r
s
P
b
O
e
t
e
l
o
s
b
O
C
0.5
c1
0.020
45° (typ.)
D
17.7
18.1
0.697
0.713
E
10
10.65
0.394
0.419
e
1.27
0.050
e3
16.51
0.65
F
7.4
7.6
0.291
0.299
L
0.4
1.27
0.016
0.050
S
8 ° (max.)
17/19
TDA7438
Table 14. Revision History
Date
Revision
Description of Changes
January 2004
6
First Issue in EDOCS DMS
June 2004
7
Changed the Style-sheet in compliance to the new “Corporate Technical
Pubblications Design Guide”
)
s
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d
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s
(
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d
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r
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P
b
e
O
t
e
l
)
o
s
(
s
t
b
c
u
O
d
o
)
r
s
P
(
t
c
e
t
u
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l
d
o
o
r
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P
b
O
e
t
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l
o
s
b
O
18/19
TDA7438
)
s
(
t
c
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d
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)
r
s
(
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t
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d
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o
o
r
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P
b
e
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t
e
l
)
o
s
(
s
t
b
c
u
O
d
o
)
r
s
P
(
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b
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o
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b
O
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