TDA7491HV
Datasheet
20 W + 20 W dual BTL class-D audio amplifier
Features
PowerSSO-36
exposed pad up
PowerSSO-36 with
exposed pad down
•
20 W + 20 W continuous output power:
RL = 8 Ω, THD = 10% at VCC = 18 V
–
•
•
•
•
•
•
•
•
•
Wide-range single-supply operation (5 - 18 V)
High efficiency (η = 90%)
Four selectable, fixed gain settings of nominally 20 dB, 26 dB, 30 dB and 32 dB
Differential input minimize common-mode noise
No ‘pop’ at turn-on/off
Standby and mute features
Short-circuit protection
Thermal overload protection
External synchronisation
Description
The TDA7491HV is a dual BTL class-D audio amplifier with single power supply
designed for LCD TVs and monitors.
Thanks to the high efficiency and exposed-pad-up (EPU) and down (EPD) packages,
no separate heatsink is required.
The TDA7491HV is pin-to-pin compatible with the TDA7491P and TDA7491LP.
Product status link
TDA7491HV
Product summary
Order code
TDA7491HV13TR
Package
PowerSSO-36 EPD
Order code
TDA7491HVU13TR
Package
PowerSSO-36 EPU
Packing
Tape and reel
Temperature
range
-40 to 85 °C
DS5624 - Rev 10 - February 2021
For further information contact your local STMicroelectronics sales office.
www.st.com
TDA7491HV
Device block diagram
1
Device block diagram
Figure 1. Internal block diagram (showing one channel only) shows the block diagram of one of the two identical
channels of the TDA7491HV.
Figure 1. Internal block diagram (showing one channel only)
DS5624 - Rev 10
page 2/50
TDA7491HV
Pin description
2
Pin description
2.1
Pinout (EPD)
Figure 2. Pin connections (top view)
DS5624 - Rev 10
S UB_GND
1
36
VS S
OUTP B
2
35
S VCC
OUTP B
3
34
VR E F
P GNDB
4
33
INNB
P GNDB
5
32
INP B
P VCC B
6
31
GAIN1
P VCC B
7
30
GAIN0
OUTNB
8
29
S VR
28
DIAG
OUTNB
9
OUTNA
10
OUTNA
P VCC A
EP
27
S GND
11
26
VDDS
12
25
S YNCLK
P VCC A
13
24
R OS C
P GNDA
14
23
INNA
P GNDA
15
22
INP A
OUTP A
16
21
MUTE
OUTP A
17
20
S TBY
P GND
18
19
VDDP W
Exposed pad down
(Connected to ground )
page 3/50
TDA7491HV
Pin list (EPD)
2.2
Pin list (EPD)
Table 1. Pin description list
DS5624 - Rev 10
Number
Name
Type
Description
1
SUB_GND
PWR
2,3
OUTPB
O
4,5
PGNDB
PWR
Power stage ground for right channel
6,7
PVCCB
PWR
Power supply for right channel
8,9
OUTNB
O
Negative PWM output for right channel
10,11
OUTNA
O
Negative PWM output for left channel
12,13
PVCCA
PWR
Power supply for left channel
14,15
PGNDA
PWR
Power stage ground for left channel
16,17
OUTPA
O
Positive PWM output for left channel
18
PGND
PWR
19
VDDPW
O
3.3-V (nominal) regulator output referred to ground for power stage
20
STBY
I
Standby mode control
21
MUTE
I
Mute mode control
22
INPA
I
Positive differential input of left channel
23
INNA
I
Negative differential input of left channel
24
ROSC
O
Master oscillator frequency-setting pin
25
SYNCLK
I/O
Clock in/out for external oscillator
26
VDDS
O
3.3-V (nominal) regulator output referred to ground for signal blocks
27
SGND
PWR
28
DIAG
O
Open-drain diagnostic output
29
SVR
O
Supply voltage rejection
30
GAIN0
I
Gain setting input 1
31
GAIN1
I
Gain setting input 2
32
INPB
I
Positive differential input of right channel
33
INNB
I
Negative differential input of right channel
34
VREF
O
Half VDDS (nominal) referred to ground
35
SVCC
PWR
36
VSS
O
3.3-V (nominal) regulator output referred to power supply
-
EP
-
Exposed pad for heatsink, to be connected to GND
Connect to the frame
Positive PWM for right channel
Power stage ground
Signal ground
Signal power supply
page 4/50
TDA7491HV
Pinout (EPU)
2.3
Pinout (EPU)
Figure 3. Pin connections (top view)
DS5624 - Rev 10
page 5/50
TDA7491HV
Pin list (EPU)
2.4
Pin list (EPU)
Table 2. Pin description list
DS5624 - Rev 10
Number
Name
Type
Description
1
SUB_GND
PWR
2, 3
OUTPB
O
4, 5
PGNDB
PWR
Power stage ground for right channel
6, 7
PVCCB
PWR
Power supply for right channel
8, 9
OUTNB
O
Negative PWM output for right channel
10, 11
OUTNA
O
Negative PWM output for left channel
12, 13
PVCCA
PWR
Power supply for left channel
14, 15
PGNDA
PWR
Power stage ground for left channel
16, 17
OUTPA
O
Positive PWM output for left channel
18
PGND
PWR
19
VDDPW
O
3.3 V (nominal) regulator output referred to ground for power stage
20
STBY
I
Standby mode control
21
MUTE
I
Mute mode control
22
INPA
I
Positive differential input of left channel
23
INNA
I
Negative differential input of left channel
24
ROSC
O
Master oscillator frequency-setting pin
25
SYNCLK
I/O
Clock in/out for external oscillator
26
VDDS
O
3.3 V (nominal) regulator output referred to ground for signal blocks
27
SGND
PWR
28
DIAG
O
Open-drain diagnostic output
29
SVR
O
Supply voltage rejection
30
GAIN0
I
Gain setting input 1
31
GAIN1
I
Gain setting input 2
32
INPB
I
Positive differential input of right channel
33
INNB
I
Negative differential input of right channel
34
VREF
O
Half VDDS (nominal) referred to ground
35
SVCC
PWR
36
VSS
O
3.3 V (nominal) regulator output referred to power supply
-
EP
-
Exposed pad for heatsink, to be connected to GND
Connect to the frame
Positive PWM for right channel
Power stage ground
Signal ground
Signal power supply
page 6/50
TDA7491HV
Absolute maximum ratings
3
Absolute maximum ratings
Table 3. Absolute maximum ratings
Symbol
VCC
Parameter
Value
Unit
23
V
DC supply voltage for pins PVCCA, PVCCB
VI
Voltage limits for input pins STBY, MUTE, INNA, INPA, INNB, INPB, GAIN0,
GAIN1
-0.3 - 3.6
V
Top
Operating temperature
-40 to 85
°C
Tj
Junction temperature
-40 to 150
°C
Tstg
Storage temperature
-40 to 150
°C
Table 4. Thermal data
Symbol
Parameter
Min.
Typ.
Max.
3
Rth j-case
Thermal resistance, junction-to-case
2
Rth j-amb
Thermal resistance, junction-to-ambient (mounted on a recommended
PCB)(1).
24
Unit
°C/W
1. FR4 with vias to copper area of 9 cm2
DS5624 - Rev 10
page 7/50
TDA7491HV
Electrical specifications
4
Electrical specifications
Unless otherwise stated, the results in Table 1 below are given for the conditions: VCC = 18 V, RL (load) = 8 Ω,
ROSC = R3 = 39 kΩ, C8 = 100 nF, f = 1 kHz, GV = 20 dB and Tamb = 25 °C.
Table 5. Electrical specifications
Symbol
VCC
Iq
IqSTBY
Test conditions
Min.
Typ.
Max.
Unit
Supply voltage
5
-
18
V
Total quiescent current
-
26
35
mA
2.5
5.0
µA
Quiescent current in standby
Play mode
-100
+100
Mute mode
-60
+60
VOS
Output offset voltage
IOCP
Overcurrent protection threshold
Tj
Junction temperature at thermal
shutdown
Ri
Input resistance
Differential input
Undervoltage protection threshold
-
VUVP
RDS(on)
Po
Po
PD
η
THD
GV
ΔGV
Power transistor on resistance
Output power
Output power
Dissipated power
RL = 0 Ω
eN
Total input noise
SVRR
Supply voltage rejection ratio
Tr, Tf
Rise and fall times
Switching frequency
60
kΩ
4.5
THD = 10%
20
THD = 1%
16
RL = 8 Ω, THD = 10%, VCC = 12
V
7.2
RL = 6 Ω, THD = 1% VCC = 25
V
4.0
THD = 10%
Ω
W
80
4.0
W
90
%
0.1
%
GAIN0 = L, GAIN1 = L
18
20
22
GAIN0 = L, GAIN1 = H
24
26
28
GAIN0 = H, GAIN1 = L
28
30
32
GAIN0 = H, GAIN1 = H
30
32
34
-1
+1
f = 1 kHz, Po=1 W
70
A curve, GV = 20 dB
20
f = 22 Hz to 22 kHz
-
fr = 100 Hz, Vr = 1 Vpp, CSVR =
10 µF
Internal oscillator, master mode
V
W
Po =20W +20 W,
Gain matching
A
°C
0.2
Po = 1 W
-
mV
150
Low-side
Total harmonic distortion
Cross-talk
54
5
0.2
Po = 20 W + 20W
Closed-loop gain
3
High-side
Efficiency
CT
fSW
DS5624 - Rev 10
Parameter
290
25
dB
dB
dB
35
µV
50
dB
40
ns
320
350
kHz
page 8/50
TDA7491HV
Electrical specifications
Symbol
Parameter
fSWR
Switching frequency range
VinH
Digital input high (H)
VinL
Digital input low (L)
AMUTE
Mute attenuation
Standby mode
Function
mode
Mute mode
Play mode
Test conditions
(1)
VMUTE = low, VSTBY= high
Min.
Typ.
Max.
Unit
250
-
400
kHz
2.3
0.8
80
V
dB
VSTBY < 0.5 V
VMUTE = X
VSTBY > 2.9 V
VMUTE < 0.8 V
VSTBY > 2.9 V
VMUTE > 2.9 V
1. Refer to Section 8.4 Internal and external clocks.
DS5624 - Rev 10
page 9/50
TDA7491HV
Characterization curves
5
Characterization curves
The following characterization curves have been produced by using the TDA7491HV evaluation board.
The LC filter for 4 Ω load uses components of 15 μH and 470 nF, whilst that for 6 Ω load uses 22 μH and 220 nF
and that for 8 Ω load uses 33 μH and 220 nF.
5.1
4 Ω loads at VCC = 14 V
Figure 4. Output power vs. supply voltage
Test Condition :
Vcc = 5~14V,
RL = 4 ohm,
Output power (W)
Rosc = 39k , Cosc =100nF,
f =1kHz,
Gv = 30dB,
Tamb = 25
Specification Limit:
Typical:
Vs =14V,Rl = 4 ohm
Po = 20W @THD =10%
Po =16W @THD =1%
Supply voltage
Figure 5. THD vs. output power (1 kHz)
THD (%)
10
Test Condition:
5
Vcc=14V,
RL=4 ohm,
Rosc=39k , Cosc=100nF,
f =1kHz,
2
1
0.5
Gv=30dB,
Tamb=25
0.2
0.1
Specification Limit:
0.05
Typical:
Po=20W @ THD=10%
0.02
0.01
100m
200m
500m
1
2
5
10
20
Output Power (W)
DS5624 - Rev 10
page 10/50
TDA7491HV
4 Ω loads at VCC = 14 V
Figure 6. THD vs. output power (100 Hz)
THD (%)
10
Test Condition:
5
Vcc=14V,
RL=4 ohm,
Rosc=39k , Cosc=100nF,
f =100Hz,
2
1
0.5
Gv=30dB,
Tamb=25
0.2
0.1
Specification Limit:
0.05
Typical:
20W @ THD=10%
0.02
0.01
100m
200m
500m
1
2
5
10
20
Output Power (W)
Figure 7. THD vs. frequency
THD (%)
0.5
Test Condition:
0.4
Vcc=14V,
0.3
RL=4 ohm,
0.2
Rosc=39k , Cosc=100nF,
f = 1kHz,
Gv=30dB,
Po=1W
Tamb=25
0.1
0.07
0.06
0.05
0.04
0.03
Specification Limit:
0.02
Typical: THD 50dB (@ f = 1kHz)
-110
-115
-120
20
50
100
200
500
1k
2k
5k
10k
20k
Frequency (Hz)
Figure 10. FFT performance (0 dB)
FFT (dB)
+10
Test Condition:
Vcc =14V,
+0
-10
-20
RL= 4 ohm,
-30
Rosc = 39k , Cosc =100nF,
-40
f =1kHz,
Gv = 30dB,
Po = 1W
Tamb = 25
-50
-60
-70
-80
-90
-100
-110
Specification Limit:
-120
Typical: >60dB
-130
for the harmonic frequency
-140
-150
20
50
100
200
500
1k
2k
5k
10k
20k
Frequency (Hz)
DS5624 - Rev 10
page 12/50
TDA7491HV
4 Ω loads at VCC = 14 V
Figure 11. FFT performance (-60 dB)
FFT (dB)
+0
-10
Test Condition:
-20
Vcc =14V,
-30
RL= 4 ohm,
-40
Rosc = 39k , Cosc = 100nF,
-50
f = 1kHz,
-60
Gv=30dB,
-70
-80
Po= -60dB (@ 1W =0dB)
-90
Tamb=25
-100
-110
Specification Limit:
-120
Typical: > 90dB
-130
for the harmonic frequency
-140
-150
20
50
100
200
500
1k
2k
5k
10k
20k
10k
20k
Frequency (Hz)
Figure 12. Power supply rejection ratio vs. frequency
+0
-10
-20
Test Condition:
Vcc =14V,
RL= 4 ohm,
Rosc = 39k , Cosc = 100nF,
Vin=0,
Ripple frequency=100Hz
-40
Ripple voltage=500mV
-50
Gv=30dB,
d
B
r
0dB refers to 500mV,100Hz
A
Tamb=25
-30
-60
-70
-80
-90
-100
20
50
100
200
500
1k
2k
5k
Hz
Figure 13. Power dissipation and efficiency vs. output power
Test Condition:
Vcc=14V,
RL=4 ohm,
Rosc=39k , Cosc=100nF,
DS5624 - Rev 10
Vcc=14V
f =1kHz,
Rload=4ohm
Gv=30dB,
Gain=30dB
Tamb=25
f=1kHz
page 13/50
TDA7491HV
4 Ω loads at VCC = 14 V
Figure 14. Closed-loop gain vs. frequency
+2
+1.5
+1
Test Conditions:
Gain=32dB
Gain=26dB
+0.5
-0
Vcc =14V,
-0.5
RL= 4 ohm,
-1
Rosc = 39k , Cosc = 100nF,
F=1kHz,
0dB@f=1kHz,,Po=1w,
Gain=32dB
-1.5
d
B
r
A
Gain=22dB
Gain=32dB
-2
-2.5
-3
-3.5
Tamb=25
-4
-4.5
-5
20
50
100
200
500
1k
2k
5k
10k
20k
30k
Hz
Figure 15. Current consumption vs. voltage on pin MUTE
Test Condition:
Vcc =14V,
RL= 4 ohm,
Rosc = 39k , Cosc = 100nF,
Vin=0,
Vcc=14V
Ta mb=25
Rload=4ohm
Gain=30dB
Vin=0
Figure 16. Attenuation vs. voltage on pin MUTE
Test Condition:
Vcc =14V,
RL= 4 ohm,
Rosc = 39k , Cosc = 100nF,
0dB@f=1kHz, Po=1w,
Gain=30dB,
Ta mb=25
DS5624 - Rev 10
Vcc=14V
Rload=4ohm
Gain=30dB
0dB@f=1kHz, Po=1w
page 14/50
TDA7491HV
4 Ω loads at VCC = 14 V
Figure 17. Current consumption vs. voltage on pin STBY
Test Condition:
Vcc =14V,
RL= 4 ohm,
Rosc = 39k , Cosc = 100nF,
Vcc=14V
Vin=0,
Rload=4ohm
Ta mb=25
Gain=30dB
Vin=0
Figure 18. Attenuation vs. voltage on pin STBY
Test Condition:
Vcc =14V,
RL= 4 ohm,
Vcc=14V
Rload=4ohm
Rosc = 39k , Cosc = 100nF,
Gain=30dB
0dB@f=1kHz,Po=1w,
Gain=30dB.
0dB@f=1kHz, Po=1w
Tamb=25
DS5624 - Rev 10
page 15/50
TDA7491HV
6 Ω loads at VCC = 16 V
5.2
6 Ω loads at VCC = 16 V
Figure 19. Output power vs. supply voltage
Test Condition :
f =1kHz
Specification Limit:
Typical:
Vs =16V,Rl =6 ohm
Po=20W @THD=10%
Po=16W @THD=1%
Figure 20. THD vs. output power (1 kHz)
THD (%)
10
Test Condition:
5
Vcc =16V,
RL= 6 ohm,
Rosc =39k , Cosc =100nF,
f =1kHz,
2
1
0.5
Gv =30dB,
Tamb =25
0.2
0.1
Specification Limit:
0.05
Typical:
Po=20W @ THD=10%
0.02
0.01
200m
500m
1
2
5
10
20
Output Power (W)
DS5624 - Rev 10
page 16/50
TDA7491HV
6 Ω loads at VCC = 16 V
Figure 21. THD vs. output power (100 Hz)
THD (%)
10
Test Condition:
5
Vcc =16V,
RL = 6 ohm,
Rosc =39k , Cosc =100nF,
f =100Hz,
Gv =30dB,
Tamb =25
2
1
0.5
0.2
0.1
0.05
Specification Limit:
Typical:
20W @ THD =10%
0.02
0.01
0.005
200m
500m
1
2
5
10
20
Output Power (W)
Figure 22. THD vs. frequency
THD (%)
2
Test Condition:
Vcc =16V,
RL= 6 ohm,
1
0.5
Ros c=39k , Cosc =100nF,
f =1kHz,
Gv =30dB,
Po =1W
0.2
0.1
Tamb =25
0.05
Specification Limit:
0.02
Typical: THD50dB (@ f =1kHz)
-105
-110
-115
-120
20
50
100
200
500
1k
2k
5k
10k
20k
Frequency (Hz)
DS5624 - Rev 10
page 18/50
TDA7491HV
6 Ω loads at VCC = 16 V
Figure 25. FFT performance (0 dB)
FFT (dB)
+10
+0
Test Condition:
-10
Vcc =16V,
-20
RL= 6 ohm,
-30
Rosc =39k , Cosc =100nF,
-40
-50
f =1kHz,
-60
Gv =30dB,
-70
-80
Po =1W
-90
Tamb =25
-100
-110
Specification Limit:
-120
Typical: >60dB
-130
for the harmonic frequency
-140
-150
20
50
100
200
500
1k
2k
5k
10k
20k
Frequency (Hz)
Figure 26. FFT performance (-60 dB)
FFT (dB)
+0
Test Condition:
Vcc =16V,
-10
-20
-30
RL= 6 ohm,
-40
Rosc =39k , Cosc =100nF,
-50
f =1kHz,
-60
Gv =30dB,
-70
Po = -60dB (@ 1W =0dB)
Tamb =25
-80
-90
-100
-110
Specification Limit:
-120
Typical: > 90dB
-130
for the harmonic frequency
-140
-150
20
50
100
200
500
1k
2k
5k
10k
20k
Frequency (Hz)
DS5624 - Rev 10
page 19/50
TDA7491HV
6 Ω loads at VCC = 16 V
Figure 27. Power supply rejection ratio vs. frequency
+0
-10
-20
Ripple voltage=500mV
Vcc =16V,
-40
d
B
r
RL= 6 ohm,
Rosc =39k , Cosc =100nF,
A
Vin=0,
Gv =30dB,
Tamb =25
Ripple frequency=100Hz
-30
Test Condition:
-50
-60
-70
,
-80
0dB refers to 500mV, 100Hz
-90
-100
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 28. Power dissipation and efficiency vs. output power
Test Condition:
Vcc =16V,
RL= 6 ohm,
Rosc =39k , Cosc =100nF,
Vcc=16V
f =1kHz,
Rload=6ohm
Gv =30dB,
Gain=30dB
Tamb =25
f=1kHz
Figure 29. Closed-loop gain vs. frequency
+2
+1.5
+1
Test Condition:
Vcc =16V,
-0
RL= 6 ohm,
Rosc =39k , Cosc =100nF,
0dB@f=1kHz,Po=1w,
Gv=32dB,
Tamb =25
Gain=26dB
Gain=32dB
+0.5
-0.5
d
B
r
A
-1
Gain=30dB
-1.5
Gain=22dB
-2
-2.5
-3
-3.5
-4
-4.5
-5
20
50
100
200
500
1k
2k
5k
10k
20k 30k
Hz
DS5624 - Rev 10
page 20/50
TDA7491HV
6 Ω loads at VCC = 16 V
Figure 30. Current consumption vs. voltage on pin MUTE
Test Condition:
Vcc =16V,
RL= 6 ohm,
Rosc =39k , Cosc =100nF,
Vcc=16V
Rload=6ohm
Vin=0,
Gain=30dB
Gain=30dB,
Vin=0
Tamb =25
Mute voltage (V)
Figure 31. Attenuation vs. voltage on pin MUTE
Test Condition:
Vcc =16V,
Vcc=16V
RL= 6 ohm,
Rload=6ohm
Rosc =39k , Cosc =100nF,
0dB@f=1kHz,Po=1w,
Gain=30dB,
Gain=30dB
0dB@f=1kHz, Po=1w
Tamb =25
Mute voltage
DS5624 - Rev 10
page 21/50
TDA7491HV
6 Ω loads at VCC = 16 V
Figure 32. Current consumption vs. voltage on pin STBY
Test Condition:
Vcc =16V,
Vcc=16V
RL= 6 ohm,
Rload=6ohm
Rosc =39k , Cosc =100nF,
Gain=30dB
Vin=0,
Vin=0
Gain=30dB,
Tamb =25
Test Condition:
Vcc =16V,
RL= 6 ohm,
Rosc =39k , Cosc =100nF,
0dB@f=1kHz,Po=1w,
Gain=30dB,
Iquiescent (mA)
Figure 33. Attenuation vs. voltage on pin STBY
Vcc=16V
Rload=6ohm
Gain=30dB
0dB@f=1kHz, Po=1w
Tamb =25
Standby voltage
DS5624 - Rev 10
page 22/50
TDA7491HV
8 Ω loads at VCC = 18 V
5.3
8 Ω loads at VCC = 18 V
Figure 34. Output power vs. supply voltage
Test conditions :
Vcc = 5~18V,
Rosc =39k , Cosc =100nF
f =1kHz,
Gv =30dB,
Tamb =25
Specification limit:
Typical:
Output power (W)
RL = 8 ohm,
Vs =18V,Rl = 8 ohm
Po =20W @THD =10%
Po =16W @THD =1%
Supply voltage
Figure 35. THD vs. output power (1 kHz)
THD (%)
10
Test Condition:
5
Vcc =18V,
RL= 8 ohm,
2
Rosc =39k , Cosc =100nF,
1
f =1kHz,
Gv =30dB,
Tamb =25
0.5
0.2
0.1
Specification Limit:
Typical:
Po =20W @ THD =10%
0.05
0.02
0.01
100m
200m
500m
1
2
5
10
20
Output Power (W)
DS5624 - Rev 10
page 23/50
TDA7491HV
8 Ω loads at VCC = 18 V
Figure 36. THD vs. output power (100 Hz)
THD (%)
10
Test Condition:
5
Vcc =18V,
RL= 8 ohm,
Rosc =39k , Cosc =100nF,
f =100Hz,
Gv =30dB,
Tamb =25
2
1
0.5
0.2
0.1
0.05
Specification Limit:
Typical:
20W @ THD =10%
0.02
0.01
0.005
100m
200m
500m
1
2
5
10
20
Output Power (W)
Figure 37. THD vs. frequency
THD (%)
2
Test Condition:
Vcc =18V,
RL= 8 ohm,
1
0.5
Rosc =39k , Cosc =100nF,
f =1kHz,
Gv =30dB,
0.2
0.1
Po =1W
Tamb =25
0.05
0.02
Specification Limit:
0.01
Typical: THD50dB (@ f =1kHz)
-105
-110
-115
-120
20
50
100
200
500
1k
2k
5k
10k
20k
Frequency (Hz)
DS5624 - Rev 10
page 25/50
TDA7491HV
8 Ω loads at VCC = 18 V
Figure 40. FFT performance (0 dB)
FFT (dB)
+10
+0
Test Condition:
-10
Vcc =18V,
-20
RL= 8 ohm,
-30
Rosc =39k , Cosc =100nF,
-40
-50
f = 1kHz,
-60
Gv =30dB,
-70
Po =1W
-80
-90
Tamb =25
-100
-110
Specification Limit:
-120
Typical: >60dB
-130
for the harmonic frequency
-140
-150
20
50
100
200
500
1k
2k
5k
10k
20k
Frequency (Hz)
Figure 41. FFT performance (-60 dB)
FFT (dB)
+0
Test Condition:
Vcc =18V,
-10
-20
-30
RL= 8 ohm,
-40
Rosc =39k , Cosc =100nF,
-50
f =1kHz,
-60
Gv =30dB,
-70
Po = -60dB (@ 1W =0dB)
Tamb =25
-80
-90
-100
-110
Specification Limit:
-120
Typical: > 90dB
-130
for the harmonic frequency
-140
-150
20
50
100
200
500
1k
2k
5k
10k
20k
Frequency (Hz)
DS5624 - Rev 10
page 26/50
TDA7491HV
8 Ω loads at VCC = 18 V
Figure 42. Power supply rejection ratio vs. frequency
+0
-10
Test Condition:
-20
Vcc =18V,
RL= 8 ohm,
-30
Ripple frequency=100Hz
-40
Ripple voltage=500mV
Rosc =39k , Cosc =100nF,
Vin=0,
Gv =30dB,
d
B
r
Tamb =25
A
0dB refers to 500mV, 100Hz
-50
-60
-70
-80
-90
-100
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
8ohm 18v PSRR.at27
Figure 43. Power dissipation and efficiency vs. output power
RL= 8 ohm,
Rosc =39k , Cosc =100nF,
f=1kHz,
Gv =30dB,
Tamb =25
Vcc=18V
Rload=8ohm
Gain=30dB
f=1kHz
Power dissipation (W)
Vcc =18V,
Efficiency %
Test Condition:
Output power per channel (W)
DS5624 - Rev 10
page 27/50
TDA7491HV
8 Ω loads at VCC = 18 V
Figure 44. Closed-loop gain vs. frequency
+2
+1.5
Test Condition:
+1
Vcc =18V,
Gain=26dB
Gain=32dB
+0.5
RL= 8 ohm,
-0
Rosc =39k , Cosc =100nF,
0dB@f=1kHz,Po=1w,
Gain=32dB,
Tamb =25
-0.5
-1
d
B
r
-1.5
A
-2
Gain=22dB
Gain=30dB
-2.5
-3
-3.5
-4
-4.5
-5
20
50
100
200
500
1k
2k
5k
10k
20k 30k
Hz
Figure 45. Current consumption vs. voltage on pin MUTE
Vcc =18V,
RL= 8 ohm,
Rosc =39k , Cosc =100nF,
Vin=0,
Gain=30dB,
Iquiescent (mA)
Test Condition:
Vcc=18V
Rload=8ohm
Gain=30dB
Vin=0
Tamb =25
Mute voltage
DS5624 - Rev 10
page 28/50
TDA7491HV
8 Ω loads at VCC = 18 V
Figure 46. Attenuation vs. voltage on pin MUTE
Iquiescent (mA)
Test Condition:
Vcc =18V,
RL= 8 ohm,
Rosc =39k , Cosc =100nF,
0dB@f=1kHz,Po=1w,
Gain=30dB,
Vcc=18V
Rload=8ohm
Gain=30dB
0dB@f=1kHz, Po=1w
Tamb =25
Mute voltage
Figure 47. Current consumption vs. voltage on pin STBY
Test Condition:
RL= 8 ohm,
Rosc =39k , Cosc =100nF,
Vin=0,
Gain=30dB,
Tamb =25
Iquiescent (mA)
Vcc =18V,
Vcc=18V
Rload=8ohm
Gain=30dB
Vin=0
Standby voltage (V)
DS5624 - Rev 10
page 29/50
TDA7491HV
8 Ω loads at VCC = 18 V
Figure 48. Attenuation vs. voltage on pin STBY
Vcc =18V,
RL= 8 ohm,
Rosc =39k , Cosc =100nF,
0dB@f=1kHz,Po=1w,
Gain=30dB,
Attenuation (dB)
Test Condition:
Vcc=18V
Rload=8ohm
Gain=30dB
0dB@f=1kHz, Po=1w
Tamb =25
Standby voltage (V)
DS5624 - Rev 10
page 30/50
TDA7491HV
Test board
6
Test board
Figure 49. Test board (TDA7491HV) layout
DS5624 - Rev 10
page 31/50
TDA7491HV
Application circuit
7
Application circuit
Figure 50. Application circuit for class-D amplifier
TDA7491HV
DS5624 - Rev 10
page 32/50
TDA7491HV
Application information
8
Application information
8.1
Mode selection
The three operating modes of the TDA7491HV are set by the two inputs, STBY (pin 20) and MUTE (pin 21).
•
Standby mode: all circuits are turned off, very low current consumption.
•
Mute mode: inputs are connected to ground and the positive and negative PWM outputs are at 50% duty
cycle.
•
Play mode: the amplifiers are active.
The protection functions of the TDA7491HV are enabled by pulling down the voltages of the STBY and MUTE
inputs shown in figure below. The input current of the corresponding pins must be limited to 200 µA.
Table 6. Mode settings
Mode
STBY
MUTE
Standby
L(1).
X (do not care)
Mute
H(1)
L
Play
H
H
1. Refer to VSTBY and VMUTE in Section 4 Electrical specifications
Figure 51. Standby and mute circuits
Standby
3.3 V
0V
STBY
R2
30 k
C7
2.2 µF
R4
30 k
C15
2.2 µF
Mute
3.3 V
0V
DS5624 - Rev 10
TDA7491HV
MUTE
page 33/50
TDA7491HV
Gain setting
Figure 52. Turn-on/off sequence for minimizing speaker “pop”
8.2
Gain setting
The gain of the TDA7491HV is set by the two inputs, GAIN0 (pin 30) and GAIN1 (pin31). Internally, the gain is set
by changing the feedback resistors of the amplifier.
Table 7. Gain settings
GAIN0
GAIN1
Nominal gain, Gv (dB)
L(1)
H(1)
20
L
H
26
H
L
30
H
H
32
1. Refer to Section 4 Electrical specifications for L and H drive levels.
DS5624 - Rev 10
page 34/50
TDA7491HV
Input resistance and capacitance
8.3
Input resistance and capacitance
The input impedance is set by an internal resistor Ri = 68 kΩ (typical). An input capacitor (Ci) is required to couple
the AC input signal.
The equivalent circuit and frequency response of the input components are shown in figure below. For Ci = 220
nF, the high-pass filter cut-off frequency is below 20 Hz:
fc = 1 / (2 * π * Ri * Ci)
Figure 53. Device input circuit and frequency response
8.4
Internal and external clocks
The clock of the class-D amplifier can be generated internally or can be driven by an external source.
If two or more class-D amplifiers are used in the same system, it is recommended that all the devices operate at
the same clock frequency. This can be implemented by using one TDA7491HV as master clock, while the other
devices are in slave mode, that is, externally clocked. The clock interconnect is via pin SYNCLK of each device.
As explained below, SYNCLK is an output in master mode and an output in master mode and an input in slave
mode.
8.4.1
Master mode (internal clock)
Using the internal oscillator, the output switching frequency, fSW, is controlled by the resistor, ROSC, connected to
pin ROSC:
fSW = 106 / ((16* ROSC+ 182) * 4) kHz
where ROSC is in kΩ.
In master mode, pin SYNCLK is used as a clock output pin whose frequency is:
fSYNCLK = 2 * fSW
For master mode to operate correctly, then resistor ROSC must be less than 60 kΩ as given below in Table 8. How
to set up SYNCLK.
DS5624 - Rev 10
page 35/50
TDA7491HV
Modulation
8.4.2
Slave mode (external clock)
In order to accept an external clock input the pin ROSC must be left open, that is, floating. This forces pin
SYNCLK to be internally configured as an input as given in table below.
The output switching frequency of the slave devices is:
fSW = fSYNCLK / 2
Table 8. How to set up SYNCLK
Mode
ROSC
SYNCLK
Master
ROSC < 60 kΩ
Output
Slave
Floating (not connected)
Input
Figure 54. Master and slave connection
Master
Slave
TDA7491HV
ROSC
TDA7491HV
SYNCLK
Output
Cosc
100 nF
8.5
SYNCLK
ROSC
Input
Rosc
39 k
Modulation
The output modulation scheme of the BTL is called unipolar pulse width modulation (PWM).
The differential output voltages change between 0 V and +VCC and between 0 V and -VCC.
This is in contrast to the traditional bipolar PWM outputs which change between +VCC
and -VCC. An advantage of this scheme is that it effectively doubles the switching frequency of the differential
output waveform on the load then reducing the current ripple accordingly. The OUTP and OUTN are in the same
phase almost overlapped when the input is zero under this condition, then the switching current is low and the
related losses in the load are low.
In practice, a short delay is introduced between these two outputs in order to avoid the BTL output switching
simultaneously when the input is zero.
Figure below shows the resulting differential output voltage and current when a positive, zero and negative input
signal is applied. The resulting differential voltage on the load has a double frequency with respect to outputs
OUTP and OUTN, resulting in reduced current ripple.
DS5624 - Rev 10
page 36/50
TDA7491HV
Reconstruction low-pass filter
Figure 55. Unipolar PWM output
8.6
Reconstruction low-pass filter
Standard applications use a low-pass filter before the speaker. The cut-off frequency should be higher than 22
kHz and much lower than the output switching frequency. It is necessary to choose the L-C component values
depending on the loud speaker impedance. Some typical values, which give a cut-off frequency of 27 kHz, are
shown in figures below.
Figure 56. Typical LC filter for an 8 Ω speaker
DS5624 - Rev 10
page 37/50
TDA7491HV
Protection functions
Figure 57. Typical LC filter for an 4 Ω speaker
8.7
Protection functions
The TDA7491HV is fully protected against undervoltage, overcurrent and thermal overloads as explained here.
Undervoltage protection (UVP)
If the supply voltage drops below the value of VUVP given in Section 4 Electrical specifications the undervoltage
protection is active and forces the outputs to the high-impedance state. When the supply voltage recovers, the
device restarts.
Overcurrent protection (OCP)
If the output current exceeds the value for IOCP given in Section 4 Electrical specifications, the overcurrent
protection is active and forces the outputs to the high-impedance state. Periodically, the device tries to restart. If
the overcurrent condition is still present then the OCP remains active. The restart time, TOC, is determined by the
R-C components connected to pin STBY.
Thermal protection (OTP)
If the junction temperature, Tj, reaches 145 °C (nominal), the device goes to mute mode and the positive and
negative PWM outputs are forced to 50% duty cycle. If the junction temperature reaches the value for Tj, given in
Section 4 Electrical specifications, the device shuts down and the output is forced to the high-impedance state.
When the device cools sufficiently the device restarts.
8.8
Diagnostic output
The output pin DIAG is an open-drain transistor. When the protection is activated it is in the high-impedance state.
The pin can be connected to a power supply (
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