TS2012
Filter-free stereo 2x2.8 W class D audio power amplifier
Datasheet - production data
Features
TS2012 - QFN20 (4x4 mm)
• Operating range from VCC = 2.5 V to 5.5 V
• Standby mode active low
• Output power per channel: 1.35 W @ 5 V or
0.68 W @ 3.6 V into 8 Ω with 1 % THD+N max
• Output power per channel: 2.2 W @ 5 V into
4 Ω with 1 % THD+N max
Pin connections (top view)
Lin+
17
• Four gains can be selected: 6, 12, 18, 24 dB
16
• Low current consumption
Rin+
AGND
18
Rin-
19
Lin-
20
• PSRR: 70 dB typ @ 217 Hz with 6 dB gain
14
• Thermal shutdown protection
3
PVCC
PVCC
13
• QFN20 4x4 mm lead-free package
4
PGND
PGND
12
Applications
5
Lout-
Rout-
11
• Cellular phone
NC
Rout+
AVCC
Lout+
2
STBYR
• Fast startup phase: 1 ms
STBYL
15
G1
NC
G0
1
6
7
8
9
10
• PDA
• Flat panel TV
Description
20
LIN +
19
LIN -
15
G0
1
G1
Gain
3
13
PVCC
PVCC
AVCC
9
Block diagram
H
PWM
Select
Bridge
LOUT+
2
LOUT-
5
The device has four different gain settings utilizing
two discrete pins: G0 and G1.
Standby
18
PGND
PGND
Control
4
STBY R
Bridge
12
STBY L
8
PWM
Select
300k
7
H
Gain
AGND
RIN -
300k
RIN +
17
300k
300k
Oscillator
16
July 2013
This is information on a product in full production.
The TS2012 is a fully differential, class D, power
amplifier stereo. It is able to drive up to 1.35 W
into an 8 Ω load at 5 V per channel. It achieves
outstanding efficiency compared to typical class
AB audio amps.
ROUT+
14
ROUT-
11
Pop and click reduction circuitry provides low
on/off switch noise while allowing the device to
start within 1 ms.
Two standby pins (active low) allow each channel
to be switched off independently.
The TS2012 is available in a QFN20 4x4 mm
package.
DocID14236 Rev 2
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www.st.com
Contents
TS2012
Contents
1
Absolute maximum ratings and operating conditions . . . . . . . . . . . . . 3
2
Typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
5
3.1
Electrical characteristic tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2
Electrical characteristic curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1
Differential configuration principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2
Gain settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3
Common mode feedback loop limitations . . . . . . . . . . . . . . . . . . . . . . . . 21
4.4
Low frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.5
Decoupling of the circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.6
Wakeup time (twu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.7
Shutdown time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.8
Consumption in shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.9
Single-ended input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.10
Output filter considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.1
QFN20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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DocID14236 Rev 2
TS2012
1
Absolute maximum ratings and operating conditions
Absolute maximum ratings and operating conditions
Table 1. Absolute maximum ratings
Symbol
VCC
Vi
Parameter
Value
Supply voltage (1)
Input voltage
6
(2)
Operating free air temperature range
-40 to + 85
Tstg
Storage temperature
-65 to +150
Rthja
Pd
ESD
Maximum junction temperature
Thermal resistance junction to ambient
°C
150
(3)
Power dissipation
100
Internally
HBM: human body model(5)
kV
200
V
200
mA
GND to VCC
V
260
°C
MM: machine model
Standby pin voltage maximum voltage
°C/W
limited(4)
2
(6)
Latch-up Latch-up immunity
VSTBY
V
GND to VCC
Toper
Tj
Unit
Lead temperature (soldering, 10 s)
1. All voltage values are measured with respect to the ground pin.
2. The magnitude of the input signal must never exceed VCC + 0.3 V / GND - 0.3 V.
3. The device is protected in case of over temperature by a thermal shutdown active @ 150 °C.
4. Exceeding the power derating curves over a long period causes abnormal operation.
5. Human body model: 100 pF discharged through a 1.5 kΩ resistor between two pins of the device, done for
all couples of pin combinations with other pins floating.
6. Machine model: a 200 pF cap is charged to the specified voltage, then discharged directly between two
pins of the device with no external series resistor (internal resistor < 5 Ω), done for all couples of pin
combinations with other pins floating.
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29
Absolute maximum ratings and operating conditions
TS2012
Table 2. Operating conditions
Symbol
VCC
VI
Vic
Parameter
Supply voltage
Value
Unit
2.5 to 5.5
Input voltage range
GND to VCC
Input common mode voltage
(1)
GND+0.5V to VCC-0.9V
V
(2)
VSTBY
Standby voltage input
Device ON
Device in STANDBY(3)
1.4 ≤ VSTBY ≤ VCC
GND ≤ VSTBY ≤ 0.4
≥4
RL
Load resistor
VIH
GO, G1 - high level input voltage(4)
1.4 ≤ VIH ≤ VCC
VIL
GO, G1 - low level input voltage
GND ≤ VIL ≤ 0.4
Rthja
Thermal resistance junction to ambient(5)
40
Ω
V
°C/W
1. I Voo I ≤ 40 mV max with all differential gains except 24 dB. For 24 dB gain, input decoupling caps are
mandatory.
2. Without any signal on VSTBY, the device is in standby (internal 300 kΩ ± 20 % pull-down resistor).
3. Minimum current consumption is obtained when VSTBY = GND.
4. Between G0, G1pins and GND, there is an internal 300kΩ (±20 %) pull-down resistor. When pins are
floating, the gain is 6 dB. In full standby (left and right channels OFF), these resistors are disconnected
(HiZ input).
5. With 4-layer PCB.
4/29
DocID14236 Rev 2
TS2012
Typical application
2
Typical application
Figure 1. Typical application schematics
Cs
VCC
100nF
Input capacitors
are optional
CsL
1μ F
VCC VCC
CsR
1μ F
Gain Select
Control
LIN +
Cin
LIN -
Left IN-
PVCC
AVCC
Cin
Differential
Left Input
PVCC
TS2012
Left IN+
Gain
H
PWM
Select
Bridge
LOUT+
Left speaker
LOUT-
G0
Oscillator
G1
Cin
Right IN-
STBY L
STBY R
Gain
H
PWM
Select
Bridge
ROUT+
ROUT-
Right speaker
Standby
Control
PGND
Differential
Right Input
RIN -
PGND
Cin
AGND
RIN +
Right IN+
Standby Control
Cs
VCC
100nF
Input capacitors
are optional
CsL
1μ F
VCC VCC
CsR
1μ F
Gain Select
Control
LIN +
Cin
LIN -
Left IN-
PVCC
AVCC
Cin
Differential
Left Input
PVCC
TS2012
Left IN+
H
Gain
PWM
Select
Bridge
LOUT+
LOUT-
LC Output Filter
Load
LC Output Filter
Load
G0
Oscillator
G1
Right IN-
Cin
STBY L
STBY R
Gain
H
PWM
Select
Bridge
ROUT+
ROUT-
Standby
Control
PGND
Differential
Right Input
RIN -
PGND
Cin
AGND
RIN +
Right IN+
4Ω LC Output Filter
Standby Control
8Ω LC Output Filter
30μH
15μH
1μ F
2μ F
15μH
DocID14236 Rev 2
2μ F
30μH
1μ F
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29
Typical application
TS2012
Table 3. External component descriptions
Components
Functional description
CS, CSL, CSR Supply capacitor that provides power supply filtering.
Cin
Input coupling capacitors (optional) that block the DC voltage at the amplifier input
terminal. The capacitors also form a high pass filter with Zin
(Fcl = 1 / (2 x π x Zin x Cin)).
Table 4. Pin descriptions
Pin number
Pin name
1
G1
2
Lout+
Left channel positive output
3
PVCC
Power supply
4
PGND
Power ground
5
Lout-
Left channel negative output
6
NC
7
STBYL
Standby pin (active low) for left channel output
8
STBYR
Standby pin (active low) for right channel output
9
AVCC
10
NC
11
Rout-
Right channel negative output
12
PGND
Power ground
13
PVCC
Power supply
14
Rout+
Right channel positive output
15
G0
16
Rin+
Right channel positive differential input
17
Rin-
Right channel negative differential input
18
AGND
19
Lin-
Left channel negative differential input
20
Lin+
Left channel positive differential input
Thermal pad
6/29
Pin description
Gain select pin (MSB)
No internal connection
Analog supply
No internal connection
Gain select pin (LSB)
Analog ground
Connect the thermal pad of the QFN package to PCB ground
DocID14236 Rev 2
TS2012
Electrical characteristics
3
Electrical characteristics
3.1
Electrical characteristic tables
Table 5. VCC = +5 V, GND = 0 V, Vic = 2.5 V, Tamb = 25 °C
(unless otherwise specified)
Symbol
ICC
ISTBY
Parameters and test conditions
Supply current
No input signal, no load, both channels
Standby current
No input signal, VSTBY = GND
Voo
Output offset voltage
Floating inputs, G = 6dB, RL = 8Ω
Po
Output power
THD + N = 1 % max, f = 1 kHz, RL = 4 Ω
THD + N = 1 % max, f = 1 kHz, RL = 8 Ω
THD + N = 10 % max, f = 1 kHz, RL = 4 Ω
THD + N = 10 % max, f = 1 kHz, RL = 8 Ω
THD + N
Total harmonic distortion + noise
Po = 0.8 W, G = 6 dB, f =1 kHz, RL = 8 Ω
Efficiency
Efficiency per channel
Po = 2.2 W, RL = 4 Ω +15 µH
Po = 1.25 W, RL = 8 Ω+15 µH
PSRR
Crosstalk
CMRR
Min.
Typ.
Max.
Unit
5
8
mA
0.2
2
µA
25
mV
2.2
1.35
2.8
1.65
W
0.07
%
81
89
Power supply rejection ratio with inputs grounded
Cin = 1 µF (1), f = 217 Hz, RL = 8 Ω, Gain = 6 dB,
Vripple = 200 mVpp
70
Channel separation
Po = 0.9 W, G = 6 dB, f = 1 kHz, RL = 8 Ω
90
Common mode rejection ratio
Cin = 1 µF, f = 217 Hz, RL = 8 Ω, Gain = 6 dB,
ΔVICM = 200 mVpp
70
Gain value
G1 = G0 = VIL
G1 = VIL & G0 = VIH
G1 = VIH & G0 = VIL
G1 = G0 = VIH
dB
5.5
11.5
17.5
23.5
6
12
18
24
6.5
12.5
18.5
24.5
Single ended input impedance
All gains, referred to ground
24
30
36
kΩ
FPWM
Pulse width modulator base frequency
190
280
370
kHz
SNR
Signal to noise ratio (A-weighting)
Po = 1.3 W, G = 6 dB, RL = 8 Ω
99
tWU
Wakeup time
1
tSTBY
Standby time
1
Gain
Zin
DocID14236 Rev 2
dB
3
ms
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Electrical characteristics
TS2012
Table 5. VCC = +5 V, GND = 0 V, Vic = 2.5 V, Tamb = 25 °C
(unless otherwise specified) (continued)
Symbol
VN
Parameters and test conditions
Output voltage noise f = 20 Hz to 20 kHz, RL=8 Ω
Unweighted (filterless, G = 6 dB)
A-weighted (filterless, G = 6 dB)
Unweighted (with LC output filter, G = 6 dB)
A-weighted (with LC output filter, G = 6 dB)
Unweighted (filterless, G = 24 dB)
A-weighted (filterless, G = 24 dB)
Unweighted (with LC output filter, G = 24 dB)
A-weighted (with LC output filter, G = 24 dB)
Min.
Typ.
63
35
60
35
115
72
109
71
Max.
Unit
µVRMS
1. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the superimposed sinus signal to VCC @ f = 217 Hz.
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DocID14236 Rev 2
TS2012
Electrical characteristics
Table 6. VCC = +3.6 V, GND = 0 V, Vic = 1.8 V, Tamb = 25 °C
(unless otherwise specified)
Symbol
ICC
ISTBY
Parameter
Typ.
Max.
Unit
Supply current
No input signal, no load, both channels
3.3
6.5
mA
Standby current
No input signal, VSTBY = GND
0.2
2
µA
25
mV
Voo
Output offset voltage
Floating inputs, G = 6dB, RL = 8Ω
Po
Output power
THD + N = 1 % max, f = 1 kHz, RL = 4 Ω
THD + N = 1 % max, f = 1 kHz, RL = 8 Ω
THD + N = 10 % max, f = 1 kHz, RL = 4 Ω
THD + N = 10 % max, f = 1 kHz, RL = 8 Ω
THD + N
Total harmonic distortion + noise
Po = 0.4 W, G = 6 dB, f =1 kHz, RL = 8 Ω
Efficiency
Efficiency per channel
Po = 1.15 W, RL = 4 Ω +15 µH
Po = 0.68 W, RL = 8 Ω +15 µH
PSRR
Crosstalk
CMRR
Min.
1.15
0.68
1.3
0.9
W
0.05
%
80
88
Power supply rejection ratio with inputs grounded
Cin= 1 µF (1), f = 217 Hz, RL = 8 Ω, Gain = 6 dB,
Vripple = 200 mVpp
70
Channel separation
Po = 0.5 W, G = 6 dB, f =1 kHz, RL = 8 Ω
90
Common mode rejection ratio
Cin = 1 µF, f = 217 Hz, RL = 8 Ω, Gain = 6 dB,
ΔVICM = 200 mVpp
70
Gain value
G1 = G0 = VIL
G1 = VIL & G0 = VIH
G1 = VIH & G0 = VIL
G1 = G0 = VIH
dB
5.5
11.5
17.5
23.5
6
12
18
24
6.5
12.5
18.5
24.5
Single ended input impedance
All gains, referred to ground
24
30
36
kΩ
FPWM
Pulse width modulator base frequency
190
280
370
kHz
SNR
Signal to noise ratio (A-weighting)
Po = 0.65 W, G = 6 dB, RL = 8 Ω
96
tWU
Wakeup time
1
tSTBY
Standby time
1
Gain
Zin
DocID14236 Rev 2
dB
3
ms
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Electrical characteristics
TS2012
Table 6. VCC = +3.6 V, GND = 0 V, Vic = 1.8 V, Tamb = 25 °C
(unless otherwise specified) (continued)
Symbol
VN
Parameter
Output voltage noise f = 20 Hz to 20 kHz, RL= 4 Ω
Unweighted (filterless, G = 6 dB)
A-weighted (filterless, G = 6 dB)
Unweighted (with LC output filter, G = 6 dB)
A-weighted (with LC output filter, G = 6 dB)
Unweighted (filterless, G = 24 dB)
A-weighted (filterless, G = 24 dB)
Unweighted (with LC output filter, G = 24 dB)
A-weighted (with LC output filter, G = 24 dB)
Min.
Typ.
58
34
55
34
111
70
105
69
Max.
Unit
µVRMS
1. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the superimposed sinus signal to VCC @ f = 217 Hz.
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DocID14236 Rev 2
TS2012
Electrical characteristics
Table 7. VCC = +2.5V, GND = 0V, Vic=1.25V, Tamb = 25°C
(unless otherwise specified)
Symbol
ICC
ISTBY
Parameter
Typ.
Max.
Unit
Supply current
No input signal, no load, both channels
2.8
4
mA
Standby current
No input signal, VSTBY = GND
0.2
2
µA
25
mV
Voo
Output offset voltage
Floating inputs, G = 6dB, RL = 8Ω
Po
Output power
THD + N = 1 % max, f = 1 kHz, RL = 4 Ω
THD + N = 1 % max, f = 1 kHz, RL = 8 Ω
THD + N = 10 % max, f = 1 kHz, RL = 4 Ω
THD + N = 10 % max, f = 1 kHz, RL = 8 Ω
THD + N
Total harmonic distortion + noise
Po = 0.2 W, G = 6 dB, f =1 kHz, RL = 8 Ω
Efficiency
Efficiency per channel
Po = 0.53 W, RL = 4 Ω +15 µH
Po = 0.32 W, RL = 8 Ω+15 µH
PSRR
Crosstalk
CMRR
Min.
0.53
0.32
0.75
0.45
W
0.04
%
80
88
Power supply rejection ratio with inputs grounded
Cin = 1 µF (1), f = 217 Hz, RL = 8 Ω, Gain = 6 dB,
Vripple = 200 mVpp
70
Channel separation
Po = 0.2 W, G = 6 dB, f = 1 kHz, RL = 8 Ω
90
Common mode rejection ratio
Cin = 1 µF, f = 217 Hz, RL = 8 Ω, Gain = 6 dB,
ΔVICM = 200 mVpp
70
Gain value
G1 = G0 = VIL
G1 = VIL & G0 = VIH
G1 = VIH & G0 = VIL
G1 = G0 = VIH
dB
5.5
11.5
17.5
23.5
6
12
18
24
6.5
12.5
18.5
24.5
Single ended input impedance
All gains, referred to ground
24
30
36
kΩ
FPWM
Pulse width modulator base frequency
190
280
370
kHz
SNR
Signal to noise ratio (A-weighting)
Po = 0.3 W, G = 6 dB, RL = 8 Ω
93
tWU
Wakeup time
1
tSTBY
Standby time
1
Gain
Zin
DocID14236 Rev 2
dB
3
ms
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Electrical characteristics
TS2012
Table 7. VCC = +2.5V, GND = 0V, Vic=1.25V, Tamb = 25°C
(unless otherwise specified) (continued)
Symbol
VN
Parameter
Min.
Output voltage noise f = 20 Hz to 20 kHz, RL = 8 Ω
Unweighted (filterless, G = 6 dB)
A-weighted (filterless, G = 6 dB)
Unweighted (with LC output filter, G = 6 dB)
A-weighted (with LC output filter, G = 6 dB)
Unweighted (filterless, G = 24 dB)
A-weighted (filterless, G = 24 dB)
Unweighted (with LC output filter, G = 24 dB)
A-weighted (with LC output filter, G = 24 dB)
Typ.
Max.
57
34
54
33
110
71
104
69
Unit
µVRMS
1. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the superimposed sinus signal to VCC @ f = 217 Hz.
3.2
Electrical characteristic curves
The graphs shown in this section use the following abbreviations:
•
RL+ 15 µH or 30 µH = pure resistor + very low series resistance inductor
•
Filter = LC output filter (1 µF + 30 µH for 4 Ω and 0.5 µF + 60 µH for 8 Ω)
All measurements are made with CSL = CSR = 1 µF and CS = 100 nF (see Figure 2), except
for the PSRR where CSL,R is removed (see Figure 3).
Figure 2. Test diagram for measurements
Vcc
CsL
(CsR)
1μF
GND
Cin
In+
Cin
GND
RL
4 or 8 Ω
Out+
15μH or 30μH
1/2 TS2012
In-
CS
100nF
Out-
or
LC Filter
GND
Audio Measurement
Bandwith < 30kHz
12/29
DocID14236 Rev 2
5th order
50kHz
low-pass filter
TS2012
Electrical characteristics
Figure 3. Test diagram for PSRR measurements
VCC
Cs
100nF
20Hz to 20kHz
Vripple
GND
1 μF
Cin
GND
Out+
In+
RL
4 or 8 Ω
15μH or 30μH
1/2 TS2012
In-
or
LC Filter
Out-
Cin
1 μF
GND
Vcc
5th order
50kHz
low-pass filter
GND
5th order
reference
50kHz
RMS Selective Measurement
Bandwith =1% of Fmeas
low-pass filter
Table 8. Index of graphics
Description
Figure
Current consumption vs. power supply voltage
Figure 4
Current consumption vs. standby voltage
Figure 5
Efficiency vs. output power
Figure 6 - Figure 9
Output power vs. power supply voltage
Figure 10, Figure 11
PSRR vs. common mode input voltage
Figure 12
PSRR vs. frequency
Figure 13
CMRR vs. common mode input voltage
Figure 14
CMRR vs. frequency
Figure 15
Gain vs. frequency
Figure 16, Figure 17
THD+N vs. output power
Figure 18 - Figure 25
THD+N vs. frequency
Figure 26 - Figure 37
Crosstalk vs. frequency
Figure 38 - Figure 41
Power derating curves
Figure 42
Startup and shutdown time
Figure 43, Figure 44
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Electrical characteristics
TS2012
Figure 4. Current consumption vs. power
supply voltage
4
Both channels ON
One channel ON
3
2
1
0
2.5
3.0
3.5
4.0
4.5
5.0
2.0
VCC=5V
1.5
VCC=2.5V
0.5
0.0
5.5
VCC=3.6V
1.0
No Load
TAMB=25°C
0
1
2
Power Supply Voltage (V)
Figure 6. Efficiency vs. output power (i)
500
Efficiency
60
75
0
0.0
0.1
50
Vcc=2.5V
RL=4Ω + ≥ 15μ H
F=1kHz
THD+N≤ 1%
0.2
0.3
Output Power (W)
0.4
25
Efficiency (%)
100
Power Dissipation (mW)
Efficiency (%)
80
20
20
0
0.00
14/29
0.05
Vcc=2.5V
RL=8Ω + ≥ 15μ H
F=1kHz
THD+N≤ 1%
0.10
0.15
0.20
Output Power (W)
0.25
200
40
80
20
Power
Dissipation
40
100
30
40
300
50
10
0
0.30
Efficiency (%)
60
60
Power
Dissipation
0.5
1.0
Output Power (W)
Vcc=5V
RL=4Ω + ≥ 15μ H
F=1kHz
THD+N≤ 1%
100
0
2.0
1.5
Figure 9. Efficiency vs. output power (iv)
Power Dissipation (mW)
Efficiency (%)
Efficiency
400
0
0.0
0
0.5
100
80
20
Figure 8. Efficiency vs. output power (iii)
80
5
100
Efficiency
Power
Dissipation
4
Figure 7. Efficiency vs. output power (ii)
125
100
40
3
Standby Voltage (V)
Power Dissipation (mW)
No Loads
200
160
Efficiency
120
60
80
40
Power
Dissipation
20
0
0.0
DocID14236 Rev 2
0.2
0.4
0.6
0.8
Output Power (W)
Vcc=5V
RL=8Ω + ≥ 15μ H
F=1kHz
THD+N≤ 1%
1.0
1.2
40
0
1.4
Power Dissipation (mW)
5
2.5
TAMB=25°C
Current Consumption (mA)
Current Consumption (mA)
6
Figure 5. Current consumption vs. standby
voltage (one channel)
TS2012
Electrical characteristics
Figure 10. Output power vs. power supply
voltage (i)
Figure 11. Output power vs. power supply
voltage (ii)
3.5
2.5
1.6
Output Power (W)
Output Power (W)
3.0
2.0
RL = 4Ω + ≥ 15μ H
F = 1kHz
BW < 30kHz
Tamb = 25°C
THD+N=10%
2.0
1.5
1.0
THD+N=1%
3.0
3.5
4.0
4.5
Power Supply Voltage (V)
5.0
1.2
0.8
0.0
2.5
5.5
Figure 12. PSRR vs. common mode input
voltage
Vcc=3V
-20
Vcc=5V
PSRR (dB)
PSRR(dB)
Vcc=2.5V
Gain=24dB
Gain=6dB
-50
-40
-70
-70
0.5
1.0 1.5 2.0 2.5 3.0 3.5 4.0
Common Mode Input Voltage (V)
4.5
-80
5.0
Gain=24dB
-50
-60
20
10k
20k
Δ Vicm=200mVpp, Vcc = 2.5, 3.6, 5V
RL ≥ 4Ω + ≥ 15μ H, Cin=1μ F, Tamb=25° C
-10
-20
Gain=24dB
Gain=6dB
-50
Vcc=2.5V
CMRR (dB)
CMRR(dB)
1k
0
Δ Vicm=200mVpp, F = 217Hz
RL ≥ 4Ω + ≥ 15μ H, Tamb = 25° C
-20
Vcc=3V
Vcc=5V
-30
-40
-60
-70
-70
0.5
1.0 1.5 2.0 2.5 3.0 3.5 4.0
Common Mode Input Voltage (V)
4.5
5.0
Gain=24dB
Gain=6dB
-50
-60
-80
0.0
100
Gain=6dB
Figure 15. CMRR vs. frequency
0
-40
5.5
Frequency (Hz)
Figure 14. CMRR vs. common mode input
voltage
-30
5.0
-30
-60
-10
3.5
4.0
4.5
Power Supply Voltage (V)
Inputs grounded, Vripple = 200mVpp
RL ≥ 4Ω + ≥ 15μ H, Cin=1μ F, Tamb=25° C
Vcc = 2.5, 3.6, 5V
-10
-30
-80
0.0
3.0
0
Vripple = 200mVpp, F = 217Hz
RL ≥ 4Ω + ≥ 15μ H, Tamb = 25° C
-20
-40
THD+N=1%
Figure 13. PSRR vs. frequency
0
-10
THD+N=10%
0.4
0.5
0.0
2.5
RL = 8Ω + ≥ 15μ H
F = 1kHz
BW < 30kHz
Tamb = 25° C
-80
20
100
1k
10k
20k
Frequency (Hz)
DocID14236 Rev 2
15/29
29
Electrical characteristics
TS2012
Figure 16. Gain vs. frequency (i)
Figure 17. Gain vs. frequency (ii)
26
8
no load
no load
24
4
Gain (dB)
Gain (dB)
6
RL=8Ω +15μ H
22
RL=8Ω +15μ H
RL=8Ω +30μ H
RL=8Ω +30μ H
Gain = 6dB
Vin = 500mV
Cin = 4.7μ F
TAMB = 25° C
2
0
20
RL=4Ω +15μ H
RL=4Ω +30μ H
100
1k
Frequency (Hz)
10k
20k
18
Vcc=3.6V
THD + N (%)
THD + N (%)
Vcc=5V
Vcc=2.5V
1k
10k
20k
1
RL = 4Ω + 30μ H
F = 1kHz
G = 6dB
BW < 30kHz
Tamb = 25° C
Vcc=5V
Vcc=3.6V
Vcc=2.5V
0.1
1E-3
0.01
0.1
Output Power (W)
1
1E-3
3
Figure 20. THD+N vs. output power (iii)
0.01
0.1
Output Power (W)
1
3
Figure 21. THD+N vs. output power (iv)
10
10
RL = 8Ω + 15μ H
F = 1kHz
G = 6dB
BW < 30kHz
Tamb = 25° C
Vcc=5V
Vcc=3.6V
THD + N (%)
THD + N (%)
100
10
RL = 4Ω + 15μ H
F = 1kHz
G = 6dB
BW < 30kHz
Tamb = 25° C
0.1
Vcc=2.5V
0.1
1E-3
16/29
RL=4Ω +30μ H
Figure 19. THD+N vs. output power (ii)
10
1
20
RL=4Ω +15μ H
Frequency (Hz)
Figure 18. THD+N vs. output power (i)
1
Gain = 24dB
Vin = 5mV
Cin = 4.7μ F
TAMB = 25° C
20
1
RL = 8Ω + 30μ H
F = 1kHz
G = 6dB
BW < 30kHz
Tamb = 25° C
Vcc=5V
Vcc=3.6V
Vcc=2.5V
0.1
0.01
0.1
Output Power (W)
1
2
1E-3
DocID14236 Rev 2
0.01
0.1
Output Power (W)
1
2
TS2012
Electrical characteristics
Figure 22. THD+N vs. output power (v)
Figure 23. THD+N vs. output power (vi)
10
RL = 4Ω + 15μ H
F = 100Hz
G = 6dB
BW < 30kHz
Tamb = 25° C
1
Vcc=3.6V
Vcc=2.5V
0.01
1E-3
0.01
0.1
Output Power (W)
1
0.01
1E-3
3
Figure 24. THD+N vs. output power (vii)
Vcc=2.5V
0.01
0.1
Output Power (W)
Vcc=5V
RL = 8Ω + 30μ H
F = 100Hz
G = 6dB
BW < 30kHz
Tamb = 25° C
Vcc=3.6V
THD + N (%)
1
Vcc=2.5V
3
1
Vcc=5V
Vcc=3.6V
Vcc=2.5V
0.1
0.01
1E-3
0.01
0.1
Output Power (W)
1
0.01
1E-3
2
Figure 26. THD+N vs. frequency (i)
0.01
0.1
Output Power (W)
1
2
Figure 27. THD+N vs. frequency (ii)
10
10
Po=0.4W
RL=4Ω + 30μ H
G=6dB
BW < 30kHz
Vcc=2.5V
Tamb = 25° C
1
THD + N (%)
RL=4Ω + 15μ H
G=6dB
BW < 30kHz
Vcc=2.5V
Tamb = 25° C
0.1
Po=0.4W
0.1
Po=0.2W
Po=0.2W
0.01
1
10
RL = 8Ω + 15μ H
F = 100Hz
G = 6dB
BW < 30kHz
Tamb = 25° C
0.1
THD + N (%)
Vcc=3.6V
Figure 25. THD+N vs. output power (viii)
10
THD + N (%)
1
Vcc=5V
0.1
0.1
1
RL = 4Ω + 30μ H
F = 100Hz
G = 6dB
BW < 30kHz
Tamb = 25° C
Vcc=5V
THD + N (%)
THD + N (%)
10
20
100
1000
Frequency (Hz)
10000 20k
0.01
20
DocID14236 Rev 2
100
1000
Frequency (Hz)
10000 20k
17/29
29
Electrical characteristics
TS2012
Figure 28. THD+N vs. frequency (iii)
Figure 29. THD+N vs. frequency (iv)
10
10
RL=8Ω + 15μ H
G=6dB
BW < 30kHz
Vcc=2.5V
Tamb = 25° C
Po=0.2W
1
THD + N (%)
THD + N (%)
1
RL=8Ω + 30μ H
G=6dB
BW < 30kHz
Vcc=2.5V
Tamb = 25° C
0.1
Po=0.2W
0.1
Po=0.1W
0.01
20
100
Po=0.1W
10000 20k
1000
Frequency (Hz)
0.01
Figure 30. THD+N vs. frequency (v)
100
1000
Frequency (Hz)
10000 20k
Figure 31. THD+N vs. frequency (vi)
10
10
RL=4Ω + 30μ H
G=6dB
BW < 30kHz
Vcc=3.6V
Tamb = 25° C
Po=0.9W
1
THD + N (%)
RL=4Ω + 15μ H
G=6dB
BW < 30kHz
Vcc=3.6V
Tamb = 25° C
1
THD + N (%)
20
0.1
Po=0.9W
0.1
Po=0.45W
Po=0.45W
0.01
20
100
1000
Frequency (Hz)
10000 20k
0.01
Figure 32. THD+N vs. frequency (vii)
1000
Frequency (Hz)
RL=8Ω + 30μ H
G=6dB
BW < 30kHz
Vcc=3.6V
Tamb = 25°C
Po=0.5W
1
0.1
Po=0.5W
0.1
Po=0.25W
0.01
18/29
10000 20k
10
RL=8Ω + 15μ H
G=6dB
BW < 30kHz
Vcc=3.6V
Tamb = 25°C
THD + N (%)
THD + N (%)
100
Figure 33. THD+N vs. frequency (viii)
10
1
20
20
100
1000
Frequency (Hz)
10000 20k
Po=0.25W
0.01
20
DocID14236 Rev 2
100
1000
Frequency (Hz)
10000 20k
TS2012
Electrical characteristics
Figure 34. THD+N vs. frequency (ix)
Figure 35. THD+N vs. frequency (x)
10
10
THD + N (%)
1
Po=1.5W
RL=4Ω + 30μ H
G=6dB
BW < 30kHz
Vcc=5V
Tamb = 25° C
1
THD + N (%)
RL=4Ω + 15μ H
G=6dB
BW < 30kHz
Vcc=5V
Tamb = 25° C
0.1
Po=1.5W
0.1
Po=0.75W
0.01
20
100
1000
Frequency (Hz)
Po=0.75W
0.01
10000 20k
20
Figure 36. THD+N vs. frequency (xi)
1000
Frequency (Hz)
10
RL=8Ω + 30μ H
G=6dB
BW < 30kHz
Vcc=5V
Tamb = 25° C
Po=0.9W
1
THD + N (%)
RL=8Ω + 15μ H
G=6dB
BW < 30kHz
Vcc=5V
Tamb = 25° C
1
0.1
Po=0.9W
0.1
Po=0.45W
0.01
20
100
1000
Frequency (Hz)
Po=0.45W
0.01
10000 20k
Figure 38. Crosstalk vs. frequency (i)
0
0
R -> L
-60
-80
-100
-120
100
1k
10k
1000
Frequency (Hz)
10000 20k
-40
-60
R -> L
-80
-100
L -> R
20
100
Vcc=2.5, 3.6, 5V
RL=8Ω +30μ H
Gain = 6dB
TAMB = 25° C
-20
Crosstalk (dB)
-40
20
Figure 39. Crosstalk vs. frequency (ii)
Vcc=2.5, 3.6, 5V
RL=4Ω +30μ H
Gain = 6dB
TAMB = 25° C
-20
Crosstalk (dB)
10000 20k
Figure 37. THD+N vs. frequency (xii)
10
THD + N (%)
100
L -> R
20k
-120
20
Frequency (Hz)
100
1k
10k
20k
Frequency (Hz)
DocID14236 Rev 2
19/29
29
Electrical characteristics
Figure 40. Crosstalk vs. frequency (iii)
Figure 41. Crosstalk vs. frequency (iv)
0
0
Vcc = 2.5, 3.6, 5V
RL = 4Ω +30μ H
Gain = 24dB
TAMB = 25° C
-40
R -> L
-60
-80
-100
QFN20 Package Power Dissipation (W)
-120
100
1k
10k
-40
R -> L
-60
-80
-100
L -> R
20
Vcc=2.5, 3.6, 5V
RL=8Ω +30μ H
Gain = 24dB
TAMB = 25° C
-20
Crosstalk (dB)
-20
Crosstalk (dB)
TS2012
20k
-120
L -> R
20
Figure 43. Startup and shutdown phase (i)
With 4-layer PCB
2.5
2.0
No Heat sink
1.5
1.0
0.5
25
50
75
100
Ambient Temperature (° C)
125
150
Figure 44. Startup and shutdown phase (ii)
20/29
10k
Figure 42. Power derating curves
3.0
0
1k
Frequency (Hz)
3.5
0.0
100
Frequency (Hz)
DocID14236 Rev 2
20k
TS2012
Application information
4
Application information
4.1
Differential configuration principle
The TS2012 is a monolithic fully-differential input/output class D power amplifier. The
TS2012 also includes a common-mode feedback loop that controls the output bias value to
average it at VCC/2 for any DC common mode input voltage. This allows the device to
always have a maximum output voltage swing, and by consequence, maximize the output
power. Moreover, as the load is connected differentially compared with a single-ended
topology, the output is four times higher for the same power supply voltage.
The advantages of a full-differential amplifier are:
4.2
•
High PSRR (power supply rejection ratio)
•
High common mode noise rejection
•
Virtually zero pop without additional circuitry, giving a faster startup time compared with
conventional single-ended input amplifiers
•
Easier interfacing with differential output audio DAC
•
No input coupling capacitors required thanks to common mode feedback loop
Gain settings
In the flat region of the frequency-response curve (no input coupling capacitor or internal
feedback loop + load effect), the differential gain can be set to 6, 12 18, or 24 dB depending
on the logic level of the G0 and G1 pins, as shown in Table 9.
Table 9. Gain settings with G0 and G1 pins
G1
G0
Gain (dB)
Gain (V/V)
0
0
6
2
0
1
12
4
1
0
18
8
1
1
24
16
Note:
Between pins G0, G1 and GND there is an internal 300 kΩ (±20 %) resistor. When the pins
are floating, the gain is 6 dB. In full standby (left and right channels OFF), these resistors are
disconnected (HiZ input).
4.3
Common mode feedback loop limitations
The common mode feedback loop allows the output DC bias voltage to be averaged at
VCC/2 for any DC common mode bias input voltage.
Due to the Vic limitation of the input stage (see Table 2: Operating conditions), the common
mode feedback loop can fulfill its role only within the defined range.
DocID14236 Rev 2
21/29
29
Application information
4.4
TS2012
Low frequency response
If a low frequency bandwidth limitation is required, it is possible to use input coupling
capacitors. In the low frequency region, the input coupling capacitor, Cin, starts to have an
effect. Cin, with the input impedance Zin, forms a first order, high-pass filter with a -3 dB cutoff frequency (see Table 5 to Table 7) as shown in Equation 1:
Equation 1
1
F CL = -------------------------------------------2 ⋅ π ⋅ Z in ⋅ C in
So, for a desired cut-off frequency, FCL, Cin is calculated as shown in Equation 2:
Equation 2
1
C in = ---------------------------------------------2 ⋅ π ⋅ Z in ⋅ F CL
with FCL in Hz, Zin in Ω and Cin in F.
The input impedance Zin is typically 30 kΩ for the whole power supply voltage range. There
is also a tolerance around the typical value (see Table 5 to Table 7). The maximum and
minimum tolerance of the FCL can be calculated using Equation 3 and Equation 4
respectively.
Equation 3
F CLmax = 1.103 ⋅ F CL
Equation 4
F CLmin = 0.915 ⋅ FCL
4.5
Decoupling of the circuit
Power supply capacitors, referred to as CS, CSL, and CSR are needed to correctly bypass
the TS2012.
The TS2012 has a typical switching frequency of 280 kHz and an output fall and rise time of
about 5 ns. Due to these very fast transients, careful decoupling is mandatory.
A 1 µF ceramic capacitor between each PVCC and PGND and also between AVCC and
AGND is enough, but they must be located very close to the TS2012 in order to avoid any
extra parasitic inductance created by a long track wire. Parasitic loop inductance, in relation
to di/dt, introduces overvoltage that decreases the global efficiency of the device and may
also cause a TS2012 breakdown if the parasitic inductance is too high.
In addition, even if a ceramic capacitor has an adequate high frequency ESR value, its
current capability is also important. A 0603 size is a good compromise, particularly when a
4 Ω load is used.
22/29
DocID14236 Rev 2
TS2012
Application information
Another important parameter is the rated voltage of the capacitor. A 1 µF/6.3 V capacitor
used at 5 V, loses about 50 % of its value. With a power supply voltage of 5 V, the
decoupling value, instead of 1 µF, could be reduced to 0.5 µF. As CS has particular influence
on the THD+N in the medium to high frequency region, this capacitor variation becomes
decisive. In addition, less decoupling means higher overshoots which can be problematic if
they reach the power supply AMR value (6 V).
4.6
Wakeup time (twu)
When standby is released to set the device ON, there is typically a delay of 1 ms. The
TS2012 has an internal digital delay that mutes the outputs and releases them after this
delay time to avoid any pop noise.
Note:
The gain increases smoothly (see Figure 44) from the mute to the gain selected by the G1
and G0 pin (Section 4.2).
4.7
Shutdown time
When the standby command is set, the time required to set the output stage to high
impedance and to put the internal circuitry in shutdown mode, is typically 1 ms. This time is
used to decrease the gain and avoid any pop noise during shutdown.
Note:
The gain decreases smoothly until the outputs are muted (see Figure 44).
4.8
Consumption in shutdown mode
Between the shutdown pin and GND there is an internal 300 kΩ (±20 %) resistor. This
resistor forces the TS2012 to be in shutdown when the shutdown input is left floating.
However, this resistor also introduces additional shutdown power consumption if the
shutdown pin voltage is not 0 V.
For example, with a 0.4 V shutdown voltage pin, the following typical and maximum values
respectively for each shutdown pin must be added to the standby current specified in
Table 5 to Table 7: 0.4 V/300 kΩ = 1.3 µA and 0.4 V/240 kΩ = 1.66 µA. This current is
provided by the external control device for standby pins.
DocID14236 Rev 2
23/29
29
Application information
4.9
TS2012
Single-ended input configuration
It is possible to use the TS2012 in a single-ended input configuration. However, input
coupling capacitors are mandatory in this configuration. The schematic diagram in Figure 45
shows a typical single-ended input application.
Figure 45. Typical application for single-ended input configuration
Cs
VCC
100nF
CsL
1μ F
VCC VCC
CsR
1μ F
Gain Select
Control
Cin
LIN +
PVCC
AVCC
Cin
PVCC
TS2012
Left Input
Gain
H
PWM
Select
LIN -
Bridge
LOUT+
LOUT-
Left speaker
G0
Oscillator
G1
RIN +
H
PWM
Select
STBY L
STBY R
Bridge
ROUT+
ROUT-
Right speaker
Standby
Control
PGND
Cin
Gain
RIN -
PGND
Cin
AGND
Right Input
Standby Control
4.10
Output filter considerations
The TS2012 is designed to operate without an output filter. However, due to very sharp
transients on the TS2012 output, EMI radiated emissions may cause some standard
compliance issues.
These EMI standard compliance issues can appear if the distance between the TS2012
outputs and the loudspeaker terminal are long (typically more than 50 mm or 100 mm, in
both directions, to the speaker terminals). As the PCB layout and internal equipment device
are different for each configuration, it is difficult to provide a one-size-fits-all solution.
However, to decrease the probability of EMI issues, the following simple rules should be
followed:
24/29
•
Reduce as much as possible the distance between the TS2012 output pins and the
speaker terminals.
•
Use a ground plane for “shielding” sensitive wires.
•
Place, as close as possible to the TS2012 and in series with each output, a ferrite bead
with a minimum rated current of 2.5 A and an impedance greater than 50 Ω at
frequencies above 30 MHz. If, after testing, these ferrite beads are not necessary,
replace them by a short-circuit.
•
Allow extra footprint to place, if necessary, a capacitor to short perturbations to ground
(see Figure 46).
DocID14236 Rev 2
TS2012
Application information
Figure 46. Ferrite chip bead placement
From output
Ferrite chip bead
to speaker
about 100pF
gnd
If the distance between the TS2012 output and the speaker terminals is too long, it is
possible to have low frequency EMI issues due to the fact that the typical operating
frequency is 280 kHz. In this configuration, it is necessary to place the output filter shown in
Figure 1: Typical application schematics as close as possible to the TS2012.
DocID14236 Rev 2
25/29
29
Package information
5
TS2012
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
5.1
QFN20 package information
The QFN20 package has an exposed pad E2 x D2. For enhanced thermal performance, the
exposed pad must be soldered to a copper area on the PCB, acting as a heatsink. This
copper area can be electrically connected to pin 4, 12, 18 (PGND, AGND) or left floating.
Figure 47. QFN20 package mechanical drawing
26/29
DocID14236 Rev 2
TS2012
Package information
Table 10. QFN20 package mechanical data
Dimensions in mm
Dimensions in inches
Ref
Min
Typ
Max
Min
Typ
Max
0.8
0.9
1
0.031
0.035
0.039
A1
0.02
0.05
0.001
0.002
A2
0.65
1
0.026
0.039
A3
0.25
A
0.010
b
0.18
0.23
0.3
0.007
0.009
0.012
D
3.85
4
4.15
0.152
0.157
0.163
D2
2.6
E
3.85
E2
0.102
4
4.15
0.152
2.6
0.157
0.163
0.102
e
0.45
0.5
0.55
0.018
0.020
0.022
L
0.3
0.4
0.5
0.012
0.016
0.020
ddd
0.08
0.003
Figure 48. QFN20 footprint recommendation
Table 11. QFN20 footprint data
Ref.
Dimensions in mm
Dimensions in inches
4.55
0.179
C
0.50
0.020
D
0.35
0.014
E
0.65
0.026
F
2.45
0.096
G
0.40
0.016
A
B
DocID14236 Rev 2
27/29
29
Ordering information
6
TS2012
Ordering information
Table 12. Order code
Part number
TS2012IQT
7
Temperature range
Package
Packaging
Marking
-40 °C to +85 °C
QFN20
Tape and reel
K012
Revision history
Table 13. Document revision history
Date
Revision
17-Dec-2007
1
First release.
2
Small text changes throughout document.
Updated titles of Figure 6 to Figure 11 and Figure 16 to Figure 44
Table 10: QFN20 package mechanical data: added package
mechanical dimensions in inches.
Added Table 11: QFN20 footprint data
Table 12: Order code; updated “Marking”
17-Jul-2013
28/29
Changes
DocID14236 Rev 2
TS2012
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