TS652IDT

TS652 DIFFERENTIAL VARIABLE GAIN AMPLIFIER ■ LOW NOISE : 4.6nV/√Hz ■ LOW DISTORTION ■ HIGH SLEW RATE : 90V/µs ■ WIDE BANDWIDTH : 52MHz @ -3dB & 18dB gain ■ GAIN PROGRAMMABLE from -9dB to +30dB with 3dB STEPS ■ POWER DOWN FUNCTION D SO-14 (Plastic Micropackage) c u d o r DESCRIPTION The gain can be set from -9dB to +30dB through a 4bit digital word, with 3dB steps. l o bs PIN CONNECTIONS (top view) O ) The gain monotonicity is guaranteed by design. s ( t c u d This device is particularly intended for applications such as preamplification in telecommunication systems using multiple carriers. o r eP APPLICATION ■ Preamplifier and automatic gain control for t e ol P e et +Vcc1 1 14 +Vcc2 Input 1 2 13 Output 1 Input 2 3 12 Output 2 LSB GC1 Assymetric Digital Subscriber Line (ADSL). s b O GC2 5 ORDER CODE Part Number TS652ID Package Temperature Range GC3 6 D -40, +85°C • MSB GC4 11 Power Down 4 7 Gain Control Logic Decoder The TS652 is a differential digitally controled variable gain amplifier featuring a high slew rate of 90V/µs, a large bandwidth, a very low distortion and a very low current and voltage noise. ) s t( 10 -Vcc 9 AGND 8 DGND D = Small Outline Package (SO) - also available in Tape & Reel (DT) October 2001 1/9 TS652 ABSOLUTE MAXIMUM RATINGS Symbol VCC Vi Parameter Supply voltage Input Voltage 1) 2) Value Unit 14 V 0 to 14 V °C Toper Operating Free Air Temperature Range TS652ID -40 to + 85 Tstd Storage Temperature -65 to +150 °C 150 °C Tj Maximum Junction Temperature Rthjc Thermal Resistance Junction to Case 22 °C/W Rthja Thermal Resistance Junction to Ambiante Area 125 °C/W Output Short Circuit Duration Infinite 1. All voltages values are with respect to network terminal. 2. The magnitude of input and output voltages must never exceed VCC +0.3V. OPERATING CONDITIONS Symbol Parameter VCC Supply Voltage Vicm Common Mode Input Voltage 5 to 12 c u d o r VCC/2 l o bs O ) s ( t c u d o r eP t e ol s b O 2/9 ) s t( Value P e et Unit V V TS652 ELECTRICAL CHARACTERISTICS. VCC = ±6Volts, Tamb = 25°C (unless otherwise specified). Symbol Parameter Test Condition Min. Typ. Max Unit DC PERFORMANCE Vi ICC ∆VOFFSET SVR Voltage on the Input Pin Total Supply Current Differential Input Offset Voltage Supply Voltage Rejection Ratio No load, Vout = 0 Vin = 0, AV = 30dB AV = 0dB 0 28 6 V mA mV dB 50 80 2 0 3.3 100kΩ 150kΩ//5pF POWER DOWN MODE Vpdw Iccpdw Zout Thershold Voltage for Power Down Mode (high level active) Power Down Total Consumption Power Down Output Impedance Low Level High Level Power Down Mode Power Down Mode 0.8 150 V V µA AC PERFORMANCE Zin VOH VOL AV PAV Avstep Avmin Bw Rbw Io SR Input Impedance High Level Output Voltage RL = 500Ω RL connected to GND Low Level Output Voltage RL = 500Ω RL connected to GND Voltage Gain F= 1MHz Gain monotonicity guaranteed by design Precision of the Voltage Gain F= 1MHz Step Value F= 1MHz Gain Mismatch between Both F= 1MHz Channels AV = -9dB Bandwidth @ -3dB AV = 0dB RL = 500Ω AV = +18dB CL = 15pF AV = +30dB AV = +30dB, F = 1MHz Bandwidth Roll-off |Source| Bandwidth @ -3dB RL = 500Ω, CL = 15pF Sink Vo = 2Vpeak Slew Rate (gain independent) l o bs NOISE AND DISTORTION c u d in Equivalent Input Noise Current en Equivalent Input Noise Voltage o r eP t e l o s THD30 Ob IM3 Harmonic Distorsion Third Order Intermodulation Product F1 = 180kHz, F2 = 280kHz IM3 Third Order Intermodulation Product F1 = 70kHz, F2 = 80kHz O ) t(s F = 100kHz F = 100kHz AV = 30dB 1Vpeak, F = 150kHz, AV = +30dB, RL = 500Ω//15pF H2 H3 H4 H5 Vout = 1Vpeak, AV = +30dB RL = 500Ω//15pF @ 80kHz @ 380kHz @640kHz @740kHz Vout = 1Vpeak, AV = +30dB RL = 500Ω//15pF @ 60kHz @ 90kHz @220kHz @230kHz 100kΩ//5pF 4 4.5 -4.5 -9 P e et 17 17 50 ) s t( -4 30 c u d o r -1 2.4 55 32 26 10 V 3 110 69 52 18 0.08 28 22 100 1 3.6 V dB dB dB 1 dB 200 132 100 36 MHz dB mA V/µs 1.5 pA/√Hz 4.6 nV/√Hz -70 -93 -98 -99 -77 -85 -86 -87 -77 -79 -83 -84 dBc dBc dBc 3/9 TS652 DIGITAL INPUTS Symbol Parameter GC1, GC2, GC3 and GC4 Min. Typ. Max. 0 0.8 Low Level High Level 2 Unit V 3.3 SIMPLIFIED SCHEMATIC The TS652 consists of two independent channels. Each channel has two stages. The first is a very low noise digitally controlled variable gain amplifier (range 0 to 18dB). The TS652 features a high input impedance and a low noise current. To minimize the overall noise figure, the source impedance must be less than 3kΩ. This value gives an equal contribution of voltage and current noises. The second stage is a gain/attenuation stage (+12dB to -9dB) featuring a low output impedance. This output stage can drive loads as low as 500Ω. ) s t( v Input1 _ + Ouput1 _ c u d o r + +Vcc1 -Vcc v P e et Analog GND (AGND) v _ _ Input2 ) s t( c du o r eP Ouput2 -O vv Power Down l o bs + + +Vcc2 GC1 GC2 GC3 GC4 GAIN CONTROL LOGIC DECODER Digital GND (DGND) POWER DOWN MODE POSITION t e ol +Vcc +Vcc s b O Power Down Input Output -Vcc 4/9 -Vcc TS652 BANDWIDTH The small signal bandwidth is almost constant for gains between +18dB to 0dB and is in the order of 52MHz to 70MHz respectively. For 30dB gain the bandwidth is around 18MHz. The power bandwidth is typically equal to 30MHz for 2V peak to peak signals. MAXIMUM INPUT LEVEL The input level must not exceed the following values : negative peak value: must be greater than -VCC + 1.5V positive peak value: must be less than +V CC - 1.5V For example, if a ±6V power supply is used, the input signal can swing between -4.5V and +4.5V. These values are due to common mode input range limitations of the input stage of the first amplifier. Some other limitations may occur, due to the slew rate of the first operational amplifier (typically in the order of 300V/µs). This means that the maximum input signal decreases at high frequency. ) s t( SINGLE SUPPLY OPERATION c u d o r The incoming signal is AC coupled to the inputs. The TS652 can be used either with a dual or a single supply. If a single supply is used, the inputs are biased to the mid supply voltage (+VCC/2). This bias network must be carefully designed, in order to reject any noise present on the supply rail. l o bs P e et The AGND pin (9) must be connected to +VCC/2. The bias current of the second stage (inverting structure) is 8µA for both amplifiers. A resistor divider structure can be used. Two resistances should be chosen by considering 8µA as the 1% of the total current through these resistances. For a single +12V supply voltage, two resistances of 7.5kΩ can be used. The differential input consists of a high pass circuit, formed by the 1µF capacitor and a 1kΩ resistance and gives a break frequency of 160Hz. s ( t c u d SINGLE +12V SUPPLY OF THE TS652 o r eP 1µF t e l o s IN+ Ob O ) 10nF 100nF TS652 12V +Vcc1 1 14 +Vcc2 1k 47k Input 1 13 Output 1 1k 47k 2 Input 2 3 1µF GC2 5 INGC3 6 1µF GC4 7 10nF 100nF 10µF Output 2 11 Power Down GC1 4 Gain Control Logic Decoder 10nF 12 12V 12V 10 -Vcc 7.5k 9 AGND 8 DGND 10nF 7.5k 1µF 5/9 TS652 GAIN CONTROL The gain and the power down mode is programmed with a 4 bit digital word : Digital Control Total Gain (dB) First Stage Gain (dB) Second Stage Gain (dB) Maximum Input Level Bandwidth Small Signal Eq. Input Noise (nV/√Hz) $0000 -9 0 -9 2.8Vrms 110mHZ 29 $0001 -6 0 -6 2.8Vrms 100MHz 26 $0010 -3 0 -3 2.8Vrms 85MHz 23 $0011 0 0 0 2.8Vrms 69MHz 22 $0100 3 3 0 2Vrms 63MHz 16 $0101 6 6 0 1.4Vrms 58MHz 12 $0110 9 9 0 1Vrms 56MHz 9 $0111 12 12 0 0.7Vrms 55MHz $1000 15 15 0 0.5Vrms 54MHz $1001 18 18 0 0.35Vrms 52MHz $1010 21 21 3 0.25Vrms 42MHz 4.7 $1011 24 24 6 175mVrms 30MHz 4.7 $1100 27 27 9 125mVrms 24MHz 4.6 $1101 30 30 12 88mVrms 18MHz 4.6 $1110 30 30 12 88mVrms 18MHz 4.6 $1111 30 30 12 18MHz 4.6 GC4....GC1 MSB LSB O ) eP let o s b 88mVrms c u d o r ) s t( 7 6 4.8 The gain is the same for both channels. The digital inputs are CMOS compatible. The supply voltage of the logic decoder used to transcode the digital word can be either 3.3V or 5V or VCC. s ( t c u d o r eP t e ol s b O 6/9 TS652 Bandwidth vs Gain Closed Loop Gain vs Frequency 100 30 90 BANDWIDTH (MHz) 40 20 Gain (dB) 10 0 -10 -20 80 70 60 50 40 30 20 -30 10 -40 10kHz 100kHz 1MHz 10MHz -9 100MHz -6 -3 0 3 Frequency VOLTAGE NOISE (nV/VHz) SLEW RATE (V/µs) 105 SR- 95 SR+ 90 85 75 70 -3 0 3 6 9 12 15 18 21 24 27 30 GAIN (dB) c u d Gain Switching (+15dB to -9dB) ) s t( o r eP 6 -O -3 0 3 6 9 12 15 18 21 24 27 30 Gain Switching (+30dB to +9dB) GC1 command 5 4 2 1 0 -1 3 2 1 0 -1 Ouput Signal -2 -2 Ouput Signal -3 -4 -6 GAIN (dB) Ouput Signal (V) Ouput Signal (V) Ob 3 P e et 6 t e l o s 4 c u d o r -9 GC4 command 5 ) s t( 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 l o bs 80 -6 12 15 18 21 24 27 30 Equivalent Input Voltage Noise vs Gain 110 -9 9 GAIN (dB) Negative & Positive Slew Rate vs Gain 100 6 -3 0 5µs 10µs 15µs 20µs Time -4 0 5µs 10µs 15µs 20µs Time measurement conditions: Vcc=±6V, Rload=500Ω, Tamb=25°C 7/9 TS652 Output/Input Isolation in Power Down Mode vs Frequency 3rd Order Intermodulation (2 tones : 180kHz and 280kHz) -70 -50 -60 80kHZ IM3 (dBc) Isolation (dB) -75 -70 -80 -80 -90 380kHZ -85 640kHZ -100 740kHZ -110 -90 10kHz 100kHz 1MHz 0 10MHz 1 Frequency 2 3 4 5 Vout peak (V) 3rd Order Intermodulation (2 tones : 180kHz and 280kHz) ) s t( c u d o r -70 l o bs -75 P e et ) s t( c du -O o r eP t e ol s b O measurement conditions: Vcc=±6V, Rload=500Ω, Tamb=25°C 8/9 IM3 (dBc) 60kHZ 90kHZ -80 220kHZ -85 230kHZ -90 0 1 2 3 Vout peak (V) 4 5 TS652 PACKAGE MECHANICAL DATA 14 PINS - PLASTIC MICROPACKAGE (SO) G c1 s e3 b1 e a1 b A a2 C L E D M 8 1 7 F 14 Millimeters c u d o r Inches Dimensions Min. A a1 a2 b b1 C c1 D (1) E e e3 F (1) G L M S Typ. Max. Min. 1.75 0.2 1.6 0.46 0.25 0.1 0.35 0.19 l o bs Typ. P e et 0.004 0.014 0.007 0.5 O ) ) s t( Max. 0.069 0.008 0.063 0.018 0.010 0.020 45° (typ.) 8.55 5.8 s ( t c u d 1.27 7.62 3.8 4.6 0.5 t e l o s o r eP 8.75 6.2 4.0 5.3 1.27 0.68 0.336 0.228 0.344 0.244 0.050 0.300 0.150 0.181 0.020 0.157 0.208 0.050 0.027 8° (max.) Note : (1) D and F do not include mold flash or protrusions - Mold flash or protrusions shall not exceed 0.15mm (.066 inc) ONLY FOR DATA BOOK. Ob Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2001 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom © http://www.st.com 9/9