TSZ182IQ2T

TSZ181, TSZ182 Datasheet Very high accuracy (25 µV) high bandwidth (3 MHz) zero drift 5 V operational amplifiers Features • DFN6 1.2x1.3 (TSZ181) DFN8 2x2 (TSZ182) SOT23-5 (TSZ181) MiniSO8 (TSZ182) SO8 (TSZ182) • • • • • • • • Very high accuracy and stability: offset voltage 25 µV max. at 25 °C, 35 µV over full temperature range (-40 °C to 125 °C) Rail-to-rail input and output Low supply voltage: 2.2 - 5.5 V Low power consumption: 1 mA max. at 5 V Gain bandwidth product: 3 MHz Automotive qualification Extended temperature range: -40 to 125 °C Micropackages: DFN8 2x2, SO8 and MiniSO8 Benefits: – Higher accuracy without calibration – Accuracy virtually unaffected by temperature change Applications • • • High accuracy signal conditioning Automotive current measurement and sensor signal conditioning Medical instrumentation Description Maturity status link TSZ181 TSZ182 Related products TSZ121 TSZ122 TSZ124 TSV711 TSV731 For zero drift amplifiers with more power savings (400 kHz for 40 μA) The TSZ181, TSZ182 are single and dual operational amplifiers featuring very low offset voltages with virtually zero drift versus temperature changes. The TSZ181, TSZ182 offer rail-to-rail input and output, excellent speed/power consumption ratio, and 3 MHz gain bandwidth product, while consuming just 1 mA at 5 V. The device also features an ultra-low input bias current. These features make the TSZ18x ideal for high-accuracy high-bandwidth sensor interfaces. For continuous-time precision amplifiers DS11863 - Rev 5 - August 2018 For further information contact your local STMicroelectronics sales office. www.st.com TSZ181, TSZ182 Package pin connections 1 Package pin connections Figure 1. Pin connections for each package (top view) SOT23-5 (TSZ181) DFN6 1.2x1.3 (TSZ181) DFN8 2x2 (TSZ182) 1. DS11863 - Rev 5 MiniSO8 and SO8 (TSZ182) The exposed pad of the DFN8 2x2 can be connected to VCC- or left floating. page 2/43 TSZ181, TSZ182 Absolute maximum ratings and operating conditions 2 Absolute maximum ratings and operating conditions Table 1. Absolute maximum ratings (AMR) Symbol Parameter VCC Supply voltage Value (1) 6 Vid Differential input voltage (2) ±VCC Vin Input voltage (3) (VCC -) - 0.2 to (VCC +) + 0.2 Iin Input current (4) 10 Tstg Storage temperature -65 to 150 Tj Maximum junction temperature 150 Rthja DFN8 2x2 57 DFN6 1.2x1.3 232 SOT23-5 250 MiniSO8 190 SO8 125 Thermal resistance junction-to-ambient (5) (6) ESD Unit HBM: human body model (7) 4 CDM: charged device model (8) 1.5 Latch-up immunity 200 V mA °C °C/W kV mA 1. All voltage values, except differential voltage, are with respect to network ground terminal. 2. The differential voltage is the non-inverting input terminal with respect to the inverting input terminal. 3. VCC - Vin must not exceed 6 V, Vin must not exceed 6 V. 4. Input current must be limited by a resistor in series with the inputs. 5. Rth are typical values. 6. Short-circuits can cause excessive heating and destructive dissipation. 7. Human body model: 100 pF discharged through a 1.5 kΩ resistor between two pins of the device, done for all couples of pin combinations with other pins floating. 8. Charged device model: all pins plus package are charged together to the specified voltage and then discharged directly to ground. Table 2. Operating conditions DS11863 - Rev 5 Symbol Parameter Value VCC Supply voltage 2.2 to 5.5 Vicm Common mode input voltage range (VCC -) - 0.1 to (VCC +) + 0.1 Toper Operating free-air temperature range -40 to 125 Unit V °C page 3/43 TSZ181, TSZ182 Electrical characteristics 3 Electrical characteristics Table 3. Electrical characteristics at V CC+ = 2.2 V with V CC- = 0 V, Vicm = V CC/2, T = 25 °C, and RL = 10 kΩ connected to V CC/2 (unless otherwise specified) Symbol Parameter Conditions Min. Typ. Max. 3.5 35 Unit DC performance Vio Input offset voltage ΔVio/ΔT Input offset voltage drift (1) Iib Input bias current (Vout = VCC/2) Iio Input offset current (Vout = VCC/2) CMR1 Common-mode rejection ratio, 20 log (ΔVicm/ ΔVio), Vic = 0 V to VCC, Vout = VCC/2, RL > 1 MΩ CMR3 Common mode rejection ratio, 20 log (ΔVicm/ ΔVio), Vic = 1.1 V to VCC, Vout = VCC/2, RL > 1 MΩ Avd Large signal voltage gain, Vout = 0.5 V to (Vcc - 0.5 V) VOH High-level output voltage, VOH = Vcc - Vout VOL Low-level output voltage Isink (Vout = VCC) Iout Isource (Vout = 0 V) ICC Supply current (per channel, Vout = VCC/2, RL > 1 MΩ) T = 25 °C -40 °C < T< 125 °C 45 -40 °C < T< 125 °C 0.1 T = 25 °C 30 T = 25 °C 60 µV/°C 200 (2) 300 (2) -40 °C < T< 125 °C µV 400 (2) pA 600 (2) -40 °C < T< 125 °C T = 25 °C 96 -40 °C < T< 125 °C 94 T = 25 °C 102 -40 °C < T< 125 °C 100 T = 25 °C 112 -40 °C < T< 125 °C 100 T = 25 °C 115 120 dB 130 15 -40 °C < T< 125 °C 40 70 T = 25 °C 10 -40 °C < T< 125 °C 30 mV 70 T = 25 °C 4 -40 °C < T< 125 °C 2.5 T = 25 °C 3.5 -40 °C < T< 125 °C 2 T = 25 °C 6 4 0.7 -40 °C < T< 125 °C mA 1 1.2 AC performance T = 25 °C, RL = 10 kΩ, GBP Gain bandwidth product CL = 100 pF -40 °C < T< 125 °C, RL = 10 kΩ, CL = 100 pF Φm Phase margin Gm Gain margin SR Slew rate (3) ts Settling time DS11863 - Rev 5 1.6 MHz 1.2 RL = 10 kΩ, CL = 100 pF T = 25 °C 3 -40 °C < T< 125 °C 2.5 To 0.1%, Vin = 0.8 Vpp 2.3 59 degrees 16 dB 4.6 500 V/µs ns page 4/43 TSZ181, TSZ182 Electrical characteristics Symbol Parameter en Equivalent input noise voltage density en-pp Conditions Min. Typ. Max. Unit f = 1 kHz 50 f = 10 kHz 50 Voltage noise f = 0.1 to 10 Hz 0.6 µVpp Cs Channel separation f = 1 kHz 120 dB tinit Initialization time, G = 100 (4) T = 25 °C 60 -40 °C < T< 125 °C 100 nV/√Hz µs 1. See Section 5.5 Input offset voltage drift over temperature. Input offset measurements are performed on x100 gain configuration. The amplifiers and the gain setting resistors are at the same temperature. 2. Guaranteed by design. 3. Slew rate value is calculated as the average between positive and negative slew rates. 4. Initialization time is defined as the delay between the moment when supply voltage exceeds 2.2 V and output voltage stabilization Table 4. Electrical characteristics at VCC+ = 3.3 V with VCC- = 0 V, Vicm = VCC/2, T = 25 °C, and RL = 10 kΩ connected to VCC/2 (unless otherwise specified) Symbol Parameter Conditions Min. Typ. Max. 2 30 Unit DC performance Vio Input offset voltage ΔVio/ΔT Input offset voltage drift (1) Iib Input bias current (Vout = VCC/2) Iio Input offset current (Vout = VCC/2) T = 25 °C -40 °C < T< 125 °C 40 -40 °C < T< 125 °C 0.1 T = 25 °C T = 25 °C Common mode rejection ratio, 20 log (ΔVicm/ ΔVio), Vout = VCC/2, RL > 1 MΩ T = 25 °C Vic = 0 V to VCC, Vic = 0 V to VCC - 1.8 V, CMR2 T = 25 °C Vic = 0 V to VCC - 2 V, -40 °C < T< 125 °C Avd Large signal voltage gain, Vout = 0.5 V to (VCC - 0.5 V) VOH High-level output voltage, VOH = Vcc - Vout VOL DS11863 - Rev 5 Low-level output voltage 104 106 120 132 -40 °C < T< 125 °C 110 138 16 -40 °C < T< 125 °C -40 °C < T< 125 °C dB 106 120 T = 25 °C pA 102 T = 25 °C T = 25 °C 400 (2) 600 (2) -40 °C < T< 125 °C -40 °C < T< 125 °C Common mode rejection ratio, 20 log (ΔVicm/ ΔVio), Vout = VCC/2, RL > 1 MΩ 60 µV/°C 200 (2) 300 (2) -40 °C < T< 125 °C Vic = 0 V to VCC, CMR1 30 µV 40 70 11 30 mV 70 page 5/43 TSZ181, TSZ182 Electrical characteristics Symbol Parameter Isink (Vout = VCC) Iout Isource (Vout = 0 V) ICC Supply current (per channel, Vout = VCC/2, RL > 1 MΩ) Conditions Min. Typ. T = 25 °C 10 15 -40 °C < T< 125 °C 7.5 T = 25 °C 6 -40 °C < T< 125 °C 4 T = 25 °C Max. mA 11 0.7 -40 °C < T< 125 °C Unit 1 1.2 mA AC performance T = 25 °C, RL = 10 kΩ, GBP Gain bandwidth product CL = 100 pF -40 °C < T< 125 °C, RL = 10 kΩ, CL = 100 pF Φm Phase margin Gm Gain margin SR Slew rate (3) ts Settling time en Equivalent input noise voltage density en-pp 2 2.8 MHz 1.6 RL = 10 kΩ, CL = 100 pF T = 25 °C 2.6 -40 °C < T< 125 °C 2.1 56 degrees 15 dB 4.5 V/µs To 0.1%, Vin = 1.2 Vpp 550 f = 1 kHz 40 f = 10 kHz 40 Voltage noise f = 0.1 to 10 Hz 0.5 µVpp Cs Channel separation f = 1 kHz 120 dB tinit Initialization time, G = 100 (4) T = 25 °C 60 -40 °C < T< 125 °C 100 ns nV/√Hz µs 1. See Section 5.5 Input offset voltage drift over temperature. Input offset measurements are performed on x100 gain configuration. The amplifiers and the gain setting resistors are at the same temperature. 2. Guaranteed by design. 3. Slew rate value is calculated as the average between positive and negative slew rates. 4. Initialization time is defined as the delay between the moment when supply voltage exceeds 2.2 V and output voltage stabilization Table 5. Electrical characteristics at VCC+ = 5 V with VCC- = 0 V, Vicm = VCC/2, T = 25 °C, and RL = 10 kΩ connected to VCC/2 (unless otherwise specified) Symbol Parameter Conditions Min. Typ. Max. 1 25 Unit DC performance Vio Input offset voltage ΔVio/ΔT Input offset voltage drift (1) Iib Iio DS11863 - Rev 5 Input bias current (Vout = VCC//2) Input offset current (Vout = VCC/2) T = 25 °C -40 °C < T< 125 °C 35 -40 °C < T< 125 °C 0.1 T = 25 °C 30 -40 °C < T< 125 °C 60 µV/°C (2) 300 (2) -40 °C < T< 125 °C T = 25 °C 200 µV 400 (2) pA 600 (2) page 6/43 TSZ181, TSZ182 Electrical characteristics Symbol Parameter Conditions Vic = 0 V to VCC , CMR1 Common mode rejection ratio, 20 log (ΔVicm/ ΔVio), Vout = VCC/2, RL > 1 MΩ T = 25 °C Vic = 0 V to VCC -40 °C < T< 125 °C Vic = 0 V to VCC - 1.8 V, CMR2 Common mode rejection ratio, 20 log (ΔVicm/ ΔVio), Vout = VCC/2, RL > 1 MΩ T = 25 °C Vic = 0 V to VCC - 2 V, -40 °C < T< 125 °C SVR1 Supply voltage rejection ratio, 20 log (ΔVCC/ ΔVio), VCC = 2.2 to 5.5 V, Vic = 0 V, RL > 1 MΩ Avd Large signal voltage gain, Vout = 0.5 V to (Vcc - 0.5 V) EMIRR (3) VOH EMI rejection ratio, EMIRR = -20 log (VRFpeak/ ΔVio) High-level output voltage, VOH = Vcc - Vout VOL Low-level output voltage Isink (Vout = VCC) Iout Isource (Vout = 0 V) ICC Supply current (per channel, Vout = VCC/2, RL > 1 MΩ) Min. Typ. 108 126 Max. Unit 108 112 136 112 T = 25 °C 105 -40 °C < T< 125 °C 104 T = 25 °C 120 -40 °C < T< 125 °C 110 dB 123 144 VRF = 100 mVp, f = 400 MHz 52 VRF = 100 mVp, f = 900 MHz 52 VRF = 100 mVp, f = 1800 MHz 72 VRF = 100 mVp,f = 2400 MHz 85 T = 25 °C 18 -40 °C < T< 125 °C 40 70 T = 25 °C 13 -40 °C < T< 125 °C 30 mV 70 T = 25 °C 20 -40 °C < T< 125 °C 15 T = 25 °C 15 -40 °C < T< 125 °C 10 T = 25 °C 29 25 0.8 -40 °C < T< 125 °C mA 1 1.2 AC performance T = 25 °C, RL = 10 kΩ, GBP Gain bandwidth product CL = 100 pF -40 °C < T< 125 °C, RL = 10 kΩ, CL = 100 pF Φm Phase margin Gm Gain margin SR Slew rate (4) ts Settling time en Equivalent input noise voltage en-pp Voltage noise DS11863 - Rev 5 2 3 MHz 1.6 RL = 10 kΩ, CL = 100 pF T = 25 °C 2.9 -40 °C < T< 125 °C 2.4 56 degrees 15 dB 4.7 V/µs To 0.1 %, Vin = 1.5 Vpp 600 ns To 0.01 %, Vin = 1 Vpp 4 µs f = 1 kHz 37 f = 10 kHz 37 f = 0.1 to 10 Hz 0.4 nV/√Hz µVpp page 7/43 TSZ181, TSZ182 Electrical characteristics Symbol Parameter Conditions Min. Typ. Cs Channel separation f = 100 Hz 135 tinit Initialization time, G = 100 (5) T = 25 °C 60 -40 °C < T< 125 °C 100 Max. Unit dB µs 1. See Section 5.5 Input offset voltage drift over temperature. Input offset measurements are performed on x100 gain configuration. The amplifiers and the gain setting resistors are at the same temperature. 2. Guaranteed by design 3. Tested on the MiniSO8 package, RF injection on the IN- pin 4. Slew rate value is calculated as the average between positive and negative slew rates 5. Initialization time is defined as the delay between the moment when supply voltage exceeds 2.2 V and output voltage stabilization DS11863 - Rev 5 page 8/43 TSZ181, TSZ182 Electrical characteristic curves 4 Electrical characteristic curves Figure 2. Supply current vs. supply voltage Figure 3. Input offset voltage distribution at VCC = 5 V Figure 4. Input offset voltage distribution at VCC = 3.3 V Figure 5. Input offset voltage distribution at VCC = 2.2 V Figure 6. Input offset voltage distribution at VCC = 5 V, T = 125 °C Figure 7. Input offset voltage distribution at VCC = 5 V, T = -40 °C DS11863 - Rev 5 page 9/43 TSZ181, TSZ182 Electrical characteristic curves Figure 8. Input offset voltage distribution at VCC = 2.2 V, T = 125 °C Figure 9. Input offset voltage distribution at VCC = 2.2 V, T = -40 °C Figure 10. Input offset voltage vs. supply voltage Figure 11. Input offset voltage vs. input common-mode at VCC = 5.5 V Figure 12. Input offset voltage vs. input common-mode at VCC = 3.3 V Figure 13. Input offset voltage vs. input common-mode at VCC = 2.2 V DS11863 - Rev 5 page 10/43 TSZ181, TSZ182 Electrical characteristic curves Figure 14. Input offset voltage vs. temperature Figure 15. VOH vs. supply voltage Figure 16. VOL vs. supply voltage Figure 17. Output current vs. output voltage at VCC = 5.5 V Figure 18. Output current vs. output voltage at VCC = 2.2 V Figure 19. Input bias current vs. common-mode at VCC = 5 V Vcc=5V T=25°C DS11863 - Rev 5 page 11/43 TSZ181, TSZ182 Electrical characteristic curves Figure 20. Input bias current vs. temperature at VCC = 5 V Figure 21. Output rail linearity Vcc = 5V Vicm = Vcc/2 Figure 22. Bode diagram at VCC = 5.5 V Figure 23. Bode diagram at VCC = 2.2 V Figure 24. Bode diagram at VCC = 3.3 V Figure 25. Open loop gain vs. frequency DS11863 - Rev 5 page 12/43 TSZ181, TSZ182 Electrical characteristic curves Figure 26. Positive slew rate vs. supply voltage Figure 27. Negative slew rate vs. supply voltage Figure 28. Noise 0.1 - 10 Hz vs. time Figure 29. Noise vs. frequency Figure 30. Noise vs. frequency and temperature Figure 31. Output overshoot vs. load capacitance DS11863 - Rev 5 page 13/43 TSZ181, TSZ182 Electrical characteristic curves Figure 32. Small signal VCC = 5 V Figure 33. Small signal VCC = 2.2 V Figure 34. Large signal VCC = 5 V Figure 35. Large signal VCC = 2.2 V Figure 36. Negative overvoltage recovery VCC = 2.2 V Figure 37. Positive overvoltage recovery VCC = 2.2 V DS11863 - Rev 5 page 14/43 TSZ181, TSZ182 Electrical characteristic curves Figure 38. Output impedance vs. frequency Figure 39. Settling time positive step (-2 V to 0 V) Figure 40. Settling time negative step (2 V to 0 V) Figure 41. Settling time positive step (-0.8 V to 0 V) Figure 42. Settling time negative step (0.8 V to 0 V) Figure 43. Maximum output voltage vs. frequency DS11863 - Rev 5 page 15/43 TSZ181, TSZ182 Electrical characteristic curves Figure 44. Crosstalk vs. frequency DS11863 - Rev 5 Figure 45. PSRR vs. frequency page 16/43 TSZ181, TSZ182 Application information 5 Application information 5.1 Operation theory The TSZ18x is a high precision CMOS device. It can achieve a low offset drift and no 1/f noise thanks to its chopper architecture. Chopper-stabilized amps constantly correct low-frequency errors across the inputs of the amplifier. Chopper-stabilized amplifiers can be explained with respect to: • Time domain • Frequency domain 5.1.1 Time domain The basis of the chopper amplifier is realized in two steps. These steps are synchronized thanks to a clock running at 2.4 MHz. Figure 46. Block diagram in the time domain (step 1) Chop 1 Vinp Vinn Chop 2 A2(f) A1(f) Filter Vo ut Figure 47. Block diagram in the time domain (step 2) Chop 1 Vinp Vinn Chop 2 A1(f) A2 (f) Filter Vo ut Figure 46. Block diagram in the time domain (step 1) shows step 1, the first clock cycle, where Vio is amplified in the normal way. Figure 47. Block diagram in the time domain (step 2) shows step 2, the second clock cycle, where Chop1 and Chop2 swap paths. At this time, the Vio is amplified in a reverse way as compared to step 1. At the end of these two steps, the average Vio is close to zero. The A2(f) amplifier has a small impact on the Vio because the Vio is expressed as the input offset and is consequently divided by A1(f). In the time domain, the offset part of the output signal before filtering is shown in Figure 48. Vio cancellation principle. DS11863 - Rev 5 page 17/43 TSZ181, TSZ182 Operating voltages Figure 48. Vio cancellation principle Step 1 Step 1 S tep 1 Vio Time Vio Step 2 Step 2 S tep 2 The low pass filter averages the output value resulting in the cancellation of the Vio offset. The 1/f noise can be considered as an offset in low frequency and it is canceled like the Vio, thanks to the chopper technique. 5.1.2 Frequency domain The frequency domain gives a more accurate vision of chopper-stabilized amplifier architecture. Figure 49. Block diagram in the frequency domain Vinn Chop1 A(f) Vi np Chop2 A(f) Filter Vout Vos + Vn 1 2 3 4 The modulation technique transposes the signal to a higher frequency where there is no 1/f noise, and demodulate it back after amplification. 1. According to Figure 49. Block diagram in the frequency domain, the input signal Vin is modulated once (Chop1) so all the input signal is transposed to the high frequency domain. The amplifier adds its own error (Vio (output offset voltage) + the noise Vn (1/f noise)) to this modulated 2. signal. 3. This signal is then demodulated (Chop2), but since the noise and the offset are modulated only once, they are transposed to the high frequency, leaving the output signal of the amplifier without any offset and low frequency noise. Consequently, the input signal is amplified with a very low offset and 1/f noise. 4. To get rid of the high frequency part of the output signal (which is useless) a low pass filter is implemented. To further suppress the remaining ripple down to a desired level, another low pass filter may be added externally on the output of the TSZ18x. 5.2 Operating voltages The TSZ18x device can operate from 2.2 to 5.5 V. The parameters are fully specified for 2.2 V, 3.3 V, and 5 V power supplies. However, the parameters are very stable in the full VCC range and several characterization curves show the TSZ18x device characteristics at 2.2 V and 5.5 V. Additionally, the main specifications are guaranteed in extended temperature ranges from -40 to 125 °C. 5.3 Input pin voltage ranges The TSZ18x device has internal ESD diode protection on the inputs. These diodes are connected between the input and each supply rail to protect the input MOSFETs from electrical discharge. DS11863 - Rev 5 page 18/43 TSZ181, TSZ182 Rail-to-rail input/output If the input pin voltage exceeds the power supply by 0.5 V, the ESD diodes become conductive and excessive current can flow through them. Without limitation this over current can damage the device. In this case, it is important to limit the current to 10 mA, by adding resistance on the input pin, as described in Figure 50. Input current limitation. Figure 50. Input current limitation VCC+ + Vin R VCC- 5.4 Rail-to-rail input/output The TSZ18x has a rail-to-rail input, and the input common mode range is extended from (VCC -) - 0.1 V to (VCC+) + 0.1 V. The operational amplifier output levels can go close to the rails: to a maximum of 40 mV above and below the rail when connected to a 10 kΩ resistive load to VCC/2. 5.5 Input offset voltage drift over temperature The maximum input voltage drift variation over temperature is defined as the offset variation related to the offset value measured at 25 °C. The operational amplifier is one of the main circuits of the signal conditioning chain, and the amplifier input offset is a major contributor to the chain accuracy. The signal chain accuracy at 25 °C can be compensated during production at application level. The maximum input voltage drift over temperature enables the system designer to anticipate the effect of temperature variations. The maximum input voltage drift over temperature is computed using Equation 1. Equation 1 ∆V io V ( T ) – V io ( 25 °C) = ma x io ∆T T – 25 °C Where T = -40 °C and 125 °C. The TSZ18x datasheet maximum value is guaranteed by measurements on a representative sample size ensuring a Cpk (process capability index) greater than 1.3. 5.6 Capacitive load Driving large capacitive loads can cause stability problems. Increasing the load capacitance produces gain peaking in the frequency response, with overshoot and ringing in the step response. It is usually considered that with a gain peaking higher than 2.3 dB an op amp might become unstable. Generally, the unity gain configuration is the worst case for stability and the ability to drive large capacitive loads. Figure 51. Stability criteria with a serial resistor at VCC = 5 V, Figure 52. Stability criteria with a serial resistor at VCC = 3.3 V, and Figure 53. Stability criteria with a serial resistor at VCC = 2.2 V show the serial resistors that must be added to the output, to make a system stable. Figure 54. Test configuration for Riso shows the test configuration using an isolation resistor, Riso. DS11863 - Rev 5 page 19/43 TSZ181, TSZ182 Capacitive load Figure 51. Stability criteria with a serial resistor at VCC = 5 V Figure 52. Stability criteria with a serial resistor at VCC = 3.3 V Figure 53. Stability criteria with a serial resistor at VCC = 2.2 V DS11863 - Rev 5 page 20/43 TSZ181, TSZ182 PCB layout recommendations Figure 54. Test configuration for Riso +VCC Riso VIN + VOUT Cload -VCC 10 kΩ Note that the resistance Riso is in series with Rload and thus acts as a voltage divider, and reduces the output swing a little. Thanks to the natural good stability of TSZ18x, the Riso needed to keep the system stable when the capacitive load exceeds 200pF is lower than 50 Ω (VCC = 5 V), and so the error introduced is generally negligible. The Riso also modifies the open loop gain of the circuit, and tends to improve the phase margin as described in Table 6. Riso impact on stability. Table 6. Riso impact on stability Capacitive load 100 pF 1 nF 10 nF 100 nF 1 µF Riso (Ω) 0 100 47 100 22 47 8 13 10 6 Measured overshoot (%) 20.9 15 23 9 16 8 21 10 12 8 Estimated phase margin (°) 47 53 46 59 52 61 47 58 56 61 5.7 PCB layout recommendations Particular attention must be paid to the layout of the PCB tracks connected to the amplifier, load and power supply. It is good practice to use short and wide PCB traces to minimize voltage drops and parasitic inductance. To minimize parasitic impedance over the entire surface, a multi-via technique that connects the bottom and top layer ground planes together in many locations is often used. The copper traces that connect the output pins to the load and supply pins should be as wide as possible to minimize trace resistance. A ground plane generally helps to reduce EMI, which is why it is generally recommended to use a multilayer PCB and use the ground plane as a shield to protect the internal track. In this case, pay attention to separate the digital from the analog ground and avoid any ground loop. Place external components as close as possible to the op amp and keep the gain resistances, Rf and Rg, close to the inverting pin to minimize parasitic capacitances. 5.8 Optimized application recommendation The TSZ18x is based on a chopper architecture. As the device includes internal switching circuitry, it is strongly recommended to place a 0.1 µF capacitor as close as possible to the supply pins. A good decoupling has several advantages for an application. First, it helps to reduce electromagnetic interference. Due to the modulation of the chopper, the decoupling capacitance also helps to reject the small ripple that may appear on the output. The TSZ18x has been optimized for use with 10 kΩ in the feedback loop. With this, or a higher value resistance, this device offers the best performance. DS11863 - Rev 5 page 21/43 TSZ181, TSZ182 EMI rejection ration (EMIRR) 5.9 EMI rejection ration (EMIRR) The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI immunity of operational amplifiers. An adverse effect that is common to many op amps is a change in the offset voltage as a result of RF signal rectification. The TSZ18x has been specially designed to minimize susceptibility to EMIRR and show an extremely good sensitivity. Figure 55. EMIRR on IN+ pin shows the EMIRR IN+, Figure 56. EMIRR on IN- pin shows the EMIRR IN- of the TSZ18x measured from 10 MHz up to 2.4 GHz. Figure 55. EMIRR on IN+ pin Figure 56. EMIRR on IN- pin 5.10 1/f noise 1/f noise, also known as pink noise or flicker noise, is caused by defects, at the atomic level, in semiconductor devices. The noise is a non-periodic signal and it cannot be calibrated. So for an application requiring precision, it is extremely important to take this noise into account. 1/f noise is a major noise contributor at low frequencies and causes a significant output voltage offset when amplified by the noise gain of the circuit. But, the TSZ18x, thanks to its chopper architecture, rejects 1/f noise and thus makes this device an excellent choice for DC high precision applications. As shown in Figure 28. Noise 0.1 - 10 Hz vs. time, 0.1 Hz to 10 Hz amplifier voltage noise is only 400 nVpp for a VCC = 5 V. Figure 29. Noise vs. frequency and Figure 30. Noise vs. frequency and temperature show the voltage noise density of the amplifier with no 1/f noise on a large bandwith. Figure 57. Noise vs frequency between 0.1 and 10 Hz exhibiting no 1/f noise below depicts noise vs frequency between 0.1 and 10 Hz exhibiting no 1/f noise. DS11863 - Rev 5 page 22/43 TSZ181, TSZ182 Overload recovery Figure 57. Noise vs frequency between 0.1 and 10 Hz exhibiting no 1/f noise 5.11 Overload recovery Overload recovery is defined as the time required for the op amp output to recover from a saturated state to a linear state. The saturation state occurs when the output voltage gets very close to either rail in the application. It can happen due to an excessive input voltage or when the gain setting is too high. When the output of the TSZ18x enters in saturation state it needs 10 µs to get back to a linear state as shown in Figure 58. Negative overvoltage recovery VCC = 5 V and Figure 59. Positive overvoltage recovery VCC = 5 V. Figure 36. Negative overvoltage recovery VCC = 2.2 V and Figure 37. Positive overvoltage recovery VCC = 2.2 V show the overvoltage recovery for a VCC = 2.2 V. Figure 58. Negative overvoltage recovery VCC = 5 V 5.12 Figure 59. Positive overvoltage recovery VCC = 5 V Phase reversal protection Some op amps can show a phase reversal when the common-mode voltage exceeds the VCC range. Phase reversal is a specific behavior of an op amp where its output reacts as if the inputs were inverted when at least one input is out of the specified common-mode voltage. The TSZ18x has been carefully designed to prevent any output phase reversal. The TSZ18x is a rail-to-rail input op amp, therefore, the common-mode range can extend up to the rails. If the input signal goes above the rail it does not cause any inversion of the output signal as shown in Figure 60. No phase reversal. If, in the application, the operating common-mode voltage is exceeded please read Section 5.3 Input pin voltage ranges. DS11863 - Rev 5 page 23/43 TSZ181, TSZ182 Open loop gain close to the rail Figure 60. No phase reversal 5.13 Open loop gain close to the rail One of the key parameters of current measurement in low-side applications is precision. Moreover, it is generally interesting to be able to make a measurement when there is no current through the shunt resistance. But, when the output voltage gets close the rail some internal transistors saturate resulting in a loss of open loop gain. Therefore, the output voltage can be as high as several mV while it is expected to be close to 0 V. The TSZ18x has been designed to keep a high gain even when the op amp output is very close to the rail, to ensure good accuracy at low current. Figure 61. Gain vs. output voltage, VCC = 5 V, RI = 10 kΩ to GND shows the open loop gain of the TSZ18x vs. output voltage. A single power supply of 5 V and a common-mode voltage of 0 V is used, with a 10 kΩ resistor connected to GND. Figure 61. Gain vs. output voltage, VCC = 5 V, RI = 10 kΩ to GND 5.14 Application examples 5.14.1 Measuring gas concentration using the NDIR principle (thermopile) A thermopile is a serial interconnected array of thermocouples. Based on the Seebeck principle, a thermocouple is able to deliver an output voltage which depends on the temperature difference between a reference junction and an active junction. An NDIR sensor (non dispersive infrared) is generally composed of an infrared (IR) source, an optical cavity, a dual channel detector, and an internal thermistor. Both channels are made with a thermopile. One channel is considered as a reference and the other is considered as the active channel. DS11863 - Rev 5 page 24/43 TSZ181, TSZ182 Application examples Certain gases absorb IR radiation at a specific wavelength. Each channel has a specific wavelength filter. The active channel has a filter centered on gas absorption while the reference channel has a filter on another wavelength which is still in the IR range. When a gas enters the optical cavity, the radiation hitting the active channel decreases, whereas it remains the same on the reference channel. The difference between the reference and active channel gives the concentration of gas present in the optical cavity. As the thermopile delivers extremely low voltages (hundreds of µV to several mV) the output signal must be amplified with a high gain and a very low offset in order to minimize DC errors. Moreover, the drift of Vio depending on temperature must be as low as possible not to impact the measurement once the calibration has been made. An NDIR sensor generally works at low frequency and the noise of the amplifiers must be as low as possible (0.1-10 Hz en-pp = 0.4 µVpp). Thanks to its chopper architecture, the TSZ18x combines all these specifications, particularly in having a ΔVio/Δt of 0.1 µV/°C, no 1/f noise in low frequency, and a white noise of 37 nV/√Hz. Figure 62. Principle schematic shows an NDIR gas sensing schematic where the active and reference channels are pre-amplified before treatment by an ADC thanks to the TSZ18x. A Vref voltage (in hundreds of mV) can be used to ensure the amplifiers are not saturated when the signal is close to the low rail. A gain of 1000 is used to allow amplification of the signal coming from the NDIR sensor (3 mV). Figure 62. Principle schematic 100 nF 10 kΩ Vref Vcc 10 Ω - VL TSZ182_a 10 nF Ref.ch ADC1 + 10 nF + Act. ch TSZ182_b ADC2 10 Ω ADC3 10 kΩ 100 nF 5.14.2 Precision instrumentation amplifier The instrumentation amplifier uses three op amps. The circuit, shown in Figure 63. Precision instrumentation amplifier schematic, exhibits high input impedance, so that the source impedance of the connected sensor has no impact on the amplification. DS11863 - Rev 5 page 25/43 TSZ181, TSZ182 Application examples Figure 63. Precision instrumentation amplifier schematic TSZ182 V1 R2 + - R4 Rf + Rg TSZ181 Vout Rf R1 + V2 R3 TSZ182 The gain is set by tuning the Rg resistor. To have the best performance, it is suggested to have R1 = R2 = R3 = R4. The output is given by Equation 2. Equation 2 The matching of R1, R2 and R3, R4 is important to ensure a good common mode rejection ratio (CMR). 5.14.3 Low-side current sensing Power management mechanisms are found in most electronic systems. Current sensing is useful for protecting applications. The low-side current sensing method consists of placing a sense resistor between the load and the circuit ground. The resulting voltage drop is amplified using the TSZ181 (see Figure 64. Low-side current sensing schematic). Figure 64. Low-side current sensing schematic C1 Rg1 Rf1 I In Rshunt Ip Rg2 5V - + + - Vout T SZ181 Rf2 Vout can be expressed as follows: Equation 3 V ou t = R shun t × I 1 – R g2 R g2 + R f2 1+ R g2 × R f2 R f1 R f1 R f1 + Ip – l n × R f1 – V io 1 + × 1+ R g2 + R f2 R g1 R g1 R g1 Assuming that Rf2 = Rf1 = Rf and Rg2 = Rg1 = Rg, Equation 3 can be simplified as follows: Equation 4 V out = R shunt × I DS11863 - Rev 5 Rf Rf – V io 1 + + R f × I io Rg Rg page 26/43 TSZ181, TSZ182 Application examples The main advantage of using the chopper of the TSZ18x for a low-side current sensing, is that the errors due to Vio and Iio are extremely low and may be neglected. Therefore, for the same accuracy, the shunt resistor can be chosen with a lower value, resulting in lower power dissipation, lower drop in the ground path, and lower cost. Particular attention must be paid to the matching and precision of Rg1, Rg2, Rf1, and Rf2, to maximize the accuracy of the measurement. DS11863 - Rev 5 page 27/43 TSZ181, TSZ182 Package information 6 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DS11863 - Rev 5 page 28/43 TSZ181, TSZ182 DFN6 1.2 x 1.3 package information 6.1 DFN6 1.2 x 1.3 package information Figure 65. DFN6 1.2 x 1.3 package outline BOTTOM VIEW e b PIN#1 ID L3 L SIDE VIEW A1 A SEATING PLANE C 8 0.05 C TOP VIEW D E PIN 1 DS11863 - Rev 5 page 29/43 TSZ181, TSZ182 DFN6 1.2 x 1.3 package information Table 7. DFN6 1.2 x 1.3 mechanical data Dimensions Ref Millimeters Inches Min. Typ. Max. Min. Typ. Max. A 0.31 0.38 0.40 0.012 0.015 0.016 A1 0.00 0.02 0.05 0.000 0.001 0.002 b 0.15 0.18 0.25 0.006 0.007 0.010 c 0.05 0.002 D 1.20 0.047 E 1.30 0.051 e 0.40 0.016 L 0.475 0.525 0.575 0.019 0.021 0.023 L3 0.375 0.425 0.475 0.015 0.017 0.019 Figure 66. DFN6 1.2 x 1.3 recommended footprint 0.40 0.25 3 1 1.20 0.475 4 DS11863 - Rev 5 6 page 30/43 TSZ181, TSZ182 DFN8 2 x 2 package information 6.2 DFN8 2 x 2 package information Figure 67. DFN8 2 x 2 package outline Table 8. DFN8 2 x 2 mechanical data Dimensions Ref. A Millimeters Min. Typ. Max. Min. Typ. Max. 0.51 0.55 0.60 0.020 0.022 0.024 A1 0.05 A3 0.002 0.15 0.006 b 0.18 0.25 0.30 0.007 0.010 0.012 D 1.85 2.00 2.15 0.073 0.079 0.085 D2 1.45 1.60 1.70 0.057 0.063 0.067 E 1.85 2.00 2.15 0.073 0.079 0.085 E2 0.75 0.90 1.00 0.030 0.035 0.039 e L ddd DS11863 - Rev 5 Inches 0.50 0.225 0.325 0.020 0.425 0.08 0.009 0.013 0.017 0.003 page 31/43 TSZ181, TSZ182 MiniSO8 package information Figure 68. DFN8 2 x 2 recommended footprint 6.3 MiniSO8 package information Figure 69. MiniSO8 package outline Table 9. MiniSO8 package mechanical data Dimensions Ref. Millimeters Min. Typ. A DS11863 - Rev 5 Inches Max. Min. Typ. 1.1 A1 0 A2 0.75 0.85 Max. 0.043 0.15 0 0.95 0.030 0.0006 0.033 0.037 page 32/43 TSZ181, TSZ182 SO8 package information Dimensions Ref. Millimeters Min. Typ. Max. Min. Typ. Max. b 0.22 0.40 0.009 0.016 c 0.08 0.23 0.003 0.009 D 2.80 3.00 3.20 0.11 0.118 0.126 E 4.65 4.90 5.15 0.183 0.193 0.203 E1 2.80 3.00 3.10 0.11 0.118 0.122 e L 0.65 0.40 0.60 0.026 0.80 0.016 0.024 L1 0.95 0.037 L2 0.25 0.010 k 0° 8° ccc 6.4 Inches 0° 0.031 8° 0.10 0.004 SO-8 package information Figure 70. SO8 package outline Table 10. SO-8 mechanical data Symbol Min. A DS11863 - Rev 5 Inches(1) Milimeters Typ. Max. Min. 1.75 A1 0.10 A2 1.25 b 0.28 0.25 Typ. Max. 0.069 0.004 0.010 0.049 0.48 0.011 0.019 page 33/43 TSZ181, TSZ182 SOT23-5 package information Symbol Inches(1) Milimeters Min. Typ. Max. Min. 0.23 0.007 Typ. Max. c 0.17 D 4.80 4.90 5.00 0.189 0.193 0.197 E 5.80 6.00 6.20 0.228 0.236 0.244 E1 3.80 3.90 4.00 0.150 0.154 0.157 e 1.27 0.010 0.050 h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 L1 k 1.04 0° 0.040 8° ccc 0° 8° 0.10 0.004 1. Values in inches are converted from mm and rounded to 4 decimal digits. 6.5 SOT23-5 package information Figure 71. SOT23-5 package outline Table 11. SOT23-5 mechanical data Dimensions Ref. A DS11863 - Rev 5 Millimeters Inches Min. Typ. Max. Min. Typ. Max. 0.90 1.20 1.45 0.035 0.047 0.057 page 34/43 TSZ181, TSZ182 SOT23-5 package information Dimensions Ref. Millimeters Min. Typ. A1 DS11863 - Rev 5 Inches Max. Min. Typ. 0.15 Max. 0.006 A2 0.90 1.05 1.30 0.035 0.041 0.051 B 0.35 0.40 0.50 0.014 0.016 0.020 C 0.09 0.15 0.20 0.004 0.006 0.008 D 2.80 2.90 3.00 0.110 0.114 0.118 D1 1.90 0.075 e 0.95 0.037 E 2.60 2.80 3.00 0.102 0.110 0.118 F 1.50 1.60 1.75 0.059 0.063 0.069 L 0.10 0.35 0.60 0.004 0.014 0.024 K 0 degrees 10 degrees 0 degrees 10 degrees page 35/43 TSZ181, TSZ182 Ordering information 7 Ordering information Table 12. Order code Order code Temperature range Package Packing Marking TSZ181ILT SOT23-5 K215 TSZ181IQ1T DFN6 1.2x1.3 KB TSZ182IQ2T -40 to 125 °C DFN8 2x2 TSZ182IST MiniSO8 TSZ182IDT SO8 TSZ181IYLT (1) TSZ182IYST (1) TSZ182IYDT Automotive grade -40 to 125°C K4G Tape and reel TSZ182I SOT23-5 K216 MiniSO8 K420 SO8 TSZ182IY 1. Qualified and characterized according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC Q001 & Q002 or equivalent. DS11863 - Rev 5 page 36/43 TSZ181, TSZ182 Revision history Table 13. Document revision history DS11863 - Rev 5 Date Revision Changes 21-Nov-2016 1 Initial release 13-Jul-2017 2 Added SO-8 package information and updated automotive qualification status in Table 10 "Order codes". 06-Nov-2017 3 Added: new packages DFN6 1.2x1.3 and SOT23-5. Updated: Table 10 "Order codes". 14-Mar-2018 4 Updated footnote Table 12. Order code. 27-Aug-2018 5 Updated Figure 1. Pin connections for each package (top view). page 37/43 TSZ181, TSZ182 Contents Contents 1 Package pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 Absolute maximum ratings and operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 Electrical characteristic curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 5.1 6 Operation theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1.1 Time domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1.2 Frequency domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2 Operating voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.3 Input pin voltage ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.4 Rail-to-rail input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.5 Input offset voltage drift over temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.6 Capacitive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.7 PCB layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.8 Optimized application recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.9 EMI rejection ration (EMIRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.10 1/f noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.11 Overload recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.12 Phase reversal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.13 Open loop gain close to the rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.14 Application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.14.1 Measuring gas concentration using the NDIR principle (thermopile) . . . . . . . . . . . . . . . . . 24 5.14.2 Precision instrumentation amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.14.3 Low-side current sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 6.1 DFN6 1.2x1.3 package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.2 DFN8 2 x 2 package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.3 MiniSO8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.4 SO-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 DS11863 - Rev 5 page 38/43 TSZ181, TSZ182 Contents 6.5 7 SOT23-5 package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 DS11863 - Rev 5 page 39/43 TSZ181, TSZ182 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Absolute maximum ratings (AMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics at V CC+ = 2.2 V with V CC- = 0 V, Vicm = V CC/2, T = 25 °C, and RL = 10 kΩ connected to V CC/2 (unless otherwise specified) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Electrical characteristics at VCC+ = 3.3 V with VCC- = 0 V, Vicm = VCC/2, T = 25 °C, and RL = 10 kΩ connected to VCC/2 (unless otherwise specified) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical characteristics at VCC+ = 5 V with VCC- = 0 V, Vicm = VCC/2, T = 25 °C, and RL = 10 kΩ connected to VCC/2 (unless otherwise specified) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Riso impact on stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DFN6 1.2 x 1.3 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 DFN8 2 x 2 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 MiniSO8 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 SOT23-5 mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 DS11863 - Rev 5 page 40/43 TSZ181, TSZ182 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. DS11863 - Rev 5 Pin connections for each package (top view) . . . . . . . . . . Supply current vs. supply voltage . . . . . . . . . . . . . . . . . . Input offset voltage distribution at VCC = 5 V . . . . . . . . . . . Input offset voltage distribution at VCC = 3.3 V . . . . . . . . . Input offset voltage distribution at VCC = 2.2 V . . . . . . . . . Input offset voltage distribution at VCC = 5 V, T = 125 °C . . Input offset voltage distribution at VCC = 5 V, T = -40 °C . . . Input offset voltage distribution at VCC = 2.2 V, T = 125 °C . Input offset voltage distribution at VCC = 2.2 V, T = -40 °C . Input offset voltage vs. supply voltage . . . . . . . . . . . . . . . Input offset voltage vs. input common-mode at VCC = 5.5 V Input offset voltage vs. input common-mode at VCC = 3.3 V Input offset voltage vs. input common-mode at VCC = 2.2 V Input offset voltage vs. temperature. . . . . . . . . . . . . . . . . VOH vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . VOL vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . Output current vs. output voltage at VCC = 5.5 V . . . . . . . . Output current vs. output voltage at VCC = 2.2 V . . . . . . . . Input bias current vs. common-mode at VCC = 5 V . . . . . . Input bias current vs. temperature at VCC = 5 V . . . . . . . . Output rail linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bode diagram at VCC = 5.5 V . . . . . . . . . . . . . . . . . . . . . Bode diagram at VCC = 2.2 V . . . . . . . . . . . . . . . . . . . . . Bode diagram at VCC = 3.3 V . . . . . . . . . . . . . . . . . . . . . Open loop gain vs. frequency . . . . . . . . . . . . . . . . . . . . . Positive slew rate vs. supply voltage . . . . . . . . . . . . . . . . Negative slew rate vs. supply voltage . . . . . . . . . . . . . . . Noise 0.1 - 10 Hz vs. time . . . . . . . . . . . . . . . . . . . . . . . Noise vs. frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . Noise vs. frequency and temperature . . . . . . . . . . . . . . . Output overshoot vs. load capacitance . . . . . . . . . . . . . . Small signal VCC = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . Small signal VCC = 2.2 V . . . . . . . . . . . . . . . . . . . . . . . . Large signal VCC = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . Large signal VCC = 2.2 V . . . . . . . . . . . . . . . . . . . . . . . . Negative overvoltage recovery VCC = 2.2 V . . . . . . . . . . . Positive overvoltage recovery VCC = 2.2 V . . . . . . . . . . . . Output impedance vs. frequency. . . . . . . . . . . . . . . . . . . Settling time positive step (-2 V to 0 V). . . . . . . . . . . . . . . Settling time negative step (2 V to 0 V) . . . . . . . . . . . . . . Settling time positive step (-0.8 V to 0 V) . . . . . . . . . . . . . Settling time negative step (0.8 V to 0 V) . . . . . . . . . . . . . Maximum output voltage vs. frequency . . . . . . . . . . . . . . Crosstalk vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . PSRR vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . Block diagram in the time domain (step 1) . . . . . . . . . . . . Block diagram in the time domain (step 2) . . . . . . . . . . . . Vio cancellation principle . . . . . . . . . . . . . . . . . . . . . . . . Block diagram in the frequency domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 9 . 9 . 9 . 9 . 9 . 9 10 10 10 10 10 10 11 11 11 11 11 11 12 12 12 12 12 12 13 13 13 13 13 13 14 14 14 14 14 14 15 15 15 15 15 15 16 16 17 17 18 18 page 41/43 TSZ181, TSZ182 List of figures Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. DS11863 - Rev 5 Input current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stability criteria with a serial resistor at VCC = 5 V . . . . . . . . . . . . Stability criteria with a serial resistor at VCC = 3.3 V. . . . . . . . . . . Stability criteria with a serial resistor at VCC = 2.2 V. . . . . . . . . . . Test configuration for Riso . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIRR on IN+ pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIRR on IN- pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Noise vs frequency between 0.1 and 10 Hz exhibiting no 1/f noise Negative overvoltage recovery VCC = 5 V. . . . . . . . . . . . . . . . . . Positive overvoltage recovery VCC = 5 V . . . . . . . . . . . . . . . . . . No phase reversal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gain vs. output voltage, VCC = 5 V, RI = 10 kΩ to GND . . . . . . . . Principle schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Precision instrumentation amplifier schematic. . . . . . . . . . . . . . . Low-side current sensing schematic . . . . . . . . . . . . . . . . . . . . . DFN6 1.2 x 1.3 package outline . . . . . . . . . . . . . . . . . . . . . . . . DFN6 1.2 x 1.3 recommended footprint . . . . . . . . . . . . . . . . . . . DFN8 2 x 2 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . DFN8 2 x 2 recommended footprint . . . . . . . . . . . . . . . . . . . . . . MiniSO8 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SO8 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SOT23-5 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 20 20 20 21 22 22 23 23 23 24 24 25 26 26 29 30 31 32 32 33 34 page 42/43 TSZ181, TSZ182 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2018 STMicroelectronics – All rights reserved DS11863 - Rev 5 page 43/43