VNI4140KTR

VNI4140K Quad high-side smart power solid-state relay IV E Datasheet - production data • Open drain diagnostic outputs NA CT • 3.3 V CMOS/TTL compatible inputs • Fast demagnetization of inductive loads • Conforms to IEC 61131-2 • ESD according to IEC 61000-4-2 up to +/25 kV PowerSSO-24 Description Vdemag(1) RDS(on)(1) VNI4140K VCC-41 V 0.08 Ω Iout(1) VCC 0.7 A 41 V • Output current: 0.7 A per channel • Shorted load protections • Junction overtemperature protection CT IV 1. Per channel. NA • Case overtemperature protection for thermal independence of the channels -I • Thermal case shutdown restart not simultaneous for the various channels • Protection against loss of ground TI VE • Current limitation Figure 1. Block diagram IN AC • Undervoltage shutdown The VNI4140K is a monolithic device made using STMicroelectronics VIPower technology, intended to drive four independent resistive or inductive loads with one side connected to ground. Active current limitation avoids dropping the system power supply in case of shorted load. Built-in thermal shutdown protects the chip from overtemperature and short-circuit. In overload conditions, channel turns OFF and back ON automatically so to maintain junction temperature between TTSD and TR. If this condition makes case temperature reach TCSD, overloaded channel is turned OFF and restart only when case temperature has decreased down to TCR. In case of more than one channel in overload, restart of the overloaded channels is not simultaneous, in order to avoid high peak current from the supply. Non-overloaded channels continue operating normally. The open drain diagnostics outputs indicate overtemperature conditions. E Type -I Features GIPD0611130956LM December 2013 This is information on a product in full production. DocID14174 Rev 13 1/25 www.st.com Contents VNI4140K Contents Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 NA CT 2.1 IV E 1 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 Switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7 Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8 Package and PC board thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.1 CT IV E -I 3 VNI4140K thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Reverse polarity protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 10 Demagnetization energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 11 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 12 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 IN AC TI VE -I NA 9 2/25 DocID14174 Rev 13 VNI4140K Pin connection IV E Figure 2. Pin connection (top view) OUT1 OUT1 OUT1 OUT2 OUT2 OUT2 OUT3 OUT3 OUT3 OUT4 OUT4 OUT4 IV E -I NA CT VCC IN1 STAT1 IN2 STAT2 GND STAT3 IN3 STAT4 IN4 NC NC Table 1. Pin description Name Tab TAB Exposed tab internally connected to Vcc 1 VCC Supply voltage 2 IN1 Channel 1 input 3.3 V CMOS/TTL compatible 3 STAT1 Channel 1 status in open drain configuration 4 IN2 Channel 2 input 3.3 V CMOS/TTL compatible 5 STA2 6 GND 8 9 -I NA Description Channel 2 status in open drain configuration Device ground connection TI VE 7 CT Pin 10 IN AC 1 Pin connection STAT3 Channel 3 status in open drain configuration IN3 Channel 3 input 3.3 V CMOS/TTL compatible STAT4 Channel 4 status in open drain configuration IN4 Channel 4 input 3.3 V CMOS/TTL compatible 11 NC 12 NC 13 OUT4 Channel 4 power stage output, internally protected 14 OUT4 Channel 4 power stage output, internally protected 15 OUT4 Channel 4 power stage output, internally protected 16 OUT3 Channel 3 power stage output, internally protected 17 OUT3 Channel 3 power stage output, internally protected DocID14174 Rev 13 3/25 25 Pin connection VNI4140K Table 1. Pin description (continued) Description 18 OUT3 Channel 3 power stage output, internally protected 19 OUT2 Channel 2 power stage output, internally protected 20 OUT2 Channel 2 power stage output, internally protected 21 OUT2 Channel 2 power stage output, internally protected 22 OUT1 Channel 1 power stage output, internally protected 23 OUT1 Channel 1 power stage output, internally protected 24 OUT1 Channel 1 power stage output, internally protected -I E IV CT NA -I TI VE IN AC 4/25 IV E Name NA CT Pin DocID14174 Rev 13 VNI4140K 2 Maximum ratings Maximum ratings Table 2. Absolute maximum ratings Power supply voltage -VCC Reverse supply voltage IGND DC ground reverse current IOUT Output current (continuous) IR Reverse output current (per channel) IIN Input current (per channel) VIN Input voltage Status pin voltage ISTAT Status pin current VESD Electrostatic discharge (R = 1.5 kΩ; C = 100 pF) EAS IOUT = 500 mA TAMB = 125 °C PTOT Power dissipation at Tc = 25 °C TJ Junction operating temperature 41 V -0.3 V -250 mA Internally limited A -5 A ± 10 mA +VCC V +VCC V ± 10 mA 2000 V 5 J Internally limited W Internally limited °C -55 to 150 °C E IV CT NA Thermal data Unit -I VSTAT Storage temperature Value IV E VCC TSTG -I Table 3. Thermal data Symbol Parameter Value Unit Thermal resistance junction-case (1) Max. 2 °C/W Rth(JA) Thermal resistance junction-ambient Max. see Figure 11 °C/W TI VE Rth(JC) 1. Per channel. IN AC 2.1 Parameter NA CT Symbol DocID14174 Rev 13 5/25 25 Electrical characteristics 3 VNI4140K Electrical characteristics 10.5 V < VCC < 36 V; -40 °C < TJ < 125 °C; unless otherwise specified Symbol Max. Unit 36 V 0.080 0.140 Ω Ω 52 V 4 µA mA Output current at turn- VCC = VSTAT = VIN = VGND = off 24 V, VOUT = 0 V 1 mA VOUT(OFF) Off state output voltage VIN = 0 V and IOUT = 0 A 1 V IOUT(OFF) Off state output current VIN = VOUT = 0 V 5 µA Charge pump frequency Channel in ON state (1) Supply voltage Vclamp Is = 20 mA ILGND FCP Typ. All channels in OFF state ON state with VIN = 5 V (TJ = 125 °C) 45 250 2.4 -I Supply current 41 E IS IOUT = 0.5 A at TJ = 25 °C IOUT = 0.5 A NA CT On-state resistance Min. 10.5 IV RDS(on) Test conditions 0 1450 kHz CT Vcc Parameter IV E Table 4. Power section 1. To cover EN55022 class A and class B normative. NA VCC = 24 V; -40 °C < TJ < 125 °C, RL = 48 Ω, input rise time < 0.1 µs td(ON) Min. Typ. Max. Unit Turn on delay - 20 - µs Rise time - 10 - µs TI VE tr Parameter -I Symbol Table 5. Switching Turn off - 30 - µs tf Fall time - 8 - µs dV/dt(ON) Turn on voltage slope - 3 - V/µs dV/dt(OFF) Turn off voltage slope - 4 - V/µs IN AC td(OFF) 6/25 DocID14174 Rev 13 VNI4140K Electrical characteristics Table 6. Logical input Parameter VIL Input low level voltage VIH Input high level voltage IIN Min. Typ. Max. Unit 0.8 V 2.20 V Input hysteresis voltage 0.15 VIN = 15 V Input current VIN = 36 V NA CT VI(HYST) Test condition IV E Symbol V 10 210 μΑ Table 7. Protection and diagnostic VUSD Undervoltage protection VUSDHYS Undervoltage hysteresis ILIM DC short-circuit current Maximum DC output current HYST Tracking limits ILSTAT Status leakage current TTSD Junction shutdown temperature VCC = 24 V; RLOAD < 10 mΩ 0.4 0.5 0.7 1 -I VCC = VSTAT = 36 V 150 Junction reset temperature Typ. 7 Dynamic load TI VE TR Min. NA IPEAK ISTAT = 1.6 mA E Status voltage output low IV VSTAT Test conditions -I Parameter CT Symbol Unit 0.6 V 10.5 V V 1.7 A 0.2 A 30 μΑ 170 190 135 7 15 TCSD Case shutdown temperature 125 130 TCR Case reset temperature 110 TCHYST Case thermal hysteresis 7 Vdemag Output voltage at turn-off DocID14174 Rev 13 °C °C Junction thermal hysteresis IOUT = 0.5 A; LLOAD >= 1 mH VCC-41 A 1.3 THYST IN AC Max. °C 135 °C °C 15 VCC-45 °C VCC-52 V 7/25 25 Electrical characteristics VNI4140K IN AC TI VE -I NA CT IV E -I NA CT IV E Figure 3. Current and voltage conventions 8/25 DocID14174 Rev 13 GIPD0611131000LM VNI4140K 4 Truth table Truth table Table 8.Truth table Normal operation L H L H Overtemperature L H L L Undervoltage L H Shorted load (current limitation) L H H H H L X X L X H H -I L L IV E Typical application circuit STATUSn IV E OUTPUTn NA CT INPUTn TI VE -I NA CT Figure 4. Typical application circuit GIPD0611131009LM IN AC 5 Condition DocID14174 Rev 13 9/25 25 Typical application circuit VNI4140K Figure 5. Thermal behavior IV E Vin(i) = H NA CT OUT(i) On STAT(i) Off (H) 1) NO YES -I Tj(i) >Ttsd E OUT(i) Off CT IV STAT(i) On (L) YES NA 4) NO Tc >Tcr 2) NO YES Tj(i) > Tjr 3) IN AC TI VE -I YES NO Tc >Tcsd 10/25 DocID14174 Rev 13 GIPD0611131015LM VNI4140K Switching waveforms TI VE -I NA CT IV E -I NA CT IV E Figure 6. Switching waveforms IN AC 6 Switching waveforms GIPD0611131025LM DocID14174 Rev 13 11/25 25 Pin functions 7 VNI4140K Pin functions CT IV E -I NA CT IV E Figure 7. Input circuit GIPD0611131030LM IN AC TI VE -I NA Figure 8. Status circuit GIPD0611131035LM 12/25 DocID14174 Rev 13 VNI4140K Pin functions GIPD0611131040LM IN AC TI VE -I NA CT IV E -I NA CT IV E Figure 9. Charge pump switching frequency (typical) vs. temperature DocID14174 Rev 13 13/25 25 VNI4140K 8 Package and PC board thermal data 8.1 VNI4140K thermal data Layout condition of Rth and Zth measurements (PCB: double layer, thermal vias, FR4 area =77 mm x 86 mm, PCB thickness =1.6 mm, Cu thickness = 70 mm (front and back side), copper areas: from minimum pad layout to 8 cm2). CT Note: IV E -I NA CT Figure 10. VNI4140K PC board IV E Package and PC board thermal data IN AC TI VE -I NA Figure 11. Rth(JA) vs. PCB copper area in open box free air condition (one channel ON) 14/25 DocID14174 Rev 13 VNI4140K Package and PC board thermal data IN AC TI VE -I NA CT IV E -I NA CT IV E Figure 12. VNI4140K thermal impedance junction ambient single pulse (one channel on) DocID14174 Rev 13 15/25 25 Reverse polarity protection 9 VNI4140K Reverse polarity protection Reverse polarity protection can be implemented on board using two different solutions: Placing a resistor (RGND) between IC GND pin and load GND 2. Placing a diode between IC GND pin and load GND IV E 1. If option 1 is selected, the minimum resistance value has to be selected according to the following equation: NA CT Equation 1 RGND ≥ VCC/IGND where IGND is the DC reverse ground pin current and can be found in Section 2: Maximum ratings of this datasheet. Power dissipated by RGND (when VCC < 0: during reverse polarity situations) is: -I Equation 2 PD = (VCC)2/RGND IV E If option 2 is selected, the diode has to be chosen by taking into account VRRM >|Vcc| and its power dissipation capability: Equation 3 In normal conditions (no reverse polarity) due to the diode, there is a voltage drop between GND of the device and GND of the system. NA Note: CT PD ≥ IS*Vf IN AC TI VE -I Figure 13. Reverse polarity protection + Vcc Inputi Outputi Statusi GND Load RGND This schematic can be used with any type of load. 16/25 DocID14174 Rev 13 Diode VNI4140K Demagnetization energy Figure 14. Maximum demagnetization energy vs. load current, typical values 5.10 IV E Tamb= 125 °C 4.60 4.10 Single channel demagnetization 3.60 2.60 Eoff (J) 2.10 1.60 1.10 0.60 0.10 0.3 0.5 0.7 Four channels demagnetization 1.1 GIPD0511130116LM TI VE -I NA CT IV E Iout (A) 0.9 -I 0.1 NA CT 3.10 IN AC 10 Demagnetization energy DocID14174 Rev 13 17/25 25 Package mechanical data 11 VNI4140K Package mechanical data IV E In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Table 9. PowerSSO-24 mechanical data NA CT mm Symbol Typ. 2.15 A2 2.15 a1 0 b 0.33 c 0.23 D 10.10 E 7.4 IV e CT e3 G G1 10.1 NA H h X 18/25 Max. 2.47 2.40 0.075 0.51 0.32 10.50 7.6 0.8 8.8 0.1 0.06 10.5 0.4 0.85 10deg 4.1 4.7 6.5 7.1 IN AC TI VE Y 0.55 -I L N E A -I Min. DocID14174 Rev 13 VNI4140K Package mechanical data IV E -I NA CT IV E Figure 15. PowerSSO-24 package dimensions TI VE -I NA CT Figure 16. PowerSSO-24 tube shipment (no suffix) Base quantity 49 Bulk quantity 1225 Tube length (± 0.5) 532 A 3.5 B 13.8 C (± 0.1) 0.6 IN AC Note: Table 10. PowerSSO-24 tube shipment All dimensions are in mm. DocID14174 Rev 13 19/25 25 Package mechanical data VNI4140K CT IV E -I NA CT IV E Figure 17. PowerSSO-24 reel shipment (suffix “TR”) Table 11. PowerSSO-24 reel dimensions Bulk quantity -I A (max.) NA Base quantity 1000 330 1.5 C (± 0.2) 13 TI VE B (min.) F 20.2 G (2 ± 0) 24.4 N (min.) 100 T (max.) 30.4 IN AC 20/25 1000 DocID14174 Rev 13 VNI4140K Package mechanical data TI VE -I NA CT IV E -I NA CT IV E Figure 18. PowerSSO-24™ tape dimensions W 24 Tape hole spacing P0 (± 0.1) 4 Component spacing P 12 Hole diameter D (± 0.05) 1.55 Hole diameter D1 (min.) 1.5 Hole position F (± 0.1) 11.5 Compartment depth K (max.) 2.85 Hole spacing P1 (± 0.1) 2 IN AC Note: Table 12. PowerSSO-24™ tape dimensions Tape width According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb 1986 DocID14174 Rev 13 21/25 25 Package mechanical data VNI4140K Figure 19. VN14140k suggested footprint    NA CT  ±  IV E -I 5  IV E  CT 6ROGHU0DVN2SHQLQJ STMicroelectronics is not responsible for any PCB related issues. The footprint shown in the above figure is a suggestion which might not be in line to the customer PCB supplier design rules. -I Note:   NA     IN AC TI VE All dimensions are in mm. 22/25 DocID14174 Rev 13 VNI4140K Ordering information Table 13. Order code Packaging VNI4140K PowerSSO-24 VNI4140KTR PowerSSO-24 IV E Package Tube Tape and reel TI VE -I NA CT IV E -I NA CT Order code IN AC 12 Ordering information DocID14174 Rev 13 23/25 25 Revision history 13 VNI4140K Revision history Table 14. Document revision history Revision 16-Nov-2007 1 Initial release. 26-Nov-2007 2 Updated electrical parameters values. 08-Jul-2008 3 Inserted: Figure 4 on page 9 and Section 9: Reverse polarity protection on page 16. 08-Apr-2008 4 Added ILGND parameter in Table 4 on page 6. 27-Aug-2009 5 Updated Section 9: Reverse polarity protection. 09-Dec-2009 6 Added Section 10: Conformity to IEC 61000-4-2 ESD immunity test. 15-Apr-2010 7 Updated Table 5 on page 6. 06-Feb-2012 8 Inserted feature: conformity to IEC 61000-4-2 ESD immunity test in cover page. Removed chapter: conformity to IEC 61000-4-2 ESD immunity test. 05-Mar-2012 9 19-Mar-2012 10 20-Dec-2012 11 NA CT -I E IV CT Suggested footprint inserted. In Table 4 parameter ILGND has been added. Minor text changes. Operating temperature range extended. 12 Updated EAS value in Table 2: Absolute maximum ratings. Added Figure 14. 13 Updated Section 9. NA 06-Nov-2013 IN AC TI VE -I 11-Dec-2013 Changes 24/25 IV E Date DocID14174 Rev 13 Please Read Carefully: NA CT IV E VNI4140K Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. -I All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. 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Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. IN AC ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2013 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com DocID14174 Rev 13 25/25 25