TPA6130A2

TPA6130A2 YZH www.ti.com RTJ SLOS488B – NOVEMBER 2006 – REVISED FEBRUARY 2008 138-mW DIRECTPATH™ STEREO HEADPHONE AMPLIFIER WITH I2C VOLUME CONTROL 1 FEATURES • • DirectPath™ Ground-Referenced Outputs – Eliminates Output DC Blocking Capacitors – Reduces Board Area – Reduces Component Height and Cost – Full Bass Response Without Attenuation • Power Supply Voltage Range: 2.5 V to 5.5 V • 64 Step Audio Taper Volume Control • High Power Supply Rejection Ratio (>100 dB PSRR) • Differential Inputs for Maximum Noise Rejection (68 dB CMRR) • High-Impedance Outputs When Disabled • Advanced Pop and Click Suppression Circuitry 2 • • • • • • Digital I2C Bus Control – Per Channel Mute and Enable – Software Shutdown – Multi-Mode Support: Stereo HP, Dual Mono HP, and Single-Channel BTL Operation – Amplifier Status Space Saving Packages – 20 Pin, 4 mm x 4 mm QFN – 16 ball, 2 mm x 2 mm WCSP ESD Protection of 8 kV HBM and IEC Contact APPLICATIONS Mobile Phones Portable Media Players Notebook Computers High Fidelity Applications DESCRIPTION The TPA6130A2 is a stereo DirectPath™ headphone amplifier with I2C digital volume control. The TPA6130A2 has minimal quiescent current consumption, with a typical IDD of 4 mA, making it optimal for portable applications. The I2C control allows maximum flexibility with a 64 step audio taper volume control, channel independent enables and mutes, and the ability to configure the outputs into stereo, dual mono, or a single receiver speaker BTL amplifier that drives 300 mW of power into 16 Ω loads. The TPA6130A2 is a high fidelity amplifier with an SNR of 98 dB. A PSRR greater than 100 dB enables direct-to-battery connections without compromising the listening experience. The output noise of 9 µVrms (typical A-weighted) provides a minimal noise background during periods of silence. Configurable differential inputs and high CMRR allow for maximum noise rejection in the noisy environment of a mobile device. TPA6130A2 packaging includes a 2 by 2 mm chip-scale package, and a 4 by 4 mm QFN package. SIMPLIFIED APPLICATION DIAGRAM Audio Source GPIO SD Left Out M 0.47 mF Left Out P 0.47 mF Right Out M 0.47 mF Right Out P 0.47 mF CPP CPN CPVSS 1 mF 1 mF VDD 1 mF RIGHTINP RIGHTINM TPA6130A2 HPRIGHT GND GND VDD LEFTINP LEFTINM HPLEFT IC 2 SCL SDA 1 mF 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DirectPath is a trademark of Texas Instruments. Copyright © 2006–2008, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TPA6130A2 SLOS488B – NOVEMBER 2006 – REVISED FEBRUARY 2008 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. FUNCTIONAL BLOCK DIAGRAM LEFTINM Left LEFTINP HPLEFT Gain Control De-Pop RIGHTINM Right RIGHTINP HPRIGHT Thermal Current Limit CPP CPN CPVSS Charge Pump Power Management I2C Interface and Control SD SDA SCL VDD GND VDD GND Headphone channels are independently enabled and muted. The I2C interface controls channel gain, device modes, and charge pump activation. The charge pump generates a negative supply voltage for the output amplifiers. This allows a 0 V bias at the outputs, eliminating the need for bulky output capacitors. The thermal block detects faults and shuts down the device before damage occurs. The I2C register records thermal fault conditions. The current limit block prevents the output current from getting high enough to damage the device. The De-Pop block eliminates audible pops during power-up, power-down, and amplifier enable and disable events. 2 Product Folder Link(s): TPA6130A2 Copyright © 2006–2008, Texas Instruments Incorporated TPA6130A2 www.ti.com SLOS488B – NOVEMBER 2006 – REVISED FEBRUARY 2008 CPVSS 16 15 GND VDD 20 19 18 17 A1 CPN B1 HPLEFT C1 VDD D1 HPRIGHT A2 CPP B2 CPVSS C2 GND D2 SCL A3 GND B3 LEFTINP C3 A4 VDD B4 LEFTINM C4 A4 VDD B4 LEFTINM C4 A3 GND B3 LEFTINP C3 A2 CPP B2 CPVSS C2 GND D2 SCL A1 CPN B1 HPLEFT C1 VDD CPN CPP LEFTINM LEFTINP GND RIGHTINP RIGHTINM 1 CPVSS HPLEFT GND VDD HPRIGHT 2 3 4 14 13 12 T op View RIGHTINP RIGHTINM D3 SDA D4 SD RIGHTINM RIGHTINP D4 SD D3 SDA 5 6 7 8 9 10 11 D1 GND Top (Symbol Side) View WCSP Package (YZH) Bottom (Ball Side) View WCSP Package (YZH) Top View QFN Package (RTJ) TERMINAL FUNCTIONS TERMINAL NAME VDD GND CPP CPN LEFTINM LEFTINP CPVSS HPLEFT RIGHTINM RIGHTINP BALL WCSP A4 A3 A2 A1 B4 B3 B2 B1 C4 C3 PIN QFN 20 19 18 17 1 2 15, 16 14 5 4 3, 9, 10, 13 12 6 7 8 11 Die Pad INPUT/ OUTPUT/ POWER (I/O/P) P P P P I I P O I I DESCRIPTION Charge pump voltage supply. VDD must be connected to the common VDD voltage supply. Decouple to GND (pin 19 on the QFN) with its own 1 µF capacitor. Charge pump ground. GND must be connected to common supply GND. It is recommended that this pin be decoupled to the VDD of the charge pump pin (pin 20 on the QFN). Charge pump flying capacitor positive terminal. Connect one side of the flying capacitor to CPP. Charge pump flying capacitor negative terminal. Connect one side of the flying capacitor to CPN. Left channel negative differential input. Impedance must be matched to LEFTINP. Connect the left input to LEFTINM when using single-ended inputs. Left channel positive differential input. Impedance must be matched to LEFTINM. AC ground LEFTINP near signal source while maintaining matched impedance to LEFTINM when using single-ended inputs. Negative supply generated by the charge pump. Decouple to pin 19 on the QFN or a GND plane. Use a 1 µF capacitor. Headphone left channel output. Connect to left terminal of headphone jack. Right channel negative differential input. Impedance must be matched to RIGHTINP. Connect the right input to RIGHTINM when using single-ended inputs. Right channel positive differential input. Impedance must be matched to RIGHTINM. AC ground RIGHTINP near signal source while maintaining matched impedance to RIGHTINM when using single-ended inputs. Analog ground. Must be connected to common supply GND. It is recommended that this pin be used to decouple VDD for analog. Use pin 13 to decouple pin 12 on the QFN package. Analog VDD. VDD must be connected to common VDD supply. Decouple with its own 1-µF capacitor to analog ground (pin 13 on the QFN). Shutdown. Active low logic. 5V tolerant input. SDA - I2C Data. 5V tolerant input. SCL - I2C Clock. 5V tolerant input. Headphone light channel output. Connect to the right terminal of the headphone jack. Solder the thermal pad on the bottom of the QFN package to the GND plane of the PCB. It is required for mechanical stability and will enhance thermal performance. GND VDD SD SDA SCL HPRIGHT Thermal pad C2 C1 D4 D3 D2 D1 N/A P P I I/O I O P GND SDA SCL SD HPRIGHT Copyright © 2006–2008, Texas Instruments Incorporated 3 Product Folder Link(s): TPA6130A2 TPA6130A2 SLOS488B – NOVEMBER 2006 – REVISED FEBRUARY 2008 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range, TA = 25°C (unless otherwise noted) VALUE / UNIT Supply voltage, VDD VI Input voltage Output continuous total power dissipation TA TJ Tstg Operating free-air temperature range Operating junction temperature range Storage temperature range Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ESD Protection IEC Contact ESD Protection (2) Minimum Load Impedance (1) (2) HBM Output Pins HBM All Other Pins No External Protection V14MLA0603 Varistors Used for External Protection RIGHTINx, LEFTINx SD, SCL, SDA –0.3 V to 6.0 V –2.7 V to 3.6 V –0.3 V to 7 V See Dissipation Rating Table –40°C to 85°C –40°C to 125°C –65°C to 150°C 260°C 8 kV 3.5 kV 8 kV 15 kV 12.8 Ω Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Tested to IEC 61000-4-2 standards on a TPA6130A2 EVM. DISSIPATION RATINGS TABLE PACKAGE RTJ YZH (1) (2) TA ≤ 25°C POWER RATING 4100 mW 970 mW DERATING FACTOR (1) (2) 41 mW/°C 9.7 mW/°C TA = 70°C POWER RATING 2250 mW 530 mW TA = 85°C POWER RATING 1640 mW 390 mW Derating factor measured with JEDEC High K board: 1S2P - One signal layer and two plane layers. See JEDEC Standard 51-3 for Low-K board, JEDEC Standard 51-7 for High-K board, and JEDEC Standard 51-12 for using package thermal information. Please see JEDEC document page for downloadable copies: http://www.jedec.org/download/default.cfm. AVAILABLE OPTIONS TA –40°C to 85°C (1) (2) PACKAGED DEVICES (1) 20-pin, 4 mm × 4 mm QFN 16-ball, 1,98 mm × 1.98 mm (+0,01mm, –0,09 mm) PART NUMBER TPA6130A2RTJ (2) TPA6130A2YZH SYMBOL BSG BRU For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. The RTJ package is only available taped and reeled. To order, add the suffix “R” to the end of the part number for a reel of 3000, or add the suffix “T” to the end of the part number for a reel of 250 (e.g., TPA6130A2RTJR). RECOMMENDED OPERATING CONDITIONS MIN Supply voltage, VDD VIH VIL TA High-level input voltage Low-level input voltage SCL, SDA, SD SCL, SDA SD –40 2.5 1.3 0.6 0.35 85 MAX 5.5 UNIT V V V V °C Operating free-air temperature 4 Product Folder Link(s): TPA6130A2 Copyright © 2006–2008, Texas Instruments Incorporated TPA6130A2 www.ti.com SLOS488B – NOVEMBER 2006 – REVISED FEBRUARY 2008 ELECTRICAL CHARACTERISTICS TA = 25°C (unless otherwise noted) PARAMETER |VOS| PSRR CMRR |IIH| |IIL| Output offset voltage Power supply rejection ratio Common mode rejection ratio High-level input current Low-level input current TEST CONDITIONS VDD = 2.5 V to 5.5 V, inputs grounded VDD = 2.5 V to 5.5 V, inputs grounded VDD = 2.5 V to 5.5 V VDD = 5.5 V, VI = VDD VDD = 5.5 V, VI = 0 V VDD = 2.5 V to 5.5 V, SD = VDD Shutdown mode, VDD = 2.5V to 5.5 V, SD = 0 V IDD Supply current SW Shutdown mode, VDD = 2.5V to 5.5 V, SWS = 1 Both HP amps disabled, VDD = 2.5V to 5.5 V, SWS = 0, Charge Pump enabled, SD = VDD SCL, SDA SD SCL, SDA, SD 4 0.4 25 1.4 MIN TYP MAX 150 –109 –68 1 10 1 6 1 75 2.5 400 –90 UNIT µV dB dB µA µA mA µA µA mA TIMING CHARACTERISTICS (1) (2) For I2C Interface Signals Over Recommended Operating Conditions (unless otherwise noted) PARAMETER fSCL tw(H) tw(L) tsu1 th1 t(buf) tsu2 th2 tsu3 (1) (2) Frequency, SCL Pulse duration, SCL high Pulse duration, SCL low Setup time, SDA to SCL Hold time, SCL to SDA Bus free time between stop and start condition Setup time, SCL to start condition Hold time, start condition to SCL Setup time, SCL to stop condition VPull-up = VDD A pull-up resistor ≤2 kΩ is required for a 5 V I2C bus voltage. TEST CONDITIONS No wait states 0.6 1.3 300 10 1.3 0.6 0.6 0.6 MIN TYP MAX 400 UNIT kHz µs µs ns ns µs µs µs µs tw(H) SCL tw(L) t su1 SDA th1 Figure 1. SCL and SDA Timing Copyright © 2006–2008, Texas Instruments Incorporated 5 Product Folder Link(s): TPA6130A2 TPA6130A2 SLOS488B – NOVEMBER 2006 – REVISED FEBRUARY 2008 www.ti.com SCL th2 tsu2 SDA t(buf) tsu3 Start Condition Stop Condition Figure 2. Start and Stop Conditions Timing OPERATING CHARACTERISTICS VDD = 3.6 V , TA = 25°C, RL = 16 Ω (unless otherwise noted) PARAMETER TEST CONDITIONS VDD = 2.5V Stereo, Outputs out of phase, THD = 1%, f = 1 kHz, Gain = 0.1 dB PO Output power Bridge-tied load, THD = 1%, f = 1 kHz, Gain = 0.1 dB VDD = 3.6V VDD = 5V VDD = 2.5V VDD = 3.6V VDD = 5V f = 100 Hz THD+N Total harmonic distortion plus noise PO = 35 mW 200 mVpp ripple, f = 217 Hz kSVR ΔAv Vn fosc Supply ripple rejection ratio Gain matching Slew rate Noise output voltage Charge pump switching frequency Start-up time from shutdown Differential input impedance SNR Signal-to-noise ratio Thermal shutdown ZO CO Tri-state HP output impedance Output capacitance See Figure 33 Po = 35 mW Threshold Hysteresis HiZ left and right bits set. HP amps disabled. DC value. 98 180 35 25 80 dB °C °C MΩ pF VDD = 3.6V, A-weighted, Gain = 0.1 dB 300 200 mVpp ripple, f = 1 kHz 200 mVpp ripple, f = 20 kHz f = 1 kHz f = 20 kHz MIN TYP 60 127 138 110 230 290 0.0029% 0.0055% 0.0027% -97 -93 -76 1% 0.3 9 400 5 500 V/µs µVRMS kHz ms -90 dB mW MAX UNIT 6 Product Folder Link(s): TPA6130A2 Copyright © 2006–2008, Texas Instruments Incorporated TPA6130A2 www.ti.com SLOS488B – NOVEMBER 2006 – REVISED FEBRUARY 2008 TYPICAL CHARACTERISTICS C(PUMP, DECOUPLE, ,BYPASS, CPVSS) = 1 µF, CI = 2.2µF. All THD + N graphs taken with outputs out of phase (unless otherwise noted). Table of Graphs FIGURE Total harmonic distortion + noise Total harmonic distortion + noise Supply voltage rejection ratio Common mode rejection ratio Output power Output voltage Power Dissipation Differential Input Impedance Shutdown time Startup time TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER THD+N - Total Harmonic Distortion + Noise - % THD+N - Total Harmonic Distortion + Noise - % vs Output power vs Frequency vs Frequency vs Frequency vs Load vs Load vs Output power vs Gain 3–8 9–22 23-25 26-27 28-29 30-31 32 33 34 35 TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER THD+N - Total Harmonic Distortion + Noise - % TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 10 RL = 16 W, Gain = 0.1 dB, fIN = 1 kHz, Stereo VDD = 2.5 V VDD = 3 V 0.1 VDD = 3.6 V 0.01 VDD = 5 V 0.001 100m 10 RL = 16 W, Gain = 0.1 dB, VDD = 3.6 V, fIN = 1 kHz, Stereo In Phase 10 RL = 32 W, Gain = 0.1 dB, VDD = 3.6 V, 1 fIN = 1 kHz, Stereo In Phase 1 1 0.1 Out of Phase 0.1 Out of Phase 0.01 0.01 0.001 100m 1m 10m 100m 1 0.001 100m PO - Output Power - W 1m 10m 100m PO - Output Power - W 1 1m 10m 100m 1 PO - Output Power - W Figure 3. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER THD+N - Total Harmonic Distortion + Noise - % THD+N - Total Harmonic Distortion + Noise - % Figure 4. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 10 RL = 16 W, Gain = 6.1 dB, fIN = 1 kHz, 1 BTL VDD = 2.5 V VDD = 3 V 0.1 VDD = 3.6 V VDD = 5 V 0.01 THD+N - Total Harmonic Distortion + Noise - % Figure 5. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 10 RL = 32 W, Gain = 6.1 dB, fIN = 1 kHz, 1 BTL VDD = 3.6 V VDD = 5 V 10 RL = 32 W, Gain = 0.1 dB, fIN = 1 kHz, 1 Stereo VDD = 2.5 V 0.1 VDD = 5 V 0.01 VDD = 3.6 V 0.001 100m VDD = 3 V 1m 10m 100m 1 0.1 VDD = 2.5 V VDD = 3 V 0.01 0.001 100m 1m 10m 100m 12 0.001 100m 1m 10m 100m 12 PO - Output Power - W PO - Output Power - W PO - Output Power - W Figure 6. Figure 7. Figure 8. Copyright © 2006–2008, Texas Instruments Incorporated 7 Product Folder Link(s): TPA6130A2 TPA6130A2 SLOS488B – NOVEMBER 2006 – REVISED FEBRUARY 2008 www.ti.com TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY THD+N - Total Harmonic Distortion + Noise - % TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY THD+N - Total Harmonic Distortion + Noise - % 100 RL = 16 W, VDD = 3 V, 10 Gain = 0.1 dB, Stereo PO = 40 mW PO = 20 mW 0.1 PO = 5 mW TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY THD+N - Total Harmonic Distortion + Noise - % 1 RL = 16 W, VDD = 3.6 V, Gain = 0.1 dB, Stereo 0.1 PO = 70 mW PO = 35 mW 0.01 PO = 5 mW 1 RL = 16 W, VDD = 2.5 V, Gain = 0.1 dB, Stereo 0.1 PO = 20 mW PO = 1 mW 0.01 PO = 4 mW 0.001 20 1 0.01 100 1k f - Frequency - Hz 10k 20k 0.001 20 100 1k f - Frequency - Hz 10k 20k 0.001 20 100 1k f - Frequency - Hz 10k 20k Figure 9. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY THD+N - Total Harmonic Distortion + Noise - % THD+N - Total Harmonic Distortion + Noise - % 1 RL = 16 W, VDD = 5 V, Gain = 0.1 dB, Stereo 0.1 PO = 50 mW Figure 10. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 1 RL = 32 W, VDD = 2.5 V, Gain = 0.1 dB, Stereo 0.1 PO = 20 mW Figure 11. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY THD+N - Total Harmonic Distortion + Noise - % 1 RL = 32 W, VDD = 3 V, Gain = 0.1 dB, Stereo 0.1 PO = 20 mW PO = 40 mW 0.01 PO = 80 mW 0.01 PO = 5 mW PO = 1 mW 0.01 PO = 4 mW 0.001 20 PO = 5 mW 0.001 20 100 1k f - Frequency - Hz 10k 20k 0.001 20 100 1k f - Frequency - Hz 10k 20k 100 1k f - Frequency - Hz 10k 20k Figure 12. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY THD+N - Total Harmonic Distortion + Noise - % 1 RL = 32 W, VDD = 3.6 V, Gain = 0.1 dB, Stereo 0.1 PO = 35 mW Figure 13. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY THD+N - Total Harmonic Distortion + Noise - % THD+N - Total Harmonic Distortion + Noise - % 1 RL = 32 W, VDD = 5 V, Gain = 0.1 dB, Stereo 0.1 PO = 70 mW PO = 50 mW Figure 14. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 1 RL = 16 W, VDD = 2.5 V, Gain = 6.1 dB, BTL 0.1 PO = 100 mW PO = 5 mW PO = 70 mW 0.01 0.01 0.01 PO = 5 mW 0.001 20 PO = 5 mW 0.001 20 PO = 25 mW 0.001 20 100 1k f - Frequency - Hz 10k 20k 100 1k f - Frequency - Hz 10k 20k 100 1k f - Frequency - Hz 10k 20k Figure 15. Figure 16. Figure 17. 8 Product Folder Link(s): TPA6130A2 Copyright © 2006–2008, Texas Instruments Incorporated TPA6130A2 www.ti.com SLOS488B – NOVEMBER 2006 – REVISED FEBRUARY 2008 TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY THD+N - Total Harmonic Distortion + Noise - % THD+N - Total Harmonic Distortion + Noise - % TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY THD+N - Total Harmonic Distortion + Noise - % TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 1 RL = 32 W, VDD = 2.5 V, Gain = 6.1 dB, BTL 0.1 PO = 100 mW PO = 5 mW 0.01 1 RL = 16 W, VDD = 3.6 V, Gain = 6.1 dB, BTL 0.1 PO = 200 mW PO = 25 mW 0.01 1 RL = 16 W, VDD = 5 V, Gain = 6.1 dB, BTL 0.1 PO = 200 mW 0.01 PO = 25 mW 0.001 20 PO = 100 mW 100 1k f - Frequency - Hz 10k 20k PO = 100 mW 0.001 20 100 1k f - Frequency - Hz 10k 20k PO = 25 mW 0.001 20 100 1k f - Frequency - Hz 10k 20k Figure 18. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY THD+N - Total Harmonic Distortion + Noise - % THD+N - Total Harmonic Distortion + Noise - % 1 RL = 32 W, VDD = 3.6 V, Gain = 6.1 dB, BTL 0.1 PO = 200 mW PO = 25 mW Figure 19. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 1 RL = 32 W, VDD = 5 V, Gain = 6.1 dB, BTL 0.1 PO = 200 mW PO = 25 mW 0 Figure 20. SUPPLY VOLTAGE REJECTION RATIO vs FREQUENCY kSVR - Supply Voltage Rejection Ratio - V RL = 16 W, -20 Gain = 0.1 dB, Cp = 1 mF, Stereo -40 -60 VDD = 3.6 V VDD = 2.5 V 0.01 0.01 -80 -100 -120 20 VDD = 5 V 0.001 20 PO = 100 mW 100 1k f - Frequency - Hz 10k 20k 0.001 20 PO = 100 mW 100 1k f - Frequency - Hz 10k 20k 100 1k 10k 20k f - Frequency - Hz Figure 21. SUPPLY VOLTAGE REJECTION RATIO vs FREQUENCY 0 0 Figure 22. SUPPLY VOLTAGE REJECTION RATIO vs FREQUENCY RL = 16 W, -20 Figure 23. COMMON MODE REJECTION RATIO vs FREQUENCY CMRR - Common-Mode Rejection Ratio - dB 0 -10 -20 -30 -40 -50 -60 -70 -80 20 VDD = 5 V VDD = 2.5 V VDD = 3.6 V kSVR - Supply Voltage Rejection Ratio - V RL = 32 W, -20 kSVR - Supply Voltage Rejection Ratio - V RL = 16 W, Gain = 0.1 dB, CI = 2.2 mF, Stereo Gain = 0.1 dB, Cp = 1 mF, Stereo Gain = 6.1 dB, Cp = 1 mF, BTL -40 VDD = 3.6 V VDD = 2.5 V -40 -60 -60 VDD = 3.6 V VDD = 2.5 V -80 -80 -100 -120 20 VDD = 5 V -100 -120 20 VDD = 5 V 100 1k 10k 20k 100 1k 10k 20k 100 1k 10k 20k f - Frequency - Hz f - Frequency - Hz f - Frequency - Hz Figure 24. Figure 25. Figure 26. Copyright © 2006–2008, Texas Instruments Incorporated 9 Product Folder Link(s): TPA6130A2 TPA6130A2 SLOS488B – NOVEMBER 2006 – REVISED FEBRUARY 2008 www.ti.com COMMON MODE REJECTION RATIO vs FREQUENCY CMRR - Common-Mode Rejection Ratio - dB 0 -10 -20 -30 -40 -50 -60 -70 -80 20 VDD = 5 V VDD = 2.5 V VDD = 3.6 V 250 OUTPUT POWER vs LOAD 500 OUTPUT POWER vs LOAD fIN = 1 kHz, Gain = 6.1 dB, THD+N = 1%, BTL VDD = 5 V RL = 16 W, PO - Output Power - mW BTL 150 PO - Output Power - mW Gain = 6.1 dB, CI = 2.2 mF, 200 fIN = 1 kHz, Gain = 0.1 dB, THD+N = 1%, Stereo VDD = 5 V 400 300 100 VDD = 3.6 V 200 VDD = 3.6 V 50 VDD = 2.5 V 100 VDD = 2.5 V 100 1k 10k 20k 0 10 100 1k 0 10 100 1k f - Frequency - Hz Load - W Load - W Figure 27. OUTPUT VOLTAGE vs LOAD 6 5.5 VDD = 5 V Figure 28. OUTPUT VOLTAGE vs LOAD 13 1 Figure 29. POWER DISSIPATION vs OUTPUT POWER RL = 16 W, Gain = 0.1 dB, Stereo VDD = 5 V 4.5 4 3.5 3 2.5 2 1.5 1 10 100 Load - W VDD = 3.6 V THD + N = 1% Gain = 0.1 dB, fIN = 1 kHz, Stereo 1000 VDD = 2.5 V 9 VDD = 5 V PD - Power Dissipation - W VO - Output Voltage - VPP VO - Output Voltage - VPP 5 11 0.8 0.6 7 VDD = 3.6 V 5 VDD = 2.5 V THD + N = 1% Gain = 6.1 dB, fIN = 1 kHz, BTL 1 10 100 Load - W 1000 0.4 VDD = 3.6 V 3 0.2 VDD = 2.5 V 0 0 50 100 150 200 250 300 350 400 PO - Output Power - mW Figure 30. Figure 31. DIFFERENTIAL INPUT IMPEDANCE vs GAIN 100 Figure 32. Differential Input Impedance - kW 90 80 70 60 50 40 VDD = 3.6 V 30 -60 -50 -40 -30 -20 -10 0 10 Gain - dB Figure 33. 10 Product Folder Link(s): TPA6130A2 Copyright © 2006–2008, Texas Instruments Incorporated TPA6130A2 www.ti.com SLOS488B – NOVEMBER 2006 – REVISED FEBRUARY 2008 1 0.75 0.5 Output SWS Disable Voltage - V 0.25 0 -0.25 -0.5 -0.75 -1 0 200m 400m 600m 800m 1m 1.2m 1.4m 1.6m 1.8m 2m t - Time - s Figure 34. Shutdown Time 1 0.75 0.5 SWS Enable Output Voltage - V 0.25 0 -0.25 -0.5 -0.75 -1 0 1m 2m 3m 4m 5m 6m 7m 8m 9m 10m t - Time - s Figure 35. Startup Time Copyright © 2006–2008, Texas Instruments Incorporated 11 Product Folder Link(s): TPA6130A2 TPA6130A2 SLOS488B – NOVEMBER 2006 – REVISED FEBRUARY 2008 www.ti.com APPLICATION INFORMATION SIMPLIFIED APPLICATIONS CIRCUIT VDD 1 mF 1 mF 20 LEFTINM 1 0.47 mF 0.47 mF LEFTINP 2 GND 3 RIGHTINP 0.47 mF 0.47 mF SD 19 18 17 CPVSS GND CPM VDD CPP 16 15 14 CPVSS HPLEFT GND VDD VDD HPRIGHT 1 mF TPA6130A2 13 12 11 4 5 6 SDA RIGHTINM 1 mF 7 SCL 8 GND SCL 9 10 GND Headphone Amplifiers Single-supply headphone amplifiers typically require dc-blocking capacitors. The capacitors are required because most headphone amplifiers have a dc bias on the outputs pin. If the dc bias is not removed, the output signal is severely clipped, and large amounts of dc current rush through the headphones, potentially damaging them. The top drawing in Figure 36 illustrates the conventional headphone amplifier connection to the headphone jack and output signal. DC blocking capacitors are often large in value. The headphone speakers (typical resistive values of 16 Ω or 32 Ω) combine with the dc blocking capacitors to form a high-pass filter. Equation 1 shows the relationship between the load impedance (RL), the capacitor (CO), and the cutoff frequency (fC). 1 fc + 2pRLC O (1) CO can be determined using Equation 2, where the load impedance and the cutoff frequency are known. 1 CO + 2pRLf c SDA SD (2) If fc is low, the capacitor must then have a large value because the load resistance is small. Large capacitance values require large package sizes. Large package sizes consume PCB area, stand high above the PCB, increase cost of assembly, and can reduce the fidelity of the audio output signal. Two different headphone amplifier applications are available that allow for the removal of the output dc blocking capacitors. The Capless amplifier architecture is implemented in the same manner as the conventional amplifier with the exception of the headphone jack shield pin. This amplifier provides a reference voltage, which is 12 Product Folder Link(s): TPA6130A2 Copyright © 2006–2008, Texas Instruments Incorporated TPA6130A2 www.ti.com SLOS488B – NOVEMBER 2006 – REVISED FEBRUARY 2008 connected to the headphone jack shield pin. This is the voltage on which the audio output signals are centered. This voltage reference is half of the amplifier power supply to allow symmetrical swing of the output voltages. Do not connect the shield to any GND reference or large currents will result. The scenario can happen if, for example, an accessory other than a floating GND headphone is plugged into the headphone connector. See the second block diagram and waveform in Figure 36. Conventional CO VOUT CO GND Capless VDD VOUT GND VBIAS DirectPathTM VDD VBIAS VDD VDD/2 GND VSS Figure 36. Amplifier Applications The DirectPath™ amplifier architecture operates from a single supply but makes use of an internal charge pump to provide a negative voltage rail. Combining the user provided positive rail and the negative rail generated by the IC, the device operates in what is effectively a split supply mode. The output voltages are now centered at zero volts with the capability to swing to the positive rail or negative rail. The DirectPath™ amplifier requires no output dc blocking capacitors, and does not place any voltage on the sleeve. The bottom block diagram and waveform of Figure 36 illustrate the ground-referenced headphone architecture. This is the architecture of the TPA6130A2. Input-Blocking Capacitors DC input-blocking capacitors block the dc portion of the audio source, and allow the inputs to properly bias. Maximum performance is achieved when the inputs of the TPA6130A2 are properly biased. Performance issues such as pop are optimized with proper input capacitors. The dc input-blocking capacitors may be removed provided the inputs are connected differentially and within the input common mode range of the amplifier, the audio signal does not exceed ±3 V, and pop performance is sufficient. Copyright © 2006–2008, Texas Instruments Incorporated 13 Product Folder Link(s): TPA6130A2 TPA6130A2 SLOS488B – NOVEMBER 2006 – REVISED FEBRUARY 2008 www.ti.com CIN is a theoretical capacitor used for mathematical calculations only. Its value is the series combination of the dc input-blocking capacitors, C(DCINPUT-BLOCKING). Use Equation 3 to determine the value of C(DCINPUT-BLOCKING). For example, if CIN is equal to 0.22 µF, then C(DCINPUT-BLOCKING) is equal to about 0.47 µF. 1C CIN = (DCINPUT-BLOCKING) 2 (3) The two C(DCINPUT-BLOCKING) capacitors form a high-pass filter with the input impedance of the TPA6130A2. Use Equation 3 to calculate CIN, then calculate the cutoff frequency using CIN and the differential input impedance of the TPA6130A2, RIN, using Equation 4. Note that the differential input impedance changes with gain. See Figure 33 for input impedance values. The frequency and/or capacitance can be determined when one of the two values are given. 1 1 fc IN + or C IN + 2p fc R 2p RIN C IN IN IN (4) If a high pass filter with a -3 dB point of no more than 20 Hz is desired over all gain settings, the minimum impedance would be used in the above equation. Figure 33 shows this to be 37 kΩ. The capacitor value by the above equation would be 0.215 µF. However, this is CIN, and the desired value is for C(DCINPUT-BLOCKING). Multiplying CIN by 2 yields 0.43 µF, which is close to the standard capacitor value of 0.47 µF. Place 0.47 µF capacitors at each input terminal of the TPA6130A2 to complete the filter. Charge Pump Flying Capacitor and CPVSS Capacitor The charge pump flying capacitor serves to transfer charge during the generation of the negative supply voltage. The CPVSS capacitor must be at least equal to the flying capacitor in order to allow maximum charge transfer. Low ESR capacitors are an ideal selection, and a value of 1 µF is typical. Decoupling Capacitors The TPA6130A2 is a DirectPath™ headphone amplifier that requires adequate power supply decoupling to ensure that the noise and total harmonic distortion (THD) are low. Use good low equivalent-series-resistance (ESR) ceramic capacitors, typically 1.0 µF. Find the smallest package possible, and place as close as possible to the device VDD lead. Placing the decoupling capacitors close to the TPA6130A2 is important for the performance of the amplifier. Use a 10 µF or greater capacitor near the TPA6130A2 to filter lower frequency noise signals. The high PSRR of the TPA6130A2 will make the 10 µF capacitor unnecessary in most applications. Layout Recommendations Exposed Pad On TPA6130A2RTJ Package Option Solder the exposed metal pad on the TPA6130A2RTJ QFN package to the a pad on the PCB. The pad on the PCB may be grounded or may be allowed to float (not be connected to ground or power). If the pad is grounded, it must be connected to the same ground as the GND pins (3, 9, 10, 13, and 19). See the layout and mechanical drawings at the end of the datasheet for proper sizing. Soldering the thermal pad improves mechanical reliability, improves grounding of the device, and enhances thermal conductivity of the package. GND Connections The GND pin for charge pump should be decoupled to the charge pump VDD pin, and the GND pin adjacent to the Analog VDD pin should be separately decoupled to each other. I2C CONTROL INTERFACE DETAILS Addressing the TPA6130A2 The device operates only as a slave device whose address is 1100000 binary. 14 Product Folder Link(s): TPA6130A2 Copyright © 2006–2008, Texas Instruments Incorporated TPA6130A2 www.ti.com SLOS488B – NOVEMBER 2006 – REVISED FEBRUARY 2008 GENERAL I2C OPERATION The I2C bus employs two signals; SDA (data) and SCL (clock), to communicate between integrated circuits in a system. Data is transferred on the bus serially, one bit at a time. The address and data are transferred in byte (8-bit) format with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data terminal (SDA) while the clock is high to indicate start and stop conditions. A high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit transitions must occur within the low time of the clock period. These conditions are shown in Figure 37. The master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another device and then wait for an acknowledge condition. The TPA6130A2 holds SDA low during acknowledge clock period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same signals via a bidirectional bus using a wired-AND connection. An external pull-up resistor must be used for the SDA and SCL signals to set the HIGH level for the bus. When the bus level is 5 V, pull-up resistors between 1 kΩ and 2 kΩ in value must be used. 8- Bit Data for Register (N) 8- Bit Data for Register (N+1) Figure 37. Typical I2C Sequence There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is shown in Figure 37. SINGLE-AND MULTIPLE-BYTE TRANSFERS The serial control interface supports both single-byte and multi-byte read/write operations for all registers. During multiple-byte read operations, the TPA6130A2 responds with data, a byte at a time, starting at the register assigned, as long as the master device continues to respond with acknowledges. The TPA6130A2 supports sequential I2C addressing. For write transactions, if a register is issued followed by data for that register and all the remaining registers that follow, a sequential I2C write transaction has taken place. For I2C sequential write transactions, the register issued then serves as the starting point, and the amount of data subsequently transmitted, before a stop or start is transmitted, determines to how many registers are written. SINGLE-BYTE WRITE As shown in Figure 38, a single-byte data write transfer begins with the master device transmitting a start condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of the data transfer. For a write data transfer, the read/write bit must be set to 0. After receiving the correct I2C device address and the read/write bit, the TPA6130A2 responds with an acknowledge bit. Next, the master transmits the register byte corresponding to the TPA6130A2 internal memory address being accessed. After receiving the register byte, the TPA6130A2 again responds with an acknowledge bit. Next, the master device transmits the data byte to be written to the memory address being accessed. After receiving the data byte, the TPA6130A2 again responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the single-byte data write transfer. Copyright © 2006–2008, Texas Instruments Incorporated 15 Product Folder Link(s): TPA6130A2 TPA6130A2 SLOS488B – NOVEMBER 2006 – REVISED FEBRUARY 2008 www.ti.com Start Condition Acknowledge Acknowledge Acknowledge A6 A5 A4 A3 A2 A1 A0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK I2C Device Address and Read/Write Bit Register Data Byte Stop Condition Figure 38. Single-Byte Write Transfer MULTIPLE-BYTE WRITE AND INCREMENTAL MULTIPLE-BYTE WRITE A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes are transmitted by the master device to the TPA6130A2 as shown in Figure 39. After receiving each data byte, the TPA6130A2 responds with an acknowledge bit. Register Figure 39. Multiple-Byte Write Transfer SINGLE-BYTE READ As shown in Figure 40, a single-byte data read transfer begins with the master device transmitting a start condition followed by the I2C device address and the read/write bit. For the data read transfer, both a write followed by a read are actually done. Initially, a write is done to transfer the address byte of the internal memory address to be read. As a result, the read/write bit is set to a 0. After receiving the TPA6130A2 address and the read/write bit, the TPA6130A2 responds with an acknowledge bit. The master then sends the internal memory address byte, after which the TPA6130A2 issues an acknowledge bit. The master device transmits another start condition followed by the TPA6130A2 address and the read/write bit again. This time the read/write bit is set to 1, indicating a read transfer. Next, the TPA6130A2 transmits the data byte from the memory address being read. After receiving the data byte, the master device transmits a not-acknowledge followed by a stop condition to complete the single-byte data read transfer. Start Condition Repeat Start Condition Acknowledge Acknowledge Acknowledge Not Acknowledge A6 A5 A1 A0 R/W ACK A7 A6 A5 A4 A0 ACK A6 A5 A1 A0 R/W ACK D7 D6 D1 D0 ACK I2C Device Address and Read/Write Bit Register I2C Device Address and Read/Write Bit Data Byte Stop Condition Figure 40. Single-Byte Read Transfer MULTIPLE-BYTE READ A multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytes are transmitted by the TPA6130A2 to the master device as shown in Figure 41. With the exception of the last data byte, the master device responds with an acknowledge bit after receiving each data byte. 16 Product Folder Link(s): TPA6130A2 Copyright © 2006–2008, Texas Instruments Incorporated TPA6130A2 www.ti.com SLOS488B – NOVEMBER 2006 – REVISED FEBRUARY 2008 Start Condition Repeat Start Condition Acknowledge Acknowledge Acknowledge Acknowledge Acknowledge Not Acknowledge A6 A0 R/W ACK A7 A6 A5 A0 ACK A6 A0 R/W ACK D7 D0 ACK D7 D0 ACK D7 D0 ACK I2C Device Address and Read/Write Bit Register I2C Device Address and Read/Write Bit First Data Byte Other Data Bytes Last Data Byte Stop Condition Figure 41. Multiple-Byte Read Transfer Register Map Table 1. Register Map Register 1 2 3 4 5 6 7 8 Bit7 HP_EN_L Mute_L Reserved Reserved RFT RFT RFT RFT Bit6 HP_EN_R Mute_R Reserved Reserved RFT RFT RFT RFT Bit5 Mode[1] Volume[5] Reserved RFT RFT RFT RFT RFT Bit4 Mode[0] Volume[4] Reserved RFT RFT RFT RFT RFT Bit3 Reserved Volume[3] Reserved Version[3] RFT RFT RFT RFT Bit2 Reserved Volume[2] Reserved Version[2] RFT RFT RFT RFT Bit1 Thermal Volume[1] HiZ_L Version[1] RFT RFT RFT RFT Bit0 SWS Volume[0] HiZ_R Version[0] RFT RFT RFT RFT Bits labeled "Reserved" are reserved for future enhancements. They may not be written to. When read, they will show a "0" value. Bits labeled "RFT" are reserved for TI testing. Under no circumstances must any data be written to these registers. Writing to these bits may change the function of the device, or cause complete failure. If read, these bits may assume any value. Control Register (Address: 1) BIT Function Reset Value 7 HP_EN_L 0 6 HP_EN_R 0 5 Mode[1] 0 4 Mode[0] 0 3 Reserved 0 2 Reserved 0 1 Thermal 0 0 SWS 0 HP_EN_L HP_EN_R Mode[1:0] Reserved Thermal Enable bit for the left-channel amplifier. Amplifier is active when bit is high. Enable bit for the right-channel amplifier. Amplifier is active when bit is high. Mode bits Mode[1] and Mode[0] select one of three modes of operation. 00 is stereo headphone mode. 01 is dual mono headphone mode. 10 is bridge-tied load mode. These bits are reserved for future enhancements. They may not be written to. When read they will read as zero. A 1 on this bit indicates a thermal shutdown was initiated by the hardware. When the temperature drops to safe levels, the device will start to operate again, regardless of bit status. This bit is clear-on-read. Software shutdown control. When the bit is one, the device is in software shutdown. When the bit is low, the charge-pump is active. SWS must be low for normal operation. SWS Copyright © 2006–2008, Texas Instruments Incorporated 17 Product Folder Link(s): TPA6130A2 TPA6130A2 SLOS488B – NOVEMBER 2006 – REVISED FEBRUARY 2008 www.ti.com Volume and Mute Register (Address: 2) BIT Function Reset Value 7 Mute_L 1 6 Mute_R 1 5 Volume[5] 0 4 Volume[4] 0 3 Volume[3] 0 2 Volume[2] 0 1 Volume[1] 0 0 Volume[0] 0 Mute_L Mute_R Volume[5:0] Left channel mute. If this bit is High the left channel is muted. Right channel mute. If this bit is High the right channel is muted. Six bits for volume control. 111111 indicates the highest gain and 000000 indicates the lowest gain. Output Impedance Register (Address: 3) BIT Function Reset Value 7 Reserved 0 6 Reserved 0 5 Reserved 0 4 Reserved 0 3 Reserved 0 2 Reserved 0 1 HiZ_L 0 0 HiZ_R 0 Reserved These bits are reserved for future enhancements. They may not be written to. When read they will read as zero. All writes to these bits will be ignored. HiZ_L HiZ_R Puts left-channel amplifier output in tri-state high impedance mode. Puts right-channel amplifier output in tri-state high impedance mode. I2C address and Version Register (Address: 4) BIT Function Reset Value 7 Reserved 0 6 Reserved 0 5 RFT 0 4 RFT 0 3 Version[3] 0 2 Version[2] 0 1 Version[1] 0 0 Version[0] 0 Reserved These bits are reserved for future enhancements. They may not be written to. When read they will read as zero. Reserved for Test. Do NOT write to these registers. Version[3:0] The version bits track the revision of the silicon. Valid values are 0010 for released TPA6130A2. RFT Reserved for test registers (Addresses: 5-8) BIT Function Reset Value 7 RFT x 6 RFT x 5 RFT x 4 RFT x 3 RFT x 2 RFT x 1 RFT x 0 RFT x RFT Reserved for Test. Do NOT write to these registers. 18 Product Folder Link(s): TPA6130A2 Copyright © 2006–2008, Texas Instruments Incorporated TPA6130A2 www.ti.com SLOS488B – NOVEMBER 2006 – REVISED FEBRUARY 2008 Modes of Operation The TPA6130A2 supports numerous modes of operation. Hardware Shutdown Hardware shutdown occurs when the SD pin is set to logic 0. The device is completely shutdown in this mode, drawing minimal current. This mode overrides all other modes. All information programmed into the registers is lost. When the device starts up again, the registers go back to their default state. Software Shutdown Software shutdown is set by placing a logic 1 in register 1, bit 0. That is the SWS bit. The software shutdown places the device in a low power state, although the current draw is higher than that of hardware shutdown (see the Electrical Characteristics Table for values). Engaging software shutdown turns off the charge pump and disables the outputs. The device is awakened by placing a logic 0 in the SWS bit. Note that when the device is in SWS mode, register 1, bits 7 and 6 will be cleared to reflect the disabled state of the amplifier. All other registers maintain their values. Re-enable the amplifer by placing a logic 0 in the SWS bit. It is necessary to reset the entire register because a full word must be used when writing just one bit. Charge Pump Enabled, HP Amplifiers Disabled The output amplifiers of the TPA6130A2 are enabled by placing a logic 1 in register 1, bits 6 and 7. Place a logic 0 in register 1, bits 6 and 7 to disable the output amplifiers. The left and right outputs can be enabled and disabled individually. When the output amplifiers are disabled, the charge-pump remains on. HiZ State HiZ is enabled by placing a logic 1 in register 3, bits 0 and 1. Place a logic 0 in register 3, bits 0 and 1 to disable the HiZ state of the outputs. The left and right outputs can be placed into a HiZ state individually. The HiZ state puts the outputs into a state of high impedance. Use this configuration when the outputs of the TPA6130A2 share traces with other devices whose outputs may be active. Note that to use the HiZ mode, the TPA6130A2 MUST be active (not in SWS or hardware shutdown). Furthermore, the output amplifiers must NOT be enabled. Stereo Headphone Drive The device is in this mode when the MODE bits in register 1 are 00 and both headphone enable bits are enabled. The two amplifier channels operate independently. This mode is appropriate for stereo playback. Dual Mono Headphone Drive The device is in this mode when the MODE bits in register 1 are 01 and both headphone enable bits are enabled. The left channel is the active input. It is amplified and distributed to both the left and right headphone outputs. Bridge-Tied Load Receiver Drive The device is in this mode when the MODE bits in register 1 are 10 and both headphone enable bits are enabled. In this mode, the device will take the left channel input and drive a single load connected between HPLEFT and HPRIGHT in a bridge-tied fashion. The minimum load for bridge-tied mode is the same as for stereo mode (see table entitled "Absolute Maximum Ratings"). Copyright © 2006–2008, Texas Instruments Incorporated 19 Product Folder Link(s): TPA6130A2 TPA6130A2 SLOS488B – NOVEMBER 2006 – REVISED FEBRUARY 2008 www.ti.com Default Mode The TPA6130A2 starts up with the following conditions: • SWS = Off, CHARGE PUMP = On • HP ENABLES = Off • HiZ = Off • MODE = Stereo • HP MUTES = On, VOLUME = -59.5 dB, VOLUME CONTROL The TPA6130A2 volume control is set through the I2C interface. The six volume control register bits are decoded to 64 volume settings that employ an audio taper. See Table 2 for the gain table. The values listed in this table are typical. Each gain step has a different input impedance. See Figure 33. Table 2. Audio Taper Gain Values Gain Control Word (Binary) Mute [7:6], V[5:0] 11XXXXXX 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 00001001 00001010 00001011 00001100 00001101 00001110 00001111 00010000 00010001 00010010 00010011 00010100 00010101 00010110 00010111 00011000 00011001 00011010 00011011 00011100 00011101 00011110 00011111 20 Product Folder Link(s): TPA6130A2 Nominal Gain (dB) Nominal Gain (V/V) Gain Control Word (Binary) Mute [7:6], V[5:0] 00100000 00100001 00100010 00100011 00100100 00100101 00100110 00100111 00101000 00101001 00101010 00101011 00101100 00101101 00101110 00101111 00110000 00110001 00110010 00110011 00110100 00110101 00110110 00110111 00111000 00111001 00111010 00111011 00111100 00111101 00111110 00111111 Nominal Gain (dB) –10.9 –10.3 –9.7 –9.0 –8.5 –7.8 –7.2 –6.7 –6.1 –5.6 –5.1 –4.5 –4.1 –3.5 –3.1 –2.6 –2.1 –1.7 –1.2 –0.8 –0.3 0.1 0.5 0.9 1.4 1.7 2.1 2.5 2.9 3.3 3.6 4.0 Nominal Gain (V/V) –100 –59.5 –53.5 –50.0 –47.5 –45.5 –43.9 –41.4 –39.5 –36.5 –35.3 –33.3 –31.7 –30.4 –28.6 –27.1 –26.3 –24.7 –23.7 –22.5 –21.7 –20.5 –19.6 –18.8 –17.8 –17.0 –16.2 –15.2 –14.5 –13.7 –13.0 –12.3 –11.6 0.00001 0.001 0.002 0.003 0.004 0.005 0.007 0.009 0.012 0.015 0.018 0.022 0.026 0.031 0.037 0.043 0.050 0.057 0.065 0.074 0.084 0.093 0.104 0.116 0.129 0.142 0.156 0.172 0.188 0.205 0.223 0.242 0.262 0.283 0.305 0.329 0.353 0.379 0.405 0.433 0.462 0.493 0.524 0.557 0.591 0.627 0.664 0.702 0.742 0.783 0.825 0.870 0.915 0.962 1.010 1.061 1.112 1.165 1.220 1.277 1.335 1.395 1.456 1.520 1.585 Copyright © 2006–2008, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 16-Apr-2009 PACKAGING INFORMATION Orderable Device TPA6130A2RTJR TPA6130A2RTJRG4 TPA6130A2RTJT TPA6130A2RTJTG4 TPA6130A2YZHR TPA6130A2YZHT (1) Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Package Type QFN QFN QFN QFN DSBGA DSBGA Package Drawing RTJ RTJ RTJ RTJ YZH YZH Pins Package Eco Plan (2) Qty 20 20 20 20 16 16 3000 Green (RoHS & no Sb/Br) 3000 Green (RoHS & no Sb/Br) 250 250 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU Call TI Call TI MSL Peak Temp (3) Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-1-260C-UNLIM Level-1-260C-UNLIM 3000 Green (RoHS & no Sb/Br) 250 Green (RoHS & no Sb/Br) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Mar-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing QFN QFN DSBGA DSBGA DSBGA DSBGA DSBGA RTJ RTJ YZH YZH YZH YZH YZH 20 20 16 16 16 16 16 SPQ Reel Reel Diameter Width (mm) W1 (mm) 330.0 180.0 180.0 180.0 180.0 180.0 180.0 12.4 12.4 8.4 8.4 8.4 8.4 8.4 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 8.0 8.0 4.0 4.0 4.0 4.0 4.0 W Pin1 (mm) Quadrant 12.0 12.0 8.0 8.0 8.0 8.0 8.0 Q2 Q2 Q1 Q1 Q1 Q1 Q1 TPA6130A2RTJR TPA6130A2RTJT TPA6130A2YZHR TPA6130A2YZHR TPA6130A2YZHR TPA6130A2YZHT TPA6130A2YZHT 3000 250 3000 3000 3000 250 250 4.3 4.3 2.07 2.07 2.07 2.07 2.07 4.3 4.3 2.07 2.07 2.07 2.07 2.07 1.5 1.5 0.81 0.81 0.81 0.81 0.81 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Mar-2009 *All dimensions are nominal Device TPA6130A2RTJR TPA6130A2RTJT TPA6130A2YZHR TPA6130A2YZHR TPA6130A2YZHR TPA6130A2YZHT TPA6130A2YZHT Package Type QFN QFN DSBGA DSBGA DSBGA DSBGA DSBGA Package Drawing RTJ RTJ YZH YZH YZH YZH YZH Pins 20 20 16 16 16 16 16 SPQ 3000 250 3000 3000 3000 250 250 Length (mm) 346.0 190.5 190.5 190.5 220.0 190.5 220.0 Width (mm) 346.0 212.7 212.7 212.7 220.0 212.7 220.0 Height (mm) 29.0 31.8 31.8 31.8 34.0 31.8 34.0 Pack Materials-Page 2 D: Max = 1964 µm, Min = 1904 µm E: Max = 1964 µm, Min = 1904 µm IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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