IRF520SPBF

IRF520S, SiHF520S www.vishay.com Vishay Siliconix Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) RDS(on) () Qg (Max.) (nC) Qgs (nC) Qgd (nC) Configuration 100 VGS = 10 V 0.27 16 4.4 7.7 Single D D2PAK (TO-263) • Halogen-free According to IEC 61249-2-21 Definition • Surface Mount Available • Available in Tape and Reel • Dynamic dV/dt Rating Available • Repetitive Avalanche Rated • 175 °C Operating Temperature • Fast Switching • Ease of Paralleling • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 Note * This datasheet provides information about parts that are RoHS-compliant and / or parts that are non-RoHS-compliant. For example, parts with lead (Pb) terminations are not RoHS-compliant. Please see the information / tables in this datasheet for details. G DESCRIPTION G D S S N-Channel MOSFET Third generation Power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The D2PAK (TO-263) is a surface mount power package capable of accommodating die size up to HEX-4. It provides the highest power capability and the lowest possible on-resistance in any existing surface mount package. The D2PAK (TO-263) is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0 W in a typical surface mount application. ORDERING INFORMATION D2PAK (TO-263) SiHF520S-GE3 SiHF520STRR-GE3 SiHF520STRL-GE3 IRF520SPbF Package Lead (Pb)-free and Halogen-free Lead (Pb)-free ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Currenta SYMBOL VDS VGS VGS at 10 V TC = 25 °C TC = 100 °C ID Pulsed Drain IDM Linear Derating Factor Linear Derating Factor (PCB Mount)e Single Pulse Avalanche Energyb EAS Avalanche Currenta IAR EAR Repetitive Avalanche Energya Maximum Power Dissipation TC = 25 °C PD Maximum Power Dissipation (PCB Mount)e TA = 25 °C dV/dt Peak Diode Recovery dV/dtc Operating Junction and Storage Temperature Range TJ, Tstg Soldering Recommendations (Peak Temperature) For 10 s Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. VDD = 25 V, starting TJ = 25 °C, L = 3.5 mH, Rg = 25 , IAS = 9.2 A (see fig. 12). c. ISD  9.2 A, dI/dt  110 A/μs, VDD  VDS, TJ  175 °C. d. 1.6 mm from case. e. When mounted on 1" square PCB (FR-4 or G-10 material). S16-1000-Rev. D, 23-May-16 LIMIT 100 ± 20 9.2 6.5 37 0.40 0.025 200 9.2 6.0 60 3.7 5.5 - 55 to + 175 300d UNIT V A W/°C mJ A mJ W V/ns °C Document Number: 91018 1 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF520S, SiHF520S www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. Maximum Junction-to-Ambient RthJA - 62 Maximum Junction-to-Ambient  (PCB Mount)a RthJA - 40 Maximum Junction-to-Case (Drain) RthJC - 2.5 UNIT °C/W Note a. When mounted on 1" square PCB (FR-4 or G-10 material). SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT VDS VGS = 0, ID = 250 μA 100 - - V VDS/TJ Reference to 25 °C, ID = 1 mA - 0.13 - V/°C VGS(th) VDS = VGS, ID = 250 μA 2.0 - 4.0 V nA Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage Gate-Source Leakage Zero Gate Voltage Drain Current Drain-Source On-State Resistance Forward Transconductance IGSS IDSS RDS(on) gfs VGS = ± 20 V - - ± 100 VDS = 100 V, VGS = 0 V - - 25 VDS = 80 V, VGS = 0 V, TJ = 150 °C - - 250 - - 0.27  2.7 - - S - 360 - ID = 5.5 Ab VGS = 10 V VDS = 50 V, ID = 5.5 Ab μA Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge Qg Gate-Source Charge Qgs VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 VGS = 10 V ID = 9.2 A, VDS = 80 V, see fig. 6 and 13b - 150 - - 34 - - - 16 - - 4.4 Gate-Drain Charge Qgd - - 7.7 Turn-On Delay Time td(on) - 8.8 - Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance tr td(off) VDD = 50 V, ID = 9.2 A, Rg = 18 , RD = 5.2 , see fig. 10b tf LD LS Between lead, 6 mm (0.25") from package and center of die contact - 30 - - 19 - - 20 - - 4.5 - - 7.5 - - - 9.2 - - 37 pF nC ns D nH G S Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current Pulsed Diode Forward Currenta Body Diode Voltage IS ISM VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Forward Turn-On Time ton MOSFET symbol showing the integral reverse p - n junction diode D A G TJ = 25 °C, IS = 9.2 A, VGS = 0 S Vb TJ = 25 °C, IF = 9.2 A, dI/dt = 100 A/μsb - - 1.8 V - 110 260 ns - 0.53 1.3 μC Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width  300 μs; duty cycle  2 %. S16-1000-Rev. D, 23-May-16 Document Number: 91018 2 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF520S, SiHF520S www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) VGS 15 V 10 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V Bottom 4.5 V Top 25 °C 101 4.5 V 100 ID, Drain Current (A) ID, Drain Current (A) 101 175 °C 100 20 µs Pulse Width TC = 25 °C 10-1 100 101 4 VDS, Drain-to-Source Voltage (V) 91018_01 20 µs Pulse Width VDS = 50 V 91018_03 Fig. 1 - Typical Output Characteristics, TC = 25 °C 4.5 V 100 20 µs Pulse Width TC = 175 °C 10-1 91018_02 100 101 VDS, Drain-to-Source Voltage (V) Fig. 2 - Typical Output Characteristics, TC = 175 °C S16-1000-Rev. D, 23-May-16 6 7 8 9 10 Fig. 3 - Typical Transfer Characteristics RDS(on), Drain-to-Source On Resistance (Normalized) ID, Drain Current (A) 101 VGS Top 15 V 10 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V Bottom 4.5 V 5 VGS, Gate-to-Source Voltage (V) 91018_04 3.0 2.5 ID = 9.2 A VGS = 10 V 2.0 1.5 1.0 0.5 0.0 - 60 - 40 - 20 0 20 40 60 80 100 120 140 160 180 TJ, Junction Temperature (°C) Fig. 4 - Normalized On-Resistance vs. Temperature Document Number: 91018 3 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF520S, SiHF520S www.vishay.com VGS = 0 V, f = 1 MHz Ciss = Cgs + Cgd, Cds Shorted Crss = Cgd Coss = Cds + Cgd Capacitance (pF) 600 450 Ciss 300 Coss 150 Crss 101 175 °C ISD, Reverse Drain Current (A) 750 Vishay Siliconix 25 °C 100 0 100 VDS, Drain-to-Source Voltage (V) 91018_05 VDS = 20 V 8 4 4 8 12 16 5 1.2 10 µs 2 100 µs 10 5 1 ms 2 10 ms 1 Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage TC = 25 °C TJ = 175 °C Single Pulse 2 0.1 0.1 20 QG, Total Gate Charge (nC) S16-1000-Rev. D, 23-May-16 1.1 102 5 For test circuit see figure 13 0 1.0 2 ID, Drain Current (A) VGS, Gate-to-Source Voltage (V) VDS = 80 V 0 0.9 Operation in this area limited by RDS(on) 5 VDS = 50 V 91018_06 0.8 VSD, Source-to-Drain Voltage (V) 103 16 0.7 Fig. 7 - Typical Source-Drain Diode Forward Voltage ID = 9.2 A 12 0.6 91018_07 Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage 20 VGS = 0 V 10-1 0.5 101 91018_08 2 5 1 2 5 10 2 5 102 2 5 103 VDS, Drain-to-Source Voltage (V) Fig. 8 - Maximum Safe Operating Area Document Number: 91018 4 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF520S, SiHF520S www.vishay.com Vishay Siliconix RD VDS VGS 10 8 ID, Drain Current (A) D.U.T. Rg + - VDD 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % 6 Fig. 10a - Switching Time Test Circuit 4 VDS 2 90 % 0 25 50 75 100 125 150 175 10 % VGS TC, Case Temperature (°C) 91018_09 td(on) Fig. 9 - Maximum Drain Current vs. Case Temperature td(off) tf tr Fig. 10b - Switching Time Waveforms Thermal Response (ZthJC) 10 1 0 - 0.5 0.2 PDM 0.1 0.05 0.1 t1 0.02 0.01 10-2 10-5 91018_11 Single Pulse (Thermal Response) 10-4 10-3 t2 Notes: 1. Duty Factor, D = t1/t2 2. Peak Tj = PDM x ZthJC + TC 10-2 0.1 1 10 t1, Rectangular Pulse Duration (s) Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case S16-1000-Rev. D, 23-May-16 Document Number: 91018 5 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF520S, SiHF520S www.vishay.com Vishay Siliconix L Vary tp to obtain required IAS VDS VDS tp D.U.T. Rg + - I AS VDD V DD VDS 10 V 0.01 Ω tp IAS Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms EAS, Single Pulse Energy (mJ) 600 ID 3.8 A 6.5 A Bottom 9.2 A Top 500 400 300 200 100 VDD = 25 V 0 25 91018_12c 50 75 100 125 150 175 Starting TJ, Junction Temperature (°C) Fig. 12c - Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. 50 kΩ QG 10 V 12 V 0.2 µF 0.3 µF QGS QGD + D.U.T. VG - VDS VGS 3 mA Charge IG ID Current sampling resistors Fig. 13a - Basic Gate Charge Waveform S16-1000-Rev. D, 23-May-16 Fig. 13b - Gate Charge Test Circuit Document Number: 91018 6 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF520S, SiHF520S www.vishay.com Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + + - - Rg • • • • dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + - VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 14 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91018. S16-1000-Rev. D, 23-May-16 Document Number: 91018 7 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix TO-263AB (HIGH VOLTAGE) A (Datum A) 3 A 4 4 L1 B A E c2 H Gauge plane 4 0° to 8° 5 D B Detail A Seating plane H 1 2 C 3 C L L3 L4 Detail “A” Rotated 90° CW scale 8:1 L2 B A1 B A 2 x b2 c 2xb E 0.010 M A M B ± 0.004 M B 2xe Plating 5 b1, b3 Base metal c1 (c) D1 4 5 (b, b2) Lead tip MILLIMETERS DIM. MIN. MAX. View A - A INCHES MIN. 4 E1 Section B - B and C - C Scale: none MILLIMETERS MAX. DIM. MIN. INCHES MAX. MIN. MAX. A 4.06 4.83 0.160 0.190 D1 6.86 - 0.270 - A1 0.00 0.25 0.000 0.010 E 9.65 10.67 0.380 0.420 6.22 - 0.245 - b 0.51 0.99 0.020 0.039 E1 b1 0.51 0.89 0.020 0.035 e b2 1.14 1.78 0.045 0.070 H 14.61 15.88 0.575 0.625 b3 1.14 1.73 0.045 0.068 L 1.78 2.79 0.070 0.110 2.54 BSC 0.100 BSC c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.066 c1 0.38 0.58 0.015 0.023 L2 - 1.78 - 0.070 c2 1.14 1.65 0.045 0.065 L3 D 8.38 9.65 0.330 0.380 L4 0.25 BSC 4.78 5.28 0.010 BSC 0.188 0.208 ECN: S-82110-Rev. A, 15-Sep-08 DWG: 5970 Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimensions are shown in millimeters (inches). 3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outmost extremes of the plastic body at datum A. 4. Thermal PAD contour optional within dimension E, L1, D1 and E1. 5. Dimension b1 and c1 apply to base metal only. 6. Datum A and B to be determined at datum plane H. 7. Outline conforms to JEDEC outline to TO-263AB. Document Number: 91364 Revision: 15-Sep-08 www.vishay.com 1 AN826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead 0.420 0.355 0.635 (16.129) (9.017) (10.668) 0.145 (3.683) 0.135 (3.429) 0.200 0.050 (5.080) (1.257) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Document Number: 73397 11-Apr-05 www.vishay.com 1 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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ALL RIGHTS RESERVED Revision: 01-Jan-2022 1 Document Number: 91000