IRF644S, SiHF644S
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Vishay Siliconix
Power MOSFET
FEATURES
D
•
•
•
•
•
•
•
•
D2PAK (TO-263)
G
G D
S
S
N-Channel MOSFET
PRODUCT SUMMARY
VDS (V)
RDS(on) ()
250
VGS = 10 V
0.28
Qg max. (nC)
68
Qgs (nC)
11
Qgd (nC)
35
Configuration
Surface-mount
Available in tape and reel
Dynamic dv/dt rating
Available
Repetitive avalanche rated
Fast switching
Available
Ease of paralleling
Simple drive requirements
Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
Note
* This datasheet provides information about parts that are
RoHS-compliant and / or parts that are non RoHS-compliant. For
example, parts with lead (Pb) terminations are not RoHS-compliant.
Please see the information / tables in this datasheet for details
DESCRIPTION
Third generation power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness.
The D2PAK (TO-263) is a surface-mount power package
capable of accommodating die size up to HEX-4. It provides
the highest power capability and the lowest possible
on-resistance in any existing surface-mount package. The
D2PAK (TO-263) is suitable for high current applications
because of its low internal connection resistance and can
dissipate up to 2.0 W in a typical surface-mount application.
Single
ORDERING INFORMATION
Package
Lead (Pb)-free and halogen-free
Lead (Pb)-free
Note
a. See device orientation
D2PAK (TO-263)
SiHF644S-GE3
IRF644SPbF
D2PAK (TO-263)
SiHF644STRL-GE3 a
IRF644STRLPbF a
D2PAK (TO-263)
SiHF644STRR-GE3 a
IRF644STRRPbF a
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
Drain-source voltage
Gate-source voltage
Continuous drain current
SYMBOL
VDS
VGS
VGS at 10 V
TC = 25 °C
TC = 100 °C
ID
IDM
Pulsed drain current a
Linear derating factor
Linear derating factor (PCB mount) e
EAS
Single pulse avalanche energy b
IAR
Avalanche current a
EAR
Repetitive avalanche energy a
Maximum power dissipation
TC = 25 °C
PD
Maximum power dissipation (PCB mount) e
TA = 25 °C
dv/dt
Peak diode recovery dv/dt c
Operating junction and storage temperature range
TJ, Tstg
Soldering recommendations (peak temperature) d
for 10 s
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. VDD = 50 V, starting TJ = 25 °C, L = 4.5 mH, Rg = 25 , IAS = 14 A (see fig. 12)
c. ISD 14 A, di/dt 150 A/μs, VDD VDS, TJ 150 °C
d. 1.6 mm from case
e. When mounted on 1" square PCB (FR-4 or G-10 material)
S20-0682-Rev. E, 07-Sep-2020
LIMIT
250
± 20
14
8.5
56
1.0
0.025
550
14
13
125
3.1
4.8
-55 to +150
300
UNIT
V
A
W/°C
mJ
A
mJ
W
V/ns
°C
Document Number: 91040
1
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum junction-to-ambient
RthJA
-
62
Maximum junction-to-ambient
(PCB mount) a
RthJA
-
40
Maximum junction-to-case (drain)
RthJC
-
1.0
UNIT
°C/W
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material)
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-source breakdown voltage
VDS temperature coefficient
Gate-source threshold voltage
VDS
VGS = 0, ID = 250 μA
250
-
-
V
VDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.34
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
2.0
-
4.0
V
Gate-source leakage
IGSS
VGS = ± 20 V
-
-
± 100
nA
Zero gate voltage drain current
IDSS
VDS = 250 V, VGS = 0 V
-
-
25
VDS = 200 V, VGS = 0 V, TJ = 125 °C
-
-
250
Drain-source on-state resistance
Forward transconductance
μA
-
-
0.28
gfs
VDS = 50 V, ID = 8.4 A b
6.7
-
-
S
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5
-
1300
-
-
330
-
-
85
-
-
-
68
RDS(on)
ID = 8.4 A b
VGS = 10 V
Dynamic
Input capacitance
Ciss
Output capacitance
Coss
Reverse transfer capacitance
Crss
Total gate charge
Qg
Gate-source charge
Qgs
Gate-drain charge
Qgd
Turn-on delay time
td(on)
Rise time
tr
Turn-off delay time
td(off)
Fall time
VGS = 10 V
ID = 7.9 A, VDS = 200 V,
see fig. 6 and 13 b
VDD = 125 V, ID = 7.9 A,
Rg = 9.1 , RD = 8.7 , see fig. 10 b
tf
Gate input resistance
LD
Internal drain inductance
LS
Internal source inductance
Rg
Between lead,
6 mm (0.25") from
package and center of
die contact
-
-
11
-
-
35
-
11
-
-
24
-
-
53
-
-
49
-
-
4.5
-
-
7.5
-
0.3
-
1.2
-
-
14
-
-
56
pF
nC
ns
D
nH
G
S
f = 1 MHz, open drain
Drain-Source Body Diode Characteristics
Continuous source-drain diode current
Pulsed diode forward current
a
Body diode voltage
IS
ISM
VSD
Body diode reverse recovery time
trr
Body diode reverse recovery charge
Qrr
Forward turn-on time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
S
TJ = 25 °C, IS = 14 A, VGS = 0 V b
TJ = 25 °C, IF = 7.9 A, di/dt = 100 A/μs b
-
-
1.8
V
-
250
500
ns
-
2.3
4.6
μC
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Pulse width 300 μs; duty cycle 2 %
S20-0682-Rev. E, 07-Sep-2020
Document Number: 91040
2
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF644S, SiHF644S
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VGS
15 V
10 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
Bottom 4.5 V
ID, Drain Current (A)
Top
101
100
4.5 V
20 µs Pulse Width
TC = 25 °C
10-1
100
101
VDS, Drain-to-Source Voltage (V)
91040_01
RDS(on), Drain-to-Source On Resistance
(Normalized)
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
3.0
ID = 7.9 A
VGS = 10 V
2.5
2.0
1.5
1.0
0.5
0.0
- 60 - 40 - 20 0
91040_04
Fig. 1 - Typical Output Characteristics, TC = 25 °C
20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
Fig. 4 - Normalized On-Resistance vs. Temperature
3000
VGS
15 V
10 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
Bottom 4.5 V
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds Shorted
Crss = Cgd
Coss = Cds + Cgd
101
2400
4.5 V
100
Capacitance (pF)
ID, Drain Current (A)
Top
1800
Ciss
1200
Coss
600
20 µs Pulse Width
TC = 150 °C
100
10-1
0
101
100
VDS, Drain-to-Source Voltage (V)
91040_02
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
25 °C
100
20 µs Pulse Width
VDS = 50 V
10-1
4
91040_03
5
6
7
8
9
VGS, Gate-to-Source Voltage (V)
Fig. 3 - Typical Transfer Characteristics
S20-0682-Rev. E, 07-Sep-2020
VGS, Gate-to-Source Voltage (V)
ID, Drain Current (A)
20
150 °C
101
VDS, Drain-to-Source Voltage (V)
91040_05
Fig. 2 - Typical Output Characteristics, TC = 150 °C
101
Crss
ID = 7.9 A
VDS = 200 V
16
VDS = 125 V
VDS = 50 V
12
8
4
For test circuit
see figure 13
0
10
0
91040_06
10
20
30
40
50
60
70
QG, Total Gate Charge (nC)
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Document Number: 91040
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF644S, SiHF644S
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12
101
ID, Drain Current (A)
ISD, Reverse Drain Current (A)
14
150 °C
25 °C
100
8
6
4
2
VGS = 0 V
10-1
0.5
0
0.6
0.7
0.9
0.8
1.1
1.0
25
VSD, Source-to-Drain Voltage (V)
91040_07
103
50
100
125
RD
VDS
VGS
2
D.U.T.
Rg
+
- VDD
102
5
10 µs
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
2
100 µs
10
5
Fig. 10a - Switching Time Test Circuit
1 ms
TC = 25 °C
TJ = 150 °C
Single Pulse
2
1
2
1
5
10
2
5
VDS
10 ms
102
2
5
150
Fig. 9 - Maximum Drain Current vs. Case Temperature
Operation in this area limited
by RDS(on)
5
75
TC, Case Temperature (°C)
91040_09
Fig. 7 - Typical Source-Drain Diode Forward Voltage
ID, Drain Current (A)
10
90 %
103
VDS, Drain-to-Source Voltage (V)
91040_08
Fig. 8 - Maximum Safe Operating Area
10 %
VGS
td(on)
td(off) tf
tr
Fig. 10b - Switching Time Waveforms
Thermal Response (ZthJC)
10
1
0 − 0.5
PDM
0.2
0.1
0.1
t1
0.05
t2
0.02
0.01
Notes:
1. Duty Factor, D = t1/t2
2. Peak Tj = PDM x ZthJC + TC
Single Pulse
(Thermal Response)
10-2
10-5
10-4
10-3
10-2
0.1
1
10
t1, Rectangular Pulse Duration (s)
91040_11
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
S20-0682-Rev. E, 07-Sep-2020
Document Number: 91040
4
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L
Vary tp to obtain
required IAS
VDS
VDS
tp
VDD
Rg
D.U.T
+
-
I AS
V DD
VDS
10 V
0.01 Ω
tp
IAS
Fig. 12b - Unclamped Inductive Waveforms
Fig. 12a - Unclamped Inductive Test Circuit
EAS, Single Pulse Energy (mJ)
1200
ID
6.3 A
8.9 A
Bottom 14 A
Top
1000
800
600
400
200
0
VDD = 50 V
25
91040_12c
50
75
100
125
150
Starting TJ, Junction Temperature (°C)
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
VGS
12 V
0.2 µF
0.3 µF
QGS
QGD
+
D.U.T.
VG
-
VDS
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
S20-0682-Rev. E, 07-Sep-2020
Fig. 13b - Gate Charge Test Circuit
Document Number: 91040
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF644S, SiHF644S
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Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
•
•
•
•
+
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91040.
S20-0682-Rev. E, 07-Sep-2020
Document Number: 91040
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
Vishay Siliconix
TO-263AB (HIGH VOLTAGE)
A
(Datum A)
3
A
4
4
L1
B
A
E
c2
H
Gauge
plane
4
0° to 8°
5
D
B
Detail A
Seating plane
H
1
2
C
3
C
L
L3
L4
Detail “A”
Rotated 90° CW
scale 8:1
L2
B
A1
B
A
2 x b2
c
2xb
E
0.010 M A M B
± 0.004 M B
2xe
Plating
5
b1, b3
Base
metal
c1
(c)
D1
4
5
(b, b2)
Lead tip
MILLIMETERS
DIM.
MIN.
MAX.
View A - A
INCHES
MIN.
4
E1
Section B - B and C - C
Scale: none
MILLIMETERS
MAX.
DIM.
MIN.
INCHES
MAX.
MIN.
MAX.
A
4.06
4.83
0.160
0.190
D1
6.86
-
0.270
-
A1
0.00
0.25
0.000
0.010
E
9.65
10.67
0.380
0.420
6.22
-
0.245
-
b
0.51
0.99
0.020
0.039
E1
b1
0.51
0.89
0.020
0.035
e
b2
1.14
1.78
0.045
0.070
H
14.61
15.88
0.575
0.625
b3
1.14
1.73
0.045
0.068
L
1.78
2.79
0.070
0.110
2.54 BSC
0.100 BSC
c
0.38
0.74
0.015
0.029
L1
-
1.65
-
0.066
c1
0.38
0.58
0.015
0.023
L2
-
1.78
-
0.070
c2
1.14
1.65
0.045
0.065
L3
D
8.38
9.65
0.330
0.380
L4
0.25 BSC
4.78
5.28
0.010 BSC
0.188
0.208
ECN: S-82110-Rev. A, 15-Sep-08
DWG: 5970
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions are shown in millimeters (inches).
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the
outmost extremes of the plastic body at datum A.
4. Thermal PAD contour optional within dimension E, L1, D1 and E1.
5. Dimension b1 and c1 apply to base metal only.
6. Datum A and B to be determined at datum plane H.
7. Outline conforms to JEDEC outline to TO-263AB.
Document Number: 91364
Revision: 15-Sep-08
www.vishay.com
1
Outline Dimensions
www.vishay.com
Vishay Semiconductors
TO-247AC 2L
DIMENSIONS in millimeters and inches
A
A
E (3)
B
A2
S
R/2 (2)
(Datum B)
Ø P (6)
Ø P1
Ø K M DBM
A
Q
D2
2 x R (2)
D1 (4)
D
Thermal pad
2
1
4
D
3
L1 (5)
C
L
A
See view B
2 x b2
2xb
0.10 M C A M
C
2x e
A1
E1 (4)
0.01 M D B M
(b1, b3)
Plating
View A - A
Base metal
D D
(c)
c1
(b, b2)
C
(4)
View B
Section C - C, D - D
SYMBOL
A
A1
A2
b
b1
b2
b3
c
c1
D
D1
D2
MILLIMETERS
MIN.
MAX.
4.65
5.31
2.21
2.59
1.17
1.37
0.99
1.40
0.99
1.35
1.65
2.39
1.65
2.34
0.38
0.89
0.38
0.84
19.71
20.70
13.08
0.51
1.35
C
INCHES
MIN.
MAX.
0.183
0.209
0.087
0.102
0.046
0.054
0.039
0.055
0.039
0.053
0.065
0.094
0.065
0.092
0.015
0.035
0.015
0.033
0.776
0.815
0.515
0.020
0.053
NOTES
SYMBOL
3
4
E
E1
e
ØK
L
L1
ØP
Ø P1
Q
R
S
MILLIMETERS
MIN.
MAX.
15.29
15.87
13.46
5.46 BSC
0.254
14.20
16.10
3.71
4.29
3.56
3.66
7.39
5.31
5.69
4.52
5.49
5.51 BSC
INCHES
MIN.
MAX.
0.602
0.625
0.53
0.215 BSC
0.010
0.559
0.634
0.146
0.169
0.14
0.144
0.291
0.209
0.224
0.178
0.216
0.217 BSC
NOTES
3
Notes
(1) Dimensioning and tolerancing per ASME Y14.5M-1994
(2) Contour of slot optional
(3) Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at
the outermost extremes of the plastic body
(4) Thermal pad contour optional with dimensions D1 and E1
(5) Lead finish uncontrolled in L1
(6) Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154")
(7) Outline conforms to JEDEC® outline TO-247 with exception of dimension Q
Revision: 07-Dec-17
Document Number: 96144
1
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
AN826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead
0.420
0.355
0.635
(16.129)
(9.017)
(10.668)
0.145
(3.683)
0.135
(3.429)
0.200
0.050
(5.080)
(1.257)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
Document Number: 73397
11-Apr-05
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Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
disclosure relating to any product.
Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or
the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all
liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,
consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular
purpose, non-infringement and merchantability.
Statements regarding the suitability of products for certain types of applications are based on Vishay's knowledge of typical
requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements
about the suitability of products for a particular application. It is the customer's responsibility to validate that a particular product
with the properties described in the product specification is suitable for use in a particular application. Parameters provided in
datasheets and / or specifications may vary in different applications and performance may vary over time. All operating
parameters, including typical parameters, must be validated for each customer application by the customer's technical experts.
Product specifications do not expand or otherwise modify Vishay's terms and conditions of purchase, including but not limited
to the warranty expressed therein.
Hyperlinks included in this datasheet may direct users to third-party websites. These links are provided as a convenience and
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Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining
applications or for any other application in which the failure of the Vishay product could result in personal injury or death.
Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk. Please
contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.
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any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.
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