IRF9510L

IRF9510 www.vishay.com Vishay Siliconix Power MOSFET FEATURES S • • • • • • • • TO-220AB G G D S D P-Channel MOSFET Note * This datasheet provides information about parts that are RoHS-compliant and / or parts that are non RoHS-compliant. For example, parts with lead (Pb) terminations are not RoHS-compliant. Please see the information / tables in this datasheet for details PRODUCT SUMMARY VDS (V) -100 RDS(on) (Ω) VGS = -10 V 8.7 Qgs (nC) 2.2 Qgd (nC) 4.1 Configuration DESCRIPTION 1.2 Qg max. (nC) Dynamic dV/dt rating Available Repetitive avalanche rated P-channel Available 175 °C operating temperature Fast switching Ease of paralleling Simple drive requirements Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 Third generation power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The TO-220AB package is universally preferred for all commercial-industrial applications at power dissipation levels to approximately 50 W. The low thermal resistance and low package cost of the TO-220AB contribute to its wide acceptance throughout the industry. Single ORDERING INFORMATION Package TO-220AB Lead (Pb)-free IRF9510PbF Lead (Pb)-free and halogen-free IRF9510PbF-BE3 ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-source voltage VDS -100 Gate-source voltage VGS ± 20 VGS at 10 V Continuous drain current TC = 25 °C TC = 100 °C Pulsed drain current a ID IDM Linear derating factor UNIT V -4.0 -2.8 A -16 0.29 W/°C Single pulse avalanche energy b EAS 200 mJ Repetitive avalanche current a IAR -4.0 A Repetitive avalanche energy a EAR 4.3 mJ PD 43 W dV/dt -5.5 V/ns TJ, Tstg -55 to +175 Maximum power dissipation Peak diode recovery dV/dt TC = 25 °C c Operating junction and storage temperature range Soldering recommendations (peak temperature) d Mounting torque For 10 s 6-32 or M3 screw 300 °C 10 lbf · in 1.1 N·m Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11) b. VDD = -25 V, starting TJ = 25 °C, L = 18 mH, Rg = 25 Ω, IAS = -4.0 A (see fig. 12) c. ISD ≤ -4.0 A, dI/dt ≤ 75 A/μs, VDD ≤ VDS, TJ ≤ 175 °C d. 1.6 mm from case S21-0852-Rev. C, 16-Aug-2021 Document Number: 91072 1 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF9510 www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. Maximum junction-to-ambient RthJA - 62 Case-to-sink, flat, greased surface RthCS 0.50 - Maximum junction-to-case (drain) RthJC - 3.5 UNIT °C/W SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-source breakdown voltage VDS temperature coefficient Gate-source threshold voltage VDS VGS = 0 V, ID = -250 μA -100 - - V ΔVDS/TJ Reference to 25 °C, ID = -1 mA - - 0.091 - V/°C VGS(th) VDS = VGS, ID = -250 μA -2.0 - -4.0 V Gate-source leakage IGSS VGS = ± 20 V - - ± 100 nA Zero gate voltage drain current IDSS VDS = -100 V, VGS = 0 V - - -100 VDS = -80 V, VGS = 0 V, TJ = 150 °C - - -500 μA - - 1.2 Ω gfs VDS = -50 V, ID = -2.4 A b 1.0 - - S Input capacitance Ciss - 200 - Output capacitance Coss Reverse transfer capacitance Crss VGS = 0 V, VDS = -25 V, f = 1.0 MHz, see fig. 5 Drain-source on-state resistance Forward transconductance RDS(on) ID = -2.4 A b VGS = -10 V Dynamic - 94 - - 18 - - - 8.7 - - 2.2 pF Total gate charge Qg Gate-source charge Qgs Gate-drain charge Qgd - - 4.1 Turn-on delay time td(on) - 10 - tr VDD = -50 V, ID = -4.0 A, Rg = 24 Ω, RD = 11 Ω, see fig. 10 b - 27 - - 15 - - 17 - f = 1 MHz, open drain 1.5 - 7.9 - 4.5 - - 7.5 - - - -4.0 - - -16 - - -5.5 V - 82 160 ns - 0.15 0.30 μC Rise time Turn-off delay time Fall time Gate input resistance td(off) VGS = -10 V ID = -4.0 A, VDS = -80 V, see fig. 6 and 13 b tf Rg Internal drain inductance LD Internal source inductance LS Between lead, 6 mm (0.25") from package and center of die contact D nC ns Ω nH G S Drain-Source Body Diode Characteristics Continuous source-drain diode current IS Pulsed diode forward current a ISM Body diode voltage VSD Body diode reverse recovery time trr Body diode reverse recovery charge Qrr Forward turn-on time ton MOSFET symbol showing the integral reverse p - n junction diode D A G S TJ = 25 °C, IS = -4.0 A, VGS = 0 V b TJ = 25 °C, IF = -4.0 A, dI/dt = 100 A/μsb Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11) b. Pulse width ≤ 300 μs; duty cycle ≤ 2 % S21-0852-Rev. C, 16-Aug-2021 Document Number: 91072 2 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF9510 www.vishay.com Vishay Siliconix VGS - 15 V - 10 V - 8.0 V - 7.0 V - 6.0 V - 5.5 V - 5.0 V Bottom - 4.5 V Top - ID, Drain Current (A) 101 100 - 4.5 V 20 µs Pulse Width TC = 25 °C 100 101 - VDS, Drain-to-Source Voltage (V) 91072_01 RDS(on), Drain-to-Source On Resistance (Normalized) TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 3.0 ID = - 4.0 A VGS = - 10 V 2.5 2.0 1.5 1.0 0.5 0.0 - 60- 40 - 20 0 91072_04 Fig. 4 - Normalized On-Resistance vs. Temperature Fig. 1 - Typical Output Characteristics, TC = 25 °C 350 VGS - 15 V - 10 V - 8.0 V - 7.0 V - 6.0 V - 5.5 V - 5.0 V Bottom - 4.5 V VGS = 0 V, f = 1 MHz Ciss = Cgs + Cgd, Cds Shorted Crss = Cgd Coss = Cds + Cgd 280 Capacitance (pF) - ID, Drain Current (A) 101 Top 100 - 4.5 V 20 40 60 80 100 120 140 160 180 TJ, Junction Temperature (°C) Ciss 210 140 Coss 70 Crss 20 µs Pulse Width TC = 175 °C 100 100 - VDS, Drain-to-Source Voltage (V) 91072_02 0 101 Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 2 - Typical Output Characteristics, TC = 175 °C - ID, Drain Current (A) 175 °C 100 20 µs Pulse Width VDS = - 50 V 4 5 6 7 8 9 Fig. 3 - Typical Transfer Characteristics ID = - 4.0 A VDS = - 80 V VDS = - 50 V 16 VDS = - 20 V 12 8 4 For test circuit see figure 13 0 10 - VGS, Gate-to-Source Voltage (V) S21-0852-Rev. C, 16-Aug-2021 - VGS, Gate-to-Source Voltage (V) 20 25 °C 91072_03 - VDS, Drain-to-Source Voltage (V) 91072_05 101 101 0 91072_06 2 4 6 8 10 QG, Total Gate Charge (nC) Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Document Number: 91072 3 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF9510 www.vishay.com Vishay Siliconix - ISD, Reverse Drain Current (A) 4.0 175 °C - ID, Drain Current (A) 101 25 °C 100 VGS = 0 V 10-1 1.0 2.0 3.0 1.0 25 - VSD, Source-to-Drain Voltage (V) 91072_07 2.0 0.0 5.0 4.0 3.0 50 125 150 175 Fig. 9 - Maximum Drain Current vs. Case Temperature RD 102 VDS Operation in this area limited by RDS(on) 5 VGS 2 - ID, Drain Current (A) 100 TC, Case Temperature (°C) 91072_09 Fig. 7 - Typical Source-Drain Diode Forward Voltage 75 10 D.U.T. RG 100 µs +VDD 5 1 ms 2 1 - 10 V 10 ms Pulse width ≤ 1 µs Duty factor ≤ 0.1 % 5 2 0.1 Fig. 10a - Switching Time Test Circuit 5 TC = 25 °C TJ = 175 °C Single Pulse 2 10-2 0.1 2 5 1 2 5 10 td(on) 2 5 102 2 5 td(off) tf tr VGS 103 10 % - VDS, Drain-to-Source Voltage (V) 91072_08 Fig. 8 - Maximum Safe Operating Area 90 % VDS Fig. 10b - Switching Time Waveforms Thermal Response (ZthJC) 10 D = 0.5 1 0.2 0.1 0.1 PDM 0.05 0.02 0.01 Single Pulse (Thermal Response) t1 t2 Notes: 1. Duty Factor, D = t1/t2 2. Peak Tj = PDM x ZthJC + TC 10-2 10-5 91072_11 10-4 10-3 10-2 0.1 1 10 t1, Rectangular Pulse Duration (s) Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case S21-0852-Rev. C, 16-Aug-2021 Document Number: 91072 4 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF9510 www.vishay.com Vishay Siliconix L Vary tp to obtain required IAS VDS D.U.T RG + V DD QG - 10 V QGS IAS QGD - 10 V 0.01 Ω tp VG Fig. 12a - Unclamped Inductive Test Circuit Charge IAS Fig. 13a - Basic Gate Charge Waveform VDS Current regulator Same type as D.U.T. VDD 50 kΩ tp 12 V 0.2 µF 0.3 µF VDS - D.U.T. Fig. 12b - Unclamped Inductive Waveforms + VDS VGS EAS, Single Pulse Energy (mJ) 700 ID Top - 1.6 A - 2.8 A Bottom - 4.0 A 600 500 - 3 mA IG ID Current sampling resistors Fig. 13b - Gate Charge Test Circuit 400 300 200 100 0 VDD = - 25 V 25 91072_12c 50 75 100 125 150 175 Starting TJ, Junction Temperature (°C) Fig. 12 c- Maximum Avalanche Energy vs. Drain Current S21-0852-Rev. C, 16-Aug-2021 Document Number: 91072 5 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF9510 www.vishay.com Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit D.U.T. + Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + + - - Rg • dV/dt controlled by Rg • ISD controlled by duty factor “D” • D.U.T. - device under test + - VDD Note • Compliment N-Channel of D.U.T. for driver Driver gate drive P.W. Period D= P.W. Period VGS = - 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple ≤ 5 % ISD Note a. VGS = - 5 V for logic level and - 3 V drive devices Fig. 14 - For P-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91072. S21-0852-Rev. C, 16-Aug-2021 Document Number: 91072 6 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information www.vishay.com Vishay Siliconix TO-220-1 A E F D H(1) Q ØP 3 2 L(1) 1 M* L b(1) C b e J(1) e(1) MILLIMETERS DIM. INCHES MIN. MAX. MIN. MAX. A 4.24 4.65 0.167 0.183 b 0.69 1.02 0.027 0.040 b(1) 1.14 1.78 0.045 0.070 c 0.36 0.61 0.014 0.024 D 14.33 15.85 0.564 0.624 E 9.96 10.52 0.392 0.414 e 2.41 2.67 0.095 0.105 e(1) 4.88 5.28 0.192 0.208 F 1.14 1.40 0.045 0.055 H(1) 6.10 6.71 0.240 0.264 J(1) 2.41 2.92 0.095 0.115 L 13.36 14.40 0.526 0.567 L(1) 3.33 4.04 0.131 0.159 ØP 3.53 3.94 0.139 0.155 Q 2.54 3.00 0.100 0.118 ECN: E21-0621-Rev. D, 04-Nov-2021 DWG: 6031 Note • M* = 0.052 inches to 0.064 inches (dimension including protrusion), heatsink hole for HVM Document Number: 66542 1 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Revison: 04-Nov-2021 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners. © 2022 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED Revision: 01-Jan-2022 1 Document Number: 91000