IRFP460A

IRFP460A www.vishay.com Vishay Siliconix Power MOSFET FEATURES D • Low gate charge Qg results in simple drive requirement TO-247 Available • Improved gate, avalanche and dynamic dV/dt ruggedness • Fully characterized capacitance and avalanche voltage and current • Effective Coss specified G S D S G • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 N-Channel MOSFET Note * This datasheet provides information about parts that are RoHS-compliant and / or parts that are non RoHS-compliant. For example, parts with lead (Pb) terminations are not RoHS-compliant. Please see the information / tables in this datasheet for details PRODUCT SUMMARY VDS (V) RDS(on) (Ω) 500 VGS = 10 V 0.27 Qg (max.) (nC) 105 Qgs (nC) 26 Qgd (nC) 42 Configuration APPLICATIONS • Switch mode power supply (SMPS) • Uninterruptable power supply • High speed power switching Single TYPICAL SMPS TOPOLOGIES • Full bridge • PFC boost ORDERING INFORMATION Package Lead (Pb)-free TO-247 IRFP460APbF ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted SYMBOL LIMIT Drain-source voltage VDS 500 Gate-source voltage VGS ± 30 PARAMETER Continuous drain current VGS at 10 V TC = 25 °C TC = 100 °C Pulsed drain current a ID UNIT V 20 13 A IDM 80 2.2 W/°C Single pulse avalanche energy b EAS 960 mJ Repetitive avalanche current a IAR 20 A Repetitive avalanche energy a EAR 28 mJ Linear derating factor Maximum power dissipation TC = 25 °C Peak diode recovery dV/dt c Operating junction and storage temperature range Soldering recommendations (peak temperature) for 10 s Mounting torque 6-32 or M3 screw PD 280 W dV/dt 3.8 V/ns TJ, Tstg -55 to +150 300 d °C 10 lbf · in 1.1 N·m Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11) b. Starting TJ = 25 °C, L = 4.3 mH, Rg = 25 Ω, IAS = 20 A (see fig. 12) c. ISD ≤ 20 A, dI/dt ≤ 125 A/μs, VDD ≤ VDS, TJ ≤ 150 °C d. 1.6 mm from case S22-0058-Rev. C, 31-Jan-2022 Document Number: 91234 1 For technical questions, contact: hvmos.techsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFP460A www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. Maximum junction-to-ambient RthJA - 40 Case-to-sink, flat, greased surface RthCS 0.24 - Maximum junction-to-case (drain) RthJC - 0.45 UNIT °C/W SPECIFICATIONS TJ = 25 °C, unless otherwise noted PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT 500 - - V - 0.61 - V/°C 2.0 - 4.0 V VGS = ± 30 V - - ± 100 nA VDS = 500 V, VGS = 0 V - - 25 VDS = 400 V, VGS = 0 V, TJ = 125 °C - - 250 ID = 12 A b - - 0.27 Ω Ab 11 - - S - 3100 - - 480 - - 18 - Static Drain-source breakdown voltage VDS temperature coefficient Gate-source threshold voltage Gate-source leakage Zero gate voltage drain current Drain-source on-state resistance Forward transconductance VDS ΔVDS/TJ VGS(th) IGSS IDSS RDS(on) gfs VGS = 0 V, ID = 250 μA Reference to 25 °C, ID = 1 mA VDS = VGS, ID = 250 μA VGS = 10 V VDS = 50 V, ID = 12 µA Dynamic Input capacitance Ciss Output capacitance Coss Reverse transfer capacitance Crss Output capacitance Effective output capacitance Total gate charge Coss VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 VGS = 0 V Coss eff. VDS = 1.0 V, f = 1.0 MHz 4430 VDS = 400 V, f = 1.0 MHz 130 VDS = 0 V to 400 Vc 140 Qg ID = 20 A, VDS = 400 V, see fig. 6 and 13 b - - 105 Gate-source charge Qgs - - 26 Gate-drain charge Qgd - - 42 Turn-on delay time td(on) - 18 - - 55 - - 45 - - 39 - - - 20 - - 80 - - 1.8 - 480 710 ns - 5.0 7.5 μC Rise time Turn-off delay time Fall time tr td(off) VGS = 10 V pF VDD = 250 V, ID = 20 A, RG = 4.3 Ω, RD = 13 Ω, see fig. 10 b tf nC ns Drain-Source Body Diode Characteristics Pulsed diode forward current a ISM MOSFET symbol showing the integral reverse p - n junction diode Body diode voltage VSD TJ = 25 °C, IS = 20A, VGS = 0 V b Continuous source-drain diode current IS Body diode reverse recovery time trr Body diode reverse recovery charge Qrr Forward turn-on time ton D A G S TJ = 25 °C, IF = 20 A, dI/dt = 100 A/μs b V Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11) b. Pulse width ≤ 300 μs; duty cycle ≤ 2 % c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDS S22-0058-Rev. C, 31-Jan-2022 Document Number: 91234 2 For technical questions, contact: hvmos.techsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFP460A www.vishay.com Vishay Siliconix 102 VGS ID, Drain-to-Source Current (A) Top 10 15 V 10 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V Bottom 4.5 V 1 4.5 V 20 µs Pulse Width TC = 25 °C 0.1 0.1 102 10 1 VDS, Drain-to-Source Voltage (V) 91234_01 RDS(on), Drain-to-Source On Resistance (Normalized) TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted ID = 20 A VGS = 10 V 2.5 2.0 1.5 1.0 0.5 0.0 - 60 - 40 - 20 0 20 40 60 80 100 120 140 160 TJ, Junction Temperature (°C) 91234_04 Fig. 4 - Normalized On-Resistance vs. Temperature Fig. 1 - Typical Output Characteristics 102 3.0 105 VGS VGS = 0 V, f = 1 MHz Ciss = Cgs + Cgd, Cds Shorted Crss = Cgd Coss = Cds + Cgd 10 15 V 10 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V Bottom 4.5 V 104 Capacitance (pF) ID, Drain-to-Source Current (A) Top 4.5 V Ciss 103 102 Coss 10 Crss 20 µs Pulse Width TC = 150 °C 1 102 10 1 VDS, Drain-to-Source Voltage (V) 91234_02 1 1 Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 2 - Typical Output Characteristics 20 25 °C 1 20 µs Pulse Width VDS = 50 V 0.1 4.0 91234_03 5.0 6.0 7.0 8.0 Fig. 3 - Typical Transfer Characteristics ID = 20 A VDS = 400 V 16 VDS = 250 V 12 VDS = 100 V 8 4 For test circuit see figure 13 0 0 9.0 VGS, Gate-to-Source Voltage (V) S22-0058-Rev. C, 31-Jan-2022 VGS, Gate-to-Source Voltage (V) ID, Drain-to-Source Current (A) 102 150 °C 103 VDS, Drain-to-Source Voltage (V) 91234_05 10 102 10 91234_06 20 40 60 80 100 QG, Total Gate Charge (nC) Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Document Number: 91234 3 For technical questions, contact: hvmos.techsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFP460A www.vishay.com Vishay Siliconix 20 ID, Drain Current (A) ISD, Reverse Drain Current (A) 102 150 °C 10 25 °C 1 15 10 5 VGS = 0 V 0.1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0 25 1.6 VSD, Source-to-Drain Voltage (V) 91234_07 91234_09 Fig. 7 - Typical Source-Drain Diode Forward Voltage 103 50 75 100 150 TC, Case Temperature (°C) Fig. 9 - Maximum Drain Current vs. Case Temperature RD Operation in this area limited by RDS(on) VDS VGS ID, Drain Current (A) 125 D.U.T. RG 102 + - VDD 10 µs 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % 100 µs 10 1 ms TC = 25 °C TJ = 150 °C Single Pulse 1 10 ms 102 10 Fig. 10 - Switching Time Test Circuit 103 VDS 104 90 % VDS, Drain-to-Source Voltage (V) 91234_08 Fig. 8 - Maximum Safe Operating Area 10 % VGS td(on) td(off) tf tr Fig. 11 - Switching Time Waveforms Thermal Response (ZthJC) 1 D = 0.5 0.1 0.2 0.1 0.05 10-2 PDM 0.02 0.01 t1 Single Pulse (Thermal Response) t2 Notes: 1. Duty Factor, D = t1/t2 2. Peak Tj = PDM x ZthJC + TC 10-3 10-5 10-4 10-3 10-2 0.1 1 t1, Rectangular Pulse Duration (S) 91234_11 Fig. 12 - Maximum Effective Transient Thermal Impedance, Junction-to-Case S22-0058-Rev. C, 31-Jan-2022 Document Number: 91234 4 For technical questions, contact: hvmos.techsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFP460A www.vishay.com Vishay Siliconix 15 V QG 10 V QGS Driver L VDS QGD VG D.U.T. RG + A - VDD IAS 20 V tp Charge 0.01 Ω Fig. 16 - Basic Gate Charge Waveform Fig. 13 - Unclamped Inductive Test Circuit 620 VDSav, Avalanche Voltage (V) VDS tp IAS Fig. 14 - Unclamped Inductive Waveforms 600 580 560 540 0 EAS, Single Pulse Avalanche Energy (mJ) ID Top 8.9 A 13 A Bottom 20 A 2000 16 12 20 IAV, Avalanche Current (A) 91234_12d 2400 8 4 Fig. 17 - Typical Drain-to-Source Voltage vs. Avalanche Current Current regulator Same type as D.U.T. 1600 1200 50 kΩ 12 V 0.2 µF 0.3 µF 800 + D.U.T. 400 VDS VGS 0 25 91234_12c - 50 75 100 125 150 Starting TJ, Junction Temperature (°C) Fig. 15 - Maximum Avalanche Energy vs. Drain Current 3 mA IG ID Current sampling resistors Fig. 18 - Gate Charge Test Circuit S22-0058-Rev. C, 31-Jan-2022 Document Number: 91234 5 For technical questions, contact: hvmos.techsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFP460A www.vishay.com Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + + - - Rg • • • • dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + - VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 19 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91234. S22-0058-Rev. C, 31-Jan-2022 Document Number: 91234 6 For technical questions, contact: hvmos.techsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information www.vishay.com Vishay Siliconix TO-247AC (High Voltage) VERSION 1: FACILITY CODE = 9 MILLIMETERS DIM. MIN. MAX. A 4.83 A1 2.29 MILLIMETERS NOTES DIM. MIN. MAX. NOTES 5.21 D1 16.25 16.85 5 2.55 D2 0.56 0.76 A2 1.50 2.49 E 15.50 15.87 b 1.12 1.33 E1 13.46 14.16 5 b1 1.12 1.28 E2 4.52 5.49 3 b2 1.91 2.39 b3 1.91 2.34 b4 2.87 3.22 b5 2.87 3.18 c 0.55 0.69 c1 0.55 0.65 D 20.40 20.70 4 6 e L 14.90 15.40 6, 8 L1 3.96 4.16 6 ØP 3.56 3.65 7 6 4 5.44 BSC Ø P1 7.19 ref. Q 5.31 5.69 S 5.54 5.74 Notes (1) Package reference: JEDEC® TO247, variation AC (2) All dimensions are in mm (3) Slot required, notch may be rounded (4) Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm per side. These dimensions are measured at the outermost extremes of the plastic body (5) Thermal pad contour optional with dimensions D1 and E1 (6) Lead finish uncontrolled in L1 (7) Ø P to have a maximum draft angle of 1.5° to the top of the part with a maximum hole diameter of 3.91 mm (8) Dimension b2 and b4 does not include dambar protrusion. Allowable dambar protrusion shall be 0.1 mm total in excess of b2 and b4 dimension at maximum material condition Revision: 19-Oct-2020 Document Number: 91360 1 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information www.vishay.com Vishay Siliconix VERSION 2: FACILITY CODE = Y A A 4 E B 3 R/2 E/2 7 ØP Ø k M DBM A2 S (Datum B) ØP1 A D2 Q 4 4 2xR (2) D1 D 1 2 4 D 3 Thermal pad 5 L1 C L See view B 2 x b2 3xb 0.10 M C A M 4 E1 A 0.01 M D B M View A - A C 2x e A1 b4 (b1, b3, b5) Planting Lead Assignments 1. Gate 2. Drain 3. Source 4. Drain D DE Base metal E C (c) C c1 (b, b2, b4) (4) Section C - C, D - D, E - E View B MILLIMETERS DIM. MIN. MAX. A 4.58 5.31 MILLIMETERS NOTES DIM. MIN. MAX. D2 0.51 1.30 15.87 A1 2.21 2.59 E 15.29 A2 1.17 2.49 E1 13.72 b 0.99 1.40 e 5.46 BSC b1 0.99 1.35 Øk b2 1.53 2.39 L 14.20 16.25 b3 1.65 2.37 L1 3.71 4.29 b4 2.42 3.43 ØP 3.51 3.66 b5 2.59 3.38 Ø P1 - 7.39 c 0.38 0.86 Q 5.31 5.69 4.52 c1 0.38 0.76 R D 19.71 20.82 S D1 13.08 - NOTES 0.254 5.49 5.51 BSC Notes (1) Dimensioning and tolerancing per ASME Y14.5M-1994 (2) Contour of slot optional (3) Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outermost extremes of the plastic body (4) Thermal pad contour optional with dimensions D1 and E1 (5) Lead finish uncontrolled in L1 (6) Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154") (7) Outline conforms to JEDEC outline TO-247 with exception of dimension c Revision: 19-Oct-2020 Document Number: 91360 2 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information www.vishay.com Vishay Siliconix VERSION 3: FACILITY CODE = N A E R/2 D2 B A P A2 D1 L1 D D K M D BM R S Q N P1 b2 L C e b b4 C E1 A1 0.01 M D B M 0.10 M C A M b1, b3, b5 c c1 Base metal Plating b, b2, b4 MILLIMETERS MILLIMETERS DIM. MIN. MAX. DIM. MIN. A 4.65 5.31 D2 0.51 MAX. 1.35 A1 2.21 2.59 E 15.29 15.87 13.46 A2 1.17 1.37 E1 b 0.99 1.40 e - b1 0.99 1.35 k b2 1.65 2.39 L 14.20 b3 1.65 2.34 L1 3.71 b4 2.59 3.43 N b5 2.59 3.38 P 3.56 c 0.38 0.89 P1 - 7.39 c1 0.38 0.84 Q 5.31 5.69 D 19.71 20.70 R 4.52 D1 13.08 - S 5.46 BSC 0.254 16.10 4.29 7.62 BSC 3.66 5.49 5.51 BSC ECN: E20-0545-Rev. F, 19-Oct-2020 DWG: 5971 Notes (1) Dimensioning and tolerancing per ASME Y14.5M-1994 (2) Contour of slot optional (3) Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outermost extremes of the plastic body (4) Thermal pad contour optional with dimensions D1 and E1 (5) Lead finish uncontrolled in L1 (6) Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154") Revision: 19-Oct-2020 Document Number: 91360 3 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. 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